crypto: hisilicon - enable error reporting again

When an error occurs on the device, an interrupt is reported.
When the firmware forwards the interrupt to the driver and masks the
error. If the driver does not enable error reporting when an error does
not need to be reset, the device does not report the error to the driver
when the error occurs again. Therefore, after the driver obtains the
information, the error reporting needs to be enabled again.

Signed-off-by: Weili Qian <qianweili@huawei.com>
Signed-off-by: Chenghai Huang <huangchenghai2@huawei.com>
Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>

authored by

Weili Qian and committed by

Herbert Xu 8 months ago 80736a97 3d716c51

+41

4 changed files

expand all

drivers

crypto

hisilicon

hpre

hpre_main.c

sec2

sec_main.c

zip

dae_main.c

zip_main.c

+11

drivers/crypto/hisilicon/hpre/hpre_main.c

··· 1399 1399 writel(nfe_mask & (~err_type), qm->io_base + HPRE_RAS_NFE_ENB); 1400 1400 } 1401 1401 1402 + static void hpre_enable_error_report(struct hisi_qm *qm) 1403 + { 1404 + u32 nfe_mask = qm->err_info.dev_err.nfe; 1405 + u32 ce_mask = qm->err_info.dev_err.ce; 1406 + 1407 + writel(nfe_mask, qm->io_base + HPRE_RAS_NFE_ENB); 1408 + writel(ce_mask, qm->io_base + HPRE_RAS_CE_ENB); 1409 + } 1410 + 1402 1411 static void hpre_open_axi_master_ooo(struct hisi_qm *qm) 1403 1412 { 1404 1413 u32 value; ··· 1435 1426 return ACC_ERR_NEED_RESET; 1436 1427 } 1437 1428 hpre_clear_hw_err_status(qm, err_status); 1429 + /* Avoid firmware disable error report, re-enable. */ 1430 + hpre_enable_error_report(qm); 1438 1431 } 1439 1432 1440 1433 return ACC_ERR_RECOVERED;

+11

drivers/crypto/hisilicon/sec2/sec_main.c

··· 1112 1112 writel(nfe_mask & (~err_type), qm->io_base + SEC_RAS_NFE_REG); 1113 1113 } 1114 1114 1115 + static void sec_enable_error_report(struct hisi_qm *qm) 1116 + { 1117 + u32 nfe_mask = qm->err_info.dev_err.nfe; 1118 + u32 ce_mask = qm->err_info.dev_err.ce; 1119 + 1120 + writel(nfe_mask, qm->io_base + SEC_RAS_NFE_REG); 1121 + writel(ce_mask, qm->io_base + SEC_RAS_CE_REG); 1122 + } 1123 + 1115 1124 static void sec_open_axi_master_ooo(struct hisi_qm *qm) 1116 1125 { 1117 1126 u32 val; ··· 1146 1137 return ACC_ERR_NEED_RESET; 1147 1138 } 1148 1139 sec_clear_hw_err_status(qm, err_status); 1140 + /* Avoid firmware disable error report, re-enable. */ 1141 + sec_enable_error_report(qm); 1149 1142 } 1150 1143 1151 1144 return ACC_ERR_RECOVERED;

drivers/crypto/hisilicon/zip/dae_main.c

··· 175 175 writel(DAE_ERR_NFE_MASK & (~err_type), qm->io_base + DAE_ERR_NFE_OFFSET); 176 176 } 177 177 178 + static void hisi_dae_enable_error_report(struct hisi_qm *qm) 179 + { 180 + writel(DAE_ERR_CE_MASK, qm->io_base + DAE_ERR_CE_OFFSET); 181 + writel(DAE_ERR_NFE_MASK, qm->io_base + DAE_ERR_NFE_OFFSET); 182 + } 183 + 178 184 static void hisi_dae_log_hw_error(struct hisi_qm *qm, u32 err_type) 179 185 { 180 186 const struct hisi_dae_hw_error *err = dae_hw_error; ··· 222 216 return ACC_ERR_NEED_RESET; 223 217 } 224 218 hisi_dae_clear_hw_err_status(qm, err_status); 219 + /* Avoid firmware disable error report, re-enable. */ 220 + hisi_dae_enable_error_report(qm); 225 221 226 222 return ACC_ERR_RECOVERED; 227 223 }

+11

drivers/crypto/hisilicon/zip/zip_main.c

··· 1188 1188 writel(nfe_mask & (~err_type), qm->io_base + HZIP_CORE_INT_RAS_NFE_ENB); 1189 1189 } 1190 1190 1191 + static void hisi_zip_enable_error_report(struct hisi_qm *qm) 1192 + { 1193 + u32 nfe_mask = qm->err_info.dev_err.nfe; 1194 + u32 ce_mask = qm->err_info.dev_err.ce; 1195 + 1196 + writel(nfe_mask, qm->io_base + HZIP_CORE_INT_RAS_NFE_ENB); 1197 + writel(ce_mask, qm->io_base + HZIP_CORE_INT_RAS_CE_ENB); 1198 + } 1199 + 1191 1200 static void hisi_zip_open_axi_master_ooo(struct hisi_qm *qm) 1192 1201 { 1193 1202 u32 val; ··· 1245 1236 zip_result = ACC_ERR_NEED_RESET; 1246 1237 } else { 1247 1238 hisi_zip_clear_hw_err_status(qm, err_status); 1239 + /* Avoid firmware disable error report, re-enable. */ 1240 + hisi_zip_enable_error_report(qm); 1248 1241 } 1249 1242 } 1250 1243

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