tjh.dev / kernel
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phy: qualcomm: qmp-pcie: define several new registers

Define several registers to be used by PCIe QMP PHYs on v6 platforms.

Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org>
Link: https://lore.kernel.org/r/20241021-sar2130p-phys-v2-5-d883acf170f7@linaro.org
Signed-off-by: Vinod Koul <vkoul@kernel.org>

authored by

Dmitry Baryshkov and committed by
Vinod Koul 8114f34d f9d35dd3

+6
+3
drivers/phy/qualcomm/phy-qcom-qmp-pcs-pcie-v6.h
··· 14 14 #define QPHY_PCIE_V6_PCS_PCIE_ENDPOINT_REFCLK_DRIVE 0x20 15 15 #define QPHY_PCIE_V6_PCS_PCIE_OSC_DTCT_ACTIONS 0x94 16 16 17 + #define QPHY_PCIE_V6_PCS_LANE1_INSIG_SW_CTRL2 0x024 18 + #define QPHY_PCIE_V6_PCS_LANE1_INSIG_MX_CTRL2 0x028 19 + 17 20 #endif
+2
drivers/phy/qualcomm/phy-qcom-qmp-pcs-v6.h
··· 17 17 #define QPHY_V6_PCS_LOCK_DETECT_CONFIG3 0x0cc 18 18 #define QPHY_V6_PCS_LOCK_DETECT_CONFIG6 0x0d8 19 19 #define QPHY_V6_PCS_REFGEN_REQ_CONFIG1 0x0dc 20 + #define QPHY_V6_PCS_G12S1_TXDEEMPH_M6DB 0x168 21 + #define QPHY_V6_PCS_G3S2_PRE_GAIN 0x170 20 22 #define QPHY_V6_PCS_RX_SIGDET_LVL 0x188 21 23 #define QPHY_V6_PCS_RCVR_DTCT_DLY_P1U2_L 0x190 22 24 #define QPHY_V6_PCS_RCVR_DTCT_DLY_P1U2_H 0x194
+1
drivers/phy/qualcomm/phy-qcom-qmp-qserdes-txrx-v6.h
··· 6 6 #ifndef QCOM_PHY_QMP_QSERDES_TXRX_USB_V6_H_ 7 7 #define QCOM_PHY_QMP_QSERDES_TXRX_USB_V6_H_ 8 8 9 + #define QSERDES_V6_TX_BIST_MODE_LANENO 0x00 9 10 #define QSERDES_V6_TX_CLKBUF_ENABLE 0x08 10 11 #define QSERDES_V6_TX_TX_EMP_POST1_LVL 0x0c 11 12 #define QSERDES_V6_TX_TX_DRV_LVL 0x14