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phy: qualcomm: qmp-pcie: split PCS_LANE1 region

The PCS_LANE1 region isn't a part of the PCS_PCIE region. It was handled
this way as it simplified handled of devices with the old bindings.
Nowadays it can be handled as is, without hacks.

Split the PCS_LANE1 region from the PCS_PCIE / PCS_MISC region space.

Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org>
Link: https://lore.kernel.org/r/20241021-sar2130p-phys-v2-4-d883acf170f7@linaro.org
Signed-off-by: Vinod Koul <vkoul@kernel.org>

authored by

Dmitry Baryshkov and committed by
Vinod Koul f9d35dd3 545069bc

+33 -9
+27 -5
drivers/phy/qualcomm/phy-qcom-qmp-pcie.c
··· 1850 1850 QMP_PHY_INIT_CFG(QPHY_V4_20_PCS_PCIE_OSC_DTCT_ACTIONS, 0x00), 1851 1851 }; 1852 1852 1853 - static const struct qmp_phy_init_tbl sdx55_qmp_pcie_ep_pcs_misc_tbl[] = { 1853 + static const struct qmp_phy_init_tbl sdx55_qmp_pcie_ep_pcs_lane1_tbl[] = { 1854 1854 QMP_PHY_INIT_CFG(QPHY_V4_20_PCS_LANE1_INSIG_SW_CTRL2, 0x00), 1855 1855 QMP_PHY_INIT_CFG(QPHY_V4_20_PCS_LANE1_INSIG_MX_CTRL2, 0x00), 1856 1856 }; ··· 1984 1984 QMP_PHY_INIT_CFG(QPHY_V5_20_PCS_PCIE_G4_EQ_CONFIG2, 0x0d), 1985 1985 QMP_PHY_INIT_CFG(QPHY_V5_20_PCS_PCIE_G4_EQ_CONFIG5, 0x02), 1986 1986 QMP_PHY_INIT_CFG(QPHY_V5_20_PCS_PCIE_G4_PRE_GAIN, 0x2e), 1987 + }; 1988 + 1989 + static const struct qmp_phy_init_tbl sdx65_qmp_pcie_pcs_lane1_tbl[] = { 1987 1990 QMP_PHY_INIT_CFG(QPHY_V5_20_PCS_LANE1_INSIG_SW_CTRL2, 0x00), 1988 1991 QMP_PHY_INIT_CFG(QPHY_V5_20_PCS_LANE1_INSIG_MX_CTRL2, 0x00), 1989 1992 }; ··· 2662 2659 static const struct qmp_phy_init_tbl sa8775p_qmp_gen4x2_pcie_pcs_alt_tbl[] = { 2663 2660 QMP_PHY_INIT_CFG(QPHY_V5_20_PCS_EQ_CONFIG4, 0x16), 2664 2661 QMP_PHY_INIT_CFG(QPHY_V5_20_PCS_EQ_CONFIG5, 0x22), 2665 - QMP_PHY_INIT_CFG(QPHY_V5_20_PCS_LANE1_INSIG_SW_CTRL2, 0x00), 2666 - QMP_PHY_INIT_CFG(QPHY_V5_20_PCS_LANE1_INSIG_MX_CTRL2, 0x00), 2667 2662 QMP_PHY_INIT_CFG(QPHY_V5_20_PCS_G3S2_PRE_GAIN, 0x2e), 2668 2663 QMP_PHY_INIT_CFG(QPHY_V5_20_PCS_RX_SIGDET_LVL, 0x66), 2669 2664 }; ··· 2806 2805 u16 serdes; 2807 2806 u16 pcs; 2808 2807 u16 pcs_misc; 2808 + u16 pcs_lane1; 2809 2809 u16 tx; 2810 2810 u16 rx; 2811 2811 u16 tx2; ··· 2831 2829 int pcs_num; 2832 2830 const struct qmp_phy_init_tbl *pcs_misc; 2833 2831 int pcs_misc_num; 2832 + const struct qmp_phy_init_tbl *pcs_lane1; 2833 + int pcs_lane1_num; 2834 2834 const struct qmp_phy_init_tbl *ln_shrd; 2835 2835 int ln_shrd_num; 2836 2836 }; ··· 2892 2888 void __iomem *serdes; 2893 2889 void __iomem *pcs; 2894 2890 void __iomem *pcs_misc; 2891 + void __iomem *pcs_lane1; 2895 2892 void __iomem *tx; 2896 2893 void __iomem *rx; 2897 2894 void __iomem *tx2; ··· 3009 3004 .serdes = 0x1000, 3010 3005 .pcs = 0x1200, 3011 3006 .pcs_misc = 0x1600, 3007 + .pcs_lane1 = 0x1e00, 3012 3008 .tx = 0x0000, 3013 3009 .rx = 0x0200, 3014 3010 .tx2 = 0x0800, ··· 3040 3034 .serdes = 0x1000, 3041 3035 .pcs = 0x1200, 3042 3036 .pcs_misc = 0x1400, 3037 + .pcs_lane1 = 0x1e00, 3043 3038 .tx = 0x0000, 3044 3039 .rx = 0x0200, 3045 3040 .tx2 = 0x0800, ··· 3549 3542 .tbls_ep = &(const struct qmp_phy_cfg_tbls) { 3550 3543 .serdes = sdx55_qmp_pcie_ep_serdes_tbl, 3551 3544 .serdes_num = ARRAY_SIZE(sdx55_qmp_pcie_ep_serdes_tbl), 3552 - .pcs_misc = sdx55_qmp_pcie_ep_pcs_misc_tbl, 3553 - .pcs_misc_num = ARRAY_SIZE(sdx55_qmp_pcie_ep_pcs_misc_tbl), 3545 + .pcs_lane1 = sdx55_qmp_pcie_ep_pcs_lane1_tbl, 3546 + .pcs_lane1_num = ARRAY_SIZE(sdx55_qmp_pcie_ep_pcs_lane1_tbl), 3554 3547 }, 3555 3548 3556 3549 .reset_list = sdm845_pciephy_reset_l, ··· 3649 3642 .pcs_num = ARRAY_SIZE(sdx65_qmp_pcie_pcs_tbl), 3650 3643 .pcs_misc = sdx65_qmp_pcie_pcs_misc_tbl, 3651 3644 .pcs_misc_num = ARRAY_SIZE(sdx65_qmp_pcie_pcs_misc_tbl), 3645 + .pcs_lane1 = sdx65_qmp_pcie_pcs_lane1_tbl, 3646 + .pcs_lane1_num = ARRAY_SIZE(sdx65_qmp_pcie_pcs_lane1_tbl), 3652 3647 }, 3653 3648 .reset_list = sdm845_pciephy_reset_l, 3654 3649 .num_resets = ARRAY_SIZE(sdm845_pciephy_reset_l), ··· 3850 3841 .pcs_num = ARRAY_SIZE(sa8775p_qmp_gen4x2_pcie_pcs_alt_tbl), 3851 3842 .pcs_misc = sa8775p_qmp_gen4_pcie_pcs_misc_tbl, 3852 3843 .pcs_misc_num = ARRAY_SIZE(sa8775p_qmp_gen4_pcie_pcs_misc_tbl), 3844 + .pcs_lane1 = sdx65_qmp_pcie_pcs_lane1_tbl, 3845 + .pcs_lane1_num = ARRAY_SIZE(sdx65_qmp_pcie_pcs_lane1_tbl), 3853 3846 }, 3854 3847 3855 3848 .tbls_rc = &(const struct qmp_phy_cfg_tbls) { ··· 4058 4047 void __iomem *rx2 = qmp->rx2; 4059 4048 void __iomem *pcs = qmp->pcs; 4060 4049 void __iomem *pcs_misc = qmp->pcs_misc; 4050 + void __iomem *pcs_lane1 = qmp->pcs_lane1; 4061 4051 void __iomem *ln_shrd = qmp->ln_shrd; 4062 4052 4063 4053 if (!tbls) ··· 4083 4071 4084 4072 qmp_configure(qmp->dev, pcs, tbls->pcs, tbls->pcs_num); 4085 4073 qmp_configure(qmp->dev, pcs_misc, tbls->pcs_misc, tbls->pcs_misc_num); 4074 + qmp_configure(qmp->dev, pcs_lane1, tbls->pcs_lane1, tbls->pcs_lane1_num); 4086 4075 4087 4076 if (cfg->lanes >= 4 && qmp->tcsr_4ln_config) { 4088 4077 qmp_configure(qmp->dev, serdes, cfg->serdes_4ln_tbl, ··· 4535 4522 } 4536 4523 } 4537 4524 4525 + /* 4526 + * For all platforms where legacy bindings existed, PCS_LANE1 was 4527 + * mapped as a part of the PCS_MISC region. 4528 + */ 4529 + if (!IS_ERR(qmp->pcs_misc) && cfg->offsets->pcs_lane1 != 0) 4530 + qmp->pcs_lane1 = qmp->pcs_misc + 4531 + (cfg->offsets->pcs_lane1 - cfg->offsets->pcs_misc); 4532 + 4538 4533 clk = devm_get_clk_from_child(dev, np, NULL); 4539 4534 if (IS_ERR(clk)) { 4540 4535 return dev_err_probe(dev, PTR_ERR(clk), ··· 4610 4589 qmp->serdes = base + offs->serdes; 4611 4590 qmp->pcs = base + offs->pcs; 4612 4591 qmp->pcs_misc = base + offs->pcs_misc; 4592 + qmp->pcs_lane1 = base + offs->pcs_lane1; 4613 4593 qmp->tx = base + offs->tx; 4614 4594 qmp->rx = base + offs->rx; 4615 4595
+3 -2
drivers/phy/qualcomm/phy-qcom-qmp-pcs-pcie-v4_20.h
··· 13 13 #define QPHY_V4_20_PCS_PCIE_G4_RXEQEVAL_TIME 0x0f4 14 14 #define QPHY_V4_20_PCS_PCIE_G4_EQ_CONFIG2 0x0fc 15 15 #define QPHY_V4_20_PCS_PCIE_G4_EQ_CONFIG5 0x108 16 - #define QPHY_V4_20_PCS_LANE1_INSIG_SW_CTRL2 0x824 17 - #define QPHY_V4_20_PCS_LANE1_INSIG_MX_CTRL2 0x828 16 + 17 + #define QPHY_V4_20_PCS_LANE1_INSIG_SW_CTRL2 0x024 18 + #define QPHY_V4_20_PCS_LANE1_INSIG_MX_CTRL2 0x028 18 19 19 20 #endif
+3 -2
drivers/phy/qualcomm/phy-qcom-qmp-pcs-pcie-v5_20.h
··· 17 17 #define QPHY_V5_20_PCS_PCIE_G4_EQ_CONFIG5 0x108 18 18 #define QPHY_V5_20_PCS_PCIE_G4_PRE_GAIN 0x15c 19 19 #define QPHY_V5_20_PCS_PCIE_RX_MARGINING_CONFIG3 0x184 20 - #define QPHY_V5_20_PCS_LANE1_INSIG_SW_CTRL2 0xa24 21 - #define QPHY_V5_20_PCS_LANE1_INSIG_MX_CTRL2 0xa28 20 + 21 + #define QPHY_V5_20_PCS_LANE1_INSIG_SW_CTRL2 0x024 22 + #define QPHY_V5_20_PCS_LANE1_INSIG_MX_CTRL2 0x028 22 23 23 24 #endif