Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
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linux
Merge tag 'pci-v4.9-fixes-3' of git://git.kernel.org/pub/scm/linux/kernel/git/helgaas/pci
Pull PCI fixes from Bjorn Helgaas:
- Update MAINTAINERS for Intel VMD driver filename
- Update Rockchip rk3399 host bridge driver DTS and resets
- Fix ROM shadow problem that made some video device initialization
fail
* tag 'pci-v4.9-fixes-3' of git://git.kernel.org/pub/scm/linux/kernel/git/helgaas/pci:
PCI: VMD: Update filename to reflect move
arm64: dts: rockchip: add three new resets for rk3399 PCIe controller
PCI: rockchip: Add three new resets as required properties
PCI: Don't attempt to claim shadow copies of ROM
+84
-6
+8
-3
Documentation/devicetree/bindings/pci/rockchip-pcie.txt
+8
-3
Documentation/devicetree/bindings/pci/rockchip-pcie.txt
···
26
26
- "sys"
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- "legacy"
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- "client"
29
-
- resets: Must contain five entries for each entry in reset-names.
29
+
- resets: Must contain seven entries for each entry in reset-names.
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See ../reset/reset.txt for details.
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31
- reset-names: Must include the following names
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32
- "core"
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- "mgmt"
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- "mgmt-sticky"
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- "pipe"
36
+
- "pm"
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+
- "aclk"
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+
- "pclk"
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- pinctrl-names : The pin control state names
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- pinctrl-0: The "default" pinctrl state
38
41
- #interrupt-cells: specifies the number of cells needed to encode an
···
89
86
reg = <0x0 0xf8000000 0x0 0x2000000>, <0x0 0xfd000000 0x0 0x1000000>;
90
87
reg-names = "axi-base", "apb-base";
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resets = <&cru SRST_PCIE_CORE>, <&cru SRST_PCIE_MGMT>,
92
-
<&cru SRST_PCIE_MGMT_STICKY>, <&cru SRST_PCIE_PIPE>;
93
-
reset-names = "core", "mgmt", "mgmt-sticky", "pipe";
89
+
<&cru SRST_PCIE_MGMT_STICKY>, <&cru SRST_PCIE_PIPE> ,
90
+
<&cru SRST_PCIE_PM>, <&cru SRST_P_PCIE>, <&cru SRST_A_PCIE>;
91
+
reset-names = "core", "mgmt", "mgmt-sticky", "pipe",
92
+
"pm", "pclk", "aclk";
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phys = <&pcie_phy>;
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phy-names = "pcie-phy";
96
95
pinctrl-names = "default";
+1
-1
MAINTAINERS
+1
-1
MAINTAINERS
+5
-2
arch/arm64/boot/dts/rockchip/rk3399.dtsi
+5
-2
arch/arm64/boot/dts/rockchip/rk3399.dtsi
···
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300
ranges = <0x83000000 0x0 0xfa000000 0x0 0xfa000000 0x0 0x600000
301
301
0x81000000 0x0 0xfa600000 0x0 0xfa600000 0x0 0x100000>;
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resets = <&cru SRST_PCIE_CORE>, <&cru SRST_PCIE_MGMT>,
303
-
<&cru SRST_PCIE_MGMT_STICKY>, <&cru SRST_PCIE_PIPE>;
304
-
reset-names = "core", "mgmt", "mgmt-sticky", "pipe";
303
+
<&cru SRST_PCIE_MGMT_STICKY>, <&cru SRST_PCIE_PIPE>,
304
+
<&cru SRST_PCIE_PM>, <&cru SRST_P_PCIE>,
305
+
<&cru SRST_A_PCIE>;
306
+
reset-names = "core", "mgmt", "mgmt-sticky", "pipe",
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+
"pm", "pclk", "aclk";
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status = "disabled";
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307
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pcie0_intc: interrupt-controller {
+62
drivers/pci/host/pcie-rockchip.c
+62
drivers/pci/host/pcie-rockchip.c
···
190
190
struct reset_control *mgmt_rst;
191
191
struct reset_control *mgmt_sticky_rst;
192
192
struct reset_control *pipe_rst;
193
+
struct reset_control *pm_rst;
194
+
struct reset_control *aclk_rst;
195
+
struct reset_control *pclk_rst;
193
196
struct clk *aclk_pcie;
194
197
struct clk *aclk_perf_pcie;
195
198
struct clk *hclk_pcie;
···
410
407
unsigned long timeout;
411
408
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409
gpiod_set_value(rockchip->ep_gpio, 0);
410
+
411
+
err = reset_control_assert(rockchip->aclk_rst);
412
+
if (err) {
413
+
dev_err(dev, "assert aclk_rst err %d\n", err);
414
+
return err;
415
+
}
416
+
417
+
err = reset_control_assert(rockchip->pclk_rst);
418
+
if (err) {
419
+
dev_err(dev, "assert pclk_rst err %d\n", err);
420
+
return err;
421
+
}
422
+
423
+
err = reset_control_assert(rockchip->pm_rst);
424
+
if (err) {
425
+
dev_err(dev, "assert pm_rst err %d\n", err);
426
+
return err;
427
+
}
428
+
429
+
udelay(10);
430
+
431
+
err = reset_control_deassert(rockchip->pm_rst);
432
+
if (err) {
433
+
dev_err(dev, "deassert pm_rst err %d\n", err);
434
+
return err;
435
+
}
436
+
437
+
err = reset_control_deassert(rockchip->aclk_rst);
438
+
if (err) {
439
+
dev_err(dev, "deassert mgmt_sticky_rst err %d\n", err);
440
+
return err;
441
+
}
442
+
443
+
err = reset_control_deassert(rockchip->pclk_rst);
444
+
if (err) {
445
+
dev_err(dev, "deassert mgmt_sticky_rst err %d\n", err);
446
+
return err;
447
+
}
413
448
414
449
err = phy_init(rockchip->phy);
415
450
if (err < 0) {
···
820
779
if (PTR_ERR(rockchip->pipe_rst) != -EPROBE_DEFER)
821
780
dev_err(dev, "missing pipe reset property in node\n");
822
781
return PTR_ERR(rockchip->pipe_rst);
782
+
}
783
+
784
+
rockchip->pm_rst = devm_reset_control_get(dev, "pm");
785
+
if (IS_ERR(rockchip->pm_rst)) {
786
+
if (PTR_ERR(rockchip->pm_rst) != -EPROBE_DEFER)
787
+
dev_err(dev, "missing pm reset property in node\n");
788
+
return PTR_ERR(rockchip->pm_rst);
789
+
}
790
+
791
+
rockchip->pclk_rst = devm_reset_control_get(dev, "pclk");
792
+
if (IS_ERR(rockchip->pclk_rst)) {
793
+
if (PTR_ERR(rockchip->pclk_rst) != -EPROBE_DEFER)
794
+
dev_err(dev, "missing pclk reset property in node\n");
795
+
return PTR_ERR(rockchip->pclk_rst);
796
+
}
797
+
798
+
rockchip->aclk_rst = devm_reset_control_get(dev, "aclk");
799
+
if (IS_ERR(rockchip->aclk_rst)) {
800
+
if (PTR_ERR(rockchip->aclk_rst) != -EPROBE_DEFER)
801
+
dev_err(dev, "missing aclk reset property in node\n");
802
+
return PTR_ERR(rockchip->aclk_rst);
823
803
}
824
804
825
805
rockchip->ep_gpio = devm_gpiod_get(dev, "ep", GPIOD_OUT_HIGH);
+8
drivers/pci/setup-res.c
+8
drivers/pci/setup-res.c
···
121
121
return -EINVAL;
122
122
}
123
123
124
+
/*
125
+
* If we have a shadow copy in RAM, the PCI device doesn't respond
126
+
* to the shadow range, so we don't need to claim it, and upstream
127
+
* bridges don't need to route the range to the device.
128
+
*/
129
+
if (res->flags & IORESOURCE_ROM_SHADOW)
130
+
return 0;
131
+
124
132
root = pci_find_parent_resource(dev, res);
125
133
if (!root) {
126
134
dev_info(&dev->dev, "can't claim BAR %d %pR: no compatible bridge window\n",