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dt-bindings: ti-serdes-mux: Add defines for J784S4 SoC

There are 4 lanes in the single instance of J784S4 SERDES. Each SERDES
lane mux can select up to 4 different IPs. Define all the possible
functions.

Signed-off-by: Matt Ranostay <mranostay@ti.com>
Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Siddharth Vadapalli <s-vadapalli@ti.com>
Signed-off-by: Peter Rosin <peda@axentia.se>
Link: https://lore.kernel.org/r/755a14f1-92ad-ce4b-3fde-2a4b0650475c@axentia.se
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>

authored by

Matt Ranostay and committed by
Greg Kroah-Hartman 8258d997 5ccf4028

+62
+62
include/dt-bindings/mux/ti-serdes.h
··· 117 117 #define J721S2_SERDES0_LANE3_USB 0x2 118 118 #define J721S2_SERDES0_LANE3_IP4_UNUSED 0x3 119 119 120 + /* J784S4 */ 121 + 122 + #define J784S4_SERDES0_LANE0_IP1_UNUSED 0x0 123 + #define J784S4_SERDES0_LANE0_PCIE1_LANE0 0x1 124 + #define J784S4_SERDES0_LANE0_IP3_UNUSED 0x2 125 + #define J784S4_SERDES0_LANE0_IP4_UNUSED 0x3 126 + 127 + #define J784S4_SERDES0_LANE1_IP1_UNUSED 0x0 128 + #define J784S4_SERDES0_LANE1_PCIE1_LANE1 0x1 129 + #define J784S4_SERDES0_LANE1_IP3_UNUSED 0x2 130 + #define J784S4_SERDES0_LANE1_IP4_UNUSED 0x3 131 + 132 + #define J784S4_SERDES0_LANE2_PCIE3_LANE0 0x0 133 + #define J784S4_SERDES0_LANE2_PCIE1_LANE2 0x1 134 + #define J784S4_SERDES0_LANE2_IP3_UNUSED 0x2 135 + #define J784S4_SERDES0_LANE2_IP4_UNUSED 0x3 136 + 137 + #define J784S4_SERDES0_LANE3_PCIE3_LANE1 0x0 138 + #define J784S4_SERDES0_LANE3_PCIE1_LANE3 0x1 139 + #define J784S4_SERDES0_LANE3_USB 0x2 140 + #define J784S4_SERDES0_LANE3_IP4_UNUSED 0x3 141 + 142 + #define J784S4_SERDES1_LANE0_QSGMII_LANE3 0x0 143 + #define J784S4_SERDES1_LANE0_PCIE0_LANE0 0x1 144 + #define J784S4_SERDES1_LANE0_IP3_UNUSED 0x2 145 + #define J784S4_SERDES1_LANE0_IP4_UNUSED 0x3 146 + 147 + #define J784S4_SERDES1_LANE1_QSGMII_LANE4 0x0 148 + #define J784S4_SERDES1_LANE1_PCIE0_LANE1 0x1 149 + #define J784S4_SERDES1_LANE1_IP3_UNUSED 0x2 150 + #define J784S4_SERDES1_LANE1_IP4_UNUSED 0x3 151 + 152 + #define J784S4_SERDES1_LANE2_QSGMII_LANE1 0x0 153 + #define J784S4_SERDES1_LANE2_PCIE0_LANE2 0x1 154 + #define J784S4_SERDES1_LANE2_PCIE2_LANE0 0x2 155 + #define J784S4_SERDES1_LANE2_IP4_UNUSED 0x3 156 + 157 + #define J784S4_SERDES1_LANE3_QSGMII_LANE2 0x0 158 + #define J784S4_SERDES1_LANE3_PCIE0_LANE3 0x1 159 + #define J784S4_SERDES1_LANE3_PCIE2_LANE1 0x2 160 + #define J784S4_SERDES1_LANE3_IP4_UNUSED 0x3 161 + 162 + #define J784S4_SERDES2_LANE0_QSGMII_LANE5 0x0 163 + #define J784S4_SERDES2_LANE0_IP2_UNUSED 0x1 164 + #define J784S4_SERDES2_LANE0_IP3_UNUSED 0x2 165 + #define J784S4_SERDES2_LANE0_IP4_UNUSED 0x3 166 + 167 + #define J784S4_SERDES2_LANE1_QSGMII_LANE6 0x0 168 + #define J784S4_SERDES2_LANE1_IP2_UNUSED 0x1 169 + #define J784S4_SERDES2_LANE1_IP3_UNUSED 0x2 170 + #define J784S4_SERDES2_LANE1_IP4_UNUSED 0x3 171 + 172 + #define J784S4_SERDES2_LANE2_QSGMII_LANE7 0x0 173 + #define J784S4_SERDES2_LANE2_QSGMII_LANE1 0x1 174 + #define J784S4_SERDES2_LANE2_IP3_UNUSED 0x2 175 + #define J784S4_SERDES2_LANE2_IP4_UNUSED 0x3 176 + 177 + #define J784S4_SERDES2_LANE3_QSGMII_LANE8 0x0 178 + #define J784S4_SERDES2_LANE3_QSGMII_LANE2 0x1 179 + #define J784S4_SERDES2_LANE3_IP3_UNUSED 0x2 180 + #define J784S4_SERDES2_LANE3_IP4_UNUSED 0x3 181 + 120 182 #endif /* _DT_BINDINGS_MUX_TI_SERDES */