Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
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linux
crypto: octeontx2 - add devlink option to set t106 mode
On CN10KA B0/CN10KB, CPT scatter gather format has modified
to support multi-seg in inline IPsec. Due to this CPT requires
new firmware and doesn't work with CN10KA0/A1 firmware. To make
HW works in backward compatibility mode or works with CN10KA0/A1
firmware, a bit(T106_MODE) is introduced in HW CSR.
This patch adds devlink parameter for configuring T106_MODE.
This patch also documents the devlink parameter under
Documentation/crypto/device_drivers.
Signed-off-by: Srujana Challa <schalla@marvell.com>
Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
authored by
Srujana Challa
and committed by
Herbert Xu
82f89f1a
92508e7f
+87
-4
+9
Documentation/crypto/device_drivers/index.rst
+9
Documentation/crypto/device_drivers/index.rst
+25
Documentation/crypto/device_drivers/octeontx2.rst
+25
Documentation/crypto/device_drivers/octeontx2.rst
···
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.. SPDX-License-Identifier: GPL-2.0
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=========================
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octeontx2 devlink support
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=========================
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This document describes the devlink features implemented by the ``octeontx2 CPT``
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device drivers.
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Parameters
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==========
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The ``octeontx2`` driver implements the following driver-specific parameters.
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.. list-table:: Driver-specific parameters implemented
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:widths: 5 5 5 85
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* - Name
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- Type
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- Mode
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- Description
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* - ``t106_mode``
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- u8
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- runtime
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- Used to configure CN10KA B0/CN10KB CPT to work as CN10KA A0/A1.
+1
Documentation/crypto/index.rst
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Documentation/crypto/index.rst
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drivers/crypto/marvell/octeontx2/otx2_cpt_common.h
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drivers/crypto/marvell/octeontx2/otx2_cpt_common.h
···
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}
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static inline bool cpt_feature_sgv2(struct pci_dev *pdev)
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{
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if (!is_dev_otx2(pdev) && !is_dev_cn10ka_ax(pdev))
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return true;
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return false;
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}
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int otx2_cpt_send_ready_msg(struct otx2_mbox *mbox, struct pci_dev *pdev);
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int otx2_cpt_send_mbox_msg(struct otx2_mbox *mbox, struct pci_dev *pdev);
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+42
-2
drivers/crypto/marvell/octeontx2/otx2_cpt_devlink.c
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-2
drivers/crypto/marvell/octeontx2/otx2_cpt_devlink.c
···
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static int otx2_cpt_dl_uc_info(struct devlink *dl, u32 id,
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struct devlink_param_gset_ctx *ctx)
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{
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ctx->val.vstr[0] = '\0';
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return 0;
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}
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static int otx2_cpt_dl_t106_mode_get(struct devlink *dl, u32 id,
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struct devlink_param_gset_ctx *ctx)
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{
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struct otx2_cpt_devlink *cpt_dl = devlink_priv(dl);
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struct otx2_cptpf_dev *cptpf = cpt_dl->cptpf;
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struct pci_dev *pdev = cptpf->pdev;
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u64 reg_val = 0;
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otx2_cpt_print_uc_dbg_info(cptpf);
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otx2_cpt_read_af_reg(&cptpf->afpf_mbox, pdev, CPT_AF_CTL, ®_val,
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BLKADDR_CPT0);
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ctx->val.vu8 = (reg_val >> 18) & 0x1;
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return 0;
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}
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static int otx2_cpt_dl_t106_mode_set(struct devlink *dl, u32 id,
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struct devlink_param_gset_ctx *ctx)
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{
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struct otx2_cpt_devlink *cpt_dl = devlink_priv(dl);
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struct otx2_cptpf_dev *cptpf = cpt_dl->cptpf;
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struct pci_dev *pdev = cptpf->pdev;
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u64 reg_val = 0;
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if (cptpf->enabled_vfs != 0 || cptpf->eng_grps.is_grps_created)
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return -EPERM;
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if (cpt_feature_sgv2(pdev)) {
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otx2_cpt_read_af_reg(&cptpf->afpf_mbox, pdev, CPT_AF_CTL,
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®_val, BLKADDR_CPT0);
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reg_val &= ~(0x1ULL << 18);
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reg_val |= ((u64)ctx->val.vu8 & 0x1) << 18;
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return otx2_cpt_write_af_reg(&cptpf->afpf_mbox, pdev,
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CPT_AF_CTL, reg_val, BLKADDR_CPT0);
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}
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return 0;
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}
···
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OTX2_CPT_DEVLINK_PARAM_ID_BASE = DEVLINK_PARAM_GENERIC_ID_MAX,
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OTX2_CPT_DEVLINK_PARAM_ID_EGRP_CREATE,
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OTX2_CPT_DEVLINK_PARAM_ID_EGRP_DELETE,
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OTX2_CPT_DEVLINK_PARAM_ID_T106_MODE,
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};
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static const struct devlink_param otx2_cpt_dl_params[] = {
···
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"egrp_delete", DEVLINK_PARAM_TYPE_STRING,
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BIT(DEVLINK_PARAM_CMODE_RUNTIME),
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otx2_cpt_dl_uc_info, otx2_cpt_dl_egrp_delete,
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NULL),
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DEVLINK_PARAM_DRIVER(OTX2_CPT_DEVLINK_PARAM_ID_T106_MODE,
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"t106_mode", DEVLINK_PARAM_TYPE_U8,
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BIT(DEVLINK_PARAM_CMODE_RUNTIME),
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otx2_cpt_dl_t106_mode_get, otx2_cpt_dl_t106_mode_set,
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NULL),
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};
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···
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devlink_free(dl);
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return ret;
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}
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-
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devlink_register(dl);
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return 0;
+2
-2
drivers/crypto/marvell/octeontx2/otx2_cptpf_main.c
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-2
drivers/crypto/marvell/octeontx2/otx2_cptpf_main.c
···
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}
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otx2_cpt_read_af_reg(&cptpf->afpf_mbox, pdev, CPT_AF_CTL, ®_val,
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BLKADDR_CPT0);
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if ((is_dev_cn10ka_b0(pdev) && (reg_val & BIT_ULL(18))) ||
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if ((cpt_feature_sgv2(pdev) && (reg_val & BIT_ULL(18))) ||
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is_dev_cn10ka_ax(pdev))
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eng_grps->rid = CPT_UC_RID_CN10K_A;
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else if (is_dev_cn10kb(pdev) || is_dev_cn10ka_b0(pdev))
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else if (cpt_feature_sgv2(pdev))
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eng_grps->rid = CPT_UC_RID_CN10K_B;
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}
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