Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
crypto: octeontx2 - add SGv2 support for CN10KB or CN10KA B0
Scatter Gather input format for CPT has changed on CN10KB/CN10KA B0 HW
to make it compatible with NIX Scatter Gather format to support SG mode
for inline IPsec. This patch modifies the code to make the driver works
for the same. This patch also enables CPT firmware load for these chips.
Signed-off-by: Srujana Challa <schalla@marvell.com>
Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
authored by
Srujana Challa
and committed by
Herbert Xu
92508e7f
711b2e2d
+436
-175
+12
-4
drivers/crypto/marvell/octeontx2/cn10k_cpt.c
+12
-4
drivers/crypto/marvell/octeontx2/cn10k_cpt.c
···
14
14
.send_cmd = otx2_cpt_send_cmd,
15
15
.cpt_get_compcode = otx2_cpt_get_compcode,
16
16
.cpt_get_uc_compcode = otx2_cpt_get_uc_compcode,
17
+
.cpt_sg_info_create = otx2_sg_info_create,
17
18
};
18
19
19
20
static struct cpt_hw_ops cn10k_hw_ops = {
20
21
.send_cmd = cn10k_cpt_send_cmd,
21
22
.cpt_get_compcode = cn10k_cpt_get_compcode,
22
23
.cpt_get_uc_compcode = cn10k_cpt_get_uc_compcode,
24
+
.cpt_sg_info_create = otx2_sg_info_create,
23
25
};
24
26
25
27
static void cn10k_cpt_send_cmd(union otx2_cpt_inst_s *cptinst, u32 insts_num,
···
80
78
struct pci_dev *pdev = cptvf->pdev;
81
79
resource_size_t offset, size;
82
80
83
-
if (!test_bit(CN10K_LMTST, &cptvf->cap_flag)) {
84
-
cptvf->lfs.ops = &otx2_hw_ops;
81
+
if (!test_bit(CN10K_LMTST, &cptvf->cap_flag))
85
82
return 0;
86
-
}
87
83
88
-
cptvf->lfs.ops = &cn10k_hw_ops;
89
84
offset = pci_resource_start(pdev, PCI_MBOX_BAR_NUM);
90
85
size = pci_resource_len(pdev, PCI_MBOX_BAR_NUM);
91
86
/* Map VF LMILINE region */
···
95
96
return 0;
96
97
}
97
98
EXPORT_SYMBOL_NS_GPL(cn10k_cptvf_lmtst_init, CRYPTO_DEV_OCTEONTX2_CPT);
99
+
100
+
void cptvf_hw_ops_get(struct otx2_cptvf_dev *cptvf)
101
+
{
102
+
if (test_bit(CN10K_LMTST, &cptvf->cap_flag))
103
+
cptvf->lfs.ops = &cn10k_hw_ops;
104
+
else
105
+
cptvf->lfs.ops = &otx2_hw_ops;
106
+
}
107
+
EXPORT_SYMBOL_NS_GPL(cptvf_hw_ops_get, CRYPTO_DEV_OCTEONTX2_CPT);
+1
drivers/crypto/marvell/octeontx2/cn10k_cpt.h
+1
drivers/crypto/marvell/octeontx2/cn10k_cpt.h
+33
-1
drivers/crypto/marvell/octeontx2/otx2_cpt_common.h
+33
-1
drivers/crypto/marvell/octeontx2/otx2_cpt_common.h
···
102
102
u64 kasumi:1;
103
103
u64 des:1;
104
104
u64 crc:1;
105
-
u64 reserved_14_63:50;
105
+
u64 mmul:1;
106
+
u64 reserved_15_33:19;
107
+
u64 pdcp_chain:1;
108
+
u64 reserved_35_63:29;
106
109
};
107
110
};
108
111
···
143
140
{
144
141
if (pdev->device == OTX2_CPT_PCI_PF_DEVICE_ID ||
145
142
pdev->device == OTX2_CPT_PCI_VF_DEVICE_ID)
143
+
return true;
144
+
145
+
return false;
146
+
}
147
+
148
+
static inline bool is_dev_cn10ka(struct pci_dev *pdev)
149
+
{
150
+
return pdev->subsystem_device == CPT_PCI_SUBSYS_DEVID_CN10K_A;
151
+
}
152
+
153
+
static inline bool is_dev_cn10ka_ax(struct pci_dev *pdev)
154
+
{
155
+
if (pdev->subsystem_device == CPT_PCI_SUBSYS_DEVID_CN10K_A &&
156
+
((pdev->revision & 0xFF) == 4 || (pdev->revision & 0xFF) == 0x50 ||
157
+
(pdev->revision & 0xff) == 0x51))
158
+
return true;
159
+
160
+
return false;
161
+
}
162
+
163
+
static inline bool is_dev_cn10kb(struct pci_dev *pdev)
164
+
{
165
+
return pdev->subsystem_device == CPT_PCI_SUBSYS_DEVID_CN10K_B;
166
+
}
167
+
168
+
static inline bool is_dev_cn10ka_b0(struct pci_dev *pdev)
169
+
{
170
+
if (pdev->subsystem_device == CPT_PCI_SUBSYS_DEVID_CN10K_A &&
171
+
(pdev->revision & 0xFF) == 0x54)
146
172
return true;
147
173
148
174
return false;
+3
drivers/crypto/marvell/octeontx2/otx2_cpt_hw_types.h
+3
drivers/crypto/marvell/octeontx2/otx2_cpt_hw_types.h
···
13
13
#define CN10K_CPT_PCI_PF_DEVICE_ID 0xA0F2
14
14
#define CN10K_CPT_PCI_VF_DEVICE_ID 0xA0F3
15
15
16
+
#define CPT_PCI_SUBSYS_DEVID_CN10K_A 0xB900
17
+
#define CPT_PCI_SUBSYS_DEVID_CN10K_B 0xBD00
18
+
16
19
/* Mailbox interrupts offset */
17
20
#define OTX2_CPT_PF_MBOX_INT 6
18
21
#define OTX2_CPT_PF_INT_VEC_E_MBOXX(x, a) ((x) + (a))
+296
drivers/crypto/marvell/octeontx2/otx2_cpt_reqmgr.h
+296
drivers/crypto/marvell/octeontx2/otx2_cpt_reqmgr.h
···
27
27
28
28
#define OTX2_CPT_MAX_REQ_SIZE 65535
29
29
30
+
#define SG_COMPS_MAX 4
31
+
#define SGV2_COMPS_MAX 3
32
+
33
+
#define SG_COMP_3 3
34
+
#define SG_COMP_2 2
35
+
#define SG_COMP_1 1
36
+
30
37
union otx2_cpt_opcode {
31
38
u16 flags;
32
39
struct {
···
150
143
unsigned long time_in;
151
144
u32 dlen;
152
145
u32 dma_len;
146
+
u64 gthr_sz;
147
+
u64 sctr_sz;
153
148
u8 extra_time;
154
149
};
155
150
···
164
155
__be64 ptr1;
165
156
__be64 ptr2;
166
157
__be64 ptr3;
158
+
};
159
+
160
+
struct cn10kb_cpt_sglist_component {
161
+
u16 len0;
162
+
u16 len1;
163
+
u16 len2;
164
+
u16 valid_segs;
165
+
u64 ptr0;
166
+
u64 ptr1;
167
+
u64 ptr2;
167
168
};
168
169
169
170
static inline void otx2_cpt_info_destroy(struct pci_dev *pdev,
···
205
186
}
206
187
}
207
188
kfree(info);
189
+
}
190
+
191
+
static inline int setup_sgio_components(struct pci_dev *pdev,
192
+
struct otx2_cpt_buf_ptr *list,
193
+
int buf_count, u8 *buffer)
194
+
{
195
+
struct otx2_cpt_sglist_component *sg_ptr;
196
+
int components;
197
+
int i, j;
198
+
199
+
if (unlikely(!list)) {
200
+
dev_err(&pdev->dev, "Input list pointer is NULL\n");
201
+
return -EINVAL;
202
+
}
203
+
204
+
for (i = 0; i < buf_count; i++) {
205
+
if (unlikely(!list[i].vptr))
206
+
continue;
207
+
list[i].dma_addr = dma_map_single(&pdev->dev, list[i].vptr,
208
+
list[i].size,
209
+
DMA_BIDIRECTIONAL);
210
+
if (unlikely(dma_mapping_error(&pdev->dev, list[i].dma_addr))) {
211
+
dev_err(&pdev->dev, "Dma mapping failed\n");
212
+
goto sg_cleanup;
213
+
}
214
+
}
215
+
components = buf_count / SG_COMPS_MAX;
216
+
sg_ptr = (struct otx2_cpt_sglist_component *)buffer;
217
+
for (i = 0; i < components; i++) {
218
+
sg_ptr->len0 = cpu_to_be16(list[i * SG_COMPS_MAX + 0].size);
219
+
sg_ptr->len1 = cpu_to_be16(list[i * SG_COMPS_MAX + 1].size);
220
+
sg_ptr->len2 = cpu_to_be16(list[i * SG_COMPS_MAX + 2].size);
221
+
sg_ptr->len3 = cpu_to_be16(list[i * SG_COMPS_MAX + 3].size);
222
+
sg_ptr->ptr0 = cpu_to_be64(list[i * SG_COMPS_MAX + 0].dma_addr);
223
+
sg_ptr->ptr1 = cpu_to_be64(list[i * SG_COMPS_MAX + 1].dma_addr);
224
+
sg_ptr->ptr2 = cpu_to_be64(list[i * SG_COMPS_MAX + 2].dma_addr);
225
+
sg_ptr->ptr3 = cpu_to_be64(list[i * SG_COMPS_MAX + 3].dma_addr);
226
+
sg_ptr++;
227
+
}
228
+
components = buf_count % SG_COMPS_MAX;
229
+
230
+
switch (components) {
231
+
case SG_COMP_3:
232
+
sg_ptr->len2 = cpu_to_be16(list[i * SG_COMPS_MAX + 2].size);
233
+
sg_ptr->ptr2 = cpu_to_be64(list[i * SG_COMPS_MAX + 2].dma_addr);
234
+
fallthrough;
235
+
case SG_COMP_2:
236
+
sg_ptr->len1 = cpu_to_be16(list[i * SG_COMPS_MAX + 1].size);
237
+
sg_ptr->ptr1 = cpu_to_be64(list[i * SG_COMPS_MAX + 1].dma_addr);
238
+
fallthrough;
239
+
case SG_COMP_1:
240
+
sg_ptr->len0 = cpu_to_be16(list[i * SG_COMPS_MAX + 0].size);
241
+
sg_ptr->ptr0 = cpu_to_be64(list[i * SG_COMPS_MAX + 0].dma_addr);
242
+
break;
243
+
default:
244
+
break;
245
+
}
246
+
return 0;
247
+
248
+
sg_cleanup:
249
+
for (j = 0; j < i; j++) {
250
+
if (list[j].dma_addr) {
251
+
dma_unmap_single(&pdev->dev, list[j].dma_addr,
252
+
list[j].size, DMA_BIDIRECTIONAL);
253
+
}
254
+
255
+
list[j].dma_addr = 0;
256
+
}
257
+
return -EIO;
258
+
}
259
+
260
+
static inline int sgv2io_components_setup(struct pci_dev *pdev,
261
+
struct otx2_cpt_buf_ptr *list,
262
+
int buf_count, u8 *buffer)
263
+
{
264
+
struct cn10kb_cpt_sglist_component *sg_ptr;
265
+
int components;
266
+
int i, j;
267
+
268
+
if (unlikely(!list)) {
269
+
dev_err(&pdev->dev, "Input list pointer is NULL\n");
270
+
return -EFAULT;
271
+
}
272
+
273
+
for (i = 0; i < buf_count; i++) {
274
+
if (unlikely(!list[i].vptr))
275
+
continue;
276
+
list[i].dma_addr = dma_map_single(&pdev->dev, list[i].vptr,
277
+
list[i].size,
278
+
DMA_BIDIRECTIONAL);
279
+
if (unlikely(dma_mapping_error(&pdev->dev, list[i].dma_addr))) {
280
+
dev_err(&pdev->dev, "Dma mapping failed\n");
281
+
goto sg_cleanup;
282
+
}
283
+
}
284
+
components = buf_count / SGV2_COMPS_MAX;
285
+
sg_ptr = (struct cn10kb_cpt_sglist_component *)buffer;
286
+
for (i = 0; i < components; i++) {
287
+
sg_ptr->len0 = list[i * SGV2_COMPS_MAX + 0].size;
288
+
sg_ptr->len1 = list[i * SGV2_COMPS_MAX + 1].size;
289
+
sg_ptr->len2 = list[i * SGV2_COMPS_MAX + 2].size;
290
+
sg_ptr->ptr0 = list[i * SGV2_COMPS_MAX + 0].dma_addr;
291
+
sg_ptr->ptr1 = list[i * SGV2_COMPS_MAX + 1].dma_addr;
292
+
sg_ptr->ptr2 = list[i * SGV2_COMPS_MAX + 2].dma_addr;
293
+
sg_ptr->valid_segs = SGV2_COMPS_MAX;
294
+
sg_ptr++;
295
+
}
296
+
components = buf_count % SGV2_COMPS_MAX;
297
+
298
+
sg_ptr->valid_segs = components;
299
+
switch (components) {
300
+
case SG_COMP_2:
301
+
sg_ptr->len1 = list[i * SGV2_COMPS_MAX + 1].size;
302
+
sg_ptr->ptr1 = list[i * SGV2_COMPS_MAX + 1].dma_addr;
303
+
fallthrough;
304
+
case SG_COMP_1:
305
+
sg_ptr->len0 = list[i * SGV2_COMPS_MAX + 0].size;
306
+
sg_ptr->ptr0 = list[i * SGV2_COMPS_MAX + 0].dma_addr;
307
+
break;
308
+
default:
309
+
break;
310
+
}
311
+
return 0;
312
+
313
+
sg_cleanup:
314
+
for (j = 0; j < i; j++) {
315
+
if (list[j].dma_addr) {
316
+
dma_unmap_single(&pdev->dev, list[j].dma_addr,
317
+
list[j].size, DMA_BIDIRECTIONAL);
318
+
}
319
+
320
+
list[j].dma_addr = 0;
321
+
}
322
+
return -EIO;
323
+
}
324
+
325
+
static inline struct otx2_cpt_inst_info *
326
+
cn10k_sgv2_info_create(struct pci_dev *pdev, struct otx2_cpt_req_info *req,
327
+
gfp_t gfp)
328
+
{
329
+
u32 dlen = 0, g_len, sg_len, info_len;
330
+
int align = OTX2_CPT_DMA_MINALIGN;
331
+
struct otx2_cpt_inst_info *info;
332
+
u16 g_sz_bytes, s_sz_bytes;
333
+
u32 total_mem_len;
334
+
int i;
335
+
336
+
g_sz_bytes = ((req->in_cnt + 2) / 3) *
337
+
sizeof(struct cn10kb_cpt_sglist_component);
338
+
s_sz_bytes = ((req->out_cnt + 2) / 3) *
339
+
sizeof(struct cn10kb_cpt_sglist_component);
340
+
341
+
g_len = ALIGN(g_sz_bytes, align);
342
+
sg_len = ALIGN(g_len + s_sz_bytes, align);
343
+
info_len = ALIGN(sizeof(*info), align);
344
+
total_mem_len = sg_len + info_len + sizeof(union otx2_cpt_res_s);
345
+
346
+
info = kzalloc(total_mem_len, gfp);
347
+
if (unlikely(!info))
348
+
return NULL;
349
+
350
+
for (i = 0; i < req->in_cnt; i++)
351
+
dlen += req->in[i].size;
352
+
353
+
info->dlen = dlen;
354
+
info->in_buffer = (u8 *)info + info_len;
355
+
info->gthr_sz = req->in_cnt;
356
+
info->sctr_sz = req->out_cnt;
357
+
358
+
/* Setup gather (input) components */
359
+
if (sgv2io_components_setup(pdev, req->in, req->in_cnt,
360
+
info->in_buffer)) {
361
+
dev_err(&pdev->dev, "Failed to setup gather list\n");
362
+
goto destroy_info;
363
+
}
364
+
365
+
if (sgv2io_components_setup(pdev, req->out, req->out_cnt,
366
+
&info->in_buffer[g_len])) {
367
+
dev_err(&pdev->dev, "Failed to setup scatter list\n");
368
+
goto destroy_info;
369
+
}
370
+
371
+
info->dma_len = total_mem_len - info_len;
372
+
info->dptr_baddr = dma_map_single(&pdev->dev, info->in_buffer,
373
+
info->dma_len, DMA_BIDIRECTIONAL);
374
+
if (unlikely(dma_mapping_error(&pdev->dev, info->dptr_baddr))) {
375
+
dev_err(&pdev->dev, "DMA Mapping failed for cpt req\n");
376
+
goto destroy_info;
377
+
}
378
+
info->rptr_baddr = info->dptr_baddr + g_len;
379
+
/*
380
+
* Get buffer for union otx2_cpt_res_s response
381
+
* structure and its physical address
382
+
*/
383
+
info->completion_addr = info->in_buffer + sg_len;
384
+
info->comp_baddr = info->dptr_baddr + sg_len;
385
+
386
+
return info;
387
+
388
+
destroy_info:
389
+
otx2_cpt_info_destroy(pdev, info);
390
+
return NULL;
391
+
}
392
+
393
+
/* SG list header size in bytes */
394
+
#define SG_LIST_HDR_SIZE 8
395
+
static inline struct otx2_cpt_inst_info *
396
+
otx2_sg_info_create(struct pci_dev *pdev, struct otx2_cpt_req_info *req,
397
+
gfp_t gfp)
398
+
{
399
+
int align = OTX2_CPT_DMA_MINALIGN;
400
+
struct otx2_cpt_inst_info *info;
401
+
u32 dlen, align_dlen, info_len;
402
+
u16 g_sz_bytes, s_sz_bytes;
403
+
u32 total_mem_len;
404
+
405
+
if (unlikely(req->in_cnt > OTX2_CPT_MAX_SG_IN_CNT ||
406
+
req->out_cnt > OTX2_CPT_MAX_SG_OUT_CNT)) {
407
+
dev_err(&pdev->dev, "Error too many sg components\n");
408
+
return NULL;
409
+
}
410
+
411
+
g_sz_bytes = ((req->in_cnt + 3) / 4) *
412
+
sizeof(struct otx2_cpt_sglist_component);
413
+
s_sz_bytes = ((req->out_cnt + 3) / 4) *
414
+
sizeof(struct otx2_cpt_sglist_component);
415
+
416
+
dlen = g_sz_bytes + s_sz_bytes + SG_LIST_HDR_SIZE;
417
+
align_dlen = ALIGN(dlen, align);
418
+
info_len = ALIGN(sizeof(*info), align);
419
+
total_mem_len = align_dlen + info_len + sizeof(union otx2_cpt_res_s);
420
+
421
+
info = kzalloc(total_mem_len, gfp);
422
+
if (unlikely(!info))
423
+
return NULL;
424
+
425
+
info->dlen = dlen;
426
+
info->in_buffer = (u8 *)info + info_len;
427
+
428
+
((u16 *)info->in_buffer)[0] = req->out_cnt;
429
+
((u16 *)info->in_buffer)[1] = req->in_cnt;
430
+
((u16 *)info->in_buffer)[2] = 0;
431
+
((u16 *)info->in_buffer)[3] = 0;
432
+
cpu_to_be64s((u64 *)info->in_buffer);
433
+
434
+
/* Setup gather (input) components */
435
+
if (setup_sgio_components(pdev, req->in, req->in_cnt,
436
+
&info->in_buffer[8])) {
437
+
dev_err(&pdev->dev, "Failed to setup gather list\n");
438
+
goto destroy_info;
439
+
}
440
+
441
+
if (setup_sgio_components(pdev, req->out, req->out_cnt,
442
+
&info->in_buffer[8 + g_sz_bytes])) {
443
+
dev_err(&pdev->dev, "Failed to setup scatter list\n");
444
+
goto destroy_info;
445
+
}
446
+
447
+
info->dma_len = total_mem_len - info_len;
448
+
info->dptr_baddr = dma_map_single(&pdev->dev, info->in_buffer,
449
+
info->dma_len, DMA_BIDIRECTIONAL);
450
+
if (unlikely(dma_mapping_error(&pdev->dev, info->dptr_baddr))) {
451
+
dev_err(&pdev->dev, "DMA Mapping failed for cpt req\n");
452
+
goto destroy_info;
453
+
}
454
+
/*
455
+
* Get buffer for union otx2_cpt_res_s response
456
+
* structure and its physical address
457
+
*/
458
+
info->completion_addr = info->in_buffer + align_dlen;
459
+
info->comp_baddr = info->dptr_baddr + align_dlen;
460
+
461
+
return info;
462
+
463
+
destroy_info:
464
+
otx2_cpt_info_destroy(pdev, info);
465
+
return NULL;
208
466
}
209
467
210
468
struct otx2_cptlf_wqe;
+3
drivers/crypto/marvell/octeontx2/otx2_cptlf.h
+3
drivers/crypto/marvell/octeontx2/otx2_cptlf.h
···
99
99
struct otx2_cptlf_info *lf);
100
100
u8 (*cpt_get_compcode)(union otx2_cpt_res_s *result);
101
101
u8 (*cpt_get_uc_compcode)(union otx2_cpt_res_s *result);
102
+
struct otx2_cpt_inst_info *
103
+
(*cpt_sg_info_create)(struct pci_dev *pdev, struct otx2_cpt_req_info *req,
104
+
gfp_t gfp);
102
105
};
103
106
104
107
struct otx2_cptlfs_info {
+21
drivers/crypto/marvell/octeontx2/otx2_cptpf_main.c
+21
drivers/crypto/marvell/octeontx2/otx2_cptpf_main.c
···
14
14
#define OTX2_CPT_DRV_STRING "Marvell RVU CPT Physical Function Driver"
15
15
16
16
#define CPT_UC_RID_CN9K_B0 1
17
+
#define CPT_UC_RID_CN10K_A 4
18
+
#define CPT_UC_RID_CN10K_B 5
17
19
18
20
static void cptpf_enable_vfpf_mbox_intr(struct otx2_cptpf_dev *cptpf,
19
21
int num_vfs)
···
589
587
return 0;
590
588
}
591
589
590
+
static void cptpf_get_rid(struct pci_dev *pdev, struct otx2_cptpf_dev *cptpf)
591
+
{
592
+
struct otx2_cpt_eng_grps *eng_grps = &cptpf->eng_grps;
593
+
u64 reg_val = 0x0;
594
+
595
+
if (is_dev_otx2(pdev)) {
596
+
eng_grps->rid = pdev->revision;
597
+
return;
598
+
}
599
+
otx2_cpt_read_af_reg(&cptpf->afpf_mbox, pdev, CPT_AF_CTL, ®_val,
600
+
BLKADDR_CPT0);
601
+
if ((is_dev_cn10ka_b0(pdev) && (reg_val & BIT_ULL(18))) ||
602
+
is_dev_cn10ka_ax(pdev))
603
+
eng_grps->rid = CPT_UC_RID_CN10K_A;
604
+
else if (is_dev_cn10kb(pdev) || is_dev_cn10ka_b0(pdev))
605
+
eng_grps->rid = CPT_UC_RID_CN10K_B;
606
+
}
607
+
592
608
static void cptpf_check_block_implemented(struct otx2_cptpf_dev *cptpf)
593
609
{
594
610
u64 cfg;
···
678
658
if (ret)
679
659
goto destroy_flr;
680
660
661
+
cptpf_get_rid(pdev, cptpf);
681
662
/* Get CPT HW capabilities using LOAD_FVC operation. */
682
663
ret = otx2_cpt_discover_eng_capabilities(cptpf);
683
664
if (ret)
+1
-1
drivers/crypto/marvell/octeontx2/otx2_cptpf_mbox.c
+1
-1
drivers/crypto/marvell/octeontx2/otx2_cptpf_mbox.c
···
78
78
rsp->hdr.sig = OTX2_MBOX_RSP_SIG;
79
79
rsp->hdr.pcifunc = req->pcifunc;
80
80
rsp->cpt_pf_drv_version = OTX2_CPT_PF_DRV_VERSION;
81
-
rsp->cpt_revision = cptpf->pdev->revision;
81
+
rsp->cpt_revision = cptpf->eng_grps.rid;
82
82
memcpy(&rsp->eng_caps, &cptpf->eng_caps, sizeof(rsp->eng_caps));
83
83
84
84
return 0;
+18
-15
drivers/crypto/marvell/octeontx2/otx2_cptpf_ucode.c
+18
-15
drivers/crypto/marvell/octeontx2/otx2_cptpf_ucode.c
···
117
117
118
118
static int get_ucode_type(struct device *dev,
119
119
struct otx2_cpt_ucode_hdr *ucode_hdr,
120
-
int *ucode_type)
120
+
int *ucode_type, u16 rid)
121
121
{
122
-
struct otx2_cptpf_dev *cptpf = dev_get_drvdata(dev);
123
122
char ver_str_prefix[OTX2_CPT_UCODE_VER_STR_SZ];
124
123
char tmp_ver_str[OTX2_CPT_UCODE_VER_STR_SZ];
125
-
struct pci_dev *pdev = cptpf->pdev;
126
124
int i, val = 0;
127
125
u8 nn;
128
126
···
128
130
for (i = 0; i < strlen(tmp_ver_str); i++)
129
131
tmp_ver_str[i] = tolower(tmp_ver_str[i]);
130
132
131
-
sprintf(ver_str_prefix, "ocpt-%02d", pdev->revision);
133
+
sprintf(ver_str_prefix, "ocpt-%02d", rid);
132
134
if (!strnstr(tmp_ver_str, ver_str_prefix, OTX2_CPT_UCODE_VER_STR_SZ))
133
135
return -EINVAL;
134
136
···
357
359
}
358
360
359
361
static int load_fw(struct device *dev, struct fw_info_t *fw_info,
360
-
char *filename)
362
+
char *filename, u16 rid)
361
363
{
362
364
struct otx2_cpt_ucode_hdr *ucode_hdr;
363
365
struct otx2_cpt_uc_info_t *uc_info;
···
373
375
goto free_uc_info;
374
376
375
377
ucode_hdr = (struct otx2_cpt_ucode_hdr *)uc_info->fw->data;
376
-
ret = get_ucode_type(dev, ucode_hdr, &ucode_type);
378
+
ret = get_ucode_type(dev, ucode_hdr, &ucode_type, rid);
377
379
if (ret)
378
380
goto release_fw;
379
381
···
387
389
set_ucode_filename(&uc_info->ucode, filename);
388
390
memcpy(uc_info->ucode.ver_str, ucode_hdr->ver_str,
389
391
OTX2_CPT_UCODE_VER_STR_SZ);
392
+
uc_info->ucode.ver_str[OTX2_CPT_UCODE_VER_STR_SZ] = 0;
390
393
uc_info->ucode.ver_num = ucode_hdr->ver_num;
391
394
uc_info->ucode.type = ucode_type;
392
395
uc_info->ucode.size = ucode_size;
···
447
448
}
448
449
}
449
450
450
-
static int cpt_ucode_load_fw(struct pci_dev *pdev, struct fw_info_t *fw_info)
451
+
static int cpt_ucode_load_fw(struct pci_dev *pdev, struct fw_info_t *fw_info,
452
+
u16 rid)
451
453
{
452
454
char filename[OTX2_CPT_NAME_LENGTH];
453
455
char eng_type[8] = {0};
···
462
462
eng_type[i] = tolower(eng_type[i]);
463
463
464
464
snprintf(filename, sizeof(filename), "mrvl/cpt%02d/%s.out",
465
-
pdev->revision, eng_type);
465
+
rid, eng_type);
466
466
/* Request firmware for each engine type */
467
-
ret = load_fw(&pdev->dev, fw_info, filename);
467
+
ret = load_fw(&pdev->dev, fw_info, filename, rid);
468
468
if (ret)
469
469
goto release_fw;
470
470
}
···
1155
1155
if (eng_grps->is_grps_created)
1156
1156
goto unlock;
1157
1157
1158
-
ret = cpt_ucode_load_fw(pdev, &fw_info);
1158
+
ret = cpt_ucode_load_fw(pdev, &fw_info, eng_grps->rid);
1159
1159
if (ret)
1160
1160
goto unlock;
1161
1161
···
1230
1230
*/
1231
1231
rnm_to_cpt_errata_fixup(&pdev->dev);
1232
1232
1233
+
otx2_cpt_read_af_reg(&cptpf->afpf_mbox, pdev, CPT_AF_CTL, ®_val,
1234
+
BLKADDR_CPT0);
1233
1235
/*
1234
1236
* Configure engine group mask to allow context prefetching
1235
1237
* for the groups and enable random number request, to enable
1236
1238
* CPT to request random numbers from RNM.
1237
1239
*/
1240
+
reg_val |= OTX2_CPT_ALL_ENG_GRPS_MASK << 3 | BIT_ULL(16);
1238
1241
otx2_cpt_write_af_reg(&cptpf->afpf_mbox, pdev, CPT_AF_CTL,
1239
-
OTX2_CPT_ALL_ENG_GRPS_MASK << 3 | BIT_ULL(16),
1240
-
BLKADDR_CPT0);
1242
+
reg_val, BLKADDR_CPT0);
1241
1243
/*
1242
1244
* Set interval to periodically flush dirty data for the next
1243
1245
* CTX cache entry. Set the interval count to maximum supported
···
1414
1412
int ret;
1415
1413
1416
1414
mutex_lock(&eng_grps->lock);
1417
-
ret = cpt_ucode_load_fw(pdev, &fw_info);
1415
+
ret = cpt_ucode_load_fw(pdev, &fw_info, eng_grps->rid);
1418
1416
if (ret) {
1419
1417
mutex_unlock(&eng_grps->lock);
1420
1418
return ret;
···
1688
1686
goto err_unlock;
1689
1687
}
1690
1688
INIT_LIST_HEAD(&fw_info.ucodes);
1691
-
ret = load_fw(dev, &fw_info, ucode_filename[0]);
1689
+
1690
+
ret = load_fw(dev, &fw_info, ucode_filename[0], eng_grps->rid);
1692
1691
if (ret) {
1693
1692
dev_err(dev, "Unable to load firmware %s\n", ucode_filename[0]);
1694
1693
goto err_unlock;
1695
1694
}
1696
1695
if (ucode_idx > 1) {
1697
-
ret = load_fw(dev, &fw_info, ucode_filename[1]);
1696
+
ret = load_fw(dev, &fw_info, ucode_filename[1], eng_grps->rid);
1698
1697
if (ret) {
1699
1698
dev_err(dev, "Unable to load firmware %s\n",
1700
1699
ucode_filename[1]);
+2
-1
drivers/crypto/marvell/octeontx2/otx2_cptpf_ucode.h
+2
-1
drivers/crypto/marvell/octeontx2/otx2_cptpf_ucode.h
···
73
73
};
74
74
75
75
struct otx2_cpt_ucode {
76
-
u8 ver_str[OTX2_CPT_UCODE_VER_STR_SZ];/*
76
+
u8 ver_str[OTX2_CPT_UCODE_VER_STR_SZ + 1];/*
77
77
* ucode version in readable
78
78
* format
79
79
*/
···
150
150
int engs_num; /* total number of engines supported */
151
151
u8 eng_ref_cnt[OTX2_CPT_MAX_ENGINES];/* engines reference count */
152
152
bool is_grps_created; /* Is the engine groups are already created */
153
+
u16 rid;
153
154
};
154
155
struct otx2_cptpf_dev;
155
156
int otx2_cpt_init_eng_grps(struct pci_dev *pdev,
+2
drivers/crypto/marvell/octeontx2/otx2_cptvf.h
+2
drivers/crypto/marvell/octeontx2/otx2_cptvf.h
···
22
22
int blkaddr;
23
23
void *bbuf_base;
24
24
unsigned long cap_flag;
25
+
u64 eng_caps[OTX2_CPT_MAX_ENG_TYPES];
25
26
};
26
27
27
28
irqreturn_t otx2_cptvf_pfvf_mbox_intr(int irq, void *arg);
···
30
29
int otx2_cptvf_send_eng_grp_num_msg(struct otx2_cptvf_dev *cptvf, int eng_type);
31
30
int otx2_cptvf_send_kvf_limits_msg(struct otx2_cptvf_dev *cptvf);
32
31
int otx2_cpt_mbox_bbuf_init(struct otx2_cptvf_dev *cptvf, struct pci_dev *pdev);
32
+
int otx2_cptvf_send_caps_msg(struct otx2_cptvf_dev *cptvf);
33
33
34
34
#endif /* __OTX2_CPTVF_H */
+11
drivers/crypto/marvell/octeontx2/otx2_cptvf_main.c
+11
drivers/crypto/marvell/octeontx2/otx2_cptvf_main.c
···
382
382
goto destroy_pfvf_mbox;
383
383
384
384
cptvf->blkaddr = BLKADDR_CPT0;
385
+
386
+
cptvf_hw_ops_get(cptvf);
387
+
388
+
ret = otx2_cptvf_send_caps_msg(cptvf);
389
+
if (ret) {
390
+
dev_err(&pdev->dev, "Couldn't get CPT engine capabilities.\n");
391
+
goto unregister_interrupts;
392
+
}
393
+
if (cptvf->eng_caps[OTX2_CPT_SE_TYPES] & BIT_ULL(35))
394
+
cptvf->lfs.ops->cpt_sg_info_create = cn10k_sgv2_info_create;
395
+
385
396
/* Initialize CPT LFs */
386
397
ret = cptvf_lf_init(cptvf);
387
398
if (ret)
+26
drivers/crypto/marvell/octeontx2/otx2_cptvf_mbox.c
+26
drivers/crypto/marvell/octeontx2/otx2_cptvf_mbox.c
···
72
72
struct otx2_cptlfs_info *lfs = &cptvf->lfs;
73
73
struct otx2_cpt_kvf_limits_rsp *rsp_limits;
74
74
struct otx2_cpt_egrp_num_rsp *rsp_grp;
75
+
struct otx2_cpt_caps_rsp *eng_caps;
75
76
struct cpt_rd_wr_reg_msg *rsp_reg;
76
77
struct msix_offset_rsp *rsp_msix;
77
78
int i;
···
127
126
case MBOX_MSG_GET_KVF_LIMITS:
128
127
rsp_limits = (struct otx2_cpt_kvf_limits_rsp *) msg;
129
128
cptvf->lfs.kvf_limits = rsp_limits->kvf_limits;
129
+
break;
130
+
case MBOX_MSG_GET_CAPS:
131
+
eng_caps = (struct otx2_cpt_caps_rsp *)msg;
132
+
memcpy(cptvf->eng_caps, eng_caps->eng_caps,
133
+
sizeof(cptvf->eng_caps));
130
134
break;
131
135
default:
132
136
dev_err(&cptvf->pdev->dev, "Unsupported msg %d received.\n",
···
206
200
return -EFAULT;
207
201
}
208
202
req->id = MBOX_MSG_GET_KVF_LIMITS;
203
+
req->sig = OTX2_MBOX_REQ_SIG;
204
+
req->pcifunc = OTX2_CPT_RVU_PFFUNC(cptvf->vf_id, 0);
205
+
206
+
return otx2_cpt_send_mbox_msg(mbox, pdev);
207
+
}
208
+
209
+
int otx2_cptvf_send_caps_msg(struct otx2_cptvf_dev *cptvf)
210
+
{
211
+
struct otx2_mbox *mbox = &cptvf->pfvf_mbox;
212
+
struct pci_dev *pdev = cptvf->pdev;
213
+
struct mbox_msghdr *req;
214
+
215
+
req = (struct mbox_msghdr *)
216
+
otx2_mbox_alloc_msg_rsp(mbox, 0, sizeof(*req),
217
+
sizeof(struct otx2_cpt_caps_rsp));
218
+
if (!req) {
219
+
dev_err(&pdev->dev, "RVU MBOX failed to get message.\n");
220
+
return -EFAULT;
221
+
}
222
+
req->id = MBOX_MSG_GET_CAPS;
209
223
req->sig = OTX2_MBOX_REQ_SIG;
210
224
req->pcifunc = OTX2_CPT_RVU_PFFUNC(cptvf->vf_id, 0);
211
225
+7
-153
drivers/crypto/marvell/octeontx2/otx2_cptvf_reqmgr.c
+7
-153
drivers/crypto/marvell/octeontx2/otx2_cptvf_reqmgr.c
···
4
4
#include "otx2_cptvf.h"
5
5
#include "otx2_cpt_common.h"
6
6
7
-
/* SG list header size in bytes */
8
-
#define SG_LIST_HDR_SIZE 8
9
-
10
7
/* Default timeout when waiting for free pending entry in us */
11
8
#define CPT_PENTRY_TIMEOUT 1000
12
9
#define CPT_PENTRY_STEP 50
···
23
26
24
27
pr_debug("Gather list size %d\n", req->in_cnt);
25
28
for (i = 0; i < req->in_cnt; i++) {
26
-
pr_debug("Buffer %d size %d, vptr 0x%p, dmaptr 0x%p\n", i,
29
+
pr_debug("Buffer %d size %d, vptr 0x%p, dmaptr 0x%llx\n", i,
27
30
req->in[i].size, req->in[i].vptr,
28
-
(void *) req->in[i].dma_addr);
31
+
req->in[i].dma_addr);
29
32
pr_debug("Buffer hexdump (%d bytes)\n",
30
33
req->in[i].size);
31
34
print_hex_dump_debug("", DUMP_PREFIX_NONE, 16, 1,
···
33
36
}
34
37
pr_debug("Scatter list size %d\n", req->out_cnt);
35
38
for (i = 0; i < req->out_cnt; i++) {
36
-
pr_debug("Buffer %d size %d, vptr 0x%p, dmaptr 0x%p\n", i,
39
+
pr_debug("Buffer %d size %d, vptr 0x%p, dmaptr 0x%llx\n", i,
37
40
req->out[i].size, req->out[i].vptr,
38
-
(void *) req->out[i].dma_addr);
41
+
req->out[i].dma_addr);
39
42
pr_debug("Buffer hexdump (%d bytes)\n", req->out[i].size);
40
43
print_hex_dump_debug("", DUMP_PREFIX_NONE, 16, 1,
41
44
req->out[i].vptr, req->out[i].size, false);
···
81
84
pentry->busy = false;
82
85
}
83
86
84
-
static inline int setup_sgio_components(struct pci_dev *pdev,
85
-
struct otx2_cpt_buf_ptr *list,
86
-
int buf_count, u8 *buffer)
87
-
{
88
-
struct otx2_cpt_sglist_component *sg_ptr = NULL;
89
-
int ret = 0, i, j;
90
-
int components;
91
-
92
-
if (unlikely(!list)) {
93
-
dev_err(&pdev->dev, "Input list pointer is NULL\n");
94
-
return -EFAULT;
95
-
}
96
-
97
-
for (i = 0; i < buf_count; i++) {
98
-
if (unlikely(!list[i].vptr))
99
-
continue;
100
-
list[i].dma_addr = dma_map_single(&pdev->dev, list[i].vptr,
101
-
list[i].size,
102
-
DMA_BIDIRECTIONAL);
103
-
if (unlikely(dma_mapping_error(&pdev->dev, list[i].dma_addr))) {
104
-
dev_err(&pdev->dev, "Dma mapping failed\n");
105
-
ret = -EIO;
106
-
goto sg_cleanup;
107
-
}
108
-
}
109
-
components = buf_count / 4;
110
-
sg_ptr = (struct otx2_cpt_sglist_component *)buffer;
111
-
for (i = 0; i < components; i++) {
112
-
sg_ptr->len0 = cpu_to_be16(list[i * 4 + 0].size);
113
-
sg_ptr->len1 = cpu_to_be16(list[i * 4 + 1].size);
114
-
sg_ptr->len2 = cpu_to_be16(list[i * 4 + 2].size);
115
-
sg_ptr->len3 = cpu_to_be16(list[i * 4 + 3].size);
116
-
sg_ptr->ptr0 = cpu_to_be64(list[i * 4 + 0].dma_addr);
117
-
sg_ptr->ptr1 = cpu_to_be64(list[i * 4 + 1].dma_addr);
118
-
sg_ptr->ptr2 = cpu_to_be64(list[i * 4 + 2].dma_addr);
119
-
sg_ptr->ptr3 = cpu_to_be64(list[i * 4 + 3].dma_addr);
120
-
sg_ptr++;
121
-
}
122
-
components = buf_count % 4;
123
-
124
-
switch (components) {
125
-
case 3:
126
-
sg_ptr->len2 = cpu_to_be16(list[i * 4 + 2].size);
127
-
sg_ptr->ptr2 = cpu_to_be64(list[i * 4 + 2].dma_addr);
128
-
fallthrough;
129
-
case 2:
130
-
sg_ptr->len1 = cpu_to_be16(list[i * 4 + 1].size);
131
-
sg_ptr->ptr1 = cpu_to_be64(list[i * 4 + 1].dma_addr);
132
-
fallthrough;
133
-
case 1:
134
-
sg_ptr->len0 = cpu_to_be16(list[i * 4 + 0].size);
135
-
sg_ptr->ptr0 = cpu_to_be64(list[i * 4 + 0].dma_addr);
136
-
break;
137
-
default:
138
-
break;
139
-
}
140
-
return ret;
141
-
142
-
sg_cleanup:
143
-
for (j = 0; j < i; j++) {
144
-
if (list[j].dma_addr) {
145
-
dma_unmap_single(&pdev->dev, list[j].dma_addr,
146
-
list[j].size, DMA_BIDIRECTIONAL);
147
-
}
148
-
149
-
list[j].dma_addr = 0;
150
-
}
151
-
return ret;
152
-
}
153
-
154
-
static inline struct otx2_cpt_inst_info *info_create(struct pci_dev *pdev,
155
-
struct otx2_cpt_req_info *req,
156
-
gfp_t gfp)
157
-
{
158
-
int align = OTX2_CPT_DMA_MINALIGN;
159
-
struct otx2_cpt_inst_info *info;
160
-
u32 dlen, align_dlen, info_len;
161
-
u16 g_sz_bytes, s_sz_bytes;
162
-
u32 total_mem_len;
163
-
164
-
if (unlikely(req->in_cnt > OTX2_CPT_MAX_SG_IN_CNT ||
165
-
req->out_cnt > OTX2_CPT_MAX_SG_OUT_CNT)) {
166
-
dev_err(&pdev->dev, "Error too many sg components\n");
167
-
return NULL;
168
-
}
169
-
170
-
g_sz_bytes = ((req->in_cnt + 3) / 4) *
171
-
sizeof(struct otx2_cpt_sglist_component);
172
-
s_sz_bytes = ((req->out_cnt + 3) / 4) *
173
-
sizeof(struct otx2_cpt_sglist_component);
174
-
175
-
dlen = g_sz_bytes + s_sz_bytes + SG_LIST_HDR_SIZE;
176
-
align_dlen = ALIGN(dlen, align);
177
-
info_len = ALIGN(sizeof(*info), align);
178
-
total_mem_len = align_dlen + info_len + sizeof(union otx2_cpt_res_s);
179
-
180
-
info = kzalloc(total_mem_len, gfp);
181
-
if (unlikely(!info))
182
-
return NULL;
183
-
184
-
info->dlen = dlen;
185
-
info->in_buffer = (u8 *)info + info_len;
186
-
187
-
((u16 *)info->in_buffer)[0] = req->out_cnt;
188
-
((u16 *)info->in_buffer)[1] = req->in_cnt;
189
-
((u16 *)info->in_buffer)[2] = 0;
190
-
((u16 *)info->in_buffer)[3] = 0;
191
-
cpu_to_be64s((u64 *)info->in_buffer);
192
-
193
-
/* Setup gather (input) components */
194
-
if (setup_sgio_components(pdev, req->in, req->in_cnt,
195
-
&info->in_buffer[8])) {
196
-
dev_err(&pdev->dev, "Failed to setup gather list\n");
197
-
goto destroy_info;
198
-
}
199
-
200
-
if (setup_sgio_components(pdev, req->out, req->out_cnt,
201
-
&info->in_buffer[8 + g_sz_bytes])) {
202
-
dev_err(&pdev->dev, "Failed to setup scatter list\n");
203
-
goto destroy_info;
204
-
}
205
-
206
-
info->dma_len = total_mem_len - info_len;
207
-
info->dptr_baddr = dma_map_single(&pdev->dev, info->in_buffer,
208
-
info->dma_len, DMA_BIDIRECTIONAL);
209
-
if (unlikely(dma_mapping_error(&pdev->dev, info->dptr_baddr))) {
210
-
dev_err(&pdev->dev, "DMA Mapping failed for cpt req\n");
211
-
goto destroy_info;
212
-
}
213
-
/*
214
-
* Get buffer for union otx2_cpt_res_s response
215
-
* structure and its physical address
216
-
*/
217
-
info->completion_addr = info->in_buffer + align_dlen;
218
-
info->comp_baddr = info->dptr_baddr + align_dlen;
219
-
220
-
return info;
221
-
222
-
destroy_info:
223
-
otx2_cpt_info_destroy(pdev, info);
224
-
return NULL;
225
-
}
226
-
227
87
static int process_request(struct pci_dev *pdev, struct otx2_cpt_req_info *req,
228
88
struct otx2_cpt_pending_queue *pqueue,
229
89
struct otx2_cptlf_info *lf)
···
101
247
if (unlikely(!otx2_cptlf_started(lf->lfs)))
102
248
return -ENODEV;
103
249
104
-
info = info_create(pdev, req, gfp);
250
+
info = lf->lfs->ops->cpt_sg_info_create(pdev, req, gfp);
105
251
if (unlikely(!info)) {
106
252
dev_err(&pdev->dev, "Setting up cpt inst info failed");
107
253
return -ENOMEM;
···
157
303
158
304
/* 64-bit swap for microcode data reads, not needed for addresses*/
159
305
cpu_to_be64s(&iq_cmd.cmd.u);
160
-
iq_cmd.dptr = info->dptr_baddr;
161
-
iq_cmd.rptr = 0;
306
+
iq_cmd.dptr = info->dptr_baddr | info->gthr_sz << 60;
307
+
iq_cmd.rptr = info->rptr_baddr | info->sctr_sz << 60;
162
308
iq_cmd.cptr.u = 0;
163
309
iq_cmd.cptr.s.grp = ctrl->s.grp;
164
310