Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
drm/amdgpu: Add more checks to PSP mailbox
Instead of checking the response flag, use status mask also to check
against any unexpected failures like a device drop. Also, log error if
waiting on a psp response fails/times out.
Signed-off-by: Lijo Lazar <lijo.lazar@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
authored by
Lijo Lazar
and committed by
Alex Deucher
8345a71f
5562b669
+107
-61
+4
drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
+4
drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
+11
drivers/gpu/drm/amd/amdgpu/amdgpu_psp.h
+11
drivers/gpu/drm/amd/amdgpu/amdgpu_psp.h
···
51
51
#define C2PMSG_CMD_SPI_GET_ROM_IMAGE_ADDR_HI 0x10
52
52
#define C2PMSG_CMD_SPI_GET_FLASH_IMAGE 0x11
53
53
54
+
/* Command register bit 31 set to indicate readiness */
55
+
#define MBOX_TOS_READY_FLAG (GFX_FLAG_RESPONSE)
56
+
#define MBOX_TOS_READY_MASK (GFX_CMD_RESPONSE_MASK | GFX_CMD_STATUS_MASK)
57
+
58
+
/* Values to check for a successful GFX_CMD response wait. Check against
59
+
* both status bits and response state - helps to detect a command failure
60
+
* or other unexpected cases like a device drop reading all 0xFFs
61
+
*/
62
+
#define MBOX_TOS_RESP_FLAG (GFX_FLAG_RESPONSE)
63
+
#define MBOX_TOS_RESP_MASK (GFX_CMD_RESPONSE_MASK | GFX_CMD_STATUS_MASK)
64
+
54
65
extern const struct attribute_group amdgpu_flash_attr_group;
55
66
56
67
enum psp_shared_mem_size {
+2
-2
drivers/gpu/drm/amd/amdgpu/psp_v10_0.c
+2
-2
drivers/gpu/drm/amd/amdgpu/psp_v10_0.c
···
94
94
95
95
/* Wait for response flag (bit 31) in C2PMSG_64 */
96
96
ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_64),
97
-
0x80000000, 0x8000FFFF, false);
97
+
MBOX_TOS_RESP_FLAG, MBOX_TOS_RESP_MASK, false);
98
98
99
99
return ret;
100
100
}
···
115
115
116
116
/* Wait for response flag (bit 31) in C2PMSG_64 */
117
117
ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_64),
118
-
0x80000000, 0x80000000, false);
118
+
MBOX_TOS_RESP_FLAG, MBOX_TOS_RESP_MASK, false);
119
119
120
120
return ret;
121
121
}
+19
-12
drivers/gpu/drm/amd/amdgpu/psp_v11_0.c
+19
-12
drivers/gpu/drm/amd/amdgpu/psp_v11_0.c
···
277
277
278
278
/* Wait for response flag (bit 31) */
279
279
if (amdgpu_sriov_vf(adev))
280
-
ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_101),
281
-
0x80000000, 0x80000000, false);
280
+
ret = psp_wait_for(
281
+
psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_101),
282
+
MBOX_TOS_RESP_FLAG, MBOX_TOS_RESP_MASK, false);
282
283
else
283
-
ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_64),
284
-
0x80000000, 0x80000000, false);
284
+
ret = psp_wait_for(
285
+
psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_64),
286
+
MBOX_TOS_RESP_FLAG, MBOX_TOS_RESP_MASK, false);
285
287
286
288
return ret;
287
289
}
···
319
317
mdelay(20);
320
318
321
319
/* Wait for response flag (bit 31) in C2PMSG_101 */
322
-
ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_101),
323
-
0x80000000, 0x8000FFFF, false);
320
+
ret = psp_wait_for(
321
+
psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_101),
322
+
MBOX_TOS_RESP_FLAG, MBOX_TOS_RESP_MASK, false);
324
323
325
324
} else {
326
325
/* Wait for sOS ready for ring creation */
327
-
ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_64),
328
-
0x80000000, 0x80000000, false);
326
+
ret = psp_wait_for(
327
+
psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_64),
328
+
MBOX_TOS_READY_FLAG, MBOX_TOS_READY_MASK, false);
329
329
if (ret) {
330
330
DRM_ERROR("Failed to wait for sOS ready for ring creation\n");
331
331
return ret;
···
351
347
mdelay(20);
352
348
353
349
/* Wait for response flag (bit 31) in C2PMSG_64 */
354
-
ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_64),
355
-
0x80000000, 0x8000FFFF, false);
350
+
ret = psp_wait_for(
351
+
psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_64),
352
+
MBOX_TOS_RESP_FLAG, MBOX_TOS_RESP_MASK, false);
356
353
}
357
354
358
355
return ret;
···
386
381
387
382
offset = SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_64);
388
383
389
-
ret = psp_wait_for(psp, offset, 0x80000000, 0x8000FFFF, false);
384
+
ret = psp_wait_for(psp, offset, MBOX_TOS_READY_FLAG,
385
+
MBOX_TOS_READY_MASK, false);
390
386
391
387
if (ret) {
392
388
DRM_INFO("psp is not working correctly before mode1 reset!\n");
···
401
395
402
396
offset = SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_33);
403
397
404
-
ret = psp_wait_for(psp, offset, 0x80000000, 0x80000000, false);
398
+
ret = psp_wait_for(psp, offset, MBOX_TOS_RESP_FLAG, MBOX_TOS_RESP_MASK,
399
+
false);
405
400
406
401
if (ret) {
407
402
DRM_INFO("psp mode 1 reset failed!\n");
+15
-10
drivers/gpu/drm/amd/amdgpu/psp_v11_0_8.c
+15
-10
drivers/gpu/drm/amd/amdgpu/psp_v11_0_8.c
···
41
41
/* there might be handshake issue with hardware which needs delay */
42
42
mdelay(20);
43
43
/* Wait for response flag (bit 31) */
44
-
ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_101),
45
-
0x80000000, 0x80000000, false);
44
+
ret = psp_wait_for(
45
+
psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_101),
46
+
MBOX_TOS_RESP_FLAG, MBOX_TOS_RESP_MASK, false);
46
47
} else {
47
48
/* Write the ring destroy command*/
48
49
WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_64,
···
51
50
/* there might be handshake issue with hardware which needs delay */
52
51
mdelay(20);
53
52
/* Wait for response flag (bit 31) */
54
-
ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_64),
55
-
0x80000000, 0x80000000, false);
53
+
ret = psp_wait_for(
54
+
psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_64),
55
+
MBOX_TOS_RESP_FLAG, MBOX_TOS_RESP_MASK, false);
56
56
}
57
57
58
58
return ret;
···
89
87
mdelay(20);
90
88
91
89
/* Wait for response flag (bit 31) in C2PMSG_101 */
92
-
ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_101),
93
-
0x80000000, 0x8000FFFF, false);
90
+
ret = psp_wait_for(
91
+
psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_101),
92
+
MBOX_TOS_RESP_FLAG, MBOX_TOS_RESP_MASK, false);
94
93
95
94
} else {
96
95
/* Wait for sOS ready for ring creation */
97
-
ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_64),
98
-
0x80000000, 0x80000000, false);
96
+
ret = psp_wait_for(
97
+
psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_64),
98
+
MBOX_TOS_READY_FLAG, MBOX_TOS_READY_MASK, false);
99
99
if (ret) {
100
100
DRM_ERROR("Failed to wait for trust OS ready for ring creation\n");
101
101
return ret;
···
121
117
mdelay(20);
122
118
123
119
/* Wait for response flag (bit 31) in C2PMSG_64 */
124
-
ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_64),
125
-
0x80000000, 0x8000FFFF, false);
120
+
ret = psp_wait_for(
121
+
psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_64),
122
+
MBOX_TOS_RESP_FLAG, MBOX_TOS_RESP_MASK, false);
126
123
}
127
124
128
125
return ret;
+11
-7
drivers/gpu/drm/amd/amdgpu/psp_v12_0.c
+11
-7
drivers/gpu/drm/amd/amdgpu/psp_v12_0.c
···
163
163
164
164
/* Wait for response flag (bit 31) in C2PMSG_64 */
165
165
ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_64),
166
-
0x80000000, 0x8000FFFF, false);
166
+
MBOX_TOS_RESP_FLAG, MBOX_TOS_RESP_MASK, false);
167
167
168
168
return ret;
169
169
}
···
184
184
185
185
/* Wait for response flag (bit 31) */
186
186
if (amdgpu_sriov_vf(adev))
187
-
ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_101),
188
-
0x80000000, 0x80000000, false);
187
+
ret = psp_wait_for(
188
+
psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_101),
189
+
MBOX_TOS_RESP_FLAG, MBOX_TOS_RESP_MASK, false);
189
190
else
190
-
ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_64),
191
-
0x80000000, 0x80000000, false);
191
+
ret = psp_wait_for(
192
+
psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_64),
193
+
MBOX_TOS_RESP_FLAG, MBOX_TOS_RESP_MASK, false);
192
194
193
195
return ret;
194
196
}
···
221
219
222
220
offset = SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_64);
223
221
224
-
ret = psp_wait_for(psp, offset, 0x80000000, 0x8000FFFF, false);
222
+
ret = psp_wait_for(psp, offset, MBOX_TOS_READY_FLAG,
223
+
MBOX_TOS_READY_MASK, false);
225
224
226
225
if (ret) {
227
226
DRM_INFO("psp is not working correctly before mode1 reset!\n");
···
236
233
237
234
offset = SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_33);
238
235
239
-
ret = psp_wait_for(psp, offset, 0x80000000, 0x80000000, false);
236
+
ret = psp_wait_for(psp, offset, MBOX_TOS_RESP_FLAG, MBOX_TOS_RESP_MASK,
237
+
false);
240
238
241
239
if (ret) {
242
240
DRM_INFO("psp mode 1 reset failed!\n");
+15
-10
drivers/gpu/drm/amd/amdgpu/psp_v13_0.c
+15
-10
drivers/gpu/drm/amd/amdgpu/psp_v13_0.c
···
384
384
/* there might be handshake issue with hardware which needs delay */
385
385
mdelay(20);
386
386
/* Wait for response flag (bit 31) */
387
-
ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, regMP0_SMN_C2PMSG_101),
388
-
0x80000000, 0x80000000, false);
387
+
ret = psp_wait_for(
388
+
psp, SOC15_REG_OFFSET(MP0, 0, regMP0_SMN_C2PMSG_101),
389
+
MBOX_TOS_RESP_FLAG, MBOX_TOS_RESP_MASK, false);
389
390
} else {
390
391
/* Write the ring destroy command*/
391
392
WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_64,
···
394
393
/* there might be handshake issue with hardware which needs delay */
395
394
mdelay(20);
396
395
/* Wait for response flag (bit 31) */
397
-
ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, regMP0_SMN_C2PMSG_64),
398
-
0x80000000, 0x80000000, false);
396
+
ret = psp_wait_for(
397
+
psp, SOC15_REG_OFFSET(MP0, 0, regMP0_SMN_C2PMSG_64),
398
+
MBOX_TOS_RESP_FLAG, MBOX_TOS_RESP_MASK, false);
399
399
}
400
400
401
401
return ret;
···
432
430
mdelay(20);
433
431
434
432
/* Wait for response flag (bit 31) in C2PMSG_101 */
435
-
ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, regMP0_SMN_C2PMSG_101),
436
-
0x80000000, 0x8000FFFF, false);
433
+
ret = psp_wait_for(
434
+
psp, SOC15_REG_OFFSET(MP0, 0, regMP0_SMN_C2PMSG_101),
435
+
MBOX_TOS_RESP_FLAG, MBOX_TOS_RESP_MASK, false);
437
436
438
437
} else {
439
438
/* Wait for sOS ready for ring creation */
440
-
ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, regMP0_SMN_C2PMSG_64),
441
-
0x80000000, 0x80000000, false);
439
+
ret = psp_wait_for(
440
+
psp, SOC15_REG_OFFSET(MP0, 0, regMP0_SMN_C2PMSG_64),
441
+
MBOX_TOS_READY_FLAG, MBOX_TOS_READY_MASK, false);
442
442
if (ret) {
443
443
DRM_ERROR("Failed to wait for trust OS ready for ring creation\n");
444
444
return ret;
···
464
460
mdelay(20);
465
461
466
462
/* Wait for response flag (bit 31) in C2PMSG_64 */
467
-
ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, regMP0_SMN_C2PMSG_64),
468
-
0x80000000, 0x8000FFFF, false);
463
+
ret = psp_wait_for(
464
+
psp, SOC15_REG_OFFSET(MP0, 0, regMP0_SMN_C2PMSG_64),
465
+
MBOX_TOS_RESP_FLAG, MBOX_TOS_RESP_MASK, false);
469
466
}
470
467
471
468
return ret;
+15
-10
drivers/gpu/drm/amd/amdgpu/psp_v13_0_4.c
+15
-10
drivers/gpu/drm/amd/amdgpu/psp_v13_0_4.c
···
204
204
/* there might be handshake issue with hardware which needs delay */
205
205
mdelay(20);
206
206
/* Wait for response flag (bit 31) */
207
-
ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, regMP0_SMN_C2PMSG_101),
208
-
0x80000000, 0x80000000, false);
207
+
ret = psp_wait_for(
208
+
psp, SOC15_REG_OFFSET(MP0, 0, regMP0_SMN_C2PMSG_101),
209
+
MBOX_TOS_RESP_FLAG, MBOX_TOS_RESP_MASK, false);
209
210
} else {
210
211
/* Write the ring destroy command*/
211
212
WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_64,
···
214
213
/* there might be handshake issue with hardware which needs delay */
215
214
mdelay(20);
216
215
/* Wait for response flag (bit 31) */
217
-
ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, regMP0_SMN_C2PMSG_64),
218
-
0x80000000, 0x80000000, false);
216
+
ret = psp_wait_for(
217
+
psp, SOC15_REG_OFFSET(MP0, 0, regMP0_SMN_C2PMSG_64),
218
+
MBOX_TOS_RESP_FLAG, MBOX_TOS_RESP_MASK, false);
219
219
}
220
220
221
221
return ret;
···
252
250
mdelay(20);
253
251
254
252
/* Wait for response flag (bit 31) in C2PMSG_101 */
255
-
ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, regMP0_SMN_C2PMSG_101),
256
-
0x80000000, 0x8000FFFF, false);
253
+
ret = psp_wait_for(
254
+
psp, SOC15_REG_OFFSET(MP0, 0, regMP0_SMN_C2PMSG_101),
255
+
MBOX_TOS_RESP_FLAG, MBOX_TOS_RESP_MASK, false);
257
256
258
257
} else {
259
258
/* Wait for sOS ready for ring creation */
260
-
ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, regMP0_SMN_C2PMSG_64),
261
-
0x80000000, 0x80000000, false);
259
+
ret = psp_wait_for(
260
+
psp, SOC15_REG_OFFSET(MP0, 0, regMP0_SMN_C2PMSG_64),
261
+
MBOX_TOS_READY_FLAG, MBOX_TOS_READY_MASK, false);
262
262
if (ret) {
263
263
DRM_ERROR("Failed to wait for trust OS ready for ring creation\n");
264
264
return ret;
···
284
280
mdelay(20);
285
281
286
282
/* Wait for response flag (bit 31) in C2PMSG_64 */
287
-
ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, regMP0_SMN_C2PMSG_64),
288
-
0x80000000, 0x8000FFFF, false);
283
+
ret = psp_wait_for(
284
+
psp, SOC15_REG_OFFSET(MP0, 0, regMP0_SMN_C2PMSG_64),
285
+
MBOX_TOS_RESP_FLAG, MBOX_TOS_RESP_MASK, false);
289
286
}
290
287
291
288
return ret;
+15
-10
drivers/gpu/drm/amd/amdgpu/psp_v14_0.c
+15
-10
drivers/gpu/drm/amd/amdgpu/psp_v14_0.c
···
248
248
/* there might be handshake issue with hardware which needs delay */
249
249
mdelay(20);
250
250
/* Wait for response flag (bit 31) */
251
-
ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, regMPASP_SMN_C2PMSG_101),
252
-
0x80000000, 0x80000000, false);
251
+
ret = psp_wait_for(
252
+
psp, SOC15_REG_OFFSET(MP0, 0, regMPASP_SMN_C2PMSG_101),
253
+
MBOX_TOS_RESP_FLAG, MBOX_TOS_RESP_MASK, false);
253
254
} else {
254
255
/* Write the ring destroy command*/
255
256
WREG32_SOC15(MP0, 0, regMPASP_SMN_C2PMSG_64,
···
258
257
/* there might be handshake issue with hardware which needs delay */
259
258
mdelay(20);
260
259
/* Wait for response flag (bit 31) */
261
-
ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, regMPASP_SMN_C2PMSG_64),
262
-
0x80000000, 0x80000000, false);
260
+
ret = psp_wait_for(
261
+
psp, SOC15_REG_OFFSET(MP0, 0, regMPASP_SMN_C2PMSG_64),
262
+
MBOX_TOS_RESP_FLAG, MBOX_TOS_RESP_MASK, false);
263
263
}
264
264
265
265
return ret;
···
296
294
mdelay(20);
297
295
298
296
/* Wait for response flag (bit 31) in C2PMSG_101 */
299
-
ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, regMPASP_SMN_C2PMSG_101),
300
-
0x80000000, 0x8000FFFF, false);
297
+
ret = psp_wait_for(
298
+
psp, SOC15_REG_OFFSET(MP0, 0, regMPASP_SMN_C2PMSG_101),
299
+
MBOX_TOS_RESP_FLAG, MBOX_TOS_RESP_MASK, false);
301
300
302
301
} else {
303
302
/* Wait for sOS ready for ring creation */
304
-
ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, regMPASP_SMN_C2PMSG_64),
305
-
0x80000000, 0x80000000, false);
303
+
ret = psp_wait_for(
304
+
psp, SOC15_REG_OFFSET(MP0, 0, regMPASP_SMN_C2PMSG_64),
305
+
MBOX_TOS_READY_FLAG, MBOX_TOS_READY_MASK, false);
306
306
if (ret) {
307
307
DRM_ERROR("Failed to wait for trust OS ready for ring creation\n");
308
308
return ret;
···
328
324
mdelay(20);
329
325
330
326
/* Wait for response flag (bit 31) in C2PMSG_64 */
331
-
ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, regMPASP_SMN_C2PMSG_64),
332
-
0x80000000, 0x8000FFFF, false);
327
+
ret = psp_wait_for(
328
+
psp, SOC15_REG_OFFSET(MP0, 0, regMPASP_SMN_C2PMSG_64),
329
+
MBOX_TOS_RESP_FLAG, MBOX_TOS_RESP_MASK, false);
333
330
}
334
331
335
332
return ret;