Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
drm/i915: move VLV IOSF SB unit specific helpers under display
Now that all the VLV IOSF SB unit specific helper users are under
display, relocate the helpers themselves under display as
well. Resurrect the vlv_sideband.[ch] name for this. Make everything
except DPIO helpers static inlines, as their implementations are
trivial.
All of this considerably simplifies the xe compat header.
v2: Rebase
Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Link: https://lore.kernel.org/r/e86c2498c9f1c1d30f8e83fa5f1c23526b87b9ab.1747061743.git.jani.nikula@intel.com
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
+213
-289
+2
-1
drivers/gpu/drm/i915/Makefile
+2
-1
drivers/gpu/drm/i915/Makefile
+1
-1
drivers/gpu/drm/i915/display/i9xx_wm.c
+1
-1
drivers/gpu/drm/i915/display/i9xx_wm.c
+1
-1
drivers/gpu/drm/i915/display/intel_cdclk.c
+1
-1
drivers/gpu/drm/i915/display/intel_cdclk.c
+1
-1
drivers/gpu/drm/i915/display/intel_display.c
+1
-1
drivers/gpu/drm/i915/display/intel_display.c
···
131
131
#include "vlv_dsi.h"
132
132
#include "vlv_dsi_pll.h"
133
133
#include "vlv_dsi_regs.h"
134
-
#include "vlv_iosf_sb.h"
134
+
#include "vlv_sideband.h"
135
135
136
136
static void intel_set_transcoder_timings(const struct intel_crtc_state *crtc_state);
137
137
static void intel_set_pipe_src_size(const struct intel_crtc_state *crtc_state);
+1
-1
drivers/gpu/drm/i915/display/intel_display_power.c
+1
-1
drivers/gpu/drm/i915/display/intel_display_power.c
···
27
27
#include "intel_snps_phy.h"
28
28
#include "skl_watermark.h"
29
29
#include "skl_watermark_regs.h"
30
-
#include "vlv_iosf_sb.h"
30
+
#include "vlv_sideband.h"
31
31
32
32
#define for_each_power_domain_well(__display, __power_well, __domain) \
33
33
for_each_power_well((__display), __power_well) \
+1
-1
drivers/gpu/drm/i915/display/intel_display_power_well.c
+1
-1
drivers/gpu/drm/i915/display/intel_display_power_well.c
+1
-1
drivers/gpu/drm/i915/display/intel_dpio_phy.c
+1
-1
drivers/gpu/drm/i915/display/intel_dpio_phy.c
+1
-1
drivers/gpu/drm/i915/display/intel_dpll.c
+1
-1
drivers/gpu/drm/i915/display/intel_dpll.c
+1
-1
drivers/gpu/drm/i915/display/intel_dsi_vbt.c
+1
-1
drivers/gpu/drm/i915/display/intel_dsi_vbt.c
+1
-1
drivers/gpu/drm/i915/display/vlv_dsi.c
+1
-1
drivers/gpu/drm/i915/display/vlv_dsi.c
+1
-1
drivers/gpu/drm/i915/display/vlv_dsi_pll.c
+1
-1
drivers/gpu/drm/i915/display/vlv_dsi_pll.c
+45
drivers/gpu/drm/i915/display/vlv_sideband.c
+45
drivers/gpu/drm/i915/display/vlv_sideband.c
···
1
+
// SPDX-License-Identifier: MIT
2
+
/* Copyright © 2025 Intel Corporation */
3
+
4
+
#include "i915_drv.h"
5
+
#include "intel_dpio_phy.h"
6
+
#include "vlv_sideband.h"
7
+
8
+
static enum vlv_iosf_sb_unit vlv_dpio_phy_to_unit(struct drm_i915_private *i915,
9
+
enum dpio_phy phy)
10
+
{
11
+
/*
12
+
* IOSF_PORT_DPIO: VLV x2 PHY (DP/HDMI B and C), CHV x1 PHY (DP/HDMI D)
13
+
* IOSF_PORT_DPIO_2: CHV x2 PHY (DP/HDMI B and C)
14
+
*/
15
+
if (IS_CHERRYVIEW(i915))
16
+
return phy == DPIO_PHY0 ? VLV_IOSF_SB_DPIO_2 : VLV_IOSF_SB_DPIO;
17
+
else
18
+
return VLV_IOSF_SB_DPIO;
19
+
}
20
+
21
+
u32 vlv_dpio_read(struct drm_i915_private *i915, enum dpio_phy phy, int reg)
22
+
{
23
+
enum vlv_iosf_sb_unit unit = vlv_dpio_phy_to_unit(i915, phy);
24
+
u32 val;
25
+
26
+
val = vlv_iosf_sb_read(i915, unit, reg);
27
+
28
+
/*
29
+
* FIXME: There might be some registers where all 1's is a valid value,
30
+
* so ideally we should check the register offset instead...
31
+
*/
32
+
drm_WARN(&i915->drm, val == 0xffffffff,
33
+
"DPIO PHY%d read reg 0x%x == 0x%x\n",
34
+
phy, reg, val);
35
+
36
+
return val;
37
+
}
38
+
39
+
void vlv_dpio_write(struct drm_i915_private *i915,
40
+
enum dpio_phy phy, int reg, u32 val)
41
+
{
42
+
enum vlv_iosf_sb_unit unit = vlv_dpio_phy_to_unit(i915, phy);
43
+
44
+
vlv_iosf_sb_write(i915, unit, reg, val);
45
+
}
+156
drivers/gpu/drm/i915/display/vlv_sideband.h
+156
drivers/gpu/drm/i915/display/vlv_sideband.h
···
1
+
/* SPDX-License-Identifier: MIT */
2
+
/* Copyright © 2025 Intel Corporation */
3
+
4
+
#ifndef _VLV_SIDEBAND_H_
5
+
#define _VLV_SIDEBAND_H_
6
+
7
+
#include <linux/bitops.h>
8
+
#include <linux/types.h>
9
+
10
+
#include "vlv_iosf_sb.h"
11
+
#include "vlv_iosf_sb_reg.h"
12
+
13
+
enum dpio_phy;
14
+
struct drm_i915_private;
15
+
16
+
static inline void vlv_bunit_get(struct drm_i915_private *i915)
17
+
{
18
+
vlv_iosf_sb_get(i915, BIT(VLV_IOSF_SB_BUNIT));
19
+
}
20
+
21
+
static inline u32 vlv_bunit_read(struct drm_i915_private *i915, u32 reg)
22
+
{
23
+
return vlv_iosf_sb_read(i915, VLV_IOSF_SB_BUNIT, reg);
24
+
}
25
+
26
+
static inline void vlv_bunit_write(struct drm_i915_private *i915, u32 reg, u32 val)
27
+
{
28
+
vlv_iosf_sb_write(i915, VLV_IOSF_SB_BUNIT, reg, val);
29
+
}
30
+
31
+
static inline void vlv_bunit_put(struct drm_i915_private *i915)
32
+
{
33
+
vlv_iosf_sb_put(i915, BIT(VLV_IOSF_SB_BUNIT));
34
+
}
35
+
36
+
static inline void vlv_cck_get(struct drm_i915_private *i915)
37
+
{
38
+
vlv_iosf_sb_get(i915, BIT(VLV_IOSF_SB_CCK));
39
+
}
40
+
41
+
static inline u32 vlv_cck_read(struct drm_i915_private *i915, u32 reg)
42
+
{
43
+
return vlv_iosf_sb_read(i915, VLV_IOSF_SB_CCK, reg);
44
+
}
45
+
46
+
static inline void vlv_cck_write(struct drm_i915_private *i915, u32 reg, u32 val)
47
+
{
48
+
vlv_iosf_sb_write(i915, VLV_IOSF_SB_CCK, reg, val);
49
+
}
50
+
51
+
static inline void vlv_cck_put(struct drm_i915_private *i915)
52
+
{
53
+
vlv_iosf_sb_put(i915, BIT(VLV_IOSF_SB_CCK));
54
+
}
55
+
56
+
static inline void vlv_ccu_get(struct drm_i915_private *i915)
57
+
{
58
+
vlv_iosf_sb_get(i915, BIT(VLV_IOSF_SB_CCU));
59
+
}
60
+
61
+
static inline u32 vlv_ccu_read(struct drm_i915_private *i915, u32 reg)
62
+
{
63
+
return vlv_iosf_sb_read(i915, VLV_IOSF_SB_CCU, reg);
64
+
}
65
+
66
+
static inline void vlv_ccu_write(struct drm_i915_private *i915, u32 reg, u32 val)
67
+
{
68
+
vlv_iosf_sb_write(i915, VLV_IOSF_SB_CCU, reg, val);
69
+
}
70
+
71
+
static inline void vlv_ccu_put(struct drm_i915_private *i915)
72
+
{
73
+
vlv_iosf_sb_put(i915, BIT(VLV_IOSF_SB_CCU));
74
+
}
75
+
76
+
static inline void vlv_dpio_get(struct drm_i915_private *i915)
77
+
{
78
+
vlv_iosf_sb_get(i915, BIT(VLV_IOSF_SB_DPIO) | BIT(VLV_IOSF_SB_DPIO_2));
79
+
}
80
+
81
+
#ifdef I915
82
+
u32 vlv_dpio_read(struct drm_i915_private *i915, enum dpio_phy phy, int reg);
83
+
void vlv_dpio_write(struct drm_i915_private *i915,
84
+
enum dpio_phy phy, int reg, u32 val);
85
+
#else
86
+
static inline u32 vlv_dpio_read(struct drm_i915_private *i915, int phy, int reg)
87
+
{
88
+
return 0;
89
+
}
90
+
static inline void vlv_dpio_write(struct drm_i915_private *i915,
91
+
int phy, int reg, u32 val)
92
+
{
93
+
}
94
+
#endif
95
+
96
+
static inline void vlv_dpio_put(struct drm_i915_private *i915)
97
+
{
98
+
vlv_iosf_sb_put(i915, BIT(VLV_IOSF_SB_DPIO) | BIT(VLV_IOSF_SB_DPIO_2));
99
+
}
100
+
101
+
static inline void vlv_flisdsi_get(struct drm_i915_private *i915)
102
+
{
103
+
vlv_iosf_sb_get(i915, BIT(VLV_IOSF_SB_FLISDSI));
104
+
}
105
+
106
+
static inline u32 vlv_flisdsi_read(struct drm_i915_private *i915, u32 reg)
107
+
{
108
+
return vlv_iosf_sb_read(i915, VLV_IOSF_SB_FLISDSI, reg);
109
+
}
110
+
111
+
static inline void vlv_flisdsi_write(struct drm_i915_private *i915, u32 reg, u32 val)
112
+
{
113
+
vlv_iosf_sb_write(i915, VLV_IOSF_SB_FLISDSI, reg, val);
114
+
}
115
+
116
+
static inline void vlv_flisdsi_put(struct drm_i915_private *i915)
117
+
{
118
+
vlv_iosf_sb_put(i915, BIT(VLV_IOSF_SB_FLISDSI));
119
+
}
120
+
121
+
static inline void vlv_nc_get(struct drm_i915_private *i915)
122
+
{
123
+
vlv_iosf_sb_get(i915, BIT(VLV_IOSF_SB_NC));
124
+
}
125
+
126
+
static inline u32 vlv_nc_read(struct drm_i915_private *i915, u8 addr)
127
+
{
128
+
return vlv_iosf_sb_read(i915, VLV_IOSF_SB_NC, addr);
129
+
}
130
+
131
+
static inline void vlv_nc_put(struct drm_i915_private *i915)
132
+
{
133
+
vlv_iosf_sb_put(i915, BIT(VLV_IOSF_SB_NC));
134
+
}
135
+
136
+
static inline void vlv_punit_get(struct drm_i915_private *i915)
137
+
{
138
+
vlv_iosf_sb_get(i915, BIT(VLV_IOSF_SB_PUNIT));
139
+
}
140
+
141
+
static inline u32 vlv_punit_read(struct drm_i915_private *i915, u32 addr)
142
+
{
143
+
return vlv_iosf_sb_read(i915, VLV_IOSF_SB_PUNIT, addr);
144
+
}
145
+
146
+
static inline int vlv_punit_write(struct drm_i915_private *i915, u32 addr, u32 val)
147
+
{
148
+
return vlv_iosf_sb_write(i915, VLV_IOSF_SB_PUNIT, addr, val);
149
+
}
150
+
151
+
static inline void vlv_punit_put(struct drm_i915_private *i915)
152
+
{
153
+
vlv_iosf_sb_put(i915, BIT(VLV_IOSF_SB_PUNIT));
154
+
}
155
+
156
+
#endif /* _VLV_SIDEBAND_H_ */
-94
drivers/gpu/drm/i915/vlv_iosf_sb.c
-94
drivers/gpu/drm/i915/vlv_iosf_sb.c
···
196
196
return vlv_sideband_rw(i915, devfn, port, opcode, addr, &val);
197
197
}
198
198
199
-
u32 vlv_punit_read(struct drm_i915_private *i915, u32 addr)
200
-
{
201
-
return vlv_iosf_sb_read(i915, VLV_IOSF_SB_PUNIT, addr);
202
-
}
203
-
204
-
int vlv_punit_write(struct drm_i915_private *i915, u32 addr, u32 val)
205
-
{
206
-
return vlv_iosf_sb_write(i915, VLV_IOSF_SB_PUNIT, addr, val);
207
-
}
208
-
209
-
u32 vlv_bunit_read(struct drm_i915_private *i915, u32 reg)
210
-
{
211
-
return vlv_iosf_sb_read(i915, VLV_IOSF_SB_BUNIT, reg);
212
-
}
213
-
214
-
void vlv_bunit_write(struct drm_i915_private *i915, u32 reg, u32 val)
215
-
{
216
-
vlv_iosf_sb_write(i915, VLV_IOSF_SB_BUNIT, reg, val);
217
-
}
218
-
219
-
u32 vlv_nc_read(struct drm_i915_private *i915, u8 addr)
220
-
{
221
-
return vlv_iosf_sb_read(i915, VLV_IOSF_SB_NC, addr);
222
-
}
223
-
224
-
u32 vlv_cck_read(struct drm_i915_private *i915, u32 reg)
225
-
{
226
-
return vlv_iosf_sb_read(i915, VLV_IOSF_SB_CCK, reg);
227
-
}
228
-
229
-
void vlv_cck_write(struct drm_i915_private *i915, u32 reg, u32 val)
230
-
{
231
-
vlv_iosf_sb_write(i915, VLV_IOSF_SB_CCK, reg, val);
232
-
}
233
-
234
-
u32 vlv_ccu_read(struct drm_i915_private *i915, u32 reg)
235
-
{
236
-
return vlv_iosf_sb_read(i915, VLV_IOSF_SB_CCU, reg);
237
-
}
238
-
239
-
void vlv_ccu_write(struct drm_i915_private *i915, u32 reg, u32 val)
240
-
{
241
-
vlv_iosf_sb_write(i915, VLV_IOSF_SB_CCU, reg, val);
242
-
}
243
-
244
-
static enum vlv_iosf_sb_unit vlv_dpio_phy_to_unit(struct drm_i915_private *i915,
245
-
enum dpio_phy phy)
246
-
{
247
-
/*
248
-
* IOSF_PORT_DPIO: VLV x2 PHY (DP/HDMI B and C), CHV x1 PHY (DP/HDMI D)
249
-
* IOSF_PORT_DPIO_2: CHV x2 PHY (DP/HDMI B and C)
250
-
*/
251
-
if (IS_CHERRYVIEW(i915))
252
-
return phy == DPIO_PHY0 ? VLV_IOSF_SB_DPIO_2 : VLV_IOSF_SB_DPIO;
253
-
else
254
-
return VLV_IOSF_SB_DPIO;
255
-
}
256
-
257
-
u32 vlv_dpio_read(struct drm_i915_private *i915, enum dpio_phy phy, int reg)
258
-
{
259
-
enum vlv_iosf_sb_unit unit = vlv_dpio_phy_to_unit(i915, phy);
260
-
u32 val;
261
-
262
-
val = vlv_iosf_sb_read(i915, unit, reg);
263
-
264
-
/*
265
-
* FIXME: There might be some registers where all 1's is a valid value,
266
-
* so ideally we should check the register offset instead...
267
-
*/
268
-
drm_WARN(&i915->drm, val == 0xffffffff,
269
-
"DPIO PHY%d read reg 0x%x == 0x%x\n",
270
-
phy, reg, val);
271
-
272
-
return val;
273
-
}
274
-
275
-
void vlv_dpio_write(struct drm_i915_private *i915,
276
-
enum dpio_phy phy, int reg, u32 val)
277
-
{
278
-
enum vlv_iosf_sb_unit unit = vlv_dpio_phy_to_unit(i915, phy);
279
-
280
-
vlv_iosf_sb_write(i915, unit, reg, val);
281
-
}
282
-
283
-
u32 vlv_flisdsi_read(struct drm_i915_private *i915, u32 reg)
284
-
{
285
-
return vlv_iosf_sb_read(i915, VLV_IOSF_SB_FLISDSI, reg);
286
-
}
287
-
288
-
void vlv_flisdsi_write(struct drm_i915_private *i915, u32 reg, u32 val)
289
-
{
290
-
vlv_iosf_sb_write(i915, VLV_IOSF_SB_FLISDSI, reg, val);
291
-
}
292
-
293
199
void vlv_iosf_sb_init(struct drm_i915_private *i915)
294
200
{
295
201
if (IS_VALLEYVIEW(i915) || IS_CHERRYVIEW(i915))
-93
drivers/gpu/drm/i915/vlv_iosf_sb.h
-93
drivers/gpu/drm/i915/vlv_iosf_sb.h
···
6
6
#ifndef _VLV_IOSF_SB_H_
7
7
#define _VLV_IOSF_SB_H_
8
8
9
-
#include <linux/bitops.h>
10
9
#include <linux/types.h>
11
10
12
11
#include "vlv_iosf_sb_reg.h"
13
12
14
-
enum dpio_phy;
15
13
struct drm_i915_private;
16
14
17
15
enum vlv_iosf_sb_unit {
···
32
34
33
35
u32 vlv_iosf_sb_read(struct drm_i915_private *i915, enum vlv_iosf_sb_unit unit, u32 addr);
34
36
int vlv_iosf_sb_write(struct drm_i915_private *i915, enum vlv_iosf_sb_unit unit, u32 addr, u32 val);
35
-
36
-
static inline void vlv_bunit_get(struct drm_i915_private *i915)
37
-
{
38
-
vlv_iosf_sb_get(i915, BIT(VLV_IOSF_SB_BUNIT));
39
-
}
40
-
41
-
u32 vlv_bunit_read(struct drm_i915_private *i915, u32 reg);
42
-
void vlv_bunit_write(struct drm_i915_private *i915, u32 reg, u32 val);
43
-
44
-
static inline void vlv_bunit_put(struct drm_i915_private *i915)
45
-
{
46
-
vlv_iosf_sb_put(i915, BIT(VLV_IOSF_SB_BUNIT));
47
-
}
48
-
49
-
static inline void vlv_cck_get(struct drm_i915_private *i915)
50
-
{
51
-
vlv_iosf_sb_get(i915, BIT(VLV_IOSF_SB_CCK));
52
-
}
53
-
54
-
u32 vlv_cck_read(struct drm_i915_private *i915, u32 reg);
55
-
void vlv_cck_write(struct drm_i915_private *i915, u32 reg, u32 val);
56
-
57
-
static inline void vlv_cck_put(struct drm_i915_private *i915)
58
-
{
59
-
vlv_iosf_sb_put(i915, BIT(VLV_IOSF_SB_CCK));
60
-
}
61
-
62
-
static inline void vlv_ccu_get(struct drm_i915_private *i915)
63
-
{
64
-
vlv_iosf_sb_get(i915, BIT(VLV_IOSF_SB_CCU));
65
-
}
66
-
67
-
u32 vlv_ccu_read(struct drm_i915_private *i915, u32 reg);
68
-
void vlv_ccu_write(struct drm_i915_private *i915, u32 reg, u32 val);
69
-
70
-
static inline void vlv_ccu_put(struct drm_i915_private *i915)
71
-
{
72
-
vlv_iosf_sb_put(i915, BIT(VLV_IOSF_SB_CCU));
73
-
}
74
-
75
-
static inline void vlv_dpio_get(struct drm_i915_private *i915)
76
-
{
77
-
vlv_iosf_sb_get(i915, BIT(VLV_IOSF_SB_DPIO) | BIT(VLV_IOSF_SB_DPIO_2));
78
-
}
79
-
80
-
u32 vlv_dpio_read(struct drm_i915_private *i915, enum dpio_phy phy, int reg);
81
-
void vlv_dpio_write(struct drm_i915_private *i915,
82
-
enum dpio_phy phy, int reg, u32 val);
83
-
84
-
static inline void vlv_dpio_put(struct drm_i915_private *i915)
85
-
{
86
-
vlv_iosf_sb_put(i915, BIT(VLV_IOSF_SB_DPIO) | BIT(VLV_IOSF_SB_DPIO_2));
87
-
}
88
-
89
-
static inline void vlv_flisdsi_get(struct drm_i915_private *i915)
90
-
{
91
-
vlv_iosf_sb_get(i915, BIT(VLV_IOSF_SB_FLISDSI));
92
-
}
93
-
94
-
u32 vlv_flisdsi_read(struct drm_i915_private *i915, u32 reg);
95
-
void vlv_flisdsi_write(struct drm_i915_private *i915, u32 reg, u32 val);
96
-
97
-
static inline void vlv_flisdsi_put(struct drm_i915_private *i915)
98
-
{
99
-
vlv_iosf_sb_put(i915, BIT(VLV_IOSF_SB_FLISDSI));
100
-
}
101
-
102
-
static inline void vlv_nc_get(struct drm_i915_private *i915)
103
-
{
104
-
vlv_iosf_sb_get(i915, BIT(VLV_IOSF_SB_NC));
105
-
}
106
-
107
-
u32 vlv_nc_read(struct drm_i915_private *i915, u8 addr);
108
-
109
-
static inline void vlv_nc_put(struct drm_i915_private *i915)
110
-
{
111
-
vlv_iosf_sb_put(i915, BIT(VLV_IOSF_SB_NC));
112
-
}
113
-
114
-
static inline void vlv_punit_get(struct drm_i915_private *i915)
115
-
{
116
-
vlv_iosf_sb_get(i915, BIT(VLV_IOSF_SB_PUNIT));
117
-
}
118
-
119
-
u32 vlv_punit_read(struct drm_i915_private *i915, u32 addr);
120
-
int vlv_punit_write(struct drm_i915_private *i915, u32 addr, u32 val);
121
-
122
-
static inline void vlv_punit_put(struct drm_i915_private *i915)
123
-
{
124
-
vlv_iosf_sb_put(i915, BIT(VLV_IOSF_SB_PUNIT));
125
-
}
126
37
127
38
#endif /* _VLV_IOSF_SB_H_ */
-91
drivers/gpu/drm/xe/compat-i915-headers/vlv_iosf_sb.h
-91
drivers/gpu/drm/xe/compat-i915-headers/vlv_iosf_sb.h
···
10
10
11
11
#include "vlv_iosf_sb_reg.h"
12
12
13
-
enum pipe;
14
13
struct drm_i915_private;
15
14
16
15
enum vlv_iosf_sb_unit {
···
36
37
return 0;
37
38
}
38
39
static inline void vlv_iosf_sb_put(struct drm_i915_private *i915, unsigned long ports)
39
-
{
40
-
}
41
-
static inline void vlv_bunit_get(struct drm_i915_private *i915)
42
-
{
43
-
}
44
-
static inline u32 vlv_bunit_read(struct drm_i915_private *i915, u32 reg)
45
-
{
46
-
return 0;
47
-
}
48
-
static inline void vlv_bunit_write(struct drm_i915_private *i915, u32 reg, u32 val)
49
-
{
50
-
}
51
-
static inline void vlv_bunit_put(struct drm_i915_private *i915)
52
-
{
53
-
}
54
-
static inline void vlv_cck_get(struct drm_i915_private *i915)
55
-
{
56
-
}
57
-
static inline u32 vlv_cck_read(struct drm_i915_private *i915, u32 reg)
58
-
{
59
-
return 0;
60
-
}
61
-
static inline void vlv_cck_write(struct drm_i915_private *i915, u32 reg, u32 val)
62
-
{
63
-
}
64
-
static inline void vlv_cck_put(struct drm_i915_private *i915)
65
-
{
66
-
}
67
-
static inline void vlv_ccu_get(struct drm_i915_private *i915)
68
-
{
69
-
}
70
-
static inline u32 vlv_ccu_read(struct drm_i915_private *i915, u32 reg)
71
-
{
72
-
return 0;
73
-
}
74
-
static inline void vlv_ccu_write(struct drm_i915_private *i915, u32 reg, u32 val)
75
-
{
76
-
}
77
-
static inline void vlv_ccu_put(struct drm_i915_private *i915)
78
-
{
79
-
}
80
-
static inline void vlv_dpio_get(struct drm_i915_private *i915)
81
-
{
82
-
}
83
-
static inline u32 vlv_dpio_read(struct drm_i915_private *i915, int pipe, int reg)
84
-
{
85
-
return 0;
86
-
}
87
-
static inline void vlv_dpio_write(struct drm_i915_private *i915,
88
-
int pipe, int reg, u32 val)
89
-
{
90
-
}
91
-
static inline void vlv_dpio_put(struct drm_i915_private *i915)
92
-
{
93
-
}
94
-
static inline void vlv_flisdsi_get(struct drm_i915_private *i915)
95
-
{
96
-
}
97
-
static inline u32 vlv_flisdsi_read(struct drm_i915_private *i915, u32 reg)
98
-
{
99
-
return 0;
100
-
}
101
-
static inline void vlv_flisdsi_write(struct drm_i915_private *i915, u32 reg, u32 val)
102
-
{
103
-
}
104
-
static inline void vlv_flisdsi_put(struct drm_i915_private *i915)
105
-
{
106
-
}
107
-
static inline void vlv_nc_get(struct drm_i915_private *i915)
108
-
{
109
-
}
110
-
static inline u32 vlv_nc_read(struct drm_i915_private *i915, u8 addr)
111
-
{
112
-
return 0;
113
-
}
114
-
static inline void vlv_nc_put(struct drm_i915_private *i915)
115
-
{
116
-
}
117
-
static inline void vlv_punit_get(struct drm_i915_private *i915)
118
-
{
119
-
}
120
-
static inline u32 vlv_punit_read(struct drm_i915_private *i915, u32 addr)
121
-
{
122
-
return 0;
123
-
}
124
-
static inline int vlv_punit_write(struct drm_i915_private *i915, u32 addr, u32 val)
125
-
{
126
-
return 0;
127
-
}
128
-
static inline void vlv_punit_put(struct drm_i915_private *i915)
129
40
{
130
41
}
131
42