Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
drm/i915: switch i915 core to generic VLV IOSF SB functions
We'll want to relocate the unit specific functions to display, making
them inaccessible to i915 core. As there aren't that many users in i915
core, we can just convert them to the generic VLV IOSF SB read/write
functions.
v2: Use BIT(unit) for get/put
Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Link: https://lore.kernel.org/r/3162c8768eeeba928bbc3d4aa2ddfc6a1030a451.1747061743.git.jani.nikula@intel.com
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
+28
-28
+3
-3
drivers/gpu/drm/i915/gt/intel_gt_pm_debugfs.c
+3
-3
drivers/gpu/drm/i915/gt/intel_gt_pm_debugfs.c
···
366
366
drm_printf(p, "SW control enabled: %s\n",
367
367
str_yes_no((rpmodectl & GEN6_RP_MEDIA_MODE_MASK) == GEN6_RP_MEDIA_SW_MODE));
368
368
369
-
vlv_punit_get(i915);
370
-
freq_sts = vlv_punit_read(i915, PUNIT_REG_GPU_FREQ_STS);
371
-
vlv_punit_put(i915);
369
+
vlv_iosf_sb_get(i915, BIT(VLV_IOSF_SB_PUNIT));
370
+
freq_sts = vlv_iosf_sb_read(i915, VLV_IOSF_SB_PUNIT, PUNIT_REG_GPU_FREQ_STS);
371
+
vlv_iosf_sb_put(i915, BIT(VLV_IOSF_SB_PUNIT));
372
372
373
373
drm_printf(p, "PUNIT_REG_GPU_FREQ_STS: 0x%08x\n", freq_sts);
374
374
+23
-23
drivers/gpu/drm/i915/gt/intel_rps.c
+23
-23
drivers/gpu/drm/i915/gt/intel_rps.c
···
820
820
struct drm_i915_private *i915 = rps_to_i915(rps);
821
821
int err;
822
822
823
-
vlv_punit_get(i915);
824
-
err = vlv_punit_write(i915, PUNIT_REG_GPU_FREQ_REQ, val);
825
-
vlv_punit_put(i915);
823
+
vlv_iosf_sb_get(i915, BIT(VLV_IOSF_SB_PUNIT));
824
+
err = vlv_iosf_sb_write(i915, VLV_IOSF_SB_PUNIT, PUNIT_REG_GPU_FREQ_REQ, val);
825
+
vlv_iosf_sb_put(i915, BIT(VLV_IOSF_SB_PUNIT));
826
826
827
827
GT_TRACE(rps_to_gt(rps), "set val:%x, freq:%d\n",
828
828
val, intel_gpu_freq(rps, val));
···
1268
1268
struct intel_gt *gt = rps_to_gt(rps);
1269
1269
u32 val;
1270
1270
1271
-
val = vlv_punit_read(i915, FB_GFX_FMAX_AT_VMAX_FUSE);
1271
+
val = vlv_iosf_sb_read(i915, VLV_IOSF_SB_PUNIT, FB_GFX_FMAX_AT_VMAX_FUSE);
1272
1272
1273
1273
switch (gt->info.sseu.eu_total) {
1274
1274
case 8:
···
1295
1295
struct drm_i915_private *i915 = rps_to_i915(rps);
1296
1296
u32 val;
1297
1297
1298
-
val = vlv_punit_read(i915, PUNIT_GPU_DUTYCYCLE_REG);
1298
+
val = vlv_iosf_sb_read(i915, VLV_IOSF_SB_PUNIT, PUNIT_GPU_DUTYCYCLE_REG);
1299
1299
val >>= PUNIT_GPU_DUTYCYCLE_RPE_FREQ_SHIFT;
1300
1300
1301
1301
return val & PUNIT_GPU_DUTYCYCLE_RPE_FREQ_MASK;
···
1306
1306
struct drm_i915_private *i915 = rps_to_i915(rps);
1307
1307
u32 val;
1308
1308
1309
-
val = vlv_punit_read(i915, FB_GFX_FMAX_AT_VMAX_FUSE);
1309
+
val = vlv_iosf_sb_read(i915, VLV_IOSF_SB_PUNIT, FB_GFX_FMAX_AT_VMAX_FUSE);
1310
1310
1311
1311
return val & FB_GFX_FREQ_FUSE_MASK;
1312
1312
}
···
1316
1316
struct drm_i915_private *i915 = rps_to_i915(rps);
1317
1317
u32 val;
1318
1318
1319
-
val = vlv_punit_read(i915, FB_GFX_FMIN_AT_VMIN_FUSE);
1319
+
val = vlv_iosf_sb_read(i915, VLV_IOSF_SB_PUNIT, FB_GFX_FMIN_AT_VMIN_FUSE);
1320
1320
val >>= FB_GFX_FMIN_AT_VMIN_FUSE_SHIFT;
1321
1321
1322
1322
return val & FB_GFX_FREQ_FUSE_MASK;
···
1350
1350
GEN6_PM_RP_DOWN_TIMEOUT);
1351
1351
1352
1352
/* Setting Fixed Bias */
1353
-
vlv_punit_get(i915);
1353
+
vlv_iosf_sb_get(i915, BIT(VLV_IOSF_SB_PUNIT));
1354
1354
1355
1355
val = VLV_OVERRIDE_EN | VLV_SOC_TDP_EN | CHV_BIAS_CPU_50_SOC_50;
1356
-
vlv_punit_write(i915, VLV_TURBO_SOC_OVERRIDE, val);
1356
+
vlv_iosf_sb_write(i915, VLV_IOSF_SB_PUNIT, VLV_TURBO_SOC_OVERRIDE, val);
1357
1357
1358
-
val = vlv_punit_read(i915, PUNIT_REG_GPU_FREQ_STS);
1358
+
val = vlv_iosf_sb_read(i915, VLV_IOSF_SB_PUNIT, PUNIT_REG_GPU_FREQ_STS);
1359
1359
1360
-
vlv_punit_put(i915);
1360
+
vlv_iosf_sb_put(i915, BIT(VLV_IOSF_SB_PUNIT));
1361
1361
1362
1362
/* RPS code assumes GPLL is used */
1363
1363
drm_WARN_ONCE(&i915->drm, (val & GPLLENABLE) == 0,
···
1375
1375
struct drm_i915_private *i915 = rps_to_i915(rps);
1376
1376
u32 val, rp1;
1377
1377
1378
-
val = vlv_nc_read(i915, IOSF_NC_FB_GFX_FREQ_FUSE);
1378
+
val = vlv_iosf_sb_read(i915, VLV_IOSF_SB_NC, IOSF_NC_FB_GFX_FREQ_FUSE);
1379
1379
1380
1380
rp1 = val & FB_GFX_FGUARANTEED_FREQ_FUSE_MASK;
1381
1381
rp1 >>= FB_GFX_FGUARANTEED_FREQ_FUSE_SHIFT;
···
1388
1388
struct drm_i915_private *i915 = rps_to_i915(rps);
1389
1389
u32 val, rp0;
1390
1390
1391
-
val = vlv_nc_read(i915, IOSF_NC_FB_GFX_FREQ_FUSE);
1391
+
val = vlv_iosf_sb_read(i915, VLV_IOSF_SB_NC, IOSF_NC_FB_GFX_FREQ_FUSE);
1392
1392
1393
1393
rp0 = (val & FB_GFX_MAX_FREQ_FUSE_MASK) >> FB_GFX_MAX_FREQ_FUSE_SHIFT;
1394
1394
/* Clamp to max */
···
1402
1402
struct drm_i915_private *i915 = rps_to_i915(rps);
1403
1403
u32 val, rpe;
1404
1404
1405
-
val = vlv_nc_read(i915, IOSF_NC_FB_GFX_FMAX_FUSE_LO);
1405
+
val = vlv_iosf_sb_read(i915, VLV_IOSF_SB_NC, IOSF_NC_FB_GFX_FMAX_FUSE_LO);
1406
1406
rpe = (val & FB_FMAX_VMIN_FREQ_LO_MASK) >> FB_FMAX_VMIN_FREQ_LO_SHIFT;
1407
-
val = vlv_nc_read(i915, IOSF_NC_FB_GFX_FMAX_FUSE_HI);
1407
+
val = vlv_iosf_sb_read(i915, VLV_IOSF_SB_NC, IOSF_NC_FB_GFX_FMAX_FUSE_HI);
1408
1408
rpe |= (val & FB_FMAX_VMIN_FREQ_HI_MASK) << 5;
1409
1409
1410
1410
return rpe;
···
1415
1415
struct drm_i915_private *i915 = rps_to_i915(rps);
1416
1416
u32 val;
1417
1417
1418
-
val = vlv_punit_read(i915, PUNIT_REG_GPU_LFM) & 0xff;
1418
+
val = vlv_iosf_sb_read(i915, VLV_IOSF_SB_PUNIT, PUNIT_REG_GPU_LFM) & 0xff;
1419
1419
/*
1420
1420
* According to the BYT Punit GPU turbo HAS 1.1.6.3 the minimum value
1421
1421
* for the minimum frequency in GPLL mode is 0xc1. Contrary to this on
···
1451
1451
/* WaGsvRC0ResidencyMethod:vlv */
1452
1452
rps->pm_events = GEN6_PM_RP_UP_EI_EXPIRED;
1453
1453
1454
-
vlv_punit_get(i915);
1454
+
vlv_iosf_sb_get(i915, BIT(VLV_IOSF_SB_PUNIT));
1455
1455
1456
1456
/* Setting Fixed Bias */
1457
1457
val = VLV_OVERRIDE_EN | VLV_SOC_TDP_EN | VLV_BIAS_CPU_125_SOC_875;
1458
-
vlv_punit_write(i915, VLV_TURBO_SOC_OVERRIDE, val);
1458
+
vlv_iosf_sb_write(i915, VLV_IOSF_SB_PUNIT, VLV_TURBO_SOC_OVERRIDE, val);
1459
1459
1460
-
val = vlv_punit_read(i915, PUNIT_REG_GPU_FREQ_STS);
1460
+
val = vlv_iosf_sb_read(i915, VLV_IOSF_SB_PUNIT, PUNIT_REG_GPU_FREQ_STS);
1461
1461
1462
-
vlv_punit_put(i915);
1462
+
vlv_iosf_sb_put(i915, BIT(VLV_IOSF_SB_PUNIT));
1463
1463
1464
1464
/* RPS code assumes GPLL is used */
1465
1465
drm_WARN_ONCE(&i915->drm, (val & GPLLENABLE) == 0,
···
2107
2107
} else if (GRAPHICS_VER(i915) >= 12) {
2108
2108
r = GEN12_RPSTAT1;
2109
2109
} else if (IS_VALLEYVIEW(i915) || IS_CHERRYVIEW(i915)) {
2110
-
vlv_punit_get(i915);
2111
-
freq = vlv_punit_read(i915, PUNIT_REG_GPU_FREQ_STS);
2112
-
vlv_punit_put(i915);
2110
+
vlv_iosf_sb_get(i915, BIT(VLV_IOSF_SB_PUNIT));
2111
+
freq = vlv_iosf_sb_read(i915, VLV_IOSF_SB_PUNIT, PUNIT_REG_GPU_FREQ_STS);
2112
+
vlv_iosf_sb_put(i915, BIT(VLV_IOSF_SB_PUNIT));
2113
2113
} else if (GRAPHICS_VER(i915) >= 6) {
2114
2114
r = GEN6_RPSTAT1;
2115
2115
} else {
+2
-2
drivers/gpu/drm/i915/soc/intel_dram.c
+2
-2
drivers/gpu/drm/i915/soc/intel_dram.c
···
98
98
u32 val;
99
99
100
100
vlv_iosf_sb_get(i915, BIT(VLV_IOSF_SB_CCK));
101
-
val = vlv_cck_read(i915, CCK_FUSE_REG);
101
+
val = vlv_iosf_sb_read(i915, VLV_IOSF_SB_CCK, CCK_FUSE_REG);
102
102
vlv_iosf_sb_put(i915, BIT(VLV_IOSF_SB_CCK));
103
103
104
104
switch ((val >> 2) & 0x7) {
···
114
114
u32 val;
115
115
116
116
vlv_iosf_sb_get(i915, BIT(VLV_IOSF_SB_PUNIT));
117
-
val = vlv_punit_read(i915, PUNIT_REG_GPU_FREQ_STS);
117
+
val = vlv_iosf_sb_read(i915, VLV_IOSF_SB_PUNIT, PUNIT_REG_GPU_FREQ_STS);
118
118
vlv_iosf_sb_put(i915, BIT(VLV_IOSF_SB_PUNIT));
119
119
120
120
switch ((val >> 6) & 3) {