Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
Merge branches 'clk-marvell', 'clk-xilinx', 'clk-mediatek' and 'clk-loongson' into clk-next
- Add Mediatek MT8196 clk drivers
* clk-marvell:
clk: mmp: pxa1908: Instantiate power driver through auxiliary bus
* clk-xilinx:
clk: clocking-wizard: Fix output clock register offset for Versal platforms
clk: xilinx: Optimize divisor search in clk_wzrd_get_divisors_ver()
* clk-mediatek: (31 commits)
clk: mediatek: Add MT8196 vencsys clock support
clk: mediatek: Add MT8196 vdecsys clock support
clk: mediatek: Add MT8196 ovl1 clock support
clk: mediatek: Add MT8196 ovl0 clock support
clk: mediatek: Add MT8196 disp-ao clock support
clk: mediatek: Add MT8196 disp1 clock support
clk: mediatek: Add MT8196 disp0 clock support
clk: mediatek: Add MT8196 mfg clock support
clk: mediatek: Add MT8196 mdpsys clock support
clk: mediatek: Add MT8196 mcu clock support
clk: mediatek: Add MT8196 I2C clock support
clk: mediatek: Add MT8196 pextpsys clock support
clk: mediatek: Add MT8196 ufssys clock support
clk: mediatek: Add MT8196 peripheral clock support
clk: mediatek: Add MT8196 vlpckgen clock support
clk: mediatek: Add MT8196 topckgen2 clock support
clk: mediatek: Add MT8196 topckgen clock support
clk: mediatek: Add MT8196 apmixedsys clock support
dt-bindings: clock: mediatek: Describe MT8196 clock controllers
clk: mediatek: clk-mtk: Add MUX_DIV_GATE macro
...
* clk-loongson:
clk: loongson2: Add clock definitions for Loongson-2K0300 SoC
clk: loongson2: Avoid hardcoding firmware name of the reference clock
clk: loongson2: Allow zero divisors for dividers
clk: loongson2: Support scale clocks with an alternative mode
clk: loongson2: Allow specifying clock flags for gate clock
dt-bindings: clock: loongson2: Add Loongson-2K0300 compatible
+6414
-77
+15
-3
Documentation/devicetree/bindings/clock/loongson,ls2k-clk.yaml
+15
-3
Documentation/devicetree/bindings/clock/loongson,ls2k-clk.yaml
···
16
16
properties:
17
17
compatible:
18
18
enum:
19
+
- loongson,ls2k0300-clk
19
20
- loongson,ls2k0500-clk
20
21
- loongson,ls2k-clk # This is for Loongson-2K1000
21
22
- loongson,ls2k2000-clk
···
25
24
maxItems: 1
26
25
27
26
clocks:
28
-
items:
29
-
- description: 100m ref
27
+
maxItems: 1
30
28
31
29
clock-names:
32
30
items:
···
38
38
ID in its "clocks" phandle cell. See include/dt-bindings/clock/loongson,ls2k-clk.h
39
39
for the full list of Loongson-2 SoC clock IDs.
40
40
41
+
allOf:
42
+
- if:
43
+
properties:
44
+
compatible:
45
+
contains:
46
+
const: loongson,ls2k0300-clk
47
+
then:
48
+
properties:
49
+
clock-names: false
50
+
else:
51
+
required:
52
+
- clock-names
53
+
41
54
required:
42
55
- compatible
43
56
- reg
44
57
- clocks
45
-
- clock-names
46
58
- '#clock-cells'
47
59
48
60
additionalProperties: false
+112
Documentation/devicetree/bindings/clock/mediatek,mt8196-clock.yaml
+112
Documentation/devicetree/bindings/clock/mediatek,mt8196-clock.yaml
···
1
+
# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
2
+
%YAML 1.2
3
+
---
4
+
$id: http://devicetree.org/schemas/clock/mediatek,mt8196-clock.yaml#
5
+
$schema: http://devicetree.org/meta-schemas/core.yaml#
6
+
7
+
title: MediaTek Functional Clock Controller for MT8196
8
+
9
+
maintainers:
10
+
- Guangjie Song <guangjie.song@mediatek.com>
11
+
- Laura Nao <laura.nao@collabora.com>
12
+
13
+
description: |
14
+
The clock architecture in MediaTek SoCs is structured like below:
15
+
PLLs -->
16
+
dividers -->
17
+
muxes
18
+
-->
19
+
clock gate
20
+
21
+
The device nodes provide clock gate control in different IP blocks.
22
+
23
+
properties:
24
+
compatible:
25
+
items:
26
+
- enum:
27
+
- mediatek,mt8196-imp-iic-wrap-c
28
+
- mediatek,mt8196-imp-iic-wrap-e
29
+
- mediatek,mt8196-imp-iic-wrap-n
30
+
- mediatek,mt8196-imp-iic-wrap-w
31
+
- mediatek,mt8196-mdpsys0
32
+
- mediatek,mt8196-mdpsys1
33
+
- mediatek,mt8196-pericfg-ao
34
+
- mediatek,mt8196-pextp0cfg-ao
35
+
- mediatek,mt8196-pextp1cfg-ao
36
+
- mediatek,mt8196-ufscfg-ao
37
+
- mediatek,mt8196-vencsys
38
+
- mediatek,mt8196-vencsys-c1
39
+
- mediatek,mt8196-vencsys-c2
40
+
- mediatek,mt8196-vdecsys
41
+
- mediatek,mt8196-vdecsys-soc
42
+
- mediatek,mt8196-vdisp-ao
43
+
- const: syscon
44
+
45
+
reg:
46
+
maxItems: 1
47
+
48
+
'#clock-cells':
49
+
const: 1
50
+
51
+
'#reset-cells':
52
+
const: 1
53
+
description:
54
+
Reset lines for PEXTP0/1 and UFS blocks.
55
+
56
+
mediatek,hardware-voter:
57
+
$ref: /schemas/types.yaml#/definitions/phandle
58
+
description: |
59
+
Phandle to the "Hardware Voter" (HWV), as named in the vendor
60
+
documentation for MT8196/MT6991.
61
+
62
+
The HWV is a SoC-internal fixed-function MCU used to collect votes from
63
+
both the Application Processor and other remote processors within the SoC.
64
+
It is intended to transparently enable or disable hardware resources (such
65
+
as power domains or clocks) based on internal vote aggregation handled by
66
+
the MCU's internal state machine.
67
+
68
+
However, in practice, this design is incomplete. While the HWV performs
69
+
some internal vote aggregation,software is still required to
70
+
- Manually enable power supplies externally, if present and if required
71
+
- Manually enable parent clocks via direct MMIO writes to clock controllers
72
+
- Enable the FENC after the clock has been ungated via direct MMIO
73
+
writes to clock controllers
74
+
75
+
As such, the HWV behaves more like a hardware-managed clock reference
76
+
counter than a true voter. Furthermore, it is not a separate
77
+
controller. It merely serves as an alternative interface to the same
78
+
underlying clock or power controller. Actual control still requires
79
+
direct access to the controller's own MMIO register space, in
80
+
addition to writing to the HWV's MMIO region.
81
+
82
+
For this reason, a custom phandle is used here - drivers need to directly
83
+
access the HWV MMIO region in a syscon-like fashion, due to how the
84
+
hardware is wired. This differs from true hardware voting systems, which
85
+
typically do not require custom phandles and rely instead on generic APIs
86
+
(clocks, power domains, interconnects).
87
+
88
+
The name "hardware-voter" is retained to match vendor documentation, but
89
+
this should not be reused or misunderstood as a proper voting mechanism.
90
+
91
+
required:
92
+
- compatible
93
+
- reg
94
+
- '#clock-cells'
95
+
96
+
additionalProperties: false
97
+
98
+
examples:
99
+
- |
100
+
pericfg_ao: clock-controller@16640000 {
101
+
compatible = "mediatek,mt8196-pericfg-ao", "syscon";
102
+
reg = <0x16640000 0x1000>;
103
+
mediatek,hardware-voter = <&scp_hwv>;
104
+
#clock-cells = <1>;
105
+
};
106
+
- |
107
+
pextp0cfg_ao: clock-controller@169b0000 {
108
+
compatible = "mediatek,mt8196-pextp0cfg-ao", "syscon";
109
+
reg = <0x169b0000 0x1000>;
110
+
#clock-cells = <1>;
111
+
#reset-cells = <1>;
112
+
};
+107
Documentation/devicetree/bindings/clock/mediatek,mt8196-sys-clock.yaml
+107
Documentation/devicetree/bindings/clock/mediatek,mt8196-sys-clock.yaml
···
1
+
# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
2
+
%YAML 1.2
3
+
---
4
+
$id: http://devicetree.org/schemas/clock/mediatek,mt8196-sys-clock.yaml#
5
+
$schema: http://devicetree.org/meta-schemas/core.yaml#
6
+
7
+
title: MediaTek System Clock Controller for MT8196
8
+
9
+
maintainers:
10
+
- Guangjie Song <guangjie.song@mediatek.com>
11
+
- Laura Nao <laura.nao@collabora.com>
12
+
13
+
description: |
14
+
The clock architecture in MediaTek SoCs is structured like below:
15
+
PLLs -->
16
+
dividers -->
17
+
muxes
18
+
-->
19
+
clock gate
20
+
21
+
The apmixedsys, apmixedsys_gp2, vlpckgen, armpll, ccipll, mfgpll and ptppll
22
+
provide most of the PLLs which are generated from the SoC's 26MHZ crystal oscillator.
23
+
The topckgen, topckgen_gp2 and vlpckgen provide dividers and muxes which
24
+
provide the clock source to other IP blocks.
25
+
26
+
properties:
27
+
compatible:
28
+
items:
29
+
- enum:
30
+
- mediatek,mt8196-apmixedsys
31
+
- mediatek,mt8196-armpll-b-pll-ctrl
32
+
- mediatek,mt8196-armpll-bl-pll-ctrl
33
+
- mediatek,mt8196-armpll-ll-pll-ctrl
34
+
- mediatek,mt8196-apmixedsys-gp2
35
+
- mediatek,mt8196-ccipll-pll-ctrl
36
+
- mediatek,mt8196-mfgpll-pll-ctrl
37
+
- mediatek,mt8196-mfgpll-sc0-pll-ctrl
38
+
- mediatek,mt8196-mfgpll-sc1-pll-ctrl
39
+
- mediatek,mt8196-ptppll-pll-ctrl
40
+
- mediatek,mt8196-topckgen
41
+
- mediatek,mt8196-topckgen-gp2
42
+
- mediatek,mt8196-vlpckgen
43
+
- const: syscon
44
+
45
+
reg:
46
+
maxItems: 1
47
+
48
+
'#clock-cells':
49
+
const: 1
50
+
51
+
mediatek,hardware-voter:
52
+
$ref: /schemas/types.yaml#/definitions/phandle
53
+
description: |
54
+
Phandle to the "Hardware Voter" (HWV), as named in the vendor
55
+
documentation for MT8196/MT6991.
56
+
57
+
The HWV is a SoC-internal fixed-function MCU used to collect votes from
58
+
both the Application Processor and other remote processors within the SoC.
59
+
It is intended to transparently enable or disable hardware resources (such
60
+
as power domains or clocks) based on internal vote aggregation handled by
61
+
the MCU's internal state machine.
62
+
63
+
However, in practice, this design is incomplete. While the HWV performs
64
+
some internal vote aggregation,software is still required to
65
+
- Manually enable power supplies externally, if present and if required
66
+
- Manually enable parent clocks via direct MMIO writes to clock controllers
67
+
- Enable the FENC after the clock has been ungated via direct MMIO
68
+
writes to clock controllers
69
+
70
+
As such, the HWV behaves more like a hardware-managed clock reference
71
+
counter than a true voter. Furthermore, it is not a separate
72
+
controller. It merely serves as an alternative interface to the same
73
+
underlying clock or power controller. Actual control still requires
74
+
direct access to the controller's own MMIO register space, in
75
+
addition to writing to the HWV's MMIO region.
76
+
77
+
For this reason, a custom phandle is used here - drivers need to directly
78
+
access the HWV MMIO region in a syscon-like fashion, due to how the
79
+
hardware is wired. This differs from true hardware voting systems, which
80
+
typically do not require custom phandles and rely instead on generic APIs
81
+
(clocks, power domains, interconnects).
82
+
83
+
The name "hardware-voter" is retained to match vendor documentation, but
84
+
this should not be reused or misunderstood as a proper voting mechanism.
85
+
86
+
required:
87
+
- compatible
88
+
- reg
89
+
- '#clock-cells'
90
+
91
+
additionalProperties: false
92
+
93
+
examples:
94
+
- |
95
+
apmixedsys_clk: syscon@10000800 {
96
+
compatible = "mediatek,mt8196-apmixedsys", "syscon";
97
+
reg = <0x10000800 0x1000>;
98
+
#clock-cells = <1>;
99
+
};
100
+
- |
101
+
topckgen: syscon@10000000 {
102
+
compatible = "mediatek,mt8196-topckgen", "syscon";
103
+
reg = <0x10000000 0x800>;
104
+
mediatek,hardware-voter = <&scp_hwv>;
105
+
#clock-cells = <1>;
106
+
};
107
+
+2
MAINTAINERS
+2
MAINTAINERS
···
2869
2869
M: Duje Mihanović <duje@dujemihanovic.xyz>
2870
2870
L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)
2871
2871
S: Maintained
2872
+
F: Documentation/devicetree/bindings/clock/marvell,pxa1908.yaml
2872
2873
F: arch/arm64/boot/dts/marvell/mmp/
2874
+
F: drivers/clk/mmp/Kconfig
2873
2875
F: drivers/clk/mmp/clk-pxa1908*.c
2874
2876
F: include/dt-bindings/clock/marvell,pxa1908.h
2875
2877
+1
drivers/clk/Kconfig
+1
drivers/clk/Kconfig
···
512
512
source "drivers/clk/ingenic/Kconfig"
513
513
source "drivers/clk/keystone/Kconfig"
514
514
source "drivers/clk/mediatek/Kconfig"
515
+
source "drivers/clk/mmp/Kconfig"
515
516
source "drivers/clk/meson/Kconfig"
516
517
source "drivers/clk/mstar/Kconfig"
517
518
source "drivers/clk/microchip/Kconfig"
+102
-20
drivers/clk/clk-loongson2.c
+102
-20
drivers/clk/clk-loongson2.c
···
13
13
#include <linux/io-64-nonatomic-lo-hi.h>
14
14
#include <dt-bindings/clock/loongson,ls2k-clk.h>
15
15
16
-
static const struct clk_parent_data pdata[] = {
17
-
{ .fw_name = "ref_100m", },
18
-
};
19
-
20
16
enum loongson2_clk_type {
21
17
CLK_TYPE_PLL,
22
18
CLK_TYPE_SCALE,
···
38
42
u8 div_width;
39
43
u8 mult_shift;
40
44
u8 mult_width;
45
+
u8 bit_idx;
41
46
};
42
47
43
48
struct loongson2_clk_board_info {
···
47
50
const char *name;
48
51
const char *parent_name;
49
52
unsigned long fixed_rate;
53
+
unsigned long flags;
50
54
u8 reg_offset;
51
55
u8 div_shift;
52
56
u8 div_width;
···
93
95
.div_width = _dwidth, \
94
96
}
95
97
98
+
#define CLK_SCALE_MODE(_id, _name, _pname, _offset, \
99
+
_dshift, _dwidth, _midx) \
100
+
{ \
101
+
.id = _id, \
102
+
.type = CLK_TYPE_SCALE, \
103
+
.name = _name, \
104
+
.parent_name = _pname, \
105
+
.reg_offset = _offset, \
106
+
.div_shift = _dshift, \
107
+
.div_width = _dwidth, \
108
+
.bit_idx = _midx + 1, \
109
+
}
110
+
96
111
#define CLK_GATE(_id, _name, _pname, _offset, _bidx) \
97
112
{ \
98
113
.id = _id, \
···
116
105
.bit_idx = _bidx, \
117
106
}
118
107
108
+
#define CLK_GATE_FLAGS(_id, _name, _pname, _offset, _bidx, \
109
+
_flags) \
110
+
{ \
111
+
.id = _id, \
112
+
.type = CLK_TYPE_GATE, \
113
+
.name = _name, \
114
+
.parent_name = _pname, \
115
+
.reg_offset = _offset, \
116
+
.bit_idx = _bidx, \
117
+
.flags = _flags \
118
+
}
119
+
119
120
#define CLK_FIXED(_id, _name, _pname, _rate) \
120
121
{ \
121
122
.id = _id, \
···
136
113
.parent_name = _pname, \
137
114
.fixed_rate = _rate, \
138
115
}
116
+
117
+
static const struct loongson2_clk_board_info ls2k0300_clks[] = {
118
+
/* Reference Clock */
119
+
CLK_PLL(LS2K0300_NODE_PLL, "pll_node", 0x00, 15, 9, 8, 7),
120
+
CLK_PLL(LS2K0300_DDR_PLL, "pll_ddr", 0x08, 15, 9, 8, 7),
121
+
CLK_PLL(LS2K0300_PIX_PLL, "pll_pix", 0x10, 15, 9, 8, 7),
122
+
CLK_FIXED(LS2K0300_CLK_STABLE, "clk_stable", NULL, 100000000),
123
+
CLK_FIXED(LS2K0300_CLK_THSENS, "clk_thsens", NULL, 10000000),
124
+
/* Node PLL */
125
+
CLK_DIV(LS2K0300_CLK_NODE_DIV, "clk_node_div", "pll_node", 0x00, 24, 7),
126
+
CLK_DIV(LS2K0300_CLK_GMAC_DIV, "clk_gmac_div", "pll_node", 0x04, 0, 7),
127
+
CLK_DIV(LS2K0300_CLK_I2S_DIV, "clk_i2s_div", "pll_node", 0x04, 8, 7),
128
+
CLK_GATE(LS2K0300_CLK_NODE_PLL_GATE, "clk_node_pll_gate", "clk_node_div", 0x00, 0),
129
+
CLK_GATE(LS2K0300_CLK_GMAC_GATE, "clk_gmac_gate", "clk_gmac_div", 0x00, 1),
130
+
CLK_GATE(LS2K0300_CLK_I2S_GATE, "clk_i2s_gate", "clk_i2s_div", 0x00, 2),
131
+
CLK_GATE_FLAGS(LS2K0300_CLK_NODE_GATE, "clk_node_gate", "clk_node_scale", 0x24, 0,
132
+
CLK_IS_CRITICAL),
133
+
CLK_SCALE_MODE(LS2K0300_CLK_NODE_SCALE, "clk_node_scale", "clk_node_pll_gate", 0x20, 0, 3,
134
+
3),
135
+
/* DDR PLL */
136
+
CLK_DIV(LS2K0300_CLK_DDR_DIV, "clk_ddr_div", "pll_ddr", 0x08, 24, 7),
137
+
CLK_DIV(LS2K0300_CLK_NET_DIV, "clk_net_div", "pll_ddr", 0x0c, 0, 7),
138
+
CLK_DIV(LS2K0300_CLK_DEV_DIV, "clk_dev_div", "pll_ddr", 0x0c, 8, 7),
139
+
CLK_GATE(LS2K0300_CLK_NET_GATE, "clk_net_gate", "clk_net_div", 0x08, 1),
140
+
CLK_GATE(LS2K0300_CLK_DEV_GATE, "clk_dev_gate", "clk_dev_div", 0x08, 2),
141
+
CLK_GATE_FLAGS(LS2K0300_CLK_DDR_GATE, "clk_ddr_gate", "clk_ddr_div", 0x08, 0,
142
+
CLK_IS_CRITICAL),
143
+
/* PIX PLL */
144
+
CLK_DIV(LS2K0300_CLK_PIX_DIV, "clk_pix_div", "pll_pix", 0x10, 24, 7),
145
+
CLK_DIV(LS2K0300_CLK_GMACBP_DIV, "clk_gmacbp_div", "pll_pix", 0x14, 0, 7),
146
+
CLK_GATE(LS2K0300_CLK_PIX_PLL_GATE, "clk_pix_pll_gate", "clk_pix_div", 0x10, 0),
147
+
CLK_GATE(LS2K0300_CLK_PIX_GATE, "clk_pix_gate", "clk_pix_scale", 0x24, 6),
148
+
CLK_GATE(LS2K0300_CLK_GMACBP_GATE, "clk_gmacbp_gate", "clk_gmacbp_div", 0x10, 1),
149
+
CLK_SCALE_MODE(LS2K0300_CLK_PIX_SCALE, "clk_pix_scale", "clk_pix_pll_gate", 0x20, 4, 3, 7),
150
+
/* clk_dev_gate */
151
+
CLK_DIV(LS2K0300_CLK_SDIO_SCALE, "clk_sdio_scale", "clk_dev_gate", 0x20, 24, 4),
152
+
CLK_GATE(LS2K0300_CLK_USB_GATE, "clk_usb_gate", "clk_usb_scale", 0x24, 2),
153
+
CLK_GATE(LS2K0300_CLK_SDIO_GATE, "clk_sdio_gate", "clk_sdio_scale", 0x24, 4),
154
+
CLK_GATE(LS2K0300_CLK_APB_GATE, "clk_apb_gate", "clk_apb_scale", 0x24, 3),
155
+
CLK_GATE_FLAGS(LS2K0300_CLK_BOOT_GATE, "clk_boot_gate", "clk_boot_scale", 0x24, 1,
156
+
CLK_IS_CRITICAL),
157
+
CLK_SCALE_MODE(LS2K0300_CLK_USB_SCALE, "clk_usb_scale", "clk_dev_gate", 0x20, 12, 3, 15),
158
+
CLK_SCALE_MODE(LS2K0300_CLK_APB_SCALE, "clk_apb_scale", "clk_dev_gate", 0x20, 16, 3, 19),
159
+
CLK_SCALE_MODE(LS2K0300_CLK_BOOT_SCALE, "clk_boot_scale", "clk_dev_gate", 0x20, 8, 3, 11),
160
+
};
139
161
140
162
static const struct loongson2_clk_board_info ls2k0500_clks[] = {
141
163
CLK_PLL(LOONGSON2_NODE_PLL, "pll_node", 0, 16, 8, 8, 6),
···
298
230
static unsigned long loongson2_freqscale_recalc_rate(struct clk_hw *hw,
299
231
unsigned long parent_rate)
300
232
{
301
-
u64 val, mult;
233
+
u64 val, scale;
234
+
u32 mode = 0;
302
235
struct loongson2_clk_data *clk = to_loongson2_clk(hw);
303
236
304
237
val = readq(clk->reg);
305
-
mult = loongson2_rate_part(val, clk->div_shift, clk->div_width) + 1;
238
+
scale = loongson2_rate_part(val, clk->div_shift, clk->div_width) + 1;
306
239
307
-
return div_u64((u64)parent_rate * mult, 8);
240
+
if (clk->bit_idx)
241
+
mode = val & BIT(clk->bit_idx - 1);
242
+
243
+
return mode == 0 ? div_u64((u64)parent_rate * scale, 8) :
244
+
div_u64((u64)parent_rate, scale);
308
245
}
309
246
310
247
static const struct clk_ops loongson2_freqscale_recalc_ops = {
311
248
.recalc_rate = loongson2_freqscale_recalc_rate,
312
249
};
313
250
314
-
static struct clk_hw *loongson2_clk_register(struct loongson2_clk_provider *clp,
251
+
static struct clk_hw *loongson2_clk_register(const char *parent,
252
+
struct loongson2_clk_provider *clp,
315
253
const struct loongson2_clk_board_info *cld,
316
254
const struct clk_ops *ops)
317
255
{
···
334
260
init.ops = ops;
335
261
init.flags = 0;
336
262
init.num_parents = 1;
337
-
338
-
if (!cld->parent_name)
339
-
init.parent_data = pdata;
340
-
else
341
-
init.parent_names = &cld->parent_name;
263
+
init.parent_names = &parent;
342
264
343
265
clk->reg = clp->base + cld->reg_offset;
344
266
clk->div_shift = cld->div_shift;
345
267
clk->div_width = cld->div_width;
346
268
clk->mult_shift = cld->mult_shift;
347
269
clk->mult_width = cld->mult_width;
270
+
clk->bit_idx = cld->bit_idx;
348
271
clk->hw.init = &init;
349
272
350
273
hw = &clk->hw;
···
359
288
struct device *dev = &pdev->dev;
360
289
struct loongson2_clk_provider *clp;
361
290
const struct loongson2_clk_board_info *p, *data;
291
+
const char *refclk_name, *parent_name;
362
292
363
293
data = device_get_match_data(dev);
364
294
if (!data)
365
295
return -EINVAL;
296
+
297
+
refclk_name = of_clk_get_parent_name(dev->of_node, 0);
298
+
if (IS_ERR(refclk_name))
299
+
return dev_err_probe(dev, PTR_ERR(refclk_name),
300
+
"failed to get refclk name\n");
366
301
367
302
for (p = data; p->name; p++)
368
303
clks_num = max(clks_num, p->id + 1);
···
391
314
392
315
for (i = 0; i < clks_num; i++) {
393
316
p = &data[i];
317
+
parent_name = p->parent_name ? p->parent_name : refclk_name;
318
+
394
319
switch (p->type) {
395
320
case CLK_TYPE_PLL:
396
-
hw = loongson2_clk_register(clp, p,
321
+
hw = loongson2_clk_register(parent_name, clp, p,
397
322
&loongson2_pll_recalc_ops);
398
323
break;
399
324
case CLK_TYPE_SCALE:
400
-
hw = loongson2_clk_register(clp, p,
325
+
hw = loongson2_clk_register(parent_name, clp, p,
401
326
&loongson2_freqscale_recalc_ops);
402
327
break;
403
328
case CLK_TYPE_DIVIDER:
404
329
hw = devm_clk_hw_register_divider(dev, p->name,
405
-
p->parent_name, 0,
330
+
parent_name, 0,
406
331
clp->base + p->reg_offset,
407
332
p->div_shift, p->div_width,
408
-
CLK_DIVIDER_ONE_BASED,
333
+
CLK_DIVIDER_ONE_BASED |
334
+
CLK_DIVIDER_ALLOW_ZERO,
409
335
&clp->clk_lock);
410
336
break;
411
337
case CLK_TYPE_GATE:
412
-
hw = devm_clk_hw_register_gate(dev, p->name, p->parent_name, 0,
338
+
hw = devm_clk_hw_register_gate(dev, p->name, parent_name,
339
+
p->flags,
413
340
clp->base + p->reg_offset,
414
341
p->bit_idx, 0,
415
342
&clp->clk_lock);
416
343
break;
417
344
case CLK_TYPE_FIXED:
418
-
hw = devm_clk_hw_register_fixed_rate_parent_data(dev, p->name, pdata,
419
-
0, p->fixed_rate);
345
+
hw = devm_clk_hw_register_fixed_rate(dev, p->name, parent_name,
346
+
0, p->fixed_rate);
420
347
break;
421
348
default:
422
349
return dev_err_probe(dev, -EINVAL, "Invalid clk type\n");
···
438
357
}
439
358
440
359
static const struct of_device_id loongson2_clk_match_table[] = {
360
+
{ .compatible = "loongson,ls2k0300-clk", .data = &ls2k0300_clks },
441
361
{ .compatible = "loongson,ls2k0500-clk", .data = &ls2k0500_clks },
442
362
{ .compatible = "loongson,ls2k-clk", .data = &ls2k1000_clks },
443
363
{ .compatible = "loongson,ls2k2000-clk", .data = &ls2k2000_clks },
+71
drivers/clk/mediatek/Kconfig
+71
drivers/clk/mediatek/Kconfig
···
1002
1002
help
1003
1003
This driver supports MediaTek MT8195 vencsys clocks.
1004
1004
1005
+
config COMMON_CLK_MT8196
1006
+
tristate "Clock driver for MediaTek MT8196"
1007
+
depends on ARM64 || COMPILE_TEST
1008
+
select COMMON_CLK_MEDIATEK
1009
+
default ARCH_MEDIATEK
1010
+
help
1011
+
This driver supports MediaTek MT8196 basic clocks.
1012
+
1013
+
config COMMON_CLK_MT8196_IMP_IIC_WRAP
1014
+
tristate "Clock driver for MediaTek MT8196 imp_iic_wrap"
1015
+
depends on COMMON_CLK_MT8196
1016
+
default COMMON_CLK_MT8196
1017
+
help
1018
+
This driver supports MediaTek MT8196 i2c clocks.
1019
+
1020
+
config COMMON_CLK_MT8196_MCUSYS
1021
+
tristate "Clock driver for MediaTek MT8196 mcusys"
1022
+
depends on COMMON_CLK_MT8196
1023
+
default COMMON_CLK_MT8196
1024
+
help
1025
+
This driver supports MediaTek MT8196 mcusys clocks.
1026
+
1027
+
config COMMON_CLK_MT8196_MDPSYS
1028
+
tristate "Clock driver for MediaTek MT8196 mdpsys"
1029
+
depends on COMMON_CLK_MT8196
1030
+
default COMMON_CLK_MT8196
1031
+
help
1032
+
This driver supports MediaTek MT8196 mdpsys clocks.
1033
+
1034
+
config COMMON_CLK_MT8196_MFGCFG
1035
+
tristate "Clock driver for MediaTek MT8196 mfgcfg"
1036
+
depends on COMMON_CLK_MT8196
1037
+
default m
1038
+
help
1039
+
This driver supports MediaTek MT8196 mfgcfg clocks.
1040
+
1041
+
config COMMON_CLK_MT8196_MMSYS
1042
+
tristate "Clock driver for MediaTek MT8196 mmsys"
1043
+
depends on COMMON_CLK_MT8196
1044
+
default m
1045
+
help
1046
+
This driver supports MediaTek MT8196 mmsys clocks.
1047
+
1048
+
config COMMON_CLK_MT8196_PEXTPSYS
1049
+
tristate "Clock driver for MediaTek MT8196 pextpsys"
1050
+
depends on COMMON_CLK_MT8196
1051
+
default COMMON_CLK_MT8196
1052
+
help
1053
+
This driver supports MediaTek MT8196 pextpsys clocks.
1054
+
1055
+
config COMMON_CLK_MT8196_UFSSYS
1056
+
tristate "Clock driver for MediaTek MT8196 ufssys"
1057
+
depends on COMMON_CLK_MT8196
1058
+
default COMMON_CLK_MT8196
1059
+
help
1060
+
This driver supports MediaTek MT8196 ufssys clocks.
1061
+
1062
+
config COMMON_CLK_MT8196_VDECSYS
1063
+
tristate "Clock driver for MediaTek MT8196 vdecsys"
1064
+
depends on COMMON_CLK_MT8196
1065
+
default m
1066
+
help
1067
+
This driver supports MediaTek MT8196 vdecsys clocks.
1068
+
1069
+
config COMMON_CLK_MT8196_VENCSYS
1070
+
tristate "Clock driver for MediaTek MT8196 vencsys"
1071
+
depends on COMMON_CLK_MT8196
1072
+
default m
1073
+
help
1074
+
This driver supports MediaTek MT8196 vencsys clocks.
1075
+
1005
1076
config COMMON_CLK_MT8365
1006
1077
tristate "Clock driver for MediaTek MT8365"
1007
1078
depends on ARCH_MEDIATEK || COMPILE_TEST
+13
drivers/clk/mediatek/Makefile
+13
drivers/clk/mediatek/Makefile
···
150
150
obj-$(CONFIG_COMMON_CLK_MT8195_VENCSYS) += clk-mt8195-venc.o
151
151
obj-$(CONFIG_COMMON_CLK_MT8195_VPPSYS) += clk-mt8195-vpp0.o clk-mt8195-vpp1.o
152
152
obj-$(CONFIG_COMMON_CLK_MT8195_WPESYS) += clk-mt8195-wpe.o
153
+
obj-$(CONFIG_COMMON_CLK_MT8196) += clk-mt8196-apmixedsys.o clk-mt8196-topckgen.o \
154
+
clk-mt8196-topckgen2.o clk-mt8196-vlpckgen.o \
155
+
clk-mt8196-peri_ao.o
156
+
obj-$(CONFIG_COMMON_CLK_MT8196_IMP_IIC_WRAP) += clk-mt8196-imp_iic_wrap.o
157
+
obj-$(CONFIG_COMMON_CLK_MT8196_MCUSYS) += clk-mt8196-mcu.o
158
+
obj-$(CONFIG_COMMON_CLK_MT8196_MDPSYS) += clk-mt8196-mdpsys.o
159
+
obj-$(CONFIG_COMMON_CLK_MT8196_MFGCFG) += clk-mt8196-mfg.o
160
+
obj-$(CONFIG_COMMON_CLK_MT8196_MMSYS) += clk-mt8196-disp0.o clk-mt8196-disp1.o clk-mt8196-vdisp_ao.o \
161
+
clk-mt8196-ovl0.o clk-mt8196-ovl1.o
162
+
obj-$(CONFIG_COMMON_CLK_MT8196_PEXTPSYS) += clk-mt8196-pextp.o
163
+
obj-$(CONFIG_COMMON_CLK_MT8196_UFSSYS) += clk-mt8196-ufs_ao.o
164
+
obj-$(CONFIG_COMMON_CLK_MT8196_VDECSYS) += clk-mt8196-vdec.o
165
+
obj-$(CONFIG_COMMON_CLK_MT8196_VENCSYS) += clk-mt8196-venc.o
153
166
obj-$(CONFIG_COMMON_CLK_MT8365) += clk-mt8365-apmixedsys.o clk-mt8365.o
154
167
obj-$(CONFIG_COMMON_CLK_MT8365_APU) += clk-mt8365-apu.o
155
168
obj-$(CONFIG_COMMON_CLK_MT8365_CAM) += clk-mt8365-cam.o
+84
-33
drivers/clk/mediatek/clk-gate.c
+84
-33
drivers/clk/mediatek/clk-gate.c
···
5
5
*/
6
6
7
7
#include <linux/clk-provider.h>
8
+
#include <linux/dev_printk.h>
8
9
#include <linux/mfd/syscon.h>
9
10
#include <linux/module.h>
10
11
#include <linux/printk.h>
···
13
12
#include <linux/slab.h>
14
13
#include <linux/types.h>
15
14
15
+
#include "clk-mtk.h"
16
16
#include "clk-gate.h"
17
17
18
18
struct mtk_clk_gate {
19
19
struct clk_hw hw;
20
20
struct regmap *regmap;
21
-
int set_ofs;
22
-
int clr_ofs;
23
-
int sta_ofs;
24
-
u8 bit;
21
+
struct regmap *regmap_hwv;
22
+
const struct mtk_gate *gate;
25
23
};
26
24
27
25
static inline struct mtk_clk_gate *to_mtk_clk_gate(struct clk_hw *hw)
···
33
33
struct mtk_clk_gate *cg = to_mtk_clk_gate(hw);
34
34
u32 val;
35
35
36
-
regmap_read(cg->regmap, cg->sta_ofs, &val);
36
+
regmap_read(cg->regmap, cg->gate->regs->sta_ofs, &val);
37
37
38
-
return val & BIT(cg->bit);
38
+
return val & BIT(cg->gate->shift);
39
39
}
40
40
41
41
static int mtk_cg_bit_is_cleared(struct clk_hw *hw)
···
52
52
{
53
53
struct mtk_clk_gate *cg = to_mtk_clk_gate(hw);
54
54
55
-
regmap_write(cg->regmap, cg->set_ofs, BIT(cg->bit));
55
+
regmap_write(cg->regmap, cg->gate->regs->set_ofs, BIT(cg->gate->shift));
56
56
}
57
57
58
58
static void mtk_cg_clr_bit(struct clk_hw *hw)
59
59
{
60
60
struct mtk_clk_gate *cg = to_mtk_clk_gate(hw);
61
61
62
-
regmap_write(cg->regmap, cg->clr_ofs, BIT(cg->bit));
62
+
regmap_write(cg->regmap, cg->gate->regs->clr_ofs, BIT(cg->gate->shift));
63
63
}
64
64
65
65
static void mtk_cg_set_bit_no_setclr(struct clk_hw *hw)
66
66
{
67
67
struct mtk_clk_gate *cg = to_mtk_clk_gate(hw);
68
68
69
-
regmap_set_bits(cg->regmap, cg->sta_ofs, BIT(cg->bit));
69
+
regmap_set_bits(cg->regmap, cg->gate->regs->sta_ofs,
70
+
BIT(cg->gate->shift));
70
71
}
71
72
72
73
static void mtk_cg_clr_bit_no_setclr(struct clk_hw *hw)
73
74
{
74
75
struct mtk_clk_gate *cg = to_mtk_clk_gate(hw);
75
76
76
-
regmap_clear_bits(cg->regmap, cg->sta_ofs, BIT(cg->bit));
77
+
regmap_clear_bits(cg->regmap, cg->gate->regs->sta_ofs,
78
+
BIT(cg->gate->shift));
77
79
}
78
80
79
81
static int mtk_cg_enable(struct clk_hw *hw)
···
102
100
mtk_cg_clr_bit(hw);
103
101
}
104
102
103
+
static int mtk_cg_hwv_set_en(struct clk_hw *hw, bool enable)
104
+
{
105
+
struct mtk_clk_gate *cg = to_mtk_clk_gate(hw);
106
+
u32 val;
107
+
108
+
regmap_write(cg->regmap_hwv,
109
+
enable ? cg->gate->hwv_regs->set_ofs :
110
+
cg->gate->hwv_regs->clr_ofs,
111
+
BIT(cg->gate->shift));
112
+
113
+
return regmap_read_poll_timeout_atomic(cg->regmap_hwv,
114
+
cg->gate->hwv_regs->sta_ofs, val,
115
+
val & BIT(cg->gate->shift), 0,
116
+
MTK_WAIT_HWV_DONE_US);
117
+
}
118
+
119
+
static int mtk_cg_hwv_enable(struct clk_hw *hw)
120
+
{
121
+
return mtk_cg_hwv_set_en(hw, true);
122
+
}
123
+
124
+
static void mtk_cg_hwv_disable(struct clk_hw *hw)
125
+
{
126
+
mtk_cg_hwv_set_en(hw, false);
127
+
}
128
+
105
129
static int mtk_cg_enable_no_setclr(struct clk_hw *hw)
106
130
{
107
131
mtk_cg_clr_bit_no_setclr(hw);
···
152
124
mtk_cg_clr_bit_no_setclr(hw);
153
125
}
154
126
127
+
static bool mtk_cg_uses_hwv(const struct clk_ops *ops)
128
+
{
129
+
if (ops == &mtk_clk_gate_hwv_ops_setclr ||
130
+
ops == &mtk_clk_gate_hwv_ops_setclr_inv)
131
+
return true;
132
+
133
+
return false;
134
+
}
135
+
155
136
const struct clk_ops mtk_clk_gate_ops_setclr = {
156
137
.is_enabled = mtk_cg_bit_is_cleared,
157
138
.enable = mtk_cg_enable,
···
174
137
.disable = mtk_cg_disable_inv,
175
138
};
176
139
EXPORT_SYMBOL_GPL(mtk_clk_gate_ops_setclr_inv);
140
+
141
+
const struct clk_ops mtk_clk_gate_hwv_ops_setclr = {
142
+
.is_enabled = mtk_cg_bit_is_cleared,
143
+
.enable = mtk_cg_hwv_enable,
144
+
.disable = mtk_cg_hwv_disable,
145
+
};
146
+
EXPORT_SYMBOL_GPL(mtk_clk_gate_hwv_ops_setclr);
147
+
148
+
const struct clk_ops mtk_clk_gate_hwv_ops_setclr_inv = {
149
+
.is_enabled = mtk_cg_bit_is_set,
150
+
.enable = mtk_cg_hwv_enable,
151
+
.disable = mtk_cg_hwv_disable,
152
+
};
153
+
EXPORT_SYMBOL_GPL(mtk_clk_gate_hwv_ops_setclr_inv);
177
154
178
155
const struct clk_ops mtk_clk_gate_ops_no_setclr = {
179
156
.is_enabled = mtk_cg_bit_is_cleared,
···
203
152
};
204
153
EXPORT_SYMBOL_GPL(mtk_clk_gate_ops_no_setclr_inv);
205
154
206
-
static struct clk_hw *mtk_clk_register_gate(struct device *dev, const char *name,
207
-
const char *parent_name,
208
-
struct regmap *regmap, int set_ofs,
209
-
int clr_ofs, int sta_ofs, u8 bit,
210
-
const struct clk_ops *ops,
211
-
unsigned long flags)
155
+
static struct clk_hw *mtk_clk_register_gate(struct device *dev,
156
+
const struct mtk_gate *gate,
157
+
struct regmap *regmap,
158
+
struct regmap *regmap_hwv)
212
159
{
213
160
struct mtk_clk_gate *cg;
214
161
int ret;
···
216
167
if (!cg)
217
168
return ERR_PTR(-ENOMEM);
218
169
219
-
init.name = name;
220
-
init.flags = flags | CLK_SET_RATE_PARENT;
221
-
init.parent_names = parent_name ? &parent_name : NULL;
222
-
init.num_parents = parent_name ? 1 : 0;
223
-
init.ops = ops;
170
+
init.name = gate->name;
171
+
init.flags = gate->flags | CLK_SET_RATE_PARENT;
172
+
init.parent_names = gate->parent_name ? &gate->parent_name : NULL;
173
+
init.num_parents = gate->parent_name ? 1 : 0;
174
+
init.ops = gate->ops;
175
+
if (mtk_cg_uses_hwv(init.ops) && !regmap_hwv)
176
+
return dev_err_ptr_probe(
177
+
dev, -ENXIO,
178
+
"regmap not found for hardware voter clocks\n");
224
179
225
180
cg->regmap = regmap;
226
-
cg->set_ofs = set_ofs;
227
-
cg->clr_ofs = clr_ofs;
228
-
cg->sta_ofs = sta_ofs;
229
-
cg->bit = bit;
230
-
181
+
cg->regmap_hwv = regmap_hwv;
182
+
cg->gate = gate;
231
183
cg->hw.init = &init;
232
184
233
185
ret = clk_hw_register(dev, &cg->hw);
···
259
209
int i;
260
210
struct clk_hw *hw;
261
211
struct regmap *regmap;
212
+
struct regmap *regmap_hwv;
262
213
263
214
if (!clk_data)
264
215
return -ENOMEM;
···
270
219
return PTR_ERR(regmap);
271
220
}
272
221
222
+
regmap_hwv = mtk_clk_get_hwv_regmap(node);
223
+
if (IS_ERR(regmap_hwv))
224
+
return dev_err_probe(
225
+
dev, PTR_ERR(regmap_hwv),
226
+
"Cannot find hardware voter regmap for %pOF\n", node);
227
+
273
228
for (i = 0; i < num; i++) {
274
229
const struct mtk_gate *gate = &clks[i];
275
230
···
285
228
continue;
286
229
}
287
230
288
-
hw = mtk_clk_register_gate(dev, gate->name, gate->parent_name,
289
-
regmap,
290
-
gate->regs->set_ofs,
291
-
gate->regs->clr_ofs,
292
-
gate->regs->sta_ofs,
293
-
gate->shift, gate->ops,
294
-
gate->flags);
231
+
hw = mtk_clk_register_gate(dev, gate, regmap, regmap_hwv);
295
232
296
233
if (IS_ERR(hw)) {
297
234
pr_err("Failed to register clk %s: %pe\n", gate->name,
+3
drivers/clk/mediatek/clk-gate.h
+3
drivers/clk/mediatek/clk-gate.h
···
19
19
extern const struct clk_ops mtk_clk_gate_ops_setclr_inv;
20
20
extern const struct clk_ops mtk_clk_gate_ops_no_setclr;
21
21
extern const struct clk_ops mtk_clk_gate_ops_no_setclr_inv;
22
+
extern const struct clk_ops mtk_clk_gate_hwv_ops_setclr;
23
+
extern const struct clk_ops mtk_clk_gate_hwv_ops_setclr_inv;
22
24
23
25
struct mtk_gate_regs {
24
26
u32 sta_ofs;
···
33
31
const char *name;
34
32
const char *parent_name;
35
33
const struct mtk_gate_regs *regs;
34
+
const struct mtk_gate_regs *hwv_regs;
36
35
int shift;
37
36
const struct clk_ops *ops;
38
37
unsigned long flags;
+1
drivers/clk/mediatek/clk-mt7622-aud.c
+1
drivers/clk/mediatek/clk-mt7622-aud.c
···
75
75
GATE_AUDIO1(CLK_AUDIO_A1SYS, "audio_a1sys", "a1sys_hp_sel", 21),
76
76
GATE_AUDIO1(CLK_AUDIO_A2SYS, "audio_a2sys", "a2sys_hp_sel", 22),
77
77
GATE_AUDIO1(CLK_AUDIO_AFE_CONN, "audio_afe_conn", "a1sys_hp_sel", 23),
78
+
GATE_AUDIO1(CLK_AUDIO_AFE_MRGIF, "audio_afe_mrgif", "aud_mux1_sel", 25),
78
79
/* AUDIO2 */
79
80
GATE_AUDIO2(CLK_AUDIO_UL1, "audio_ul1", "a1sys_hp_sel", 0),
80
81
GATE_AUDIO2(CLK_AUDIO_UL2, "audio_ul2", "a1sys_hp_sel", 1),
+1
-1
drivers/clk/mediatek/clk-mt8195-infra_ao.c
+1
-1
drivers/clk/mediatek/clk-mt8195-infra_ao.c
···
103
103
GATE_INFRA_AO0(CLK_INFRA_AO_CQ_DMA_FPC, "infra_ao_cq_dma_fpc", "fpc", 28),
104
104
GATE_INFRA_AO0(CLK_INFRA_AO_UART5, "infra_ao_uart5", "top_uart", 29),
105
105
/* INFRA_AO1 */
106
-
GATE_INFRA_AO1(CLK_INFRA_AO_HDMI_26M, "infra_ao_hdmi_26m", "clk26m", 0),
106
+
GATE_INFRA_AO1(CLK_INFRA_AO_HDMI_26M, "infra_ao_hdmi_26m", "top_hdmi_xtal", 0),
107
107
GATE_INFRA_AO1(CLK_INFRA_AO_SPI0, "infra_ao_spi0", "top_spi", 1),
108
108
GATE_INFRA_AO1(CLK_INFRA_AO_MSDC0, "infra_ao_msdc0", "top_msdc50_0_hclk", 2),
109
109
GATE_INFRA_AO1(CLK_INFRA_AO_MSDC1, "infra_ao_msdc1", "top_axi", 4),
+204
drivers/clk/mediatek/clk-mt8196-apmixedsys.c
+204
drivers/clk/mediatek/clk-mt8196-apmixedsys.c
···
1
+
// SPDX-License-Identifier: GPL-2.0-only
2
+
/*
3
+
* Copyright (c) 2025 MediaTek Inc.
4
+
* Guangjie Song <guangjie.song@mediatek.com>
5
+
* Copyright (c) 2025 Collabora Ltd.
6
+
* Laura Nao <laura.nao@collabora.com>
7
+
*/
8
+
#include <dt-bindings/clock/mediatek,mt8196-clock.h>
9
+
10
+
#include <linux/clk.h>
11
+
#include <linux/module.h>
12
+
#include <linux/of.h>
13
+
#include <linux/of_address.h>
14
+
#include <linux/of_device.h>
15
+
#include <linux/platform_device.h>
16
+
17
+
#include "clk-mtk.h"
18
+
#include "clk-pll.h"
19
+
20
+
/* APMIXEDSYS PLL control register offsets */
21
+
#define MAINPLL_CON0 0x250
22
+
#define MAINPLL_CON1 0x254
23
+
#define UNIVPLL_CON0 0x264
24
+
#define UNIVPLL_CON1 0x268
25
+
#define MSDCPLL_CON0 0x278
26
+
#define MSDCPLL_CON1 0x27c
27
+
#define ADSPPLL_CON0 0x28c
28
+
#define ADSPPLL_CON1 0x290
29
+
#define EMIPLL_CON0 0x2a0
30
+
#define EMIPLL_CON1 0x2a4
31
+
#define EMIPLL2_CON0 0x2b4
32
+
#define EMIPLL2_CON1 0x2b8
33
+
#define NET1PLL_CON0 0x2c8
34
+
#define NET1PLL_CON1 0x2cc
35
+
#define SGMIIPLL_CON0 0x2dc
36
+
#define SGMIIPLL_CON1 0x2e0
37
+
38
+
/* APMIXEDSYS_GP2 PLL control register offsets*/
39
+
#define MAINPLL2_CON0 0x250
40
+
#define MAINPLL2_CON1 0x254
41
+
#define UNIVPLL2_CON0 0x264
42
+
#define UNIVPLL2_CON1 0x268
43
+
#define MMPLL2_CON0 0x278
44
+
#define MMPLL2_CON1 0x27c
45
+
#define IMGPLL_CON0 0x28c
46
+
#define IMGPLL_CON1 0x290
47
+
#define TVDPLL1_CON0 0x2a0
48
+
#define TVDPLL1_CON1 0x2a4
49
+
#define TVDPLL2_CON0 0x2b4
50
+
#define TVDPLL2_CON1 0x2b8
51
+
#define TVDPLL3_CON0 0x2c8
52
+
#define TVDPLL3_CON1 0x2cc
53
+
54
+
#define PLLEN_ALL 0x080
55
+
#define PLLEN_ALL_SET 0x084
56
+
#define PLLEN_ALL_CLR 0x088
57
+
58
+
#define FENC_STATUS_CON0 0x03c
59
+
60
+
#define MT8196_PLL_FMAX (3800UL * MHZ)
61
+
#define MT8196_PLL_FMIN (1500UL * MHZ)
62
+
#define MT8196_INTEGER_BITS 8
63
+
64
+
#define PLL_FENC(_id, _name, _reg, _fenc_sta_ofs, _fenc_sta_bit,\
65
+
_flags, _pd_reg, _pd_shift, \
66
+
_pcw_reg, _pcw_shift, _pcwbits, \
67
+
_pll_en_bit) { \
68
+
.id = _id, \
69
+
.name = _name, \
70
+
.reg = _reg, \
71
+
.fenc_sta_ofs = _fenc_sta_ofs, \
72
+
.fenc_sta_bit = _fenc_sta_bit, \
73
+
.flags = _flags, \
74
+
.fmax = MT8196_PLL_FMAX, \
75
+
.fmin = MT8196_PLL_FMIN, \
76
+
.pd_reg = _pd_reg, \
77
+
.pd_shift = _pd_shift, \
78
+
.pcw_reg = _pcw_reg, \
79
+
.pcw_shift = _pcw_shift, \
80
+
.pcwbits = _pcwbits, \
81
+
.pcwibits = MT8196_INTEGER_BITS, \
82
+
.en_reg = PLLEN_ALL, \
83
+
.en_set_reg = PLLEN_ALL_SET, \
84
+
.en_clr_reg = PLLEN_ALL_CLR, \
85
+
.pll_en_bit = _pll_en_bit, \
86
+
.ops = &mtk_pll_fenc_clr_set_ops, \
87
+
}
88
+
89
+
struct mtk_pll_desc {
90
+
const struct mtk_pll_data *clks;
91
+
size_t num_clks;
92
+
};
93
+
94
+
static const struct mtk_pll_data apmixed_plls[] = {
95
+
PLL_FENC(CLK_APMIXED_MAINPLL, "mainpll", MAINPLL_CON0, FENC_STATUS_CON0,
96
+
7, PLL_AO, MAINPLL_CON1, 24, MAINPLL_CON1, 0, 22, 0),
97
+
PLL_FENC(CLK_APMIXED_UNIVPLL, "univpll", UNIVPLL_CON0, FENC_STATUS_CON0,
98
+
6, 0, UNIVPLL_CON1, 24, UNIVPLL_CON1, 0, 22, 1),
99
+
PLL_FENC(CLK_APMIXED_MSDCPLL, "msdcpll", MSDCPLL_CON0, FENC_STATUS_CON0,
100
+
5, 0, MSDCPLL_CON1, 24, MSDCPLL_CON1, 0, 22, 2),
101
+
PLL_FENC(CLK_APMIXED_ADSPPLL, "adsppll", ADSPPLL_CON0, FENC_STATUS_CON0,
102
+
4, 0, ADSPPLL_CON1, 24, ADSPPLL_CON1, 0, 22, 3),
103
+
PLL_FENC(CLK_APMIXED_EMIPLL, "emipll", EMIPLL_CON0, FENC_STATUS_CON0, 3,
104
+
PLL_AO, EMIPLL_CON1, 24, EMIPLL_CON1, 0, 22, 4),
105
+
PLL_FENC(CLK_APMIXED_EMIPLL2, "emipll2", EMIPLL2_CON0, FENC_STATUS_CON0,
106
+
2, PLL_AO, EMIPLL2_CON1, 24, EMIPLL2_CON1, 0, 22, 5),
107
+
PLL_FENC(CLK_APMIXED_NET1PLL, "net1pll", NET1PLL_CON0, FENC_STATUS_CON0,
108
+
1, 0, NET1PLL_CON1, 24, NET1PLL_CON1, 0, 22, 6),
109
+
PLL_FENC(CLK_APMIXED_SGMIIPLL, "sgmiipll", SGMIIPLL_CON0, FENC_STATUS_CON0,
110
+
0, 0, SGMIIPLL_CON1, 24, SGMIIPLL_CON1, 0, 22, 7),
111
+
};
112
+
113
+
static const struct mtk_pll_desc apmixed_desc = {
114
+
.clks = apmixed_plls,
115
+
.num_clks = ARRAY_SIZE(apmixed_plls),
116
+
};
117
+
118
+
static const struct mtk_pll_data apmixed2_plls[] = {
119
+
PLL_FENC(CLK_APMIXED2_MAINPLL2, "mainpll2", MAINPLL2_CON0, FENC_STATUS_CON0,
120
+
6, 0, MAINPLL2_CON1, 24, MAINPLL2_CON1, 0, 22, 0),
121
+
PLL_FENC(CLK_APMIXED2_UNIVPLL2, "univpll2", UNIVPLL2_CON0, FENC_STATUS_CON0,
122
+
5, 0, UNIVPLL2_CON1, 24, UNIVPLL2_CON1, 0, 22, 1),
123
+
PLL_FENC(CLK_APMIXED2_MMPLL2, "mmpll2", MMPLL2_CON0, FENC_STATUS_CON0,
124
+
4, 0, MMPLL2_CON1, 24, MMPLL2_CON1, 0, 22, 2),
125
+
PLL_FENC(CLK_APMIXED2_IMGPLL, "imgpll", IMGPLL_CON0, FENC_STATUS_CON0,
126
+
3, 0, IMGPLL_CON1, 24, IMGPLL_CON1, 0, 22, 3),
127
+
PLL_FENC(CLK_APMIXED2_TVDPLL1, "tvdpll1", TVDPLL1_CON0, FENC_STATUS_CON0,
128
+
2, 0, TVDPLL1_CON1, 24, TVDPLL1_CON1, 0, 22, 4),
129
+
PLL_FENC(CLK_APMIXED2_TVDPLL2, "tvdpll2", TVDPLL2_CON0, FENC_STATUS_CON0,
130
+
1, 0, TVDPLL2_CON1, 24, TVDPLL2_CON1, 0, 22, 5),
131
+
PLL_FENC(CLK_APMIXED2_TVDPLL3, "tvdpll3", TVDPLL3_CON0, FENC_STATUS_CON0,
132
+
0, 0, TVDPLL3_CON1, 24, TVDPLL3_CON1, 0, 22, 6),
133
+
};
134
+
135
+
static const struct mtk_pll_desc apmixed2_desc = {
136
+
.clks = apmixed2_plls,
137
+
.num_clks = ARRAY_SIZE(apmixed2_plls),
138
+
};
139
+
140
+
static int clk_mt8196_apmixed_probe(struct platform_device *pdev)
141
+
{
142
+
struct clk_hw_onecell_data *clk_data;
143
+
struct device_node *node = pdev->dev.of_node;
144
+
const struct mtk_pll_desc *mcd;
145
+
int r;
146
+
147
+
mcd = device_get_match_data(&pdev->dev);
148
+
if (!mcd)
149
+
return -EINVAL;
150
+
151
+
clk_data = mtk_alloc_clk_data(mcd->num_clks);
152
+
if (!clk_data)
153
+
return -ENOMEM;
154
+
155
+
r = mtk_clk_register_plls(node, mcd->clks, mcd->num_clks, clk_data);
156
+
if (r)
157
+
goto free_apmixed_data;
158
+
159
+
r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data);
160
+
if (r)
161
+
goto unregister_plls;
162
+
163
+
platform_set_drvdata(pdev, clk_data);
164
+
165
+
return r;
166
+
167
+
unregister_plls:
168
+
mtk_clk_unregister_plls(mcd->clks, mcd->num_clks, clk_data);
169
+
free_apmixed_data:
170
+
mtk_free_clk_data(clk_data);
171
+
return r;
172
+
}
173
+
174
+
static void clk_mt8196_apmixed_remove(struct platform_device *pdev)
175
+
{
176
+
const struct mtk_pll_desc *mcd = device_get_match_data(&pdev->dev);
177
+
struct clk_hw_onecell_data *clk_data = platform_get_drvdata(pdev);
178
+
struct device_node *node = pdev->dev.of_node;
179
+
180
+
of_clk_del_provider(node);
181
+
mtk_clk_unregister_plls(mcd->clks, mcd->num_clks, clk_data);
182
+
mtk_free_clk_data(clk_data);
183
+
}
184
+
185
+
static const struct of_device_id of_match_clk_mt8196_apmixed[] = {
186
+
{ .compatible = "mediatek,mt8196-apmixedsys", .data = &apmixed_desc },
187
+
{ .compatible = "mediatek,mt8196-apmixedsys-gp2",
188
+
.data = &apmixed2_desc },
189
+
{ /* sentinel */ }
190
+
};
191
+
MODULE_DEVICE_TABLE(of, of_match_clk_mt8196_apmixed);
192
+
193
+
static struct platform_driver clk_mt8196_apmixed_drv = {
194
+
.probe = clk_mt8196_apmixed_probe,
195
+
.remove = clk_mt8196_apmixed_remove,
196
+
.driver = {
197
+
.name = "clk-mt8196-apmixed",
198
+
.of_match_table = of_match_clk_mt8196_apmixed,
199
+
},
200
+
};
201
+
module_platform_driver(clk_mt8196_apmixed_drv);
202
+
203
+
MODULE_DESCRIPTION("MediaTek MT8196 apmixedsys clocks driver");
204
+
MODULE_LICENSE("GPL");
+170
drivers/clk/mediatek/clk-mt8196-disp0.c
+170
drivers/clk/mediatek/clk-mt8196-disp0.c
···
1
+
// SPDX-License-Identifier: GPL-2.0-only
2
+
/*
3
+
* Copyright (c) 2025 MediaTek Inc.
4
+
* Guangjie Song <guangjie.song@mediatek.com>
5
+
* Copyright (c) 2025 Collabora Ltd.
6
+
* Laura Nao <laura.nao@collabora.com>
7
+
*/
8
+
#include <dt-bindings/clock/mediatek,mt8196-clock.h>
9
+
10
+
#include <linux/clk-provider.h>
11
+
#include <linux/module.h>
12
+
#include <linux/of_device.h>
13
+
#include <linux/platform_device.h>
14
+
15
+
#include "clk-gate.h"
16
+
#include "clk-mtk.h"
17
+
18
+
static const struct mtk_gate_regs mm0_cg_regs = {
19
+
.set_ofs = 0x104,
20
+
.clr_ofs = 0x108,
21
+
.sta_ofs = 0x100,
22
+
};
23
+
24
+
static const struct mtk_gate_regs mm0_hwv_regs = {
25
+
.set_ofs = 0x0020,
26
+
.clr_ofs = 0x0024,
27
+
.sta_ofs = 0x2c10,
28
+
};
29
+
30
+
static const struct mtk_gate_regs mm1_cg_regs = {
31
+
.set_ofs = 0x114,
32
+
.clr_ofs = 0x118,
33
+
.sta_ofs = 0x110,
34
+
};
35
+
36
+
static const struct mtk_gate_regs mm1_hwv_regs = {
37
+
.set_ofs = 0x0028,
38
+
.clr_ofs = 0x002c,
39
+
.sta_ofs = 0x2c14,
40
+
};
41
+
42
+
#define GATE_MM0(_id, _name, _parent, _shift) { \
43
+
.id = _id, \
44
+
.name = _name, \
45
+
.parent_name = _parent, \
46
+
.regs = &mm0_cg_regs, \
47
+
.shift = _shift, \
48
+
.flags = CLK_OPS_PARENT_ENABLE, \
49
+
.ops = &mtk_clk_gate_ops_setclr,\
50
+
}
51
+
52
+
#define GATE_HWV_MM0(_id, _name, _parent, _shift) { \
53
+
.id = _id, \
54
+
.name = _name, \
55
+
.parent_name = _parent, \
56
+
.regs = &mm0_cg_regs, \
57
+
.hwv_regs = &mm0_hwv_regs, \
58
+
.shift = _shift, \
59
+
.ops = &mtk_clk_gate_hwv_ops_setclr, \
60
+
.flags = CLK_OPS_PARENT_ENABLE \
61
+
}
62
+
63
+
#define GATE_MM1(_id, _name, _parent, _shift) { \
64
+
.id = _id, \
65
+
.name = _name, \
66
+
.parent_name = _parent, \
67
+
.regs = &mm1_cg_regs, \
68
+
.shift = _shift, \
69
+
.flags = CLK_OPS_PARENT_ENABLE, \
70
+
.ops = &mtk_clk_gate_ops_setclr,\
71
+
}
72
+
73
+
#define GATE_HWV_MM1(_id, _name, _parent, _shift) { \
74
+
.id = _id, \
75
+
.name = _name, \
76
+
.parent_name = _parent, \
77
+
.regs = &mm1_cg_regs, \
78
+
.hwv_regs = &mm1_hwv_regs, \
79
+
.shift = _shift, \
80
+
.ops = &mtk_clk_gate_hwv_ops_setclr, \
81
+
.flags = CLK_OPS_PARENT_ENABLE, \
82
+
}
83
+
84
+
static const struct mtk_gate mm_clks[] = {
85
+
/* MM0 */
86
+
GATE_HWV_MM0(CLK_MM_CONFIG, "mm_config", "disp", 0),
87
+
GATE_HWV_MM0(CLK_MM_DISP_MUTEX0, "mm_disp_mutex0", "disp", 1),
88
+
GATE_HWV_MM0(CLK_MM_DISP_AAL0, "mm_disp_aal0", "disp", 2),
89
+
GATE_HWV_MM0(CLK_MM_DISP_AAL1, "mm_disp_aal1", "disp", 3),
90
+
GATE_MM0(CLK_MM_DISP_C3D0, "mm_disp_c3d0", "disp", 4),
91
+
GATE_MM0(CLK_MM_DISP_C3D1, "mm_disp_c3d1", "disp", 5),
92
+
GATE_MM0(CLK_MM_DISP_C3D2, "mm_disp_c3d2", "disp", 6),
93
+
GATE_MM0(CLK_MM_DISP_C3D3, "mm_disp_c3d3", "disp", 7),
94
+
GATE_MM0(CLK_MM_DISP_CCORR0, "mm_disp_ccorr0", "disp", 8),
95
+
GATE_MM0(CLK_MM_DISP_CCORR1, "mm_disp_ccorr1", "disp", 9),
96
+
GATE_MM0(CLK_MM_DISP_CCORR2, "mm_disp_ccorr2", "disp", 10),
97
+
GATE_MM0(CLK_MM_DISP_CCORR3, "mm_disp_ccorr3", "disp", 11),
98
+
GATE_MM0(CLK_MM_DISP_CHIST0, "mm_disp_chist0", "disp", 12),
99
+
GATE_MM0(CLK_MM_DISP_CHIST1, "mm_disp_chist1", "disp", 13),
100
+
GATE_MM0(CLK_MM_DISP_COLOR0, "mm_disp_color0", "disp", 14),
101
+
GATE_MM0(CLK_MM_DISP_COLOR1, "mm_disp_color1", "disp", 15),
102
+
GATE_MM0(CLK_MM_DISP_DITHER0, "mm_disp_dither0", "disp", 16),
103
+
GATE_MM0(CLK_MM_DISP_DITHER1, "mm_disp_dither1", "disp", 17),
104
+
GATE_HWV_MM0(CLK_MM_DISP_DLI_ASYNC0, "mm_disp_dli_async0", "disp", 18),
105
+
GATE_HWV_MM0(CLK_MM_DISP_DLI_ASYNC1, "mm_disp_dli_async1", "disp", 19),
106
+
GATE_HWV_MM0(CLK_MM_DISP_DLI_ASYNC2, "mm_disp_dli_async2", "disp", 20),
107
+
GATE_HWV_MM0(CLK_MM_DISP_DLI_ASYNC3, "mm_disp_dli_async3", "disp", 21),
108
+
GATE_HWV_MM0(CLK_MM_DISP_DLI_ASYNC4, "mm_disp_dli_async4", "disp", 22),
109
+
GATE_HWV_MM0(CLK_MM_DISP_DLI_ASYNC5, "mm_disp_dli_async5", "disp", 23),
110
+
GATE_HWV_MM0(CLK_MM_DISP_DLI_ASYNC6, "mm_disp_dli_async6", "disp", 24),
111
+
GATE_HWV_MM0(CLK_MM_DISP_DLI_ASYNC7, "mm_disp_dli_async7", "disp", 25),
112
+
GATE_HWV_MM0(CLK_MM_DISP_DLI_ASYNC8, "mm_disp_dli_async8", "disp", 26),
113
+
GATE_HWV_MM0(CLK_MM_DISP_DLI_ASYNC9, "mm_disp_dli_async9", "disp", 27),
114
+
GATE_HWV_MM0(CLK_MM_DISP_DLI_ASYNC10, "mm_disp_dli_async10", "disp", 28),
115
+
GATE_HWV_MM0(CLK_MM_DISP_DLI_ASYNC11, "mm_disp_dli_async11", "disp", 29),
116
+
GATE_HWV_MM0(CLK_MM_DISP_DLI_ASYNC12, "mm_disp_dli_async12", "disp", 30),
117
+
GATE_HWV_MM0(CLK_MM_DISP_DLI_ASYNC13, "mm_disp_dli_async13", "disp", 31),
118
+
/* MM1 */
119
+
GATE_HWV_MM1(CLK_MM_DISP_DLI_ASYNC14, "mm_disp_dli_async14", "disp", 0),
120
+
GATE_HWV_MM1(CLK_MM_DISP_DLI_ASYNC15, "mm_disp_dli_async15", "disp", 1),
121
+
GATE_HWV_MM1(CLK_MM_DISP_DLO_ASYNC0, "mm_disp_dlo_async0", "disp", 2),
122
+
GATE_HWV_MM1(CLK_MM_DISP_DLO_ASYNC1, "mm_disp_dlo_async1", "disp", 3),
123
+
GATE_HWV_MM1(CLK_MM_DISP_DLO_ASYNC2, "mm_disp_dlo_async2", "disp", 4),
124
+
GATE_HWV_MM1(CLK_MM_DISP_DLO_ASYNC3, "mm_disp_dlo_async3", "disp", 5),
125
+
GATE_HWV_MM1(CLK_MM_DISP_DLO_ASYNC4, "mm_disp_dlo_async4", "disp", 6),
126
+
GATE_HWV_MM1(CLK_MM_DISP_DLO_ASYNC5, "mm_disp_dlo_async5", "disp", 7),
127
+
GATE_HWV_MM1(CLK_MM_DISP_DLO_ASYNC6, "mm_disp_dlo_async6", "disp", 8),
128
+
GATE_HWV_MM1(CLK_MM_DISP_DLO_ASYNC7, "mm_disp_dlo_async7", "disp", 9),
129
+
GATE_HWV_MM1(CLK_MM_DISP_DLO_ASYNC8, "mm_disp_dlo_async8", "disp", 10),
130
+
GATE_MM1(CLK_MM_DISP_GAMMA0, "mm_disp_gamma0", "disp", 11),
131
+
GATE_MM1(CLK_MM_DISP_GAMMA1, "mm_disp_gamma1", "disp", 12),
132
+
GATE_MM1(CLK_MM_MDP_AAL0, "mm_mdp_aal0", "disp", 13),
133
+
GATE_MM1(CLK_MM_MDP_AAL1, "mm_mdp_aal1", "disp", 14),
134
+
GATE_HWV_MM1(CLK_MM_MDP_RDMA0, "mm_mdp_rdma0", "disp", 15),
135
+
GATE_HWV_MM1(CLK_MM_DISP_POSTMASK0, "mm_disp_postmask0", "disp", 16),
136
+
GATE_HWV_MM1(CLK_MM_DISP_POSTMASK1, "mm_disp_postmask1", "disp", 17),
137
+
GATE_HWV_MM1(CLK_MM_MDP_RSZ0, "mm_mdp_rsz0", "disp", 18),
138
+
GATE_HWV_MM1(CLK_MM_MDP_RSZ1, "mm_mdp_rsz1", "disp", 19),
139
+
GATE_HWV_MM1(CLK_MM_DISP_SPR0, "mm_disp_spr0", "disp", 20),
140
+
GATE_MM1(CLK_MM_DISP_TDSHP0, "mm_disp_tdshp0", "disp", 21),
141
+
GATE_MM1(CLK_MM_DISP_TDSHP1, "mm_disp_tdshp1", "disp", 22),
142
+
GATE_HWV_MM1(CLK_MM_DISP_WDMA0, "mm_disp_wdma0", "disp", 23),
143
+
GATE_HWV_MM1(CLK_MM_DISP_Y2R0, "mm_disp_y2r0", "disp", 24),
144
+
GATE_HWV_MM1(CLK_MM_SMI_SUB_COMM0, "mm_ssc", "disp", 25),
145
+
GATE_HWV_MM1(CLK_MM_DISP_FAKE_ENG0, "mm_disp_fake_eng0", "disp", 26),
146
+
};
147
+
148
+
static const struct mtk_clk_desc mm_mcd = {
149
+
.clks = mm_clks,
150
+
.num_clks = ARRAY_SIZE(mm_clks),
151
+
};
152
+
153
+
static const struct platform_device_id clk_mt8196_disp0_id_table[] = {
154
+
{ .name = "clk-mt8196-disp0", .driver_data = (kernel_ulong_t)&mm_mcd },
155
+
{ /* sentinel */ }
156
+
};
157
+
MODULE_DEVICE_TABLE(platform, clk_mt8196_disp0_id_table);
158
+
159
+
static struct platform_driver clk_mt8196_disp0_drv = {
160
+
.probe = mtk_clk_pdev_probe,
161
+
.remove = mtk_clk_pdev_remove,
162
+
.driver = {
163
+
.name = "clk-mt8196-disp0",
164
+
},
165
+
.id_table = clk_mt8196_disp0_id_table,
166
+
};
167
+
module_platform_driver(clk_mt8196_disp0_drv);
168
+
169
+
MODULE_DESCRIPTION("MediaTek MT8196 disp0 clocks driver");
170
+
MODULE_LICENSE("GPL");
+170
drivers/clk/mediatek/clk-mt8196-disp1.c
+170
drivers/clk/mediatek/clk-mt8196-disp1.c
···
1
+
// SPDX-License-Identifier: GPL-2.0-only
2
+
/*
3
+
* Copyright (c) 2025 MediaTek Inc.
4
+
* Guangjie Song <guangjie.song@mediatek.com>
5
+
* Copyright (c) 2025 Collabora Ltd.
6
+
* Laura Nao <laura.nao@collabora.com>
7
+
*/
8
+
#include <dt-bindings/clock/mediatek,mt8196-clock.h>
9
+
10
+
#include <linux/clk-provider.h>
11
+
#include <linux/module.h>
12
+
#include <linux/of_device.h>
13
+
#include <linux/platform_device.h>
14
+
15
+
#include "clk-gate.h"
16
+
#include "clk-mtk.h"
17
+
18
+
static const struct mtk_gate_regs mm10_cg_regs = {
19
+
.set_ofs = 0x104,
20
+
.clr_ofs = 0x108,
21
+
.sta_ofs = 0x100,
22
+
};
23
+
24
+
static const struct mtk_gate_regs mm10_hwv_regs = {
25
+
.set_ofs = 0x0010,
26
+
.clr_ofs = 0x0014,
27
+
.sta_ofs = 0x2c08,
28
+
};
29
+
30
+
static const struct mtk_gate_regs mm11_cg_regs = {
31
+
.set_ofs = 0x114,
32
+
.clr_ofs = 0x118,
33
+
.sta_ofs = 0x110,
34
+
};
35
+
36
+
static const struct mtk_gate_regs mm11_hwv_regs = {
37
+
.set_ofs = 0x0018,
38
+
.clr_ofs = 0x001c,
39
+
.sta_ofs = 0x2c0c,
40
+
};
41
+
42
+
#define GATE_MM10(_id, _name, _parent, _shift) {\
43
+
.id = _id, \
44
+
.name = _name, \
45
+
.parent_name = _parent, \
46
+
.regs = &mm10_cg_regs, \
47
+
.shift = _shift, \
48
+
.flags = CLK_OPS_PARENT_ENABLE, \
49
+
.ops = &mtk_clk_gate_ops_setclr,\
50
+
}
51
+
52
+
#define GATE_HWV_MM10(_id, _name, _parent, _shift) { \
53
+
.id = _id, \
54
+
.name = _name, \
55
+
.parent_name = _parent, \
56
+
.regs = &mm10_cg_regs, \
57
+
.hwv_regs = &mm10_hwv_regs, \
58
+
.shift = _shift, \
59
+
.ops = &mtk_clk_gate_hwv_ops_setclr, \
60
+
.flags = CLK_OPS_PARENT_ENABLE, \
61
+
}
62
+
63
+
#define GATE_MM11(_id, _name, _parent, _shift) {\
64
+
.id = _id, \
65
+
.name = _name, \
66
+
.parent_name = _parent, \
67
+
.regs = &mm11_cg_regs, \
68
+
.shift = _shift, \
69
+
.flags = CLK_OPS_PARENT_ENABLE, \
70
+
.ops = &mtk_clk_gate_ops_setclr,\
71
+
}
72
+
73
+
#define GATE_HWV_MM11(_id, _name, _parent, _shift) { \
74
+
.id = _id, \
75
+
.name = _name, \
76
+
.parent_name = _parent, \
77
+
.regs = &mm11_cg_regs, \
78
+
.hwv_regs = &mm11_hwv_regs, \
79
+
.shift = _shift, \
80
+
.ops = &mtk_clk_gate_hwv_ops_setclr, \
81
+
}
82
+
83
+
static const struct mtk_gate mm1_clks[] = {
84
+
/* MM10 */
85
+
GATE_HWV_MM10(CLK_MM1_DISPSYS1_CONFIG, "mm1_dispsys1_config", "disp", 0),
86
+
GATE_HWV_MM10(CLK_MM1_DISPSYS1_S_CONFIG, "mm1_dispsys1_s_config", "disp", 1),
87
+
GATE_HWV_MM10(CLK_MM1_DISP_MUTEX0, "mm1_disp_mutex0", "disp", 2),
88
+
GATE_HWV_MM10(CLK_MM1_DISP_DLI_ASYNC20, "mm1_disp_dli_async20", "disp", 3),
89
+
GATE_HWV_MM10(CLK_MM1_DISP_DLI_ASYNC21, "mm1_disp_dli_async21", "disp", 4),
90
+
GATE_HWV_MM10(CLK_MM1_DISP_DLI_ASYNC22, "mm1_disp_dli_async22", "disp", 5),
91
+
GATE_HWV_MM10(CLK_MM1_DISP_DLI_ASYNC23, "mm1_disp_dli_async23", "disp", 6),
92
+
GATE_HWV_MM10(CLK_MM1_DISP_DLI_ASYNC24, "mm1_disp_dli_async24", "disp", 7),
93
+
GATE_HWV_MM10(CLK_MM1_DISP_DLI_ASYNC25, "mm1_disp_dli_async25", "disp", 8),
94
+
GATE_HWV_MM10(CLK_MM1_DISP_DLI_ASYNC26, "mm1_disp_dli_async26", "disp", 9),
95
+
GATE_HWV_MM10(CLK_MM1_DISP_DLI_ASYNC27, "mm1_disp_dli_async27", "disp", 10),
96
+
GATE_HWV_MM10(CLK_MM1_DISP_DLI_ASYNC28, "mm1_disp_dli_async28", "disp", 11),
97
+
GATE_HWV_MM10(CLK_MM1_DISP_RELAY0, "mm1_disp_relay0", "disp", 12),
98
+
GATE_HWV_MM10(CLK_MM1_DISP_RELAY1, "mm1_disp_relay1", "disp", 13),
99
+
GATE_HWV_MM10(CLK_MM1_DISP_RELAY2, "mm1_disp_relay2", "disp", 14),
100
+
GATE_HWV_MM10(CLK_MM1_DISP_RELAY3, "mm1_disp_relay3", "disp", 15),
101
+
GATE_HWV_MM10(CLK_MM1_DISP_DP_INTF0, "mm1_DP_CLK", "disp", 16),
102
+
GATE_HWV_MM10(CLK_MM1_DISP_DP_INTF1, "mm1_disp_dp_intf1", "disp", 17),
103
+
GATE_HWV_MM10(CLK_MM1_DISP_DSC_WRAP0, "mm1_disp_dsc_wrap0", "disp", 18),
104
+
GATE_HWV_MM10(CLK_MM1_DISP_DSC_WRAP1, "mm1_disp_dsc_wrap1", "disp", 19),
105
+
GATE_HWV_MM10(CLK_MM1_DISP_DSC_WRAP2, "mm1_disp_dsc_wrap2", "disp", 20),
106
+
GATE_HWV_MM10(CLK_MM1_DISP_DSC_WRAP3, "mm1_disp_dsc_wrap3", "disp", 21),
107
+
GATE_HWV_MM10(CLK_MM1_DISP_DSI0, "mm1_CLK0", "disp", 22),
108
+
GATE_HWV_MM10(CLK_MM1_DISP_DSI1, "mm1_CLK1", "disp", 23),
109
+
GATE_HWV_MM10(CLK_MM1_DISP_DSI2, "mm1_CLK2", "disp", 24),
110
+
GATE_HWV_MM10(CLK_MM1_DISP_DVO0, "mm1_disp_dvo0", "disp", 25),
111
+
GATE_HWV_MM10(CLK_MM1_DISP_GDMA0, "mm1_disp_gdma0", "disp", 26),
112
+
GATE_HWV_MM10(CLK_MM1_DISP_MERGE0, "mm1_disp_merge0", "disp", 27),
113
+
GATE_HWV_MM10(CLK_MM1_DISP_MERGE1, "mm1_disp_merge1", "disp", 28),
114
+
GATE_HWV_MM10(CLK_MM1_DISP_MERGE2, "mm1_disp_merge2", "disp", 29),
115
+
GATE_HWV_MM10(CLK_MM1_DISP_ODDMR0, "mm1_disp_oddmr0", "disp", 30),
116
+
GATE_HWV_MM10(CLK_MM1_DISP_POSTALIGN0, "mm1_disp_postalign0", "disp", 31),
117
+
/* MM11 */
118
+
GATE_HWV_MM11(CLK_MM1_DISP_DITHER2, "mm1_disp_dither2", "disp", 0),
119
+
GATE_HWV_MM11(CLK_MM1_DISP_R2Y0, "mm1_disp_r2y0", "disp", 1),
120
+
GATE_HWV_MM11(CLK_MM1_DISP_SPLITTER0, "mm1_disp_splitter0", "disp", 2),
121
+
GATE_HWV_MM11(CLK_MM1_DISP_SPLITTER1, "mm1_disp_splitter1", "disp", 3),
122
+
GATE_HWV_MM11(CLK_MM1_DISP_SPLITTER2, "mm1_disp_splitter2", "disp", 4),
123
+
GATE_HWV_MM11(CLK_MM1_DISP_SPLITTER3, "mm1_disp_splitter3", "disp", 5),
124
+
GATE_HWV_MM11(CLK_MM1_DISP_VDCM0, "mm1_disp_vdcm0", "disp", 6),
125
+
GATE_HWV_MM11(CLK_MM1_DISP_WDMA1, "mm1_disp_wdma1", "disp", 7),
126
+
GATE_HWV_MM11(CLK_MM1_DISP_WDMA2, "mm1_disp_wdma2", "disp", 8),
127
+
GATE_HWV_MM11(CLK_MM1_DISP_WDMA3, "mm1_disp_wdma3", "disp", 9),
128
+
GATE_HWV_MM11(CLK_MM1_DISP_WDMA4, "mm1_disp_wdma4", "disp", 10),
129
+
GATE_HWV_MM11(CLK_MM1_MDP_RDMA1, "mm1_mdp_rdma1", "disp", 11),
130
+
GATE_HWV_MM11(CLK_MM1_SMI_LARB0, "mm1_smi_larb0", "disp", 12),
131
+
GATE_HWV_MM11(CLK_MM1_MOD1, "mm1_mod1", "clk26m", 13),
132
+
GATE_HWV_MM11(CLK_MM1_MOD2, "mm1_mod2", "clk26m", 14),
133
+
GATE_HWV_MM11(CLK_MM1_MOD3, "mm1_mod3", "clk26m", 15),
134
+
GATE_HWV_MM11(CLK_MM1_MOD4, "mm1_mod4", "dp0", 16),
135
+
GATE_HWV_MM11(CLK_MM1_MOD5, "mm1_mod5", "dp1", 17),
136
+
GATE_HWV_MM11(CLK_MM1_MOD6, "mm1_mod6", "dp1", 18),
137
+
GATE_HWV_MM11(CLK_MM1_CG0, "mm1_cg0", "disp", 20),
138
+
GATE_HWV_MM11(CLK_MM1_CG1, "mm1_cg1", "disp", 21),
139
+
GATE_HWV_MM11(CLK_MM1_CG2, "mm1_cg2", "disp", 22),
140
+
GATE_HWV_MM11(CLK_MM1_CG3, "mm1_cg3", "disp", 23),
141
+
GATE_HWV_MM11(CLK_MM1_CG4, "mm1_cg4", "disp", 24),
142
+
GATE_HWV_MM11(CLK_MM1_CG5, "mm1_cg5", "disp", 25),
143
+
GATE_HWV_MM11(CLK_MM1_CG6, "mm1_cg6", "disp", 26),
144
+
GATE_HWV_MM11(CLK_MM1_CG7, "mm1_cg7", "disp", 27),
145
+
GATE_HWV_MM11(CLK_MM1_F26M, "mm1_f26m_ck", "clk26m", 28),
146
+
};
147
+
148
+
static const struct mtk_clk_desc mm1_mcd = {
149
+
.clks = mm1_clks,
150
+
.num_clks = ARRAY_SIZE(mm1_clks),
151
+
};
152
+
153
+
static const struct platform_device_id clk_mt8196_disp1_id_table[] = {
154
+
{ .name = "clk-mt8196-disp1", .driver_data = (kernel_ulong_t)&mm1_mcd },
155
+
{ /* sentinel */ }
156
+
};
157
+
MODULE_DEVICE_TABLE(platform, clk_mt8196_disp1_id_table);
158
+
159
+
static struct platform_driver clk_mt8196_disp1_drv = {
160
+
.probe = mtk_clk_pdev_probe,
161
+
.remove = mtk_clk_pdev_remove,
162
+
.driver = {
163
+
.name = "clk-mt8196-disp1",
164
+
},
165
+
.id_table = clk_mt8196_disp1_id_table,
166
+
};
167
+
module_platform_driver(clk_mt8196_disp1_drv);
168
+
169
+
MODULE_DESCRIPTION("MediaTek MT8196 disp1 clocks driver");
170
+
MODULE_LICENSE("GPL");
+118
drivers/clk/mediatek/clk-mt8196-imp_iic_wrap.c
+118
drivers/clk/mediatek/clk-mt8196-imp_iic_wrap.c
···
1
+
// SPDX-License-Identifier: GPL-2.0-only
2
+
/*
3
+
* Copyright (c) 2025 MediaTek Inc.
4
+
* Guangjie Song <guangjie.song@mediatek.com>
5
+
* Copyright (c) 2025 Collabora Ltd.
6
+
* Laura Nao <laura.nao@collabora.com>
7
+
*/
8
+
#include <dt-bindings/clock/mediatek,mt8196-clock.h>
9
+
10
+
#include <linux/clk-provider.h>
11
+
#include <linux/module.h>
12
+
#include <linux/of_device.h>
13
+
#include <linux/platform_device.h>
14
+
15
+
#include "clk-gate.h"
16
+
#include "clk-mtk.h"
17
+
18
+
static const struct mtk_gate_regs imp_cg_regs = {
19
+
.set_ofs = 0xe08,
20
+
.clr_ofs = 0xe04,
21
+
.sta_ofs = 0xe00,
22
+
};
23
+
24
+
#define GATE_IMP(_id, _name, _parent, _shift) { \
25
+
.id = _id, \
26
+
.name = _name, \
27
+
.parent_name = _parent, \
28
+
.regs = &imp_cg_regs, \
29
+
.shift = _shift, \
30
+
.flags = CLK_OPS_PARENT_ENABLE, \
31
+
.ops = &mtk_clk_gate_ops_setclr, \
32
+
}
33
+
34
+
static const struct mtk_gate impc_clks[] = {
35
+
GATE_IMP(CLK_IMPC_I2C11, "impc_i2c11", "i2c_p", 0),
36
+
GATE_IMP(CLK_IMPC_I2C12, "impc_i2c12", "i2c_p", 1),
37
+
GATE_IMP(CLK_IMPC_I2C13, "impc_i2c13", "i2c_p", 2),
38
+
GATE_IMP(CLK_IMPC_I2C14, "impc_i2c14", "i2c_p", 3),
39
+
};
40
+
41
+
static const struct mtk_clk_desc impc_mcd = {
42
+
.clks = impc_clks,
43
+
.num_clks = ARRAY_SIZE(impc_clks),
44
+
};
45
+
46
+
static const struct mtk_gate impe_clks[] = {
47
+
GATE_IMP(CLK_IMPE_I2C5, "impe_i2c5", "i2c_east", 0),
48
+
};
49
+
50
+
static const struct mtk_clk_desc impe_mcd = {
51
+
.clks = impe_clks,
52
+
.num_clks = ARRAY_SIZE(impe_clks),
53
+
};
54
+
55
+
static const struct mtk_gate_regs impn_hwv_regs = {
56
+
.set_ofs = 0x0000,
57
+
.clr_ofs = 0x0004,
58
+
.sta_ofs = 0x2c00,
59
+
};
60
+
61
+
#define GATE_HWV_IMPN(_id, _name, _parent, _shift) { \
62
+
.id = _id, \
63
+
.name = _name, \
64
+
.parent_name = _parent, \
65
+
.regs = &imp_cg_regs, \
66
+
.hwv_regs = &impn_hwv_regs, \
67
+
.shift = _shift, \
68
+
.ops = &mtk_clk_gate_hwv_ops_setclr, \
69
+
.flags = CLK_OPS_PARENT_ENABLE, \
70
+
}
71
+
72
+
static const struct mtk_gate impn_clks[] = {
73
+
GATE_IMP(CLK_IMPN_I2C1, "impn_i2c1", "i2c_north", 0),
74
+
GATE_IMP(CLK_IMPN_I2C2, "impn_i2c2", "i2c_north", 1),
75
+
GATE_IMP(CLK_IMPN_I2C4, "impn_i2c4", "i2c_north", 2),
76
+
GATE_HWV_IMPN(CLK_IMPN_I2C7, "impn_i2c7", "i2c_north", 3),
77
+
GATE_IMP(CLK_IMPN_I2C8, "impn_i2c8", "i2c_north", 4),
78
+
GATE_IMP(CLK_IMPN_I2C9, "impn_i2c9", "i2c_north", 5),
79
+
};
80
+
81
+
static const struct mtk_clk_desc impn_mcd = {
82
+
.clks = impn_clks,
83
+
.num_clks = ARRAY_SIZE(impn_clks),
84
+
};
85
+
86
+
static const struct mtk_gate impw_clks[] = {
87
+
GATE_IMP(CLK_IMPW_I2C0, "impw_i2c0", "i2c_west", 0),
88
+
GATE_IMP(CLK_IMPW_I2C3, "impw_i2c3", "i2c_west", 1),
89
+
GATE_IMP(CLK_IMPW_I2C6, "impw_i2c6", "i2c_west", 2),
90
+
GATE_IMP(CLK_IMPW_I2C10, "impw_i2c10", "i2c_west", 3),
91
+
};
92
+
93
+
static const struct mtk_clk_desc impw_mcd = {
94
+
.clks = impw_clks,
95
+
.num_clks = ARRAY_SIZE(impw_clks),
96
+
};
97
+
98
+
static const struct of_device_id of_match_clk_mt8196_imp_iic_wrap[] = {
99
+
{ .compatible = "mediatek,mt8196-imp-iic-wrap-c", .data = &impc_mcd },
100
+
{ .compatible = "mediatek,mt8196-imp-iic-wrap-e", .data = &impe_mcd },
101
+
{ .compatible = "mediatek,mt8196-imp-iic-wrap-n", .data = &impn_mcd },
102
+
{ .compatible = "mediatek,mt8196-imp-iic-wrap-w", .data = &impw_mcd },
103
+
{ /* sentinel */ }
104
+
};
105
+
MODULE_DEVICE_TABLE(of, of_match_clk_mt8196_imp_iic_wrap);
106
+
107
+
static struct platform_driver clk_mt8196_imp_iic_wrap_drv = {
108
+
.probe = mtk_clk_simple_probe,
109
+
.remove = mtk_clk_simple_remove,
110
+
.driver = {
111
+
.name = "clk-mt8196-imp_iic_wrap",
112
+
.of_match_table = of_match_clk_mt8196_imp_iic_wrap,
113
+
},
114
+
};
115
+
module_platform_driver(clk_mt8196_imp_iic_wrap_drv);
116
+
117
+
MODULE_DESCRIPTION("MediaTek MT8196 I2C Wrapper clocks driver");
118
+
MODULE_LICENSE("GPL");
+167
drivers/clk/mediatek/clk-mt8196-mcu.c
+167
drivers/clk/mediatek/clk-mt8196-mcu.c
···
1
+
// SPDX-License-Identifier: GPL-2.0-only
2
+
/*
3
+
* Copyright (c) 2025 MediaTek Inc.
4
+
* Guangjie Song <guangjie.song@mediatek.com>
5
+
* Copyright (c) 2025 Collabora Ltd.
6
+
* Laura Nao <laura.nao@collabora.com>
7
+
*/
8
+
#include <dt-bindings/clock/mediatek,mt8196-clock.h>
9
+
10
+
#include <linux/clk.h>
11
+
#include <linux/module.h>
12
+
#include <linux/of.h>
13
+
#include <linux/of_address.h>
14
+
#include <linux/of_device.h>
15
+
#include <linux/platform_device.h>
16
+
17
+
#include "clk-mtk.h"
18
+
#include "clk-pll.h"
19
+
20
+
#define ARMPLL_LL_CON0 0x008
21
+
#define ARMPLL_LL_CON1 0x00c
22
+
#define ARMPLL_LL_CON2 0x010
23
+
#define ARMPLL_LL_CON3 0x014
24
+
#define ARMPLL_BL_CON0 0x008
25
+
#define ARMPLL_BL_CON1 0x00c
26
+
#define ARMPLL_BL_CON2 0x010
27
+
#define ARMPLL_BL_CON3 0x014
28
+
#define ARMPLL_B_CON0 0x008
29
+
#define ARMPLL_B_CON1 0x00c
30
+
#define ARMPLL_B_CON2 0x010
31
+
#define ARMPLL_B_CON3 0x014
32
+
#define CCIPLL_CON0 0x008
33
+
#define CCIPLL_CON1 0x00c
34
+
#define CCIPLL_CON2 0x010
35
+
#define CCIPLL_CON3 0x014
36
+
#define PTPPLL_CON0 0x008
37
+
#define PTPPLL_CON1 0x00c
38
+
#define PTPPLL_CON2 0x010
39
+
#define PTPPLL_CON3 0x014
40
+
41
+
#define MT8196_PLL_FMAX (3800UL * MHZ)
42
+
#define MT8196_PLL_FMIN (1500UL * MHZ)
43
+
#define MT8196_INTEGER_BITS 8
44
+
45
+
#define PLL(_id, _name, _reg, _en_reg, _en_mask, _pll_en_bit, \
46
+
_flags, _rst_bar_mask, \
47
+
_pd_reg, _pd_shift, _tuner_reg, \
48
+
_tuner_en_reg, _tuner_en_bit, \
49
+
_pcw_reg, _pcw_shift, _pcwbits) { \
50
+
.id = _id, \
51
+
.name = _name, \
52
+
.reg = _reg, \
53
+
.en_reg = _en_reg, \
54
+
.en_mask = _en_mask, \
55
+
.pll_en_bit = _pll_en_bit, \
56
+
.flags = _flags, \
57
+
.rst_bar_mask = _rst_bar_mask, \
58
+
.fmax = MT8196_PLL_FMAX, \
59
+
.fmin = MT8196_PLL_FMIN, \
60
+
.pd_reg = _pd_reg, \
61
+
.pd_shift = _pd_shift, \
62
+
.tuner_reg = _tuner_reg, \
63
+
.tuner_en_reg = _tuner_en_reg, \
64
+
.tuner_en_bit = _tuner_en_bit, \
65
+
.pcw_reg = _pcw_reg, \
66
+
.pcw_shift = _pcw_shift, \
67
+
.pcwbits = _pcwbits, \
68
+
.pcwibits = MT8196_INTEGER_BITS, \
69
+
}
70
+
71
+
static const struct mtk_pll_data cpu_bl_plls[] = {
72
+
PLL(CLK_CPBL_ARMPLL_BL, "armpll-bl", ARMPLL_BL_CON0, ARMPLL_BL_CON0, 0,
73
+
0, PLL_AO, BIT(0), ARMPLL_BL_CON1, 24, 0, 0, 0, ARMPLL_BL_CON1, 0, 22),
74
+
};
75
+
76
+
static const struct mtk_pll_data cpu_b_plls[] = {
77
+
PLL(CLK_CPB_ARMPLL_B, "armpll-b", ARMPLL_B_CON0, ARMPLL_B_CON0, 0, 0,
78
+
PLL_AO, BIT(0), ARMPLL_B_CON1, 24, 0, 0, 0, ARMPLL_B_CON1, 0, 22),
79
+
};
80
+
81
+
static const struct mtk_pll_data cpu_ll_plls[] = {
82
+
PLL(CLK_CPLL_ARMPLL_LL, "armpll-ll", ARMPLL_LL_CON0, ARMPLL_LL_CON0, 0,
83
+
0, PLL_AO, BIT(0), ARMPLL_LL_CON1, 24, 0, 0, 0, ARMPLL_LL_CON1, 0, 22),
84
+
};
85
+
86
+
static const struct mtk_pll_data cci_plls[] = {
87
+
PLL(CLK_CCIPLL, "ccipll", CCIPLL_CON0, CCIPLL_CON0, 0, 0, PLL_AO,
88
+
BIT(0), CCIPLL_CON1, 24, 0, 0, 0, CCIPLL_CON1, 0, 22),
89
+
};
90
+
91
+
static const struct mtk_pll_data ptp_plls[] = {
92
+
PLL(CLK_PTPPLL, "ptppll", PTPPLL_CON0, PTPPLL_CON0, 0, 0, PLL_AO,
93
+
BIT(0), PTPPLL_CON1, 24, 0, 0, 0, PTPPLL_CON1, 0, 22),
94
+
};
95
+
96
+
static const struct of_device_id of_match_clk_mt8196_mcu[] = {
97
+
{ .compatible = "mediatek,mt8196-armpll-bl-pll-ctrl",
98
+
.data = &cpu_bl_plls },
99
+
{ .compatible = "mediatek,mt8196-armpll-b-pll-ctrl",
100
+
.data = &cpu_b_plls },
101
+
{ .compatible = "mediatek,mt8196-armpll-ll-pll-ctrl",
102
+
.data = &cpu_ll_plls },
103
+
{ .compatible = "mediatek,mt8196-ccipll-pll-ctrl", .data = &cci_plls },
104
+
{ .compatible = "mediatek,mt8196-ptppll-pll-ctrl", .data = &ptp_plls },
105
+
{ /* sentinel */ }
106
+
};
107
+
MODULE_DEVICE_TABLE(of, of_match_clk_mt8196_mcu);
108
+
109
+
static int clk_mt8196_mcu_probe(struct platform_device *pdev)
110
+
{
111
+
const struct mtk_pll_data *plls;
112
+
struct clk_hw_onecell_data *clk_data;
113
+
struct device_node *node = pdev->dev.of_node;
114
+
const int num_plls = 1;
115
+
int r;
116
+
117
+
plls = of_device_get_match_data(&pdev->dev);
118
+
if (!plls)
119
+
return -EINVAL;
120
+
121
+
clk_data = mtk_alloc_clk_data(num_plls);
122
+
if (!clk_data)
123
+
return -ENOMEM;
124
+
125
+
r = mtk_clk_register_plls(node, plls, num_plls, clk_data);
126
+
if (r)
127
+
goto free_clk_data;
128
+
129
+
r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data);
130
+
if (r)
131
+
goto unregister_plls;
132
+
133
+
platform_set_drvdata(pdev, clk_data);
134
+
135
+
return r;
136
+
137
+
unregister_plls:
138
+
mtk_clk_unregister_plls(plls, num_plls, clk_data);
139
+
free_clk_data:
140
+
mtk_free_clk_data(clk_data);
141
+
142
+
return r;
143
+
}
144
+
145
+
static void clk_mt8196_mcu_remove(struct platform_device *pdev)
146
+
{
147
+
const struct mtk_pll_data *plls = of_device_get_match_data(&pdev->dev);
148
+
struct clk_hw_onecell_data *clk_data = platform_get_drvdata(pdev);
149
+
struct device_node *node = pdev->dev.of_node;
150
+
151
+
of_clk_del_provider(node);
152
+
mtk_clk_unregister_plls(plls, 1, clk_data);
153
+
mtk_free_clk_data(clk_data);
154
+
}
155
+
156
+
static struct platform_driver clk_mt8196_mcu_drv = {
157
+
.probe = clk_mt8196_mcu_probe,
158
+
.remove = clk_mt8196_mcu_remove,
159
+
.driver = {
160
+
.name = "clk-mt8196-mcu",
161
+
.of_match_table = of_match_clk_mt8196_mcu,
162
+
},
163
+
};
164
+
module_platform_driver(clk_mt8196_mcu_drv);
165
+
166
+
MODULE_DESCRIPTION("MediaTek MT8196 mcusys clocks driver");
167
+
MODULE_LICENSE("GPL");
+186
drivers/clk/mediatek/clk-mt8196-mdpsys.c
+186
drivers/clk/mediatek/clk-mt8196-mdpsys.c
···
1
+
// SPDX-License-Identifier: GPL-2.0-only
2
+
/*
3
+
* Copyright (c) 2025 MediaTek Inc.
4
+
* Guangjie Song <guangjie.song@mediatek.com>
5
+
* Copyright (c) 2025 Collabora Ltd.
6
+
* Laura Nao <laura.nao@collabora.com>
7
+
*/
8
+
#include <dt-bindings/clock/mediatek,mt8196-clock.h>
9
+
10
+
#include <linux/clk-provider.h>
11
+
#include <linux/module.h>
12
+
#include <linux/of_device.h>
13
+
#include <linux/platform_device.h>
14
+
15
+
#include "clk-gate.h"
16
+
#include "clk-mtk.h"
17
+
18
+
static const struct mtk_gate_regs mdp0_cg_regs = {
19
+
.set_ofs = 0x104,
20
+
.clr_ofs = 0x108,
21
+
.sta_ofs = 0x100,
22
+
};
23
+
24
+
static const struct mtk_gate_regs mdp1_cg_regs = {
25
+
.set_ofs = 0x114,
26
+
.clr_ofs = 0x118,
27
+
.sta_ofs = 0x110,
28
+
};
29
+
30
+
static const struct mtk_gate_regs mdp2_cg_regs = {
31
+
.set_ofs = 0x124,
32
+
.clr_ofs = 0x128,
33
+
.sta_ofs = 0x120,
34
+
};
35
+
36
+
#define GATE_MDP0(_id, _name, _parent, _shift) { \
37
+
.id = _id, \
38
+
.name = _name, \
39
+
.parent_name = _parent, \
40
+
.regs = &mdp0_cg_regs, \
41
+
.shift = _shift, \
42
+
.flags = CLK_OPS_PARENT_ENABLE, \
43
+
.ops = &mtk_clk_gate_ops_setclr, \
44
+
}
45
+
46
+
#define GATE_MDP1(_id, _name, _parent, _shift) { \
47
+
.id = _id, \
48
+
.name = _name, \
49
+
.parent_name = _parent, \
50
+
.regs = &mdp1_cg_regs, \
51
+
.shift = _shift, \
52
+
.ops = &mtk_clk_gate_ops_setclr, \
53
+
}
54
+
55
+
#define GATE_MDP2(_id, _name, _parent, _shift) { \
56
+
.id = _id, \
57
+
.name = _name, \
58
+
.parent_name = _parent, \
59
+
.regs = &mdp2_cg_regs, \
60
+
.shift = _shift, \
61
+
.flags = CLK_OPS_PARENT_ENABLE, \
62
+
.ops = &mtk_clk_gate_ops_setclr, \
63
+
}
64
+
65
+
static const struct mtk_gate mdp1_clks[] = {
66
+
/* MDP1-0 */
67
+
GATE_MDP0(CLK_MDP1_MDP_MUTEX0, "mdp1_mdp_mutex0", "mdp", 0),
68
+
GATE_MDP0(CLK_MDP1_SMI0, "mdp1_smi0", "mdp", 1),
69
+
GATE_MDP0(CLK_MDP1_APB_BUS, "mdp1_apb_bus", "mdp", 2),
70
+
GATE_MDP0(CLK_MDP1_MDP_RDMA0, "mdp1_mdp_rdma0", "mdp", 3),
71
+
GATE_MDP0(CLK_MDP1_MDP_RDMA1, "mdp1_mdp_rdma1", "mdp", 4),
72
+
GATE_MDP0(CLK_MDP1_MDP_RDMA2, "mdp1_mdp_rdma2", "mdp", 5),
73
+
GATE_MDP0(CLK_MDP1_MDP_BIRSZ0, "mdp1_mdp_birsz0", "mdp", 6),
74
+
GATE_MDP0(CLK_MDP1_MDP_HDR0, "mdp1_mdp_hdr0", "mdp", 7),
75
+
GATE_MDP0(CLK_MDP1_MDP_AAL0, "mdp1_mdp_aal0", "mdp", 8),
76
+
GATE_MDP0(CLK_MDP1_MDP_RSZ0, "mdp1_mdp_rsz0", "mdp", 9),
77
+
GATE_MDP0(CLK_MDP1_MDP_RSZ2, "mdp1_mdp_rsz2", "mdp", 10),
78
+
GATE_MDP0(CLK_MDP1_MDP_TDSHP0, "mdp1_mdp_tdshp0", "mdp", 11),
79
+
GATE_MDP0(CLK_MDP1_MDP_COLOR0, "mdp1_mdp_color0", "mdp", 12),
80
+
GATE_MDP0(CLK_MDP1_MDP_WROT0, "mdp1_mdp_wrot0", "mdp", 13),
81
+
GATE_MDP0(CLK_MDP1_MDP_WROT1, "mdp1_mdp_wrot1", "mdp", 14),
82
+
GATE_MDP0(CLK_MDP1_MDP_WROT2, "mdp1_mdp_wrot2", "mdp", 15),
83
+
GATE_MDP0(CLK_MDP1_MDP_FAKE_ENG0, "mdp1_mdp_fake_eng0", "mdp", 16),
84
+
GATE_MDP0(CLK_MDP1_APB_DB, "mdp1_apb_db", "mdp", 17),
85
+
GATE_MDP0(CLK_MDP1_MDP_DLI_ASYNC0, "mdp1_mdp_dli_async0", "mdp", 18),
86
+
GATE_MDP0(CLK_MDP1_MDP_DLI_ASYNC1, "mdp1_mdp_dli_async1", "mdp", 19),
87
+
GATE_MDP0(CLK_MDP1_MDP_DLO_ASYNC0, "mdp1_mdp_dlo_async0", "mdp", 20),
88
+
GATE_MDP0(CLK_MDP1_MDP_DLO_ASYNC1, "mdp1_mdp_dlo_async1", "mdp", 21),
89
+
GATE_MDP0(CLK_MDP1_MDP_DLI_ASYNC2, "mdp1_mdp_dli_async2", "mdp", 22),
90
+
GATE_MDP0(CLK_MDP1_MDP_DLO_ASYNC2, "mdp1_mdp_dlo_async2", "mdp", 23),
91
+
GATE_MDP0(CLK_MDP1_MDP_DLO_ASYNC3, "mdp1_mdp_dlo_async3", "mdp", 24),
92
+
GATE_MDP0(CLK_MDP1_IMG_DL_ASYNC0, "mdp1_img_dl_async0", "mdp", 25),
93
+
GATE_MDP0(CLK_MDP1_MDP_RROT0, "mdp1_mdp_rrot0", "mdp", 26),
94
+
GATE_MDP0(CLK_MDP1_MDP_MERGE0, "mdp1_mdp_merge0", "mdp", 27),
95
+
GATE_MDP0(CLK_MDP1_MDP_C3D0, "mdp1_mdp_c3d0", "mdp", 28),
96
+
GATE_MDP0(CLK_MDP1_MDP_FG0, "mdp1_mdp_fg0", "mdp", 29),
97
+
GATE_MDP0(CLK_MDP1_MDP_CLA2, "mdp1_mdp_cla2", "mdp", 30),
98
+
GATE_MDP0(CLK_MDP1_MDP_DLO_ASYNC4, "mdp1_mdp_dlo_async4", "mdp", 31),
99
+
/* MDP1-1 */
100
+
GATE_MDP1(CLK_MDP1_VPP_RSZ0, "mdp1_vpp_rsz0", "mdp", 0),
101
+
GATE_MDP1(CLK_MDP1_VPP_RSZ1, "mdp1_vpp_rsz1", "mdp", 1),
102
+
GATE_MDP1(CLK_MDP1_MDP_DLO_ASYNC5, "mdp1_mdp_dlo_async5", "mdp", 2),
103
+
GATE_MDP1(CLK_MDP1_IMG0, "mdp1_img0", "mdp", 3),
104
+
GATE_MDP1(CLK_MDP1_F26M, "mdp1_f26m", "clk26m", 27),
105
+
/* MDP1-2 */
106
+
GATE_MDP2(CLK_MDP1_IMG_DL_RELAY0, "mdp1_img_dl_relay0", "mdp", 0),
107
+
GATE_MDP2(CLK_MDP1_IMG_DL_RELAY1, "mdp1_img_dl_relay1", "mdp", 8),
108
+
};
109
+
110
+
static const struct mtk_clk_desc mdp1_mcd = {
111
+
.clks = mdp1_clks,
112
+
.num_clks = ARRAY_SIZE(mdp1_clks),
113
+
.need_runtime_pm = true,
114
+
};
115
+
116
+
117
+
static const struct mtk_gate mdp_clks[] = {
118
+
/* MDP0 */
119
+
GATE_MDP0(CLK_MDP_MDP_MUTEX0, "mdp_mdp_mutex0", "mdp", 0),
120
+
GATE_MDP0(CLK_MDP_SMI0, "mdp_smi0", "mdp", 1),
121
+
GATE_MDP0(CLK_MDP_APB_BUS, "mdp_apb_bus", "mdp", 2),
122
+
GATE_MDP0(CLK_MDP_MDP_RDMA0, "mdp_mdp_rdma0", "mdp", 3),
123
+
GATE_MDP0(CLK_MDP_MDP_RDMA1, "mdp_mdp_rdma1", "mdp", 4),
124
+
GATE_MDP0(CLK_MDP_MDP_RDMA2, "mdp_mdp_rdma2", "mdp", 5),
125
+
GATE_MDP0(CLK_MDP_MDP_BIRSZ0, "mdp_mdp_birsz0", "mdp", 6),
126
+
GATE_MDP0(CLK_MDP_MDP_HDR0, "mdp_mdp_hdr0", "mdp", 7),
127
+
GATE_MDP0(CLK_MDP_MDP_AAL0, "mdp_mdp_aal0", "mdp", 8),
128
+
GATE_MDP0(CLK_MDP_MDP_RSZ0, "mdp_mdp_rsz0", "mdp", 9),
129
+
GATE_MDP0(CLK_MDP_MDP_RSZ2, "mdp_mdp_rsz2", "mdp", 10),
130
+
GATE_MDP0(CLK_MDP_MDP_TDSHP0, "mdp_mdp_tdshp0", "mdp", 11),
131
+
GATE_MDP0(CLK_MDP_MDP_COLOR0, "mdp_mdp_color0", "mdp", 12),
132
+
GATE_MDP0(CLK_MDP_MDP_WROT0, "mdp_mdp_wrot0", "mdp", 13),
133
+
GATE_MDP0(CLK_MDP_MDP_WROT1, "mdp_mdp_wrot1", "mdp", 14),
134
+
GATE_MDP0(CLK_MDP_MDP_WROT2, "mdp_mdp_wrot2", "mdp", 15),
135
+
GATE_MDP0(CLK_MDP_MDP_FAKE_ENG0, "mdp_mdp_fake_eng0", "mdp", 16),
136
+
GATE_MDP0(CLK_MDP_APB_DB, "mdp_apb_db", "mdp", 17),
137
+
GATE_MDP0(CLK_MDP_MDP_DLI_ASYNC0, "mdp_mdp_dli_async0", "mdp", 18),
138
+
GATE_MDP0(CLK_MDP_MDP_DLI_ASYNC1, "mdp_mdp_dli_async1", "mdp", 19),
139
+
GATE_MDP0(CLK_MDP_MDP_DLO_ASYNC0, "mdp_mdp_dlo_async0", "mdp", 20),
140
+
GATE_MDP0(CLK_MDP_MDP_DLO_ASYNC1, "mdp_mdp_dlo_async1", "mdp", 21),
141
+
GATE_MDP0(CLK_MDP_MDP_DLI_ASYNC2, "mdp_mdp_dli_async2", "mdp", 22),
142
+
GATE_MDP0(CLK_MDP_MDP_DLO_ASYNC2, "mdp_mdp_dlo_async2", "mdp", 23),
143
+
GATE_MDP0(CLK_MDP_MDP_DLO_ASYNC3, "mdp_mdp_dlo_async3", "mdp", 24),
144
+
GATE_MDP0(CLK_MDP_IMG_DL_ASYNC0, "mdp_img_dl_async0", "mdp", 25),
145
+
GATE_MDP0(CLK_MDP_MDP_RROT0, "mdp_mdp_rrot0", "mdp", 26),
146
+
GATE_MDP0(CLK_MDP_MDP_MERGE0, "mdp_mdp_merge0", "mdp", 27),
147
+
GATE_MDP0(CLK_MDP_MDP_C3D0, "mdp_mdp_c3d0", "mdp", 28),
148
+
GATE_MDP0(CLK_MDP_MDP_FG0, "mdp_mdp_fg0", "mdp", 29),
149
+
GATE_MDP0(CLK_MDP_MDP_CLA2, "mdp_mdp_cla2", "mdp", 30),
150
+
GATE_MDP0(CLK_MDP_MDP_DLO_ASYNC4, "mdp_mdp_dlo_async4", "mdp", 31),
151
+
/* MDP1 */
152
+
GATE_MDP1(CLK_MDP_VPP_RSZ0, "mdp_vpp_rsz0", "mdp", 0),
153
+
GATE_MDP1(CLK_MDP_VPP_RSZ1, "mdp_vpp_rsz1", "mdp", 1),
154
+
GATE_MDP1(CLK_MDP_MDP_DLO_ASYNC5, "mdp_mdp_dlo_async5", "mdp", 2),
155
+
GATE_MDP1(CLK_MDP_IMG0, "mdp_img0", "mdp", 3),
156
+
GATE_MDP1(CLK_MDP_F26M, "mdp_f26m", "clk26m", 27),
157
+
/* MDP2 */
158
+
GATE_MDP2(CLK_MDP_IMG_DL_RELAY0, "mdp_img_dl_relay0", "mdp", 0),
159
+
GATE_MDP2(CLK_MDP_IMG_DL_RELAY1, "mdp_img_dl_relay1", "mdp", 8),
160
+
};
161
+
162
+
static const struct mtk_clk_desc mdp_mcd = {
163
+
.clks = mdp_clks,
164
+
.num_clks = ARRAY_SIZE(mdp_clks),
165
+
.need_runtime_pm = true,
166
+
};
167
+
168
+
static const struct of_device_id of_match_clk_mt8196_mdpsys[] = {
169
+
{ .compatible = "mediatek,mt8196-mdpsys0", .data = &mdp_mcd },
170
+
{ .compatible = "mediatek,mt8196-mdpsys1", .data = &mdp1_mcd },
171
+
{ /* sentinel */ }
172
+
};
173
+
MODULE_DEVICE_TABLE(of, of_match_clk_mt8196_mdpsys);
174
+
175
+
static struct platform_driver clk_mt8196_mdpsys_drv = {
176
+
.probe = mtk_clk_simple_probe,
177
+
.remove = mtk_clk_simple_remove,
178
+
.driver = {
179
+
.name = "clk-mt8196-mdpsys",
180
+
.of_match_table = of_match_clk_mt8196_mdpsys,
181
+
},
182
+
};
183
+
module_platform_driver(clk_mt8196_mdpsys_drv);
184
+
185
+
MODULE_DESCRIPTION("MediaTek MT8196 Multimedia Data Path clocks driver");
186
+
MODULE_LICENSE("GPL");
+150
drivers/clk/mediatek/clk-mt8196-mfg.c
+150
drivers/clk/mediatek/clk-mt8196-mfg.c
···
1
+
// SPDX-License-Identifier: GPL-2.0-only
2
+
/*
3
+
* Copyright (c) 2025 MediaTek Inc.
4
+
* Guangjie Song <guangjie.song@mediatek.com>
5
+
* Copyright (c) 2025 Collabora Ltd.
6
+
* Laura Nao <laura.nao@collabora.com>
7
+
*/
8
+
#include <dt-bindings/clock/mediatek,mt8196-clock.h>
9
+
10
+
#include <linux/clk.h>
11
+
#include <linux/module.h>
12
+
#include <linux/of.h>
13
+
#include <linux/of_address.h>
14
+
#include <linux/of_device.h>
15
+
#include <linux/platform_device.h>
16
+
17
+
#include "clk-mtk.h"
18
+
#include "clk-pll.h"
19
+
20
+
#define MFGPLL_CON0 0x008
21
+
#define MFGPLL_CON1 0x00c
22
+
#define MFGPLL_CON2 0x010
23
+
#define MFGPLL_CON3 0x014
24
+
#define MFGPLL_SC0_CON0 0x008
25
+
#define MFGPLL_SC0_CON1 0x00c
26
+
#define MFGPLL_SC0_CON2 0x010
27
+
#define MFGPLL_SC0_CON3 0x014
28
+
#define MFGPLL_SC1_CON0 0x008
29
+
#define MFGPLL_SC1_CON1 0x00c
30
+
#define MFGPLL_SC1_CON2 0x010
31
+
#define MFGPLL_SC1_CON3 0x014
32
+
33
+
#define MT8196_PLL_FMAX (3800UL * MHZ)
34
+
#define MT8196_PLL_FMIN (1500UL * MHZ)
35
+
#define MT8196_INTEGER_BITS 8
36
+
37
+
#define PLL(_id, _name, _reg, _en_reg, _en_mask, _pll_en_bit, \
38
+
_flags, _rst_bar_mask, \
39
+
_pd_reg, _pd_shift, _tuner_reg, \
40
+
_tuner_en_reg, _tuner_en_bit, \
41
+
_pcw_reg, _pcw_shift, _pcwbits) { \
42
+
.id = _id, \
43
+
.name = _name, \
44
+
.reg = _reg, \
45
+
.en_reg = _en_reg, \
46
+
.en_mask = _en_mask, \
47
+
.pll_en_bit = _pll_en_bit, \
48
+
.flags = _flags, \
49
+
.rst_bar_mask = _rst_bar_mask, \
50
+
.fmax = MT8196_PLL_FMAX, \
51
+
.fmin = MT8196_PLL_FMIN, \
52
+
.pd_reg = _pd_reg, \
53
+
.pd_shift = _pd_shift, \
54
+
.tuner_reg = _tuner_reg, \
55
+
.tuner_en_reg = _tuner_en_reg, \
56
+
.tuner_en_bit = _tuner_en_bit, \
57
+
.pcw_reg = _pcw_reg, \
58
+
.pcw_shift = _pcw_shift, \
59
+
.pcwbits = _pcwbits, \
60
+
.pcwibits = MT8196_INTEGER_BITS, \
61
+
}
62
+
63
+
static const struct mtk_pll_data mfg_ao_plls[] = {
64
+
PLL(CLK_MFG_AO_MFGPLL, "mfgpll", MFGPLL_CON0, MFGPLL_CON0, 0, 0, 0,
65
+
BIT(0), MFGPLL_CON1, 24, 0, 0, 0,
66
+
MFGPLL_CON1, 0, 22),
67
+
};
68
+
69
+
static const struct mtk_pll_data mfgsc0_ao_plls[] = {
70
+
PLL(CLK_MFGSC0_AO_MFGPLL_SC0, "mfgpll-sc0", MFGPLL_SC0_CON0,
71
+
MFGPLL_SC0_CON0, 0, 0, 0, BIT(0), MFGPLL_SC0_CON1, 24, 0, 0, 0,
72
+
MFGPLL_SC0_CON1, 0, 22),
73
+
};
74
+
75
+
static const struct mtk_pll_data mfgsc1_ao_plls[] = {
76
+
PLL(CLK_MFGSC1_AO_MFGPLL_SC1, "mfgpll-sc1", MFGPLL_SC1_CON0,
77
+
MFGPLL_SC1_CON0, 0, 0, 0, BIT(0), MFGPLL_SC1_CON1, 24, 0, 0, 0,
78
+
MFGPLL_SC1_CON1, 0, 22),
79
+
};
80
+
81
+
static const struct of_device_id of_match_clk_mt8196_mfg[] = {
82
+
{ .compatible = "mediatek,mt8196-mfgpll-pll-ctrl",
83
+
.data = &mfg_ao_plls },
84
+
{ .compatible = "mediatek,mt8196-mfgpll-sc0-pll-ctrl",
85
+
.data = &mfgsc0_ao_plls },
86
+
{ .compatible = "mediatek,mt8196-mfgpll-sc1-pll-ctrl",
87
+
.data = &mfgsc1_ao_plls },
88
+
{ /* sentinel */ }
89
+
};
90
+
MODULE_DEVICE_TABLE(of, of_match_clk_mt8196_mfg);
91
+
92
+
static int clk_mt8196_mfg_probe(struct platform_device *pdev)
93
+
{
94
+
const struct mtk_pll_data *plls;
95
+
struct clk_hw_onecell_data *clk_data;
96
+
struct device_node *node = pdev->dev.of_node;
97
+
const int num_plls = 1;
98
+
int r;
99
+
100
+
plls = of_device_get_match_data(&pdev->dev);
101
+
if (!plls)
102
+
return -EINVAL;
103
+
104
+
clk_data = mtk_alloc_clk_data(num_plls);
105
+
if (!clk_data)
106
+
return -ENOMEM;
107
+
108
+
r = mtk_clk_register_plls(node, plls, num_plls, clk_data);
109
+
if (r)
110
+
goto free_clk_data;
111
+
112
+
r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data);
113
+
if (r)
114
+
goto unregister_plls;
115
+
116
+
platform_set_drvdata(pdev, clk_data);
117
+
118
+
return r;
119
+
120
+
unregister_plls:
121
+
mtk_clk_unregister_plls(plls, num_plls, clk_data);
122
+
free_clk_data:
123
+
mtk_free_clk_data(clk_data);
124
+
125
+
return r;
126
+
}
127
+
128
+
static void clk_mt8196_mfg_remove(struct platform_device *pdev)
129
+
{
130
+
const struct mtk_pll_data *plls = of_device_get_match_data(&pdev->dev);
131
+
struct clk_hw_onecell_data *clk_data = platform_get_drvdata(pdev);
132
+
struct device_node *node = pdev->dev.of_node;
133
+
134
+
of_clk_del_provider(node);
135
+
mtk_clk_unregister_plls(plls, 1, clk_data);
136
+
mtk_free_clk_data(clk_data);
137
+
}
138
+
139
+
static struct platform_driver clk_mt8196_mfg_drv = {
140
+
.probe = clk_mt8196_mfg_probe,
141
+
.remove = clk_mt8196_mfg_remove,
142
+
.driver = {
143
+
.name = "clk-mt8196-mfg",
144
+
.of_match_table = of_match_clk_mt8196_mfg,
145
+
},
146
+
};
147
+
module_platform_driver(clk_mt8196_mfg_drv);
148
+
149
+
MODULE_DESCRIPTION("MediaTek MT8196 GPU mfg clocks driver");
150
+
MODULE_LICENSE("GPL");
+154
drivers/clk/mediatek/clk-mt8196-ovl0.c
+154
drivers/clk/mediatek/clk-mt8196-ovl0.c
···
1
+
// SPDX-License-Identifier: GPL-2.0-only
2
+
/*
3
+
* Copyright (c) 2025 MediaTek Inc.
4
+
* Guangjie Song <guangjie.song@mediatek.com>
5
+
* Copyright (c) 2025 Collabora Ltd.
6
+
* Laura Nao <laura.nao@collabora.com>
7
+
*/
8
+
#include <dt-bindings/clock/mediatek,mt8196-clock.h>
9
+
10
+
#include <linux/clk-provider.h>
11
+
#include <linux/module.h>
12
+
#include <linux/of_device.h>
13
+
#include <linux/platform_device.h>
14
+
15
+
#include "clk-gate.h"
16
+
#include "clk-mtk.h"
17
+
18
+
static const struct mtk_gate_regs ovl0_cg_regs = {
19
+
.set_ofs = 0x104,
20
+
.clr_ofs = 0x108,
21
+
.sta_ofs = 0x100,
22
+
};
23
+
24
+
static const struct mtk_gate_regs ovl0_hwv_regs = {
25
+
.set_ofs = 0x0060,
26
+
.clr_ofs = 0x0064,
27
+
.sta_ofs = 0x2c30,
28
+
};
29
+
30
+
static const struct mtk_gate_regs ovl1_cg_regs = {
31
+
.set_ofs = 0x114,
32
+
.clr_ofs = 0x118,
33
+
.sta_ofs = 0x110,
34
+
};
35
+
36
+
static const struct mtk_gate_regs ovl1_hwv_regs = {
37
+
.set_ofs = 0x0068,
38
+
.clr_ofs = 0x006c,
39
+
.sta_ofs = 0x2c34,
40
+
};
41
+
42
+
#define GATE_HWV_OVL0(_id, _name, _parent, _shift) { \
43
+
.id = _id, \
44
+
.name = _name, \
45
+
.parent_name = _parent, \
46
+
.regs = &ovl0_cg_regs, \
47
+
.hwv_regs = &ovl0_hwv_regs, \
48
+
.shift = _shift, \
49
+
.ops = &mtk_clk_gate_hwv_ops_setclr, \
50
+
.flags = CLK_OPS_PARENT_ENABLE, \
51
+
}
52
+
53
+
#define GATE_HWV_OVL1(_id, _name, _parent, _shift) { \
54
+
.id = _id, \
55
+
.name = _name, \
56
+
.parent_name = _parent, \
57
+
.regs = &ovl1_cg_regs, \
58
+
.hwv_regs = &ovl1_hwv_regs, \
59
+
.shift = _shift, \
60
+
.ops = &mtk_clk_gate_hwv_ops_setclr, \
61
+
.flags = CLK_OPS_PARENT_ENABLE, \
62
+
}
63
+
64
+
static const struct mtk_gate ovl_clks[] = {
65
+
/* OVL0 */
66
+
GATE_HWV_OVL0(CLK_OVLSYS_CONFIG, "ovlsys_config", "disp", 0),
67
+
GATE_HWV_OVL0(CLK_OVL_FAKE_ENG0, "ovl_fake_eng0", "disp", 1),
68
+
GATE_HWV_OVL0(CLK_OVL_FAKE_ENG1, "ovl_fake_eng1", "disp", 2),
69
+
GATE_HWV_OVL0(CLK_OVL_MUTEX0, "ovl_mutex0", "disp", 3),
70
+
GATE_HWV_OVL0(CLK_OVL_EXDMA0, "ovl_exdma0", "disp", 4),
71
+
GATE_HWV_OVL0(CLK_OVL_EXDMA1, "ovl_exdma1", "disp", 5),
72
+
GATE_HWV_OVL0(CLK_OVL_EXDMA2, "ovl_exdma2", "disp", 6),
73
+
GATE_HWV_OVL0(CLK_OVL_EXDMA3, "ovl_exdma3", "disp", 7),
74
+
GATE_HWV_OVL0(CLK_OVL_EXDMA4, "ovl_exdma4", "disp", 8),
75
+
GATE_HWV_OVL0(CLK_OVL_EXDMA5, "ovl_exdma5", "disp", 9),
76
+
GATE_HWV_OVL0(CLK_OVL_EXDMA6, "ovl_exdma6", "disp", 10),
77
+
GATE_HWV_OVL0(CLK_OVL_EXDMA7, "ovl_exdma7", "disp", 11),
78
+
GATE_HWV_OVL0(CLK_OVL_EXDMA8, "ovl_exdma8", "disp", 12),
79
+
GATE_HWV_OVL0(CLK_OVL_EXDMA9, "ovl_exdma9", "disp", 13),
80
+
GATE_HWV_OVL0(CLK_OVL_BLENDER0, "ovl_blender0", "disp", 14),
81
+
GATE_HWV_OVL0(CLK_OVL_BLENDER1, "ovl_blender1", "disp", 15),
82
+
GATE_HWV_OVL0(CLK_OVL_BLENDER2, "ovl_blender2", "disp", 16),
83
+
GATE_HWV_OVL0(CLK_OVL_BLENDER3, "ovl_blender3", "disp", 17),
84
+
GATE_HWV_OVL0(CLK_OVL_BLENDER4, "ovl_blender4", "disp", 18),
85
+
GATE_HWV_OVL0(CLK_OVL_BLENDER5, "ovl_blender5", "disp", 19),
86
+
GATE_HWV_OVL0(CLK_OVL_BLENDER6, "ovl_blender6", "disp", 20),
87
+
GATE_HWV_OVL0(CLK_OVL_BLENDER7, "ovl_blender7", "disp", 21),
88
+
GATE_HWV_OVL0(CLK_OVL_BLENDER8, "ovl_blender8", "disp", 22),
89
+
GATE_HWV_OVL0(CLK_OVL_BLENDER9, "ovl_blender9", "disp", 23),
90
+
GATE_HWV_OVL0(CLK_OVL_OUTPROC0, "ovl_outproc0", "disp", 24),
91
+
GATE_HWV_OVL0(CLK_OVL_OUTPROC1, "ovl_outproc1", "disp", 25),
92
+
GATE_HWV_OVL0(CLK_OVL_OUTPROC2, "ovl_outproc2", "disp", 26),
93
+
GATE_HWV_OVL0(CLK_OVL_OUTPROC3, "ovl_outproc3", "disp", 27),
94
+
GATE_HWV_OVL0(CLK_OVL_OUTPROC4, "ovl_outproc4", "disp", 28),
95
+
GATE_HWV_OVL0(CLK_OVL_OUTPROC5, "ovl_outproc5", "disp", 29),
96
+
GATE_HWV_OVL0(CLK_OVL_MDP_RSZ0, "ovl_mdp_rsz0", "disp", 30),
97
+
GATE_HWV_OVL0(CLK_OVL_MDP_RSZ1, "ovl_mdp_rsz1", "disp", 31),
98
+
/* OVL1 */
99
+
GATE_HWV_OVL1(CLK_OVL_DISP_WDMA0, "ovl_disp_wdma0", "disp", 0),
100
+
GATE_HWV_OVL1(CLK_OVL_DISP_WDMA1, "ovl_disp_wdma1", "disp", 1),
101
+
GATE_HWV_OVL1(CLK_OVL_UFBC_WDMA0, "ovl_ufbc_wdma0", "disp", 2),
102
+
GATE_HWV_OVL1(CLK_OVL_MDP_RDMA0, "ovl_mdp_rdma0", "disp", 3),
103
+
GATE_HWV_OVL1(CLK_OVL_MDP_RDMA1, "ovl_mdp_rdma1", "disp", 4),
104
+
GATE_HWV_OVL1(CLK_OVL_BWM0, "ovl_bwm0", "disp", 5),
105
+
GATE_HWV_OVL1(CLK_OVL_DLI0, "ovl_dli0", "disp", 6),
106
+
GATE_HWV_OVL1(CLK_OVL_DLI1, "ovl_dli1", "disp", 7),
107
+
GATE_HWV_OVL1(CLK_OVL_DLI2, "ovl_dli2", "disp", 8),
108
+
GATE_HWV_OVL1(CLK_OVL_DLI3, "ovl_dli3", "disp", 9),
109
+
GATE_HWV_OVL1(CLK_OVL_DLI4, "ovl_dli4", "disp", 10),
110
+
GATE_HWV_OVL1(CLK_OVL_DLI5, "ovl_dli5", "disp", 11),
111
+
GATE_HWV_OVL1(CLK_OVL_DLI6, "ovl_dli6", "disp", 12),
112
+
GATE_HWV_OVL1(CLK_OVL_DLI7, "ovl_dli7", "disp", 13),
113
+
GATE_HWV_OVL1(CLK_OVL_DLI8, "ovl_dli8", "disp", 14),
114
+
GATE_HWV_OVL1(CLK_OVL_DLO0, "ovl_dlo0", "disp", 15),
115
+
GATE_HWV_OVL1(CLK_OVL_DLO1, "ovl_dlo1", "disp", 16),
116
+
GATE_HWV_OVL1(CLK_OVL_DLO2, "ovl_dlo2", "disp", 17),
117
+
GATE_HWV_OVL1(CLK_OVL_DLO3, "ovl_dlo3", "disp", 18),
118
+
GATE_HWV_OVL1(CLK_OVL_DLO4, "ovl_dlo4", "disp", 19),
119
+
GATE_HWV_OVL1(CLK_OVL_DLO5, "ovl_dlo5", "disp", 20),
120
+
GATE_HWV_OVL1(CLK_OVL_DLO6, "ovl_dlo6", "disp", 21),
121
+
GATE_HWV_OVL1(CLK_OVL_DLO7, "ovl_dlo7", "disp", 22),
122
+
GATE_HWV_OVL1(CLK_OVL_DLO8, "ovl_dlo8", "disp", 23),
123
+
GATE_HWV_OVL1(CLK_OVL_DLO9, "ovl_dlo9", "disp", 24),
124
+
GATE_HWV_OVL1(CLK_OVL_DLO10, "ovl_dlo10", "disp", 25),
125
+
GATE_HWV_OVL1(CLK_OVL_DLO11, "ovl_dlo11", "disp", 26),
126
+
GATE_HWV_OVL1(CLK_OVL_DLO12, "ovl_dlo12", "disp", 27),
127
+
GATE_HWV_OVL1(CLK_OVLSYS_RELAY0, "ovlsys_relay0", "disp", 28),
128
+
GATE_HWV_OVL1(CLK_OVL_INLINEROT0, "ovl_inlinerot0", "disp", 29),
129
+
GATE_HWV_OVL1(CLK_OVL_SMI, "ovl_smi", "disp", 30),
130
+
};
131
+
132
+
static const struct mtk_clk_desc ovl_mcd = {
133
+
.clks = ovl_clks,
134
+
.num_clks = ARRAY_SIZE(ovl_clks),
135
+
};
136
+
137
+
static const struct platform_device_id clk_mt8196_ovl0_id_table[] = {
138
+
{ .name = "clk-mt8196-ovl0", .driver_data = (kernel_ulong_t)&ovl_mcd },
139
+
{ /* sentinel */ }
140
+
};
141
+
MODULE_DEVICE_TABLE(platform, clk_mt8196_ovl0_id_table);
142
+
143
+
static struct platform_driver clk_mt8196_ovl0_drv = {
144
+
.probe = mtk_clk_pdev_probe,
145
+
.remove = mtk_clk_pdev_remove,
146
+
.driver = {
147
+
.name = "clk-mt8196-ovl0",
148
+
},
149
+
.id_table = clk_mt8196_ovl0_id_table,
150
+
};
151
+
module_platform_driver(clk_mt8196_ovl0_drv);
152
+
153
+
MODULE_DESCRIPTION("MediaTek MT8196 ovl0 clocks driver");
154
+
MODULE_LICENSE("GPL");
+154
drivers/clk/mediatek/clk-mt8196-ovl1.c
+154
drivers/clk/mediatek/clk-mt8196-ovl1.c
···
1
+
// SPDX-License-Identifier: GPL-2.0-only
2
+
/*
3
+
* Copyright (c) 2025 MediaTek Inc.
4
+
* Guangjie Song <guangjie.song@mediatek.com>
5
+
* Copyright (c) 2025 Collabora Ltd.
6
+
* Laura Nao <laura.nao@collabora.com>
7
+
*/
8
+
#include <dt-bindings/clock/mediatek,mt8196-clock.h>
9
+
10
+
#include <linux/clk-provider.h>
11
+
#include <linux/module.h>
12
+
#include <linux/of_device.h>
13
+
#include <linux/platform_device.h>
14
+
15
+
#include "clk-gate.h"
16
+
#include "clk-mtk.h"
17
+
18
+
static const struct mtk_gate_regs ovl10_cg_regs = {
19
+
.set_ofs = 0x104,
20
+
.clr_ofs = 0x108,
21
+
.sta_ofs = 0x100,
22
+
};
23
+
24
+
static const struct mtk_gate_regs ovl10_hwv_regs = {
25
+
.set_ofs = 0x0050,
26
+
.clr_ofs = 0x0054,
27
+
.sta_ofs = 0x2c28,
28
+
};
29
+
30
+
static const struct mtk_gate_regs ovl11_cg_regs = {
31
+
.set_ofs = 0x114,
32
+
.clr_ofs = 0x118,
33
+
.sta_ofs = 0x110,
34
+
};
35
+
36
+
static const struct mtk_gate_regs ovl11_hwv_regs = {
37
+
.set_ofs = 0x0058,
38
+
.clr_ofs = 0x005c,
39
+
.sta_ofs = 0x2c2c,
40
+
};
41
+
42
+
#define GATE_HWV_OVL10(_id, _name, _parent, _shift) { \
43
+
.id = _id, \
44
+
.name = _name, \
45
+
.parent_name = _parent, \
46
+
.regs = &ovl10_cg_regs, \
47
+
.hwv_regs = &ovl10_hwv_regs, \
48
+
.shift = _shift, \
49
+
.ops = &mtk_clk_gate_hwv_ops_setclr, \
50
+
.flags = CLK_OPS_PARENT_ENABLE, \
51
+
}
52
+
53
+
#define GATE_HWV_OVL11(_id, _name, _parent, _shift) { \
54
+
.id = _id, \
55
+
.name = _name, \
56
+
.parent_name = _parent, \
57
+
.regs = &ovl11_cg_regs, \
58
+
.hwv_regs = &ovl11_hwv_regs, \
59
+
.shift = _shift, \
60
+
.ops = &mtk_clk_gate_hwv_ops_setclr, \
61
+
.flags = CLK_OPS_PARENT_ENABLE, \
62
+
}
63
+
64
+
static const struct mtk_gate ovl1_clks[] = {
65
+
/* OVL10 */
66
+
GATE_HWV_OVL10(CLK_OVL1_OVLSYS_CONFIG, "ovl1_ovlsys_config", "disp", 0),
67
+
GATE_HWV_OVL10(CLK_OVL1_OVL_FAKE_ENG0, "ovl1_ovl_fake_eng0", "disp", 1),
68
+
GATE_HWV_OVL10(CLK_OVL1_OVL_FAKE_ENG1, "ovl1_ovl_fake_eng1", "disp", 2),
69
+
GATE_HWV_OVL10(CLK_OVL1_OVL_MUTEX0, "ovl1_ovl_mutex0", "disp", 3),
70
+
GATE_HWV_OVL10(CLK_OVL1_OVL_EXDMA0, "ovl1_ovl_exdma0", "disp", 4),
71
+
GATE_HWV_OVL10(CLK_OVL1_OVL_EXDMA1, "ovl1_ovl_exdma1", "disp", 5),
72
+
GATE_HWV_OVL10(CLK_OVL1_OVL_EXDMA2, "ovl1_ovl_exdma2", "disp", 6),
73
+
GATE_HWV_OVL10(CLK_OVL1_OVL_EXDMA3, "ovl1_ovl_exdma3", "disp", 7),
74
+
GATE_HWV_OVL10(CLK_OVL1_OVL_EXDMA4, "ovl1_ovl_exdma4", "disp", 8),
75
+
GATE_HWV_OVL10(CLK_OVL1_OVL_EXDMA5, "ovl1_ovl_exdma5", "disp", 9),
76
+
GATE_HWV_OVL10(CLK_OVL1_OVL_EXDMA6, "ovl1_ovl_exdma6", "disp", 10),
77
+
GATE_HWV_OVL10(CLK_OVL1_OVL_EXDMA7, "ovl1_ovl_exdma7", "disp", 11),
78
+
GATE_HWV_OVL10(CLK_OVL1_OVL_EXDMA8, "ovl1_ovl_exdma8", "disp", 12),
79
+
GATE_HWV_OVL10(CLK_OVL1_OVL_EXDMA9, "ovl1_ovl_exdma9", "disp", 13),
80
+
GATE_HWV_OVL10(CLK_OVL1_OVL_BLENDER0, "ovl1_ovl_blender0", "disp", 14),
81
+
GATE_HWV_OVL10(CLK_OVL1_OVL_BLENDER1, "ovl1_ovl_blender1", "disp", 15),
82
+
GATE_HWV_OVL10(CLK_OVL1_OVL_BLENDER2, "ovl1_ovl_blender2", "disp", 16),
83
+
GATE_HWV_OVL10(CLK_OVL1_OVL_BLENDER3, "ovl1_ovl_blender3", "disp", 17),
84
+
GATE_HWV_OVL10(CLK_OVL1_OVL_BLENDER4, "ovl1_ovl_blender4", "disp", 18),
85
+
GATE_HWV_OVL10(CLK_OVL1_OVL_BLENDER5, "ovl1_ovl_blender5", "disp", 19),
86
+
GATE_HWV_OVL10(CLK_OVL1_OVL_BLENDER6, "ovl1_ovl_blender6", "disp", 20),
87
+
GATE_HWV_OVL10(CLK_OVL1_OVL_BLENDER7, "ovl1_ovl_blender7", "disp", 21),
88
+
GATE_HWV_OVL10(CLK_OVL1_OVL_BLENDER8, "ovl1_ovl_blender8", "disp", 22),
89
+
GATE_HWV_OVL10(CLK_OVL1_OVL_BLENDER9, "ovl1_ovl_blender9", "disp", 23),
90
+
GATE_HWV_OVL10(CLK_OVL1_OVL_OUTPROC0, "ovl1_ovl_outproc0", "disp", 24),
91
+
GATE_HWV_OVL10(CLK_OVL1_OVL_OUTPROC1, "ovl1_ovl_outproc1", "disp", 25),
92
+
GATE_HWV_OVL10(CLK_OVL1_OVL_OUTPROC2, "ovl1_ovl_outproc2", "disp", 26),
93
+
GATE_HWV_OVL10(CLK_OVL1_OVL_OUTPROC3, "ovl1_ovl_outproc3", "disp", 27),
94
+
GATE_HWV_OVL10(CLK_OVL1_OVL_OUTPROC4, "ovl1_ovl_outproc4", "disp", 28),
95
+
GATE_HWV_OVL10(CLK_OVL1_OVL_OUTPROC5, "ovl1_ovl_outproc5", "disp", 29),
96
+
GATE_HWV_OVL10(CLK_OVL1_OVL_MDP_RSZ0, "ovl1_ovl_mdp_rsz0", "disp", 30),
97
+
GATE_HWV_OVL10(CLK_OVL1_OVL_MDP_RSZ1, "ovl1_ovl_mdp_rsz1", "disp", 31),
98
+
/* OVL11 */
99
+
GATE_HWV_OVL11(CLK_OVL1_OVL_DISP_WDMA0, "ovl1_ovl_disp_wdma0", "disp", 0),
100
+
GATE_HWV_OVL11(CLK_OVL1_OVL_DISP_WDMA1, "ovl1_ovl_disp_wdma1", "disp", 1),
101
+
GATE_HWV_OVL11(CLK_OVL1_OVL_UFBC_WDMA0, "ovl1_ovl_ufbc_wdma0", "disp", 2),
102
+
GATE_HWV_OVL11(CLK_OVL1_OVL_MDP_RDMA0, "ovl1_ovl_mdp_rdma0", "disp", 3),
103
+
GATE_HWV_OVL11(CLK_OVL1_OVL_MDP_RDMA1, "ovl1_ovl_mdp_rdma1", "disp", 4),
104
+
GATE_HWV_OVL11(CLK_OVL1_OVL_BWM0, "ovl1_ovl_bwm0", "disp", 5),
105
+
GATE_HWV_OVL11(CLK_OVL1_DLI0, "ovl1_dli0", "disp", 6),
106
+
GATE_HWV_OVL11(CLK_OVL1_DLI1, "ovl1_dli1", "disp", 7),
107
+
GATE_HWV_OVL11(CLK_OVL1_DLI2, "ovl1_dli2", "disp", 8),
108
+
GATE_HWV_OVL11(CLK_OVL1_DLI3, "ovl1_dli3", "disp", 9),
109
+
GATE_HWV_OVL11(CLK_OVL1_DLI4, "ovl1_dli4", "disp", 10),
110
+
GATE_HWV_OVL11(CLK_OVL1_DLI5, "ovl1_dli5", "disp", 11),
111
+
GATE_HWV_OVL11(CLK_OVL1_DLI6, "ovl1_dli6", "disp", 12),
112
+
GATE_HWV_OVL11(CLK_OVL1_DLI7, "ovl1_dli7", "disp", 13),
113
+
GATE_HWV_OVL11(CLK_OVL1_DLI8, "ovl1_dli8", "disp", 14),
114
+
GATE_HWV_OVL11(CLK_OVL1_DLO0, "ovl1_dlo0", "disp", 15),
115
+
GATE_HWV_OVL11(CLK_OVL1_DLO1, "ovl1_dlo1", "disp", 16),
116
+
GATE_HWV_OVL11(CLK_OVL1_DLO2, "ovl1_dlo2", "disp", 17),
117
+
GATE_HWV_OVL11(CLK_OVL1_DLO3, "ovl1_dlo3", "disp", 18),
118
+
GATE_HWV_OVL11(CLK_OVL1_DLO4, "ovl1_dlo4", "disp", 19),
119
+
GATE_HWV_OVL11(CLK_OVL1_DLO5, "ovl1_dlo5", "disp", 20),
120
+
GATE_HWV_OVL11(CLK_OVL1_DLO6, "ovl1_dlo6", "disp", 21),
121
+
GATE_HWV_OVL11(CLK_OVL1_DLO7, "ovl1_dlo7", "disp", 22),
122
+
GATE_HWV_OVL11(CLK_OVL1_DLO8, "ovl1_dlo8", "disp", 23),
123
+
GATE_HWV_OVL11(CLK_OVL1_DLO9, "ovl1_dlo9", "disp", 24),
124
+
GATE_HWV_OVL11(CLK_OVL1_DLO10, "ovl1_dlo10", "disp", 25),
125
+
GATE_HWV_OVL11(CLK_OVL1_DLO11, "ovl1_dlo11", "disp", 26),
126
+
GATE_HWV_OVL11(CLK_OVL1_DLO12, "ovl1_dlo12", "disp", 27),
127
+
GATE_HWV_OVL11(CLK_OVL1_OVLSYS_RELAY0, "ovl1_ovlsys_relay0", "disp", 28),
128
+
GATE_HWV_OVL11(CLK_OVL1_OVL_INLINEROT0, "ovl1_ovl_inlinerot0", "disp", 29),
129
+
GATE_HWV_OVL11(CLK_OVL1_SMI, "ovl1_smi", "disp", 30),
130
+
};
131
+
132
+
static const struct mtk_clk_desc ovl1_mcd = {
133
+
.clks = ovl1_clks,
134
+
.num_clks = ARRAY_SIZE(ovl1_clks),
135
+
};
136
+
137
+
static const struct platform_device_id clk_mt8196_ovl1_id_table[] = {
138
+
{ .name = "clk-mt8196-ovl1", .driver_data = (kernel_ulong_t)&ovl1_mcd },
139
+
{ /* sentinel */ }
140
+
};
141
+
MODULE_DEVICE_TABLE(platform, clk_mt8196_ovl1_id_table);
142
+
143
+
static struct platform_driver clk_mt8196_ovl1_drv = {
144
+
.probe = mtk_clk_pdev_probe,
145
+
.remove = mtk_clk_pdev_remove,
146
+
.driver = {
147
+
.name = "clk-mt8196-ovl1",
148
+
},
149
+
.id_table = clk_mt8196_ovl1_id_table,
150
+
};
151
+
module_platform_driver(clk_mt8196_ovl1_drv);
152
+
153
+
MODULE_DESCRIPTION("MediaTek MT8196 ovl1 clocks driver");
154
+
MODULE_LICENSE("GPL");
+142
drivers/clk/mediatek/clk-mt8196-peri_ao.c
+142
drivers/clk/mediatek/clk-mt8196-peri_ao.c
···
1
+
// SPDX-License-Identifier: GPL-2.0-only
2
+
/*
3
+
* Copyright (c) 2025 MediaTek Inc.
4
+
* Guangjie Song <guangjie.song@mediatek.com>
5
+
* Copyright (c) 2025 Collabora Ltd.
6
+
* Laura Nao <laura.nao@collabora.com>
7
+
*/
8
+
#include <dt-bindings/clock/mediatek,mt8196-clock.h>
9
+
10
+
#include <linux/clk-provider.h>
11
+
#include <linux/module.h>
12
+
#include <linux/of_device.h>
13
+
#include <linux/platform_device.h>
14
+
15
+
#include "clk-gate.h"
16
+
#include "clk-mtk.h"
17
+
18
+
static const struct mtk_gate_regs peri_ao0_cg_regs = {
19
+
.set_ofs = 0x24,
20
+
.clr_ofs = 0x28,
21
+
.sta_ofs = 0x10,
22
+
};
23
+
24
+
static const struct mtk_gate_regs peri_ao1_cg_regs = {
25
+
.set_ofs = 0x2c,
26
+
.clr_ofs = 0x30,
27
+
.sta_ofs = 0x14,
28
+
};
29
+
30
+
static const struct mtk_gate_regs peri_ao1_hwv_regs = {
31
+
.set_ofs = 0x0008,
32
+
.clr_ofs = 0x000c,
33
+
.sta_ofs = 0x2c04,
34
+
};
35
+
36
+
static const struct mtk_gate_regs peri_ao2_cg_regs = {
37
+
.set_ofs = 0x34,
38
+
.clr_ofs = 0x38,
39
+
.sta_ofs = 0x18,
40
+
};
41
+
42
+
#define GATE_PERI_AO0(_id, _name, _parent, _shift) { \
43
+
.id = _id, \
44
+
.name = _name, \
45
+
.parent_name = _parent, \
46
+
.regs = &peri_ao0_cg_regs, \
47
+
.shift = _shift, \
48
+
.ops = &mtk_clk_gate_ops_setclr, \
49
+
}
50
+
51
+
#define GATE_PERI_AO1(_id, _name, _parent, _shift) { \
52
+
.id = _id, \
53
+
.name = _name, \
54
+
.parent_name = _parent, \
55
+
.regs = &peri_ao1_cg_regs, \
56
+
.shift = _shift, \
57
+
.ops = &mtk_clk_gate_ops_setclr, \
58
+
}
59
+
60
+
#define GATE_HWV_PERI_AO1(_id, _name, _parent, _shift) {\
61
+
.id = _id, \
62
+
.name = _name, \
63
+
.parent_name = _parent, \
64
+
.regs = &peri_ao1_cg_regs, \
65
+
.hwv_regs = &peri_ao1_hwv_regs, \
66
+
.shift = _shift, \
67
+
.ops = &mtk_clk_gate_hwv_ops_setclr, \
68
+
}
69
+
70
+
#define GATE_PERI_AO2(_id, _name, _parent, _shift) { \
71
+
.id = _id, \
72
+
.name = _name, \
73
+
.parent_name = _parent, \
74
+
.regs = &peri_ao2_cg_regs, \
75
+
.shift = _shift, \
76
+
.ops = &mtk_clk_gate_ops_setclr, \
77
+
}
78
+
79
+
static const struct mtk_gate peri_ao_clks[] = {
80
+
/* PERI_AO0 */
81
+
GATE_PERI_AO0(CLK_PERI_AO_UART0_BCLK, "peri_ao_uart0_bclk", "uart", 0),
82
+
GATE_PERI_AO0(CLK_PERI_AO_UART1_BCLK, "peri_ao_uart1_bclk", "uart", 1),
83
+
GATE_PERI_AO0(CLK_PERI_AO_UART2_BCLK, "peri_ao_uart2_bclk", "uart", 2),
84
+
GATE_PERI_AO0(CLK_PERI_AO_UART3_BCLK, "peri_ao_uart3_bclk", "uart", 3),
85
+
GATE_PERI_AO0(CLK_PERI_AO_UART4_BCLK, "peri_ao_uart4_bclk", "uart", 4),
86
+
GATE_PERI_AO0(CLK_PERI_AO_UART5_BCLK, "peri_ao_uart5_bclk", "uart", 5),
87
+
GATE_PERI_AO0(CLK_PERI_AO_PWM_X16W_HCLK, "peri_ao_pwm_x16w", "p_axi", 12),
88
+
GATE_PERI_AO0(CLK_PERI_AO_PWM_X16W_BCLK, "peri_ao_pwm_x16w_bclk", "pwm", 13),
89
+
GATE_PERI_AO0(CLK_PERI_AO_PWM_PWM_BCLK0, "peri_ao_pwm_pwm_bclk0", "pwm", 14),
90
+
GATE_PERI_AO0(CLK_PERI_AO_PWM_PWM_BCLK1, "peri_ao_pwm_pwm_bclk1", "pwm", 15),
91
+
GATE_PERI_AO0(CLK_PERI_AO_PWM_PWM_BCLK2, "peri_ao_pwm_pwm_bclk2", "pwm", 16),
92
+
GATE_PERI_AO0(CLK_PERI_AO_PWM_PWM_BCLK3, "peri_ao_pwm_pwm_bclk3", "pwm", 17),
93
+
/* PERI_AO1 */
94
+
GATE_HWV_PERI_AO1(CLK_PERI_AO_SPI0_BCLK, "peri_ao_spi0_bclk", "spi0_b", 0),
95
+
GATE_HWV_PERI_AO1(CLK_PERI_AO_SPI1_BCLK, "peri_ao_spi1_bclk", "spi1_b", 2),
96
+
GATE_HWV_PERI_AO1(CLK_PERI_AO_SPI2_BCLK, "peri_ao_spi2_bclk", "spi2_b", 3),
97
+
GATE_HWV_PERI_AO1(CLK_PERI_AO_SPI3_BCLK, "peri_ao_spi3_bclk", "spi3_b", 4),
98
+
GATE_HWV_PERI_AO1(CLK_PERI_AO_SPI4_BCLK, "peri_ao_spi4_bclk", "spi4_b", 5),
99
+
GATE_HWV_PERI_AO1(CLK_PERI_AO_SPI5_BCLK, "peri_ao_spi5_bclk", "spi5_b", 6),
100
+
GATE_HWV_PERI_AO1(CLK_PERI_AO_SPI6_BCLK, "peri_ao_spi6_bclk", "spi6_b", 7),
101
+
GATE_HWV_PERI_AO1(CLK_PERI_AO_SPI7_BCLK, "peri_ao_spi7_bclk", "spi7_b", 8),
102
+
GATE_PERI_AO1(CLK_PERI_AO_FLASHIF_FLASH, "peri_ao_flashif_flash", "peri_ao_flashif_27m",
103
+
18),
104
+
GATE_PERI_AO1(CLK_PERI_AO_FLASHIF_27M, "peri_ao_flashif_27m", "sflash", 19),
105
+
GATE_PERI_AO1(CLK_PERI_AO_FLASHIF_DRAM, "peri_ao_flashif_dram", "p_axi", 20),
106
+
GATE_PERI_AO1(CLK_PERI_AO_FLASHIF_AXI, "peri_ao_flashif_axi", "peri_ao_flashif_dram", 21),
107
+
GATE_PERI_AO1(CLK_PERI_AO_FLASHIF_BCLK, "peri_ao_flashif_bclk", "p_axi", 22),
108
+
GATE_PERI_AO1(CLK_PERI_AO_AP_DMA_X32W_BCLK, "peri_ao_ap_dma_x32w_bclk", "p_axi", 26),
109
+
/* PERI_AO2 */
110
+
GATE_PERI_AO2(CLK_PERI_AO_MSDC1_MSDC_SRC, "peri_ao_msdc1_msdc_src", "msdc30_1", 1),
111
+
GATE_PERI_AO2(CLK_PERI_AO_MSDC1_HCLK, "peri_ao_msdc1", "peri_ao_msdc1_axi", 2),
112
+
GATE_PERI_AO2(CLK_PERI_AO_MSDC1_AXI, "peri_ao_msdc1_axi", "p_axi", 3),
113
+
GATE_PERI_AO2(CLK_PERI_AO_MSDC1_HCLK_WRAP, "peri_ao_msdc1_h_wrap", "peri_ao_msdc1", 4),
114
+
GATE_PERI_AO2(CLK_PERI_AO_MSDC2_MSDC_SRC, "peri_ao_msdc2_msdc_src", "msdc30_2", 10),
115
+
GATE_PERI_AO2(CLK_PERI_AO_MSDC2_HCLK, "peri_ao_msdc2", "peri_ao_msdc2_axi", 11),
116
+
GATE_PERI_AO2(CLK_PERI_AO_MSDC2_AXI, "peri_ao_msdc2_axi", "p_axi", 12),
117
+
GATE_PERI_AO2(CLK_PERI_AO_MSDC2_HCLK_WRAP, "peri_ao_msdc2_h_wrap", "peri_ao_msdc2", 13),
118
+
};
119
+
120
+
static const struct mtk_clk_desc peri_ao_mcd = {
121
+
.clks = peri_ao_clks,
122
+
.num_clks = ARRAY_SIZE(peri_ao_clks),
123
+
};
124
+
125
+
static const struct of_device_id of_match_clk_mt8196_peri_ao[] = {
126
+
{ .compatible = "mediatek,mt8196-pericfg-ao", .data = &peri_ao_mcd },
127
+
{ /* sentinel */ }
128
+
};
129
+
MODULE_DEVICE_TABLE(of, of_match_clk_mt8196_peri_ao);
130
+
131
+
static struct platform_driver clk_mt8196_peri_ao_drv = {
132
+
.probe = mtk_clk_simple_probe,
133
+
.remove = mtk_clk_simple_remove,
134
+
.driver = {
135
+
.name = "clk-mt8196-peri-ao",
136
+
.of_match_table = of_match_clk_mt8196_peri_ao,
137
+
},
138
+
};
139
+
140
+
MODULE_DESCRIPTION("MediaTek MT8196 pericfg_ao clock controller driver");
141
+
module_platform_driver(clk_mt8196_peri_ao_drv);
142
+
MODULE_LICENSE("GPL");
+131
drivers/clk/mediatek/clk-mt8196-pextp.c
+131
drivers/clk/mediatek/clk-mt8196-pextp.c
···
1
+
// SPDX-License-Identifier: GPL-2.0-only
2
+
/*
3
+
* Copyright (c) 2025 MediaTek Inc.
4
+
* Guangjie Song <guangjie.song@mediatek.com>
5
+
* Copyright (c) 2025 Collabora Ltd.
6
+
* Laura Nao <laura.nao@collabora.com>
7
+
*/
8
+
#include <dt-bindings/clock/mediatek,mt8196-clock.h>
9
+
#include <dt-bindings/reset/mediatek,mt8196-resets.h>
10
+
11
+
#include <linux/clk-provider.h>
12
+
#include <linux/module.h>
13
+
#include <linux/of_device.h>
14
+
#include <linux/platform_device.h>
15
+
16
+
#include "clk-gate.h"
17
+
#include "clk-mtk.h"
18
+
#include "reset.h"
19
+
20
+
#define MT8196_PEXTP_RST0_SET_OFFSET 0x8
21
+
22
+
static const struct mtk_gate_regs pext_cg_regs = {
23
+
.set_ofs = 0x18,
24
+
.clr_ofs = 0x1c,
25
+
.sta_ofs = 0x14,
26
+
};
27
+
28
+
#define GATE_PEXT(_id, _name, _parent, _shift) {\
29
+
.id = _id, \
30
+
.name = _name, \
31
+
.parent_name = _parent, \
32
+
.regs = &pext_cg_regs, \
33
+
.shift = _shift, \
34
+
.ops = &mtk_clk_gate_ops_setclr,\
35
+
}
36
+
37
+
static const struct mtk_gate pext_clks[] = {
38
+
GATE_PEXT(CLK_PEXT_PEXTP_MAC_P0_TL, "pext_pm0_tl", "tl", 0),
39
+
GATE_PEXT(CLK_PEXT_PEXTP_MAC_P0_REF, "pext_pm0_ref", "clk26m", 1),
40
+
GATE_PEXT(CLK_PEXT_PEXTP_PHY_P0_MCU_BUS, "pext_pp0_mcu_bus", "clk26m", 6),
41
+
GATE_PEXT(CLK_PEXT_PEXTP_PHY_P0_PEXTP_REF, "pext_pp0_pextp_ref", "clk26m", 7),
42
+
GATE_PEXT(CLK_PEXT_PEXTP_MAC_P0_AXI_250, "pext_pm0_axi_250", "ufs_pexpt0_mem_sub", 12),
43
+
GATE_PEXT(CLK_PEXT_PEXTP_MAC_P0_AHB_APB, "pext_pm0_ahb_apb", "ufs_pextp0_axi", 13),
44
+
GATE_PEXT(CLK_PEXT_PEXTP_MAC_P0_PL_P, "pext_pm0_pl_p", "clk26m", 14),
45
+
GATE_PEXT(CLK_PEXT_PEXTP_VLP_AO_P0_LP, "pext_pextp_vlp_ao_p0_lp", "clk26m", 19),
46
+
};
47
+
48
+
static u16 pext_rst_ofs[] = { MT8196_PEXTP_RST0_SET_OFFSET };
49
+
50
+
static u16 pext_rst_idx_map[] = {
51
+
[MT8196_PEXTP0_RST0_PCIE0_MAC] = 0,
52
+
[MT8196_PEXTP0_RST0_PCIE0_PHY] = 1,
53
+
};
54
+
55
+
static const struct mtk_clk_rst_desc pext_rst_desc = {
56
+
.version = MTK_RST_SET_CLR,
57
+
.rst_bank_ofs = pext_rst_ofs,
58
+
.rst_bank_nr = ARRAY_SIZE(pext_rst_ofs),
59
+
.rst_idx_map = pext_rst_idx_map,
60
+
.rst_idx_map_nr = ARRAY_SIZE(pext_rst_idx_map),
61
+
};
62
+
63
+
static const struct mtk_clk_desc pext_mcd = {
64
+
.clks = pext_clks,
65
+
.num_clks = ARRAY_SIZE(pext_clks),
66
+
.rst_desc = &pext_rst_desc,
67
+
};
68
+
69
+
static const struct mtk_gate pext1_clks[] = {
70
+
GATE_PEXT(CLK_PEXT1_PEXTP_MAC_P1_TL, "pext1_pm1_tl", "tl_p1", 0),
71
+
GATE_PEXT(CLK_PEXT1_PEXTP_MAC_P1_REF, "pext1_pm1_ref", "clk26m", 1),
72
+
GATE_PEXT(CLK_PEXT1_PEXTP_MAC_P2_TL, "pext1_pm2_tl", "tl_p2", 2),
73
+
GATE_PEXT(CLK_PEXT1_PEXTP_MAC_P2_REF, "pext1_pm2_ref", "clk26m", 3),
74
+
GATE_PEXT(CLK_PEXT1_PEXTP_PHY_P1_MCU_BUS, "pext1_pp1_mcu_bus", "clk26m", 8),
75
+
GATE_PEXT(CLK_PEXT1_PEXTP_PHY_P1_PEXTP_REF, "pext1_pp1_pextp_ref", "clk26m", 9),
76
+
GATE_PEXT(CLK_PEXT1_PEXTP_PHY_P2_MCU_BUS, "pext1_pp2_mcu_bus", "clk26m", 10),
77
+
GATE_PEXT(CLK_PEXT1_PEXTP_PHY_P2_PEXTP_REF, "pext1_pp2_pextp_ref", "clk26m", 11),
78
+
GATE_PEXT(CLK_PEXT1_PEXTP_MAC_P1_AXI_250, "pext1_pm1_axi_250",
79
+
"pextp1_usb_axi", 16),
80
+
GATE_PEXT(CLK_PEXT1_PEXTP_MAC_P1_AHB_APB, "pext1_pm1_ahb_apb",
81
+
"pextp1_usb_mem_sub", 17),
82
+
GATE_PEXT(CLK_PEXT1_PEXTP_MAC_P1_PL_P, "pext1_pm1_pl_p", "clk26m", 18),
83
+
GATE_PEXT(CLK_PEXT1_PEXTP_MAC_P2_AXI_250, "pext1_pm2_axi_250",
84
+
"pextp1_usb_axi", 19),
85
+
GATE_PEXT(CLK_PEXT1_PEXTP_MAC_P2_AHB_APB, "pext1_pm2_ahb_apb",
86
+
"pextp1_usb_mem_sub", 20),
87
+
GATE_PEXT(CLK_PEXT1_PEXTP_MAC_P2_PL_P, "pext1_pm2_pl_p", "clk26m", 21),
88
+
GATE_PEXT(CLK_PEXT1_PEXTP_VLP_AO_P1_LP, "pext1_pextp_vlp_ao_p1_lp", "clk26m", 26),
89
+
GATE_PEXT(CLK_PEXT1_PEXTP_VLP_AO_P2_LP, "pext1_pextp_vlp_ao_p2_lp", "clk26m", 27),
90
+
};
91
+
92
+
static u16 pext1_rst_idx_map[] = {
93
+
[MT8196_PEXTP1_RST0_PCIE1_MAC] = 0,
94
+
[MT8196_PEXTP1_RST0_PCIE1_PHY] = 1,
95
+
[MT8196_PEXTP1_RST0_PCIE2_MAC] = 8,
96
+
[MT8196_PEXTP1_RST0_PCIE2_PHY] = 9,
97
+
};
98
+
99
+
static const struct mtk_clk_rst_desc pext1_rst_desc = {
100
+
.version = MTK_RST_SET_CLR,
101
+
.rst_bank_ofs = pext_rst_ofs,
102
+
.rst_bank_nr = ARRAY_SIZE(pext_rst_ofs),
103
+
.rst_idx_map = pext1_rst_idx_map,
104
+
.rst_idx_map_nr = ARRAY_SIZE(pext1_rst_idx_map),
105
+
};
106
+
107
+
static const struct mtk_clk_desc pext1_mcd = {
108
+
.clks = pext1_clks,
109
+
.num_clks = ARRAY_SIZE(pext1_clks),
110
+
.rst_desc = &pext1_rst_desc,
111
+
};
112
+
113
+
static const struct of_device_id of_match_clk_mt8196_pextp[] = {
114
+
{ .compatible = "mediatek,mt8196-pextp0cfg-ao", .data = &pext_mcd },
115
+
{ .compatible = "mediatek,mt8196-pextp1cfg-ao", .data = &pext1_mcd },
116
+
{ /* sentinel */ }
117
+
};
118
+
MODULE_DEVICE_TABLE(of, of_match_clk_mt8196_pextp);
119
+
120
+
static struct platform_driver clk_mt8196_pextp_drv = {
121
+
.probe = mtk_clk_simple_probe,
122
+
.remove = mtk_clk_simple_remove,
123
+
.driver = {
124
+
.name = "clk-mt8196-pextp",
125
+
.of_match_table = of_match_clk_mt8196_pextp,
126
+
},
127
+
};
128
+
129
+
module_platform_driver(clk_mt8196_pextp_drv);
130
+
MODULE_DESCRIPTION("MediaTek MT8196 PCIe transmit phy clocks driver");
131
+
MODULE_LICENSE("GPL");
+985
drivers/clk/mediatek/clk-mt8196-topckgen.c
+985
drivers/clk/mediatek/clk-mt8196-topckgen.c
···
1
+
// SPDX-License-Identifier: GPL-2.0-only
2
+
/*
3
+
* Copyright (c) 2025 MediaTek Inc.
4
+
* Guangjie Song <guangjie.song@mediatek.com>
5
+
* Copyright (c) 2025 Collabora Ltd.
6
+
* Laura Nao <laura.nao@collabora.com>
7
+
*/
8
+
#include <dt-bindings/clock/mediatek,mt8196-clock.h>
9
+
10
+
#include <linux/clk.h>
11
+
#include <linux/module.h>
12
+
#include <linux/of.h>
13
+
#include <linux/of_address.h>
14
+
#include <linux/of_device.h>
15
+
#include <linux/platform_device.h>
16
+
17
+
#include "clk-mtk.h"
18
+
#include "clk-mux.h"
19
+
20
+
/* MUX SEL REG */
21
+
#define CLK_CFG_UPDATE 0x0004
22
+
#define CLK_CFG_UPDATE1 0x0008
23
+
#define CLK_CFG_UPDATE2 0x000c
24
+
#define CLK_CFG_0 0x0010
25
+
#define CLK_CFG_0_SET 0x0014
26
+
#define CLK_CFG_0_CLR 0x0018
27
+
#define CLK_CFG_1 0x0020
28
+
#define CLK_CFG_1_SET 0x0024
29
+
#define CLK_CFG_1_CLR 0x0028
30
+
#define CLK_CFG_2 0x0030
31
+
#define CLK_CFG_2_SET 0x0034
32
+
#define CLK_CFG_2_CLR 0x0038
33
+
#define CLK_CFG_3 0x0040
34
+
#define CLK_CFG_3_SET 0x0044
35
+
#define CLK_CFG_3_CLR 0x0048
36
+
#define CLK_CFG_4 0x0050
37
+
#define CLK_CFG_4_SET 0x0054
38
+
#define CLK_CFG_4_CLR 0x0058
39
+
#define CLK_CFG_5 0x0060
40
+
#define CLK_CFG_5_SET 0x0064
41
+
#define CLK_CFG_5_CLR 0x0068
42
+
#define CLK_CFG_6 0x0070
43
+
#define CLK_CFG_6_SET 0x0074
44
+
#define CLK_CFG_6_CLR 0x0078
45
+
#define CLK_CFG_7 0x0080
46
+
#define CLK_CFG_7_SET 0x0084
47
+
#define CLK_CFG_7_CLR 0x0088
48
+
#define CLK_CFG_8 0x0090
49
+
#define CLK_CFG_8_SET 0x0094
50
+
#define CLK_CFG_8_CLR 0x0098
51
+
#define CLK_CFG_9 0x00a0
52
+
#define CLK_CFG_9_SET 0x00a4
53
+
#define CLK_CFG_9_CLR 0x00a8
54
+
#define CLK_CFG_10 0x00b0
55
+
#define CLK_CFG_10_SET 0x00b4
56
+
#define CLK_CFG_10_CLR 0x00b8
57
+
#define CLK_CFG_11 0x00c0
58
+
#define CLK_CFG_11_SET 0x00c4
59
+
#define CLK_CFG_11_CLR 0x00c8
60
+
#define CLK_CFG_12 0x00d0
61
+
#define CLK_CFG_12_SET 0x00d4
62
+
#define CLK_CFG_12_CLR 0x00d8
63
+
#define CLK_CFG_13 0x00e0
64
+
#define CLK_CFG_13_SET 0x00e4
65
+
#define CLK_CFG_13_CLR 0x00e8
66
+
#define CLK_CFG_14 0x00f0
67
+
#define CLK_CFG_14_SET 0x00f4
68
+
#define CLK_CFG_14_CLR 0x00f8
69
+
#define CLK_CFG_15 0x0100
70
+
#define CLK_CFG_15_SET 0x0104
71
+
#define CLK_CFG_15_CLR 0x0108
72
+
#define CLK_CFG_16 0x0110
73
+
#define CLK_CFG_16_SET 0x0114
74
+
#define CLK_CFG_16_CLR 0x0118
75
+
#define CLK_CFG_17 0x0120
76
+
#define CLK_CFG_17_SET 0x0124
77
+
#define CLK_CFG_17_CLR 0x0128
78
+
#define CLK_CFG_18 0x0130
79
+
#define CLK_CFG_18_SET 0x0134
80
+
#define CLK_CFG_18_CLR 0x0138
81
+
#define CLK_CFG_19 0x0140
82
+
#define CLK_CFG_19_SET 0x0144
83
+
#define CLK_CFG_19_CLR 0x0148
84
+
#define CLK_AUDDIV_0 0x020c
85
+
#define CLK_FENC_STATUS_MON_0 0x0270
86
+
#define CLK_FENC_STATUS_MON_1 0x0274
87
+
#define CLK_FENC_STATUS_MON_2 0x0278
88
+
89
+
/* MUX SHIFT */
90
+
#define TOP_MUX_AXI_SHIFT 0
91
+
#define TOP_MUX_MEM_SUB_SHIFT 1
92
+
#define TOP_MUX_IO_NOC_SHIFT 2
93
+
#define TOP_MUX_PERI_AXI_SHIFT 3
94
+
#define TOP_MUX_UFS_PEXTP0_AXI_SHIFT 4
95
+
#define TOP_MUX_PEXTP1_USB_AXI_SHIFT 5
96
+
#define TOP_MUX_PERI_FMEM_SUB_SHIFT 6
97
+
#define TOP_MUX_UFS_PEXPT0_MEM_SUB_SHIFT 7
98
+
#define TOP_MUX_PEXTP1_USB_MEM_SUB_SHIFT 8
99
+
#define TOP_MUX_PERI_NOC_SHIFT 9
100
+
#define TOP_MUX_EMI_N_SHIFT 10
101
+
#define TOP_MUX_EMI_S_SHIFT 11
102
+
#define TOP_MUX_AP2CONN_HOST_SHIFT 14
103
+
#define TOP_MUX_ATB_SHIFT 15
104
+
#define TOP_MUX_CIRQ_SHIFT 16
105
+
#define TOP_MUX_PBUS_156M_SHIFT 17
106
+
#define TOP_MUX_EFUSE_SHIFT 20
107
+
#define TOP_MUX_MCU_L3GIC_SHIFT 21
108
+
#define TOP_MUX_MCU_INFRA_SHIFT 22
109
+
#define TOP_MUX_DSP_SHIFT 23
110
+
#define TOP_MUX_MFG_REF_SHIFT 24
111
+
#define TOP_MUX_MFG_EB_SHIFT 26
112
+
#define TOP_MUX_UART_SHIFT 27
113
+
#define TOP_MUX_SPI0_BCLK_SHIFT 28
114
+
#define TOP_MUX_SPI1_BCLK_SHIFT 29
115
+
#define TOP_MUX_SPI2_BCLK_SHIFT 30
116
+
#define TOP_MUX_SPI3_BCLK_SHIFT 0
117
+
#define TOP_MUX_SPI4_BCLK_SHIFT 1
118
+
#define TOP_MUX_SPI5_BCLK_SHIFT 2
119
+
#define TOP_MUX_SPI6_BCLK_SHIFT 3
120
+
#define TOP_MUX_SPI7_BCLK_SHIFT 4
121
+
#define TOP_MUX_MSDC30_1_SHIFT 7
122
+
#define TOP_MUX_MSDC30_2_SHIFT 8
123
+
#define TOP_MUX_DISP_PWM_SHIFT 9
124
+
#define TOP_MUX_USB_TOP_1P_SHIFT 10
125
+
#define TOP_MUX_SSUSB_XHCI_1P_SHIFT 11
126
+
#define TOP_MUX_SSUSB_FMCNT_P1_SHIFT 12
127
+
#define TOP_MUX_I2C_PERI_SHIFT 13
128
+
#define TOP_MUX_I2C_EAST_SHIFT 14
129
+
#define TOP_MUX_I2C_WEST_SHIFT 15
130
+
#define TOP_MUX_I2C_NORTH_SHIFT 16
131
+
#define TOP_MUX_AES_UFSFDE_SHIFT 17
132
+
#define TOP_MUX_UFS_SHIFT 18
133
+
#define TOP_MUX_AUD_1_SHIFT 21
134
+
#define TOP_MUX_AUD_2_SHIFT 22
135
+
#define TOP_MUX_ADSP_SHIFT 23
136
+
#define TOP_MUX_ADSP_UARTHUB_B_SHIFT 24
137
+
#define TOP_MUX_DPMAIF_MAIN_SHIFT 25
138
+
#define TOP_MUX_PWM_SHIFT 26
139
+
#define TOP_MUX_MCUPM_SHIFT 27
140
+
#define TOP_MUX_SFLASH_SHIFT 28
141
+
#define TOP_MUX_IPSEAST_SHIFT 29
142
+
#define TOP_MUX_TL_SHIFT 0
143
+
#define TOP_MUX_TL_P1_SHIFT 1
144
+
#define TOP_MUX_TL_P2_SHIFT 2
145
+
#define TOP_MUX_EMI_INTERFACE_546_SHIFT 3
146
+
#define TOP_MUX_SDF_SHIFT 4
147
+
#define TOP_MUX_UARTHUB_BCLK_SHIFT 5
148
+
#define TOP_MUX_DPSW_CMP_26M_SHIFT 6
149
+
#define TOP_MUX_SMAPCK_SHIFT 7
150
+
#define TOP_MUX_SSR_PKA_SHIFT 8
151
+
#define TOP_MUX_SSR_DMA_SHIFT 9
152
+
#define TOP_MUX_SSR_KDF_SHIFT 10
153
+
#define TOP_MUX_SSR_RNG_SHIFT 11
154
+
#define TOP_MUX_SPU0_SHIFT 12
155
+
#define TOP_MUX_SPU1_SHIFT 13
156
+
#define TOP_MUX_DXCC_SHIFT 14
157
+
158
+
/* CKSTA REG */
159
+
#define CKSTA_REG 0x01c8
160
+
#define CKSTA_REG1 0x01cc
161
+
#define CKSTA_REG2 0x01d0
162
+
163
+
/* DIVIDER REG */
164
+
#define CLK_AUDDIV_2 0x0214
165
+
#define CLK_AUDDIV_3 0x0220
166
+
#define CLK_AUDDIV_4 0x0224
167
+
#define CLK_AUDDIV_5 0x0228
168
+
169
+
/* HW Voter REG */
170
+
#define HWV_CG_0_SET 0x0000
171
+
#define HWV_CG_0_CLR 0x0004
172
+
#define HWV_CG_0_DONE 0x2c00
173
+
#define HWV_CG_1_SET 0x0008
174
+
#define HWV_CG_1_CLR 0x000c
175
+
#define HWV_CG_1_DONE 0x2c04
176
+
#define HWV_CG_2_SET 0x0010
177
+
#define HWV_CG_2_CLR 0x0014
178
+
#define HWV_CG_2_DONE 0x2c08
179
+
#define HWV_CG_3_SET 0x0018
180
+
#define HWV_CG_3_CLR 0x001c
181
+
#define HWV_CG_3_DONE 0x2c0c
182
+
#define HWV_CG_4_SET 0x0020
183
+
#define HWV_CG_4_CLR 0x0024
184
+
#define HWV_CG_4_DONE 0x2c10
185
+
#define HWV_CG_5_SET 0x0028
186
+
#define HWV_CG_5_CLR 0x002c
187
+
#define HWV_CG_5_DONE 0x2c14
188
+
#define HWV_CG_6_SET 0x0030
189
+
#define HWV_CG_6_CLR 0x0034
190
+
#define HWV_CG_6_DONE 0x2c18
191
+
#define HWV_CG_7_SET 0x0038
192
+
#define HWV_CG_7_CLR 0x003c
193
+
#define HWV_CG_7_DONE 0x2c1c
194
+
#define HWV_CG_8_SET 0x0040
195
+
#define HWV_CG_8_CLR 0x0044
196
+
#define HWV_CG_8_DONE 0x2c20
197
+
198
+
static const struct mtk_fixed_factor top_divs[] = {
199
+
FACTOR(CLK_TOP_MAINPLL_D3, "mainpll_d3", "mainpll", 1, 3),
200
+
FACTOR(CLK_TOP_MAINPLL_D4, "mainpll_d4", "mainpll", 1, 4),
201
+
FACTOR(CLK_TOP_MAINPLL_D4_D2, "mainpll_d4_d2", "mainpll", 1, 8),
202
+
FACTOR(CLK_TOP_MAINPLL_D4_D4, "mainpll_d4_d4", "mainpll", 1, 16),
203
+
FACTOR(CLK_TOP_MAINPLL_D4_D8, "mainpll_d4_d8", "mainpll", 1, 32),
204
+
FACTOR(CLK_TOP_MAINPLL_D5, "mainpll_d5", "mainpll", 1, 5),
205
+
FACTOR(CLK_TOP_MAINPLL_D5_D2, "mainpll_d5_d2", "mainpll", 1, 10),
206
+
FACTOR(CLK_TOP_MAINPLL_D5_D4, "mainpll_d5_d4", "mainpll", 1, 20),
207
+
FACTOR(CLK_TOP_MAINPLL_D5_D8, "mainpll_d5_d8", "mainpll", 1, 40),
208
+
FACTOR(CLK_TOP_MAINPLL_D6, "mainpll_d6", "mainpll", 1, 6),
209
+
FACTOR(CLK_TOP_MAINPLL_D6_D2, "mainpll_d6_d2", "mainpll", 1, 12),
210
+
FACTOR(CLK_TOP_MAINPLL_D7, "mainpll_d7", "mainpll", 1, 7),
211
+
FACTOR(CLK_TOP_MAINPLL_D7_D2, "mainpll_d7_d2", "mainpll", 1, 14),
212
+
FACTOR(CLK_TOP_MAINPLL_D7_D4, "mainpll_d7_d4", "mainpll", 1, 28),
213
+
FACTOR(CLK_TOP_MAINPLL_D7_D8, "mainpll_d7_d8", "mainpll", 1, 56),
214
+
FACTOR(CLK_TOP_MAINPLL_D9, "mainpll_d9", "mainpll", 1, 9),
215
+
FACTOR(CLK_TOP_UNIVPLL_D4, "univpll_d4", "univpll", 1, 4),
216
+
FACTOR(CLK_TOP_UNIVPLL_D4_D2, "univpll_d4_d2", "univpll", 1, 8),
217
+
FACTOR(CLK_TOP_UNIVPLL_D4_D4, "univpll_d4_d4", "univpll", 1, 16),
218
+
FACTOR(CLK_TOP_UNIVPLL_D4_D8, "univpll_d4_d8", "univpll", 1, 32),
219
+
FACTOR(CLK_TOP_UNIVPLL_D5, "univpll_d5", "univpll", 1, 5),
220
+
FACTOR(CLK_TOP_UNIVPLL_D5_D2, "univpll_d5_d2", "univpll", 1, 10),
221
+
FACTOR(CLK_TOP_UNIVPLL_D5_D4, "univpll_d5_d4", "univpll", 1, 20),
222
+
FACTOR(CLK_TOP_UNIVPLL_D6, "univpll_d6", "univpll", 1, 6),
223
+
FACTOR(CLK_TOP_UNIVPLL_D6_D2, "univpll_d6_d2", "univpll", 1, 12),
224
+
FACTOR(CLK_TOP_UNIVPLL_D6_D4, "univpll_d6_d4", "univpll", 1, 24),
225
+
FACTOR(CLK_TOP_UNIVPLL_D6_D8, "univpll_d6_d8", "univpll", 1, 48),
226
+
FACTOR(CLK_TOP_UNIVPLL_D6_D16, "univpll_d6_d16", "univpll", 1, 96),
227
+
FACTOR(CLK_TOP_UNIVPLL_192M, "univpll_192m", "univpll", 1, 13),
228
+
FACTOR(CLK_TOP_UNIVPLL_192M_D4, "univpll_192m_d4", "univpll", 1, 52),
229
+
FACTOR(CLK_TOP_UNIVPLL_192M_D8, "univpll_192m_d8", "univpll", 1, 104),
230
+
FACTOR(CLK_TOP_UNIVPLL_192M_D16, "univpll_192m_d16", "univpll", 1, 208),
231
+
FACTOR(CLK_TOP_UNIVPLL_192M_D32, "univpll_192m_d32", "univpll", 1, 416),
232
+
FACTOR(CLK_TOP_UNIVPLL_192M_D10, "univpll_192m_d10", "univpll", 1, 130),
233
+
FACTOR(CLK_TOP_TVDPLL1_D2, "tvdpll1_d2", "tvdpll1", 1, 2),
234
+
FACTOR(CLK_TOP_MSDCPLL_D2, "msdcpll_d2", "msdcpll", 1, 2),
235
+
FACTOR(CLK_TOP_OSC_D2, "osc_d2", "ulposc", 1, 2),
236
+
FACTOR(CLK_TOP_OSC_D3, "osc_d3", "ulposc", 1, 3),
237
+
FACTOR(CLK_TOP_OSC_D4, "osc_d4", "ulposc", 1, 4),
238
+
FACTOR(CLK_TOP_OSC_D5, "osc_d5", "ulposc", 1, 5),
239
+
FACTOR(CLK_TOP_OSC_D7, "osc_d7", "ulposc", 1, 7),
240
+
FACTOR(CLK_TOP_OSC_D8, "osc_d8", "ulposc", 1, 8),
241
+
FACTOR(CLK_TOP_OSC_D10, "osc_d10", "ulposc", 1, 10),
242
+
FACTOR(CLK_TOP_OSC_D14, "osc_d14", "ulposc", 1, 14),
243
+
FACTOR(CLK_TOP_OSC_D20, "osc_d20", "ulposc", 1, 20),
244
+
FACTOR(CLK_TOP_OSC_D32, "osc_d32", "ulposc", 1, 32),
245
+
FACTOR(CLK_TOP_OSC_D40, "osc_d40", "ulposc", 1, 40),
246
+
};
247
+
248
+
static const char * const axi_parents[] = {
249
+
"clk26m",
250
+
"osc_d20",
251
+
"osc_d8",
252
+
"osc_d4",
253
+
"mainpll_d4_d4",
254
+
"mainpll_d7_d2"
255
+
};
256
+
257
+
static const char * const mem_sub_parents[] = {
258
+
"clk26m",
259
+
"osc_d20",
260
+
"osc_d4",
261
+
"univpll_d4_d4",
262
+
"osc_d3",
263
+
"mainpll_d5_d2",
264
+
"mainpll_d4_d2",
265
+
"mainpll_d6",
266
+
"mainpll_d5",
267
+
"univpll_d5",
268
+
"mainpll_d4",
269
+
"mainpll_d3"
270
+
};
271
+
272
+
static const char * const io_noc_parents[] = {
273
+
"clk26m",
274
+
"osc_d20",
275
+
"osc_d8",
276
+
"osc_d4",
277
+
"mainpll_d6_d2",
278
+
"mainpll_d9"
279
+
};
280
+
281
+
static const char * const shared_axi_parents[] = {
282
+
"clk26m",
283
+
"mainpll_d7_d8",
284
+
"mainpll_d5_d8",
285
+
"osc_d8",
286
+
"mainpll_d7_d4",
287
+
"mainpll_d5_d4",
288
+
"mainpll_d4_d4",
289
+
"mainpll_d7_d2"
290
+
};
291
+
292
+
static const char * const shared_sub_parents[] = {
293
+
"clk26m",
294
+
"mainpll_d5_d8",
295
+
"mainpll_d5_d4",
296
+
"osc_d4",
297
+
"univpll_d4_d4",
298
+
"mainpll_d5_d2",
299
+
"mainpll_d4_d2",
300
+
"mainpll_d6",
301
+
"mainpll_d5",
302
+
"univpll_d5",
303
+
"mainpll_d4"
304
+
};
305
+
306
+
static const char * const p_noc_parents[] = {
307
+
"clk26m",
308
+
"mainpll_d5_d8",
309
+
"mainpll_d5_d4",
310
+
"osc_d4",
311
+
"univpll_d4_d4",
312
+
"mainpll_d5_d2",
313
+
"mainpll_d4_d2",
314
+
"mainpll_d6",
315
+
"mainpll_d5",
316
+
"univpll_d5",
317
+
"mainpll_d4",
318
+
"mainpll_d3"
319
+
};
320
+
321
+
static const char * const emi_parents[] = {
322
+
"clk26m",
323
+
"osc_d4",
324
+
"mainpll_d5_d8",
325
+
"mainpll_d5_d4",
326
+
"mainpll_d4_d4",
327
+
"emipll1_ck"
328
+
};
329
+
330
+
static const char * const ap2conn_host_parents[] = {
331
+
"clk26m",
332
+
"mainpll_d7_d4"
333
+
};
334
+
335
+
static const char * const atb_parents[] = {
336
+
"clk26m",
337
+
"mainpll_d5_d2",
338
+
"mainpll_d4_d2",
339
+
"mainpll_d6"
340
+
};
341
+
342
+
static const char * const cirq_parents[] = {
343
+
"clk26m",
344
+
"osc_d20",
345
+
"mainpll_d7_d4"
346
+
};
347
+
348
+
static const char * const pbus_156m_parents[] = {
349
+
"clk26m",
350
+
"mainpll_d7_d2",
351
+
"osc_d2",
352
+
"mainpll_d7"
353
+
};
354
+
355
+
static const char * const efuse_parents[] = {
356
+
"clk26m",
357
+
"osc_d20"
358
+
};
359
+
360
+
static const char * const mcu_l3gic_parents[] = {
361
+
"clk26m",
362
+
"osc_d8",
363
+
"mainpll_d4_d4",
364
+
"mainpll_d7_d2"
365
+
};
366
+
367
+
static const char * const mcu_infra_parents[] = {
368
+
"clk26m",
369
+
"osc_d20",
370
+
"mainpll_d7_d2",
371
+
"mainpll_d5_d2",
372
+
"mainpll_d4_d2",
373
+
"mainpll_d9",
374
+
"mainpll_d6"
375
+
};
376
+
377
+
static const char * const dsp_parents[] = {
378
+
"clk26m",
379
+
"osc_d5",
380
+
"osc_d4",
381
+
"osc_d3",
382
+
"univpll_d6_d2",
383
+
"osc_d2",
384
+
"univpll_d5",
385
+
"osc"
386
+
};
387
+
388
+
static const char * const mfg_ref_parents[] = {
389
+
"clk26m",
390
+
"mainpll_d7_d2"
391
+
};
392
+
393
+
static const char * const mfg_eb_parents[] = {
394
+
"clk26m",
395
+
"mainpll_d7_d2",
396
+
"mainpll_d6_d2",
397
+
"mainpll_d5_d2"
398
+
};
399
+
400
+
static const char * const uart_parents[] = {
401
+
"clk26m",
402
+
"univpll_d6_d8",
403
+
"univpll_d6_d4",
404
+
"univpll_d6_d2"
405
+
};
406
+
407
+
static const char * const spi_b_parents[] = {
408
+
"clk26m",
409
+
"univpll_d6_d4",
410
+
"univpll_d5_d4",
411
+
"mainpll_d4_d4",
412
+
"univpll_d4_d4",
413
+
"mainpll_d6_d2",
414
+
"univpll_192m",
415
+
"univpll_d6_d2"
416
+
};
417
+
418
+
static const char * const msdc30_parents[] = {
419
+
"clk26m",
420
+
"univpll_d6_d4",
421
+
"mainpll_d6_d2",
422
+
"univpll_d6_d2",
423
+
"msdcpll_d2"
424
+
};
425
+
426
+
static const char * const disp_pwm_parents[] = {
427
+
"clk26m",
428
+
"osc_d32",
429
+
"osc_d8",
430
+
"univpll_d6_d4",
431
+
"univpll_d5_d4",
432
+
"osc_d4",
433
+
"mainpll_d4_d4"
434
+
};
435
+
436
+
static const char * const usb_1p_parents[] = {
437
+
"clk26m",
438
+
"univpll_d5_d4"
439
+
};
440
+
441
+
static const char * const usb_fmcnt_p1_parents[] = {
442
+
"clk26m",
443
+
"univpll_192m_d4"
444
+
};
445
+
446
+
static const char * const i2c_parents[] = {
447
+
"clk26m",
448
+
"mainpll_d4_d8",
449
+
"univpll_d5_d4",
450
+
"mainpll_d4_d4",
451
+
"univpll_d5_d2"
452
+
};
453
+
454
+
static const char * const aes_ufsfde_parents[] = {
455
+
"clk26m",
456
+
"mainpll_d4_d4",
457
+
"univpll_d6_d2",
458
+
"mainpll_d4_d2",
459
+
"univpll_d6",
460
+
"mainpll_d4"
461
+
};
462
+
463
+
static const char * const ufs_parents[] = {
464
+
"clk26m",
465
+
"mainpll_d4_d4",
466
+
"univpll_d6_d2",
467
+
"mainpll_d4_d2",
468
+
"univpll_d6",
469
+
"mainpll_d5",
470
+
"univpll_d5"
471
+
};
472
+
473
+
static const char * const aud_1_parents[] = {
474
+
"clk26m",
475
+
"vlp_apll1"
476
+
};
477
+
478
+
static const char * const aud_2_parents[] = {
479
+
"clk26m",
480
+
"vlp_apll2"
481
+
};
482
+
483
+
static const char * const adsp_parents[] = {
484
+
"clk26m",
485
+
"adsppll"
486
+
};
487
+
488
+
static const char * const adsp_uarthub_b_parents[] = {
489
+
"clk26m",
490
+
"univpll_d6_d4",
491
+
"univpll_d6_d2"
492
+
};
493
+
494
+
static const char * const dpmaif_main_parents[] = {
495
+
"clk26m",
496
+
"univpll_d4_d4",
497
+
"univpll_d5_d2",
498
+
"mainpll_d4_d2",
499
+
"univpll_d4_d2",
500
+
"mainpll_d6",
501
+
"univpll_d6",
502
+
"mainpll_d5",
503
+
"univpll_d5"
504
+
};
505
+
506
+
static const char * const pwm_parents[] = {
507
+
"clk26m",
508
+
"mainpll_d7_d4",
509
+
"univpll_d4_d8"
510
+
};
511
+
512
+
static const char * const mcupm_parents[] = {
513
+
"clk26m",
514
+
"mainpll_d7_d2",
515
+
"mainpll_d6_d2",
516
+
"univpll_d6_d2",
517
+
"mainpll_d5_d2"
518
+
};
519
+
520
+
static const char * const ipseast_parents[] = {
521
+
"clk26m",
522
+
"mainpll_d6",
523
+
"mainpll_d5",
524
+
"mainpll_d4",
525
+
"mainpll_d3"
526
+
};
527
+
528
+
static const char * const tl_parents[] = {
529
+
"clk26m",
530
+
"mainpll_d7_d4",
531
+
"mainpll_d4_d4",
532
+
"mainpll_d5_d2"
533
+
};
534
+
535
+
static const char * const md_emi_parents[] = {
536
+
"clk26m",
537
+
"mainpll_d4"
538
+
};
539
+
540
+
static const char * const sdf_parents[] = {
541
+
"clk26m",
542
+
"mainpll_d5_d2",
543
+
"mainpll_d4_d2",
544
+
"mainpll_d6",
545
+
"mainpll_d4",
546
+
"univpll_d4"
547
+
};
548
+
549
+
static const char * const uarthub_b_parents[] = {
550
+
"clk26m",
551
+
"univpll_d6_d4",
552
+
"univpll_d6_d2"
553
+
};
554
+
555
+
static const char * const dpsw_cmp_26m_parents[] = {
556
+
"clk26m",
557
+
"osc_d20"
558
+
};
559
+
560
+
static const char * const smapparents[] = {
561
+
"clk26m",
562
+
"mainpll_d4_d8"
563
+
};
564
+
565
+
static const char * const ssr_parents[] = {
566
+
"clk26m",
567
+
"mainpll_d4_d4",
568
+
"mainpll_d4_d2",
569
+
"mainpll_d7",
570
+
"mainpll_d6",
571
+
"mainpll_d5"
572
+
};
573
+
574
+
static const char * const ssr_kdf_parents[] = {
575
+
"clk26m",
576
+
"mainpll_d4_d4",
577
+
"mainpll_d4_d2",
578
+
"mainpll_d7"
579
+
};
580
+
581
+
static const char * const ssr_rng_parents[] = {
582
+
"clk26m",
583
+
"mainpll_d4_d4",
584
+
"mainpll_d5_d2",
585
+
"mainpll_d4_d2"
586
+
};
587
+
588
+
static const char * const spu_parents[] = {
589
+
"clk26m",
590
+
"mainpll_d4_d4",
591
+
"mainpll_d4_d2",
592
+
"mainpll_d7",
593
+
"mainpll_d6",
594
+
"mainpll_d5"
595
+
};
596
+
597
+
static const char * const dxcc_parents[] = {
598
+
"clk26m",
599
+
"mainpll_d4_d8",
600
+
"mainpll_d4_d4",
601
+
"mainpll_d4_d2"
602
+
};
603
+
604
+
static const char * const apll_m_parents[] = {
605
+
"aud_1",
606
+
"aud_2"
607
+
};
608
+
609
+
static const char * const sflash_parents[] = {
610
+
"clk26m",
611
+
"mainpll_d7_d8",
612
+
"univpll_d6_d8"
613
+
};
614
+
615
+
static const struct mtk_mux top_muxes[] = {
616
+
/* CLK_CFG_0 */
617
+
MUX_CLR_SET_UPD(CLK_TOP_AXI, "axi",
618
+
axi_parents, CLK_CFG_0, CLK_CFG_0_SET,
619
+
CLK_CFG_0_CLR, 0, 3,
620
+
CLK_CFG_UPDATE, TOP_MUX_AXI_SHIFT),
621
+
MUX_CLR_SET_UPD(CLK_TOP_MEM_SUB, "mem_sub",
622
+
mem_sub_parents, CLK_CFG_0, CLK_CFG_0_SET,
623
+
CLK_CFG_0_CLR, 8, 4,
624
+
CLK_CFG_UPDATE, TOP_MUX_MEM_SUB_SHIFT),
625
+
MUX_CLR_SET_UPD(CLK_TOP_IO_NOC, "io_noc",
626
+
io_noc_parents, CLK_CFG_0, CLK_CFG_0_SET,
627
+
CLK_CFG_0_CLR, 16, 3,
628
+
CLK_CFG_UPDATE, TOP_MUX_IO_NOC_SHIFT),
629
+
MUX_CLR_SET_UPD(CLK_TOP_P_AXI, "p_axi",
630
+
shared_axi_parents, CLK_CFG_0, CLK_CFG_0_SET,
631
+
CLK_CFG_0_CLR, 24, 3,
632
+
CLK_CFG_UPDATE, TOP_MUX_PERI_AXI_SHIFT),
633
+
/* CLK_CFG_1 */
634
+
MUX_CLR_SET_UPD(CLK_TOP_UFS_PEXTP0_AXI, "ufs_pextp0_axi",
635
+
shared_axi_parents, CLK_CFG_1, CLK_CFG_1_SET,
636
+
CLK_CFG_1_CLR, 0, 3,
637
+
CLK_CFG_UPDATE, TOP_MUX_UFS_PEXTP0_AXI_SHIFT),
638
+
MUX_CLR_SET_UPD(CLK_TOP_PEXTP1_USB_AXI, "pextp1_usb_axi",
639
+
shared_axi_parents, CLK_CFG_1, CLK_CFG_1_SET,
640
+
CLK_CFG_1_CLR, 8, 3,
641
+
CLK_CFG_UPDATE, TOP_MUX_PEXTP1_USB_AXI_SHIFT),
642
+
MUX_CLR_SET_UPD(CLK_TOP_P_FMEM_SUB, "p_fmem_sub",
643
+
shared_sub_parents, CLK_CFG_1, CLK_CFG_1_SET,
644
+
CLK_CFG_1_CLR, 16, 4,
645
+
CLK_CFG_UPDATE, TOP_MUX_PERI_FMEM_SUB_SHIFT),
646
+
MUX_CLR_SET_UPD(CLK_TOP_PEXPT0_MEM_SUB, "ufs_pexpt0_mem_sub",
647
+
shared_sub_parents, CLK_CFG_1, CLK_CFG_1_SET,
648
+
CLK_CFG_1_CLR, 24, 4,
649
+
CLK_CFG_UPDATE, TOP_MUX_UFS_PEXPT0_MEM_SUB_SHIFT),
650
+
/* CLK_CFG_2 */
651
+
MUX_CLR_SET_UPD(CLK_TOP_PEXTP1_USB_MEM_SUB, "pextp1_usb_mem_sub",
652
+
shared_sub_parents, CLK_CFG_2, CLK_CFG_2_SET,
653
+
CLK_CFG_2_CLR, 0, 4,
654
+
CLK_CFG_UPDATE, TOP_MUX_PEXTP1_USB_MEM_SUB_SHIFT),
655
+
MUX_CLR_SET_UPD(CLK_TOP_P_NOC, "p_noc",
656
+
p_noc_parents, CLK_CFG_2, CLK_CFG_2_SET,
657
+
CLK_CFG_2_CLR, 8, 4,
658
+
CLK_CFG_UPDATE, TOP_MUX_PERI_NOC_SHIFT),
659
+
MUX_CLR_SET_UPD(CLK_TOP_EMI_N, "emi_n",
660
+
emi_parents, CLK_CFG_2, CLK_CFG_2_SET,
661
+
CLK_CFG_2_CLR, 16, 3,
662
+
CLK_CFG_UPDATE, TOP_MUX_EMI_N_SHIFT),
663
+
MUX_CLR_SET_UPD(CLK_TOP_EMI_S, "emi_s",
664
+
emi_parents, CLK_CFG_2, CLK_CFG_2_SET,
665
+
CLK_CFG_2_CLR, 24, 3,
666
+
CLK_CFG_UPDATE, TOP_MUX_EMI_S_SHIFT),
667
+
/* CLK_CFG_3 */
668
+
MUX_CLR_SET_UPD(CLK_TOP_AP2CONN_HOST, "ap2conn_host",
669
+
ap2conn_host_parents, CLK_CFG_3, CLK_CFG_3_SET,
670
+
CLK_CFG_3_CLR, 16, 1,
671
+
CLK_CFG_UPDATE, TOP_MUX_AP2CONN_HOST_SHIFT),
672
+
MUX_CLR_SET_UPD(CLK_TOP_ATB, "atb",
673
+
atb_parents, CLK_CFG_3, CLK_CFG_3_SET,
674
+
CLK_CFG_3_CLR, 24, 2,
675
+
CLK_CFG_UPDATE, TOP_MUX_ATB_SHIFT),
676
+
/* CLK_CFG_4 */
677
+
MUX_CLR_SET_UPD(CLK_TOP_CIRQ, "cirq",
678
+
cirq_parents, CLK_CFG_4, CLK_CFG_4_SET,
679
+
CLK_CFG_4_CLR, 0, 2,
680
+
CLK_CFG_UPDATE, TOP_MUX_CIRQ_SHIFT),
681
+
MUX_CLR_SET_UPD(CLK_TOP_PBUS_156M, "pbus_156m",
682
+
pbus_156m_parents, CLK_CFG_4, CLK_CFG_4_SET,
683
+
CLK_CFG_4_CLR, 8, 2,
684
+
CLK_CFG_UPDATE, TOP_MUX_PBUS_156M_SHIFT),
685
+
/* CLK_CFG_5 */
686
+
MUX_CLR_SET_UPD(CLK_TOP_EFUSE, "efuse",
687
+
efuse_parents, CLK_CFG_5, CLK_CFG_5_SET,
688
+
CLK_CFG_5_CLR, 0, 1,
689
+
CLK_CFG_UPDATE, TOP_MUX_EFUSE_SHIFT),
690
+
MUX_CLR_SET_UPD(CLK_TOP_MCL3GIC, "mcu_l3gic",
691
+
mcu_l3gic_parents, CLK_CFG_5, CLK_CFG_5_SET,
692
+
CLK_CFG_5_CLR, 8, 2,
693
+
CLK_CFG_UPDATE, TOP_MUX_MCU_L3GIC_SHIFT),
694
+
MUX_CLR_SET_UPD(CLK_TOP_MCINFRA, "mcu_infra",
695
+
mcu_infra_parents, CLK_CFG_5, CLK_CFG_5_SET,
696
+
CLK_CFG_5_CLR, 16, 3,
697
+
CLK_CFG_UPDATE, TOP_MUX_MCU_INFRA_SHIFT),
698
+
MUX_CLR_SET_UPD(CLK_TOP_DSP, "dsp",
699
+
dsp_parents, CLK_CFG_5, CLK_CFG_5_SET,
700
+
CLK_CFG_5_CLR, 24, 3,
701
+
CLK_CFG_UPDATE, TOP_MUX_DSP_SHIFT),
702
+
/* CLK_CFG_6 */
703
+
MUX_GATE_FENC_CLR_SET_UPD_FLAGS(CLK_TOP_MFG_REF, "mfg_ref", mfg_ref_parents,
704
+
NULL, ARRAY_SIZE(mfg_ref_parents),
705
+
CLK_CFG_6, CLK_CFG_6_SET, CLK_CFG_6_CLR,
706
+
0, 1, 7, CLK_CFG_UPDATE, TOP_MUX_MFG_REF_SHIFT,
707
+
CLK_FENC_STATUS_MON_0, 7, CLK_IGNORE_UNUSED),
708
+
MUX_GATE_CLR_SET_UPD(CLK_TOP_MFG_EB, "mfg_eb",
709
+
mfg_eb_parents, CLK_CFG_6, CLK_CFG_6_SET,
710
+
CLK_CFG_6_CLR, 16, 2,
711
+
23, CLK_CFG_UPDATE, TOP_MUX_MFG_EB_SHIFT),
712
+
MUX_GATE_HWV_FENC_CLR_SET_UPD(CLK_TOP_UART, "uart", uart_parents,
713
+
CLK_CFG_6, CLK_CFG_6_SET, CLK_CFG_6_CLR,
714
+
HWV_CG_3_DONE, HWV_CG_3_SET, HWV_CG_3_CLR,
715
+
24, 2, 31, CLK_CFG_UPDATE, TOP_MUX_UART_SHIFT,
716
+
CLK_FENC_STATUS_MON_0, 4),
717
+
/* CLK_CFG_7 */
718
+
MUX_GATE_HWV_FENC_CLR_SET_UPD(CLK_TOP_SPI0_BCLK, "spi0_b", spi_b_parents,
719
+
CLK_CFG_7, CLK_CFG_7_SET, CLK_CFG_7_CLR,
720
+
HWV_CG_4_DONE, HWV_CG_4_SET, HWV_CG_4_CLR,
721
+
0, 3, 7, CLK_CFG_UPDATE, TOP_MUX_SPI0_BCLK_SHIFT,
722
+
CLK_FENC_STATUS_MON_0, 3),
723
+
MUX_GATE_HWV_FENC_CLR_SET_UPD(CLK_TOP_SPI1_BCLK, "spi1_b", spi_b_parents,
724
+
CLK_CFG_7, CLK_CFG_7_SET, CLK_CFG_7_CLR,
725
+
HWV_CG_4_DONE, HWV_CG_4_SET, HWV_CG_4_CLR,
726
+
8, 3, 15, CLK_CFG_UPDATE, TOP_MUX_SPI1_BCLK_SHIFT,
727
+
CLK_FENC_STATUS_MON_0, 2),
728
+
MUX_GATE_HWV_FENC_CLR_SET_UPD(CLK_TOP_SPI2_BCLK, "spi2_b", spi_b_parents,
729
+
CLK_CFG_7, CLK_CFG_7_SET, CLK_CFG_7_CLR,
730
+
HWV_CG_4_DONE, HWV_CG_4_SET, HWV_CG_4_CLR,
731
+
16, 3, 23, CLK_CFG_UPDATE, TOP_MUX_SPI2_BCLK_SHIFT,
732
+
CLK_FENC_STATUS_MON_0, 1),
733
+
MUX_GATE_HWV_FENC_CLR_SET_UPD(CLK_TOP_SPI3_BCLK, "spi3_b", spi_b_parents,
734
+
CLK_CFG_7, CLK_CFG_7_SET, CLK_CFG_7_CLR,
735
+
HWV_CG_4_DONE, HWV_CG_4_SET, HWV_CG_4_CLR,
736
+
24, 3, 31, CLK_CFG_UPDATE1, TOP_MUX_SPI3_BCLK_SHIFT,
737
+
CLK_FENC_STATUS_MON_0, 0),
738
+
/* CLK_CFG_8 */
739
+
MUX_GATE_HWV_FENC_CLR_SET_UPD(CLK_TOP_SPI4_BCLK, "spi4_b", spi_b_parents,
740
+
CLK_CFG_8, CLK_CFG_8_SET, CLK_CFG_8_CLR,
741
+
HWV_CG_5_DONE, HWV_CG_5_SET, HWV_CG_5_CLR,
742
+
0, 3, 7, CLK_CFG_UPDATE1, TOP_MUX_SPI4_BCLK_SHIFT,
743
+
CLK_FENC_STATUS_MON_1, 31),
744
+
MUX_GATE_HWV_FENC_CLR_SET_UPD(CLK_TOP_SPI5_BCLK, "spi5_b", spi_b_parents,
745
+
CLK_CFG_8, CLK_CFG_8_SET, CLK_CFG_8_CLR,
746
+
HWV_CG_5_DONE, HWV_CG_5_SET, HWV_CG_5_CLR,
747
+
8, 3, 15, CLK_CFG_UPDATE1, TOP_MUX_SPI5_BCLK_SHIFT,
748
+
CLK_FENC_STATUS_MON_1, 30),
749
+
MUX_GATE_HWV_FENC_CLR_SET_UPD(CLK_TOP_SPI6_BCLK, "spi6_b", spi_b_parents,
750
+
CLK_CFG_8, CLK_CFG_8_SET, CLK_CFG_8_CLR,
751
+
HWV_CG_5_DONE, HWV_CG_5_SET, HWV_CG_5_CLR,
752
+
16, 3, 23, CLK_CFG_UPDATE1, TOP_MUX_SPI6_BCLK_SHIFT,
753
+
CLK_FENC_STATUS_MON_1, 29),
754
+
MUX_GATE_HWV_FENC_CLR_SET_UPD(CLK_TOP_SPI7_BCLK, "spi7_b", spi_b_parents,
755
+
CLK_CFG_8, CLK_CFG_8_SET, CLK_CFG_8_CLR,
756
+
HWV_CG_5_DONE, HWV_CG_5_SET, HWV_CG_5_CLR,
757
+
24, 3, 31, CLK_CFG_UPDATE1, TOP_MUX_SPI7_BCLK_SHIFT,
758
+
CLK_FENC_STATUS_MON_1, 28),
759
+
/* CLK_CFG_9 */
760
+
MUX_GATE_FENC_CLR_SET_UPD(CLK_TOP_MSDC30_1, "msdc30_1", msdc30_parents,
761
+
CLK_CFG_9, CLK_CFG_9_SET, CLK_CFG_9_CLR,
762
+
16, 3, 23, CLK_CFG_UPDATE1, TOP_MUX_MSDC30_1_SHIFT,
763
+
CLK_FENC_STATUS_MON_1, 25),
764
+
MUX_GATE_FENC_CLR_SET_UPD(CLK_TOP_MSDC30_2, "msdc30_2", msdc30_parents,
765
+
CLK_CFG_9, CLK_CFG_9_SET, CLK_CFG_9_CLR,
766
+
24, 3, 31, CLK_CFG_UPDATE1, TOP_MUX_MSDC30_2_SHIFT,
767
+
CLK_FENC_STATUS_MON_1, 24),
768
+
/* CLK_CFG_10 */
769
+
MUX_GATE_FENC_CLR_SET_UPD(CLK_TOP_DISP_PWM, "disp_pwm", disp_pwm_parents,
770
+
CLK_CFG_10, CLK_CFG_10_SET, CLK_CFG_10_CLR,
771
+
0, 3, 7, CLK_CFG_UPDATE1, TOP_MUX_DISP_PWM_SHIFT,
772
+
CLK_FENC_STATUS_MON_1, 23),
773
+
MUX_GATE_FENC_CLR_SET_UPD(CLK_TOP_USB_TOP_1P, "usb_1p", usb_1p_parents,
774
+
CLK_CFG_10, CLK_CFG_10_SET, CLK_CFG_10_CLR,
775
+
8, 1, 15, CLK_CFG_UPDATE1, TOP_MUX_USB_TOP_1P_SHIFT,
776
+
CLK_FENC_STATUS_MON_1, 22),
777
+
MUX_GATE_FENC_CLR_SET_UPD(CLK_TOP_USB_XHCI_1P, "usb_xhci_1p", usb_1p_parents,
778
+
CLK_CFG_10, CLK_CFG_10_SET, CLK_CFG_10_CLR,
779
+
16, 1, 23, CLK_CFG_UPDATE1, TOP_MUX_SSUSB_XHCI_1P_SHIFT,
780
+
CLK_FENC_STATUS_MON_1, 21),
781
+
MUX_GATE_FENC_CLR_SET_UPD(CLK_TOP_USB_FMCNT_P1, "usb_fmcnt_p1", usb_fmcnt_p1_parents,
782
+
CLK_CFG_10, CLK_CFG_10_SET, CLK_CFG_10_CLR,
783
+
24, 1, 31, CLK_CFG_UPDATE1, TOP_MUX_SSUSB_FMCNT_P1_SHIFT,
784
+
CLK_FENC_STATUS_MON_1, 20),
785
+
/* CLK_CFG_11 */
786
+
MUX_GATE_FENC_CLR_SET_UPD(CLK_TOP_I2C_P, "i2c_p", i2c_parents,
787
+
CLK_CFG_11, CLK_CFG_11_SET, CLK_CFG_11_CLR,
788
+
0, 3, 7, CLK_CFG_UPDATE1, TOP_MUX_I2C_PERI_SHIFT,
789
+
CLK_FENC_STATUS_MON_1, 19),
790
+
MUX_GATE_FENC_CLR_SET_UPD(CLK_TOP_I2C_EAST, "i2c_east", i2c_parents,
791
+
CLK_CFG_11, CLK_CFG_11_SET, CLK_CFG_11_CLR,
792
+
8, 3, 15, CLK_CFG_UPDATE1, TOP_MUX_I2C_EAST_SHIFT,
793
+
CLK_FENC_STATUS_MON_1, 18),
794
+
MUX_GATE_FENC_CLR_SET_UPD(CLK_TOP_I2C_WEST, "i2c_west", i2c_parents,
795
+
CLK_CFG_11, CLK_CFG_11_SET, CLK_CFG_11_CLR,
796
+
16, 3, 23, CLK_CFG_UPDATE1, TOP_MUX_I2C_WEST_SHIFT,
797
+
CLK_FENC_STATUS_MON_1, 17),
798
+
MUX_GATE_HWV_FENC_CLR_SET_UPD(CLK_TOP_I2C_NORTH, "i2c_north", i2c_parents,
799
+
CLK_CFG_11, CLK_CFG_11_SET, CLK_CFG_11_CLR,
800
+
HWV_CG_6_DONE, HWV_CG_6_SET, HWV_CG_6_CLR,
801
+
24, 3, 31, CLK_CFG_UPDATE1, TOP_MUX_I2C_NORTH_SHIFT,
802
+
CLK_FENC_STATUS_MON_1, 16),
803
+
/* CLK_CFG_12 */
804
+
MUX_GATE_FENC_CLR_SET_UPD(CLK_TOP_AES_UFSFDE, "aes_ufsfde", aes_ufsfde_parents,
805
+
CLK_CFG_12, CLK_CFG_12_SET, CLK_CFG_12_CLR,
806
+
0, 3, 7, CLK_CFG_UPDATE1, TOP_MUX_AES_UFSFDE_SHIFT,
807
+
CLK_FENC_STATUS_MON_1, 15),
808
+
MUX_GATE_FENC_CLR_SET_UPD(CLK_TOP_UFS, "ufs", ufs_parents,
809
+
CLK_CFG_12, CLK_CFG_12_SET, CLK_CFG_12_CLR,
810
+
8, 3, 15, CLK_CFG_UPDATE1, TOP_MUX_UFS_SHIFT,
811
+
CLK_FENC_STATUS_MON_1, 14),
812
+
/* CLK_CFG_13 */
813
+
MUX_GATE_FENC_CLR_SET_UPD(CLK_TOP_AUD_1, "aud_1", aud_1_parents,
814
+
CLK_CFG_13, CLK_CFG_13_SET, CLK_CFG_13_CLR,
815
+
0, 1, 7, CLK_CFG_UPDATE1, TOP_MUX_AUD_1_SHIFT,
816
+
CLK_FENC_STATUS_MON_1, 11),
817
+
MUX_GATE_FENC_CLR_SET_UPD(CLK_TOP_AUD_2, "aud_2", aud_2_parents,
818
+
CLK_CFG_13, CLK_CFG_13_SET, CLK_CFG_13_CLR,
819
+
8, 1, 15, CLK_CFG_UPDATE1, TOP_MUX_AUD_2_SHIFT,
820
+
CLK_FENC_STATUS_MON_1, 10),
821
+
MUX_GATE_FENC_CLR_SET_UPD(CLK_TOP_ADSP, "adsp", adsp_parents,
822
+
CLK_CFG_13, CLK_CFG_13_SET, CLK_CFG_13_CLR,
823
+
16, 1, 23, CLK_CFG_UPDATE1, TOP_MUX_ADSP_SHIFT,
824
+
CLK_FENC_STATUS_MON_1, 9),
825
+
MUX_GATE_CLR_SET_UPD(CLK_TOP_ADSP_UARTHUB_B, "adsp_uarthub_b",
826
+
adsp_uarthub_b_parents, CLK_CFG_13, CLK_CFG_13_SET,
827
+
CLK_CFG_13_CLR, 24, 2, 31,
828
+
CLK_CFG_UPDATE1, TOP_MUX_ADSP_UARTHUB_B_SHIFT),
829
+
/* CLK_CFG_14 */
830
+
MUX_GATE_FENC_CLR_SET_UPD(CLK_TOP_DPMAIF_MAIN, "dpmaif_main", dpmaif_main_parents,
831
+
CLK_CFG_14, CLK_CFG_14_SET, CLK_CFG_14_CLR,
832
+
0, 4, 7, CLK_CFG_UPDATE1, TOP_MUX_DPMAIF_MAIN_SHIFT,
833
+
CLK_FENC_STATUS_MON_1, 7),
834
+
MUX_GATE_FENC_CLR_SET_UPD(CLK_TOP_PWM, "pwm", pwm_parents,
835
+
CLK_CFG_14, CLK_CFG_14_SET, CLK_CFG_14_CLR,
836
+
8, 2, 15, CLK_CFG_UPDATE1, TOP_MUX_PWM_SHIFT,
837
+
CLK_FENC_STATUS_MON_1, 6),
838
+
MUX_CLR_SET_UPD(CLK_TOP_MCUPM, "mcupm",
839
+
mcupm_parents, CLK_CFG_14, CLK_CFG_14_SET,
840
+
CLK_CFG_14_CLR, 16, 3,
841
+
CLK_CFG_UPDATE1, TOP_MUX_MCUPM_SHIFT),
842
+
MUX_GATE_FENC_CLR_SET_UPD(CLK_TOP_SFLASH, "sflash", sflash_parents,
843
+
CLK_CFG_14, CLK_CFG_14_SET, CLK_CFG_14_CLR,
844
+
24, 2, 31, CLK_CFG_UPDATE1, TOP_MUX_SFLASH_SHIFT,
845
+
CLK_FENC_STATUS_MON_1, 4),
846
+
/* CLK_CFG_15 */
847
+
MUX_GATE_FENC_CLR_SET_UPD(CLK_TOP_IPSEAST, "ipseast", ipseast_parents,
848
+
CLK_CFG_15, CLK_CFG_15_SET, CLK_CFG_15_CLR,
849
+
0, 3, 7, CLK_CFG_UPDATE1, TOP_MUX_IPSEAST_SHIFT,
850
+
CLK_FENC_STATUS_MON_1, 3),
851
+
MUX_GATE_FENC_CLR_SET_UPD(CLK_TOP_TL, "tl", tl_parents,
852
+
CLK_CFG_15, CLK_CFG_15_SET, CLK_CFG_15_CLR,
853
+
16, 2, 23, CLK_CFG_UPDATE2, TOP_MUX_TL_SHIFT,
854
+
CLK_FENC_STATUS_MON_1, 1),
855
+
MUX_GATE_FENC_CLR_SET_UPD(CLK_TOP_TL_P1, "tl_p1", tl_parents,
856
+
CLK_CFG_15, CLK_CFG_15_SET, CLK_CFG_15_CLR,
857
+
24, 2, 31, CLK_CFG_UPDATE2, TOP_MUX_TL_P1_SHIFT,
858
+
CLK_FENC_STATUS_MON_1, 0),
859
+
/* CLK_CFG_16 */
860
+
MUX_GATE_FENC_CLR_SET_UPD(CLK_TOP_TL_P2, "tl_p2", tl_parents,
861
+
CLK_CFG_16, CLK_CFG_16_SET, CLK_CFG_16_CLR,
862
+
0, 2, 7, CLK_CFG_UPDATE2, TOP_MUX_TL_P2_SHIFT,
863
+
CLK_FENC_STATUS_MON_2, 31),
864
+
MUX_CLR_SET_UPD(CLK_TOP_EMI_INTERFACE_546, "emi_interface_546",
865
+
md_emi_parents, CLK_CFG_16, CLK_CFG_16_SET,
866
+
CLK_CFG_16_CLR, 8, 1,
867
+
CLK_CFG_UPDATE2, TOP_MUX_EMI_INTERFACE_546_SHIFT),
868
+
MUX_CLR_SET_UPD(CLK_TOP_SDF, "sdf",
869
+
sdf_parents, CLK_CFG_16, CLK_CFG_16_SET,
870
+
CLK_CFG_16_CLR, 16, 3,
871
+
CLK_CFG_UPDATE2, TOP_MUX_SDF_SHIFT),
872
+
MUX_GATE_HWV_FENC_CLR_SET_UPD(CLK_TOP_UARTHUB_BCLK, "uarthub_b", uarthub_b_parents,
873
+
CLK_CFG_16, CLK_CFG_16_SET, CLK_CFG_16_CLR,
874
+
HWV_CG_7_DONE, HWV_CG_7_SET, HWV_CG_7_CLR,
875
+
24, 2, 31, CLK_CFG_UPDATE2, TOP_MUX_UARTHUB_BCLK_SHIFT,
876
+
CLK_FENC_STATUS_MON_2, 28),
877
+
/* CLK_CFG_17 */
878
+
MUX_CLR_SET_UPD(CLK_TOP_DPSW_CMP_26M, "dpsw_cmp_26m",
879
+
dpsw_cmp_26m_parents, CLK_CFG_17, CLK_CFG_17_SET,
880
+
CLK_CFG_17_CLR, 0, 1,
881
+
CLK_CFG_UPDATE2, TOP_MUX_DPSW_CMP_26M_SHIFT),
882
+
MUX_CLR_SET_UPD(CLK_TOP_SMAP, "smap",
883
+
smapparents, CLK_CFG_17, CLK_CFG_17_SET,
884
+
CLK_CFG_17_CLR, 8, 1,
885
+
CLK_CFG_UPDATE2, TOP_MUX_SMAPCK_SHIFT),
886
+
MUX_CLR_SET_UPD(CLK_TOP_SSR_PKA, "ssr_pka",
887
+
ssr_parents, CLK_CFG_17, CLK_CFG_17_SET,
888
+
CLK_CFG_17_CLR, 16, 3,
889
+
CLK_CFG_UPDATE2, TOP_MUX_SSR_PKA_SHIFT),
890
+
MUX_CLR_SET_UPD(CLK_TOP_SSR_DMA, "ssr_dma",
891
+
ssr_parents, CLK_CFG_17, CLK_CFG_17_SET,
892
+
CLK_CFG_17_CLR, 24, 3,
893
+
CLK_CFG_UPDATE2, TOP_MUX_SSR_DMA_SHIFT),
894
+
/* CLK_CFG_18 */
895
+
MUX_CLR_SET_UPD(CLK_TOP_SSR_KDF, "ssr_kdf",
896
+
ssr_kdf_parents, CLK_CFG_18, CLK_CFG_18_SET,
897
+
CLK_CFG_18_CLR, 0, 2,
898
+
CLK_CFG_UPDATE2, TOP_MUX_SSR_KDF_SHIFT),
899
+
MUX_CLR_SET_UPD(CLK_TOP_SSR_RNG, "ssr_rng",
900
+
ssr_rng_parents, CLK_CFG_18, CLK_CFG_18_SET,
901
+
CLK_CFG_18_CLR, 8, 2,
902
+
CLK_CFG_UPDATE2, TOP_MUX_SSR_RNG_SHIFT),
903
+
MUX_CLR_SET_UPD(CLK_TOP_SPU0, "spu0",
904
+
spu_parents, CLK_CFG_18, CLK_CFG_18_SET,
905
+
CLK_CFG_18_CLR, 16, 3,
906
+
CLK_CFG_UPDATE2, TOP_MUX_SPU0_SHIFT),
907
+
MUX_CLR_SET_UPD(CLK_TOP_SPU1, "spu1",
908
+
spu_parents, CLK_CFG_18, CLK_CFG_18_SET,
909
+
CLK_CFG_18_CLR, 24, 3,
910
+
CLK_CFG_UPDATE2, TOP_MUX_SPU1_SHIFT),
911
+
/* CLK_CFG_19 */
912
+
MUX_CLR_SET_UPD(CLK_TOP_DXCC, "dxcc",
913
+
dxcc_parents, CLK_CFG_19, CLK_CFG_19_SET,
914
+
CLK_CFG_19_CLR, 0, 2,
915
+
CLK_CFG_UPDATE2, TOP_MUX_DXCC_SHIFT),
916
+
};
917
+
918
+
static const struct mtk_composite top_aud_divs[] = {
919
+
/* CLK_AUDDIV_2 */
920
+
MUX_DIV_GATE(CLK_TOP_APLL_I2SIN0, "apll_i2sin0_m", apll_m_parents,
921
+
CLK_AUDDIV_0, 16, 1, CLK_AUDDIV_2, 0, 8, CLK_AUDDIV_0, 0),
922
+
MUX_DIV_GATE(CLK_TOP_APLL_I2SIN1, "apll_i2sin1_m", apll_m_parents,
923
+
CLK_AUDDIV_0, 17, 1, CLK_AUDDIV_2, 8, 8, CLK_AUDDIV_0, 1),
924
+
MUX_DIV_GATE(CLK_TOP_APLL_I2SIN2, "apll_i2sin2_m", apll_m_parents,
925
+
CLK_AUDDIV_0, 18, 1, CLK_AUDDIV_2, 16, 8, CLK_AUDDIV_0, 2),
926
+
MUX_DIV_GATE(CLK_TOP_APLL_I2SIN3, "apll_i2sin3_m", apll_m_parents,
927
+
CLK_AUDDIV_0, 19, 1, CLK_AUDDIV_2, 24, 8, CLK_AUDDIV_0, 3),
928
+
/* CLK_AUDDIV_3 */
929
+
MUX_DIV_GATE(CLK_TOP_APLL_I2SIN4, "apll_i2sin4_m", apll_m_parents,
930
+
CLK_AUDDIV_0, 20, 1, CLK_AUDDIV_3, 0, 8, CLK_AUDDIV_0, 4),
931
+
MUX_DIV_GATE(CLK_TOP_APLL_I2SIN6, "apll_i2sin6_m", apll_m_parents,
932
+
CLK_AUDDIV_0, 21, 1, CLK_AUDDIV_3, 8, 8, CLK_AUDDIV_0, 5),
933
+
MUX_DIV_GATE(CLK_TOP_APLL_I2SOUT0, "apll_i2sout0_m", apll_m_parents,
934
+
CLK_AUDDIV_0, 22, 1, CLK_AUDDIV_3, 16, 8, CLK_AUDDIV_0, 6),
935
+
MUX_DIV_GATE(CLK_TOP_APLL_I2SOUT1, "apll_i2sout1_m", apll_m_parents,
936
+
CLK_AUDDIV_0, 23, 1, CLK_AUDDIV_3, 24, 8, CLK_AUDDIV_0, 7),
937
+
/* CLK_AUDDIV_4 */
938
+
MUX_DIV_GATE(CLK_TOP_APLL_I2SOUT2, "apll_i2sout2_m", apll_m_parents,
939
+
CLK_AUDDIV_0, 24, 1, CLK_AUDDIV_4, 0, 8, CLK_AUDDIV_0, 8),
940
+
MUX_DIV_GATE(CLK_TOP_APLL_I2SOUT3, "apll_i2sout3_m", apll_m_parents,
941
+
CLK_AUDDIV_0, 25, 1, CLK_AUDDIV_4, 8, 8, CLK_AUDDIV_0, 9),
942
+
MUX_DIV_GATE(CLK_TOP_APLL_I2SOUT4, "apll_i2sout4_m", apll_m_parents,
943
+
CLK_AUDDIV_0, 26, 1, CLK_AUDDIV_4, 16, 8, CLK_AUDDIV_0, 10),
944
+
MUX_DIV_GATE(CLK_TOP_APLL_I2SOUT6, "apll_i2sout6_m", apll_m_parents,
945
+
CLK_AUDDIV_0, 27, 1, CLK_AUDDIV_4, 24, 8, CLK_AUDDIV_0, 11),
946
+
/* CLK_AUDDIV_5 */
947
+
MUX_DIV_GATE(CLK_TOP_APLL_FMI2S, "apll_fmi2s_m", apll_m_parents,
948
+
CLK_AUDDIV_0, 28, 1, CLK_AUDDIV_5, 0, 8, CLK_AUDDIV_0, 12),
949
+
MUX(CLK_TOP_APLL_TDMOUT, "apll_tdmout_m",
950
+
apll_m_parents, CLK_AUDDIV_0, 29, 1),
951
+
DIV_GATE(CLK_TOP_APLL12_DIV_TDMOUT_M, "apll12_div_tdmout_m",
952
+
"apll_tdmout_m", CLK_AUDDIV_0,
953
+
13, CLK_AUDDIV_5, 8, 8),
954
+
DIV_GATE(CLK_TOP_APLL12_DIV_TDMOUT_B, "apll12_div_tdmout_b",
955
+
"apll_tdmout_m", CLK_AUDDIV_0,
956
+
14, CLK_AUDDIV_5, 8, 16),
957
+
};
958
+
959
+
static const struct mtk_clk_desc topck_desc = {
960
+
.factor_clks = top_divs,
961
+
.num_factor_clks = ARRAY_SIZE(top_divs),
962
+
.mux_clks = top_muxes,
963
+
.num_mux_clks = ARRAY_SIZE(top_muxes),
964
+
.composite_clks = top_aud_divs,
965
+
.num_composite_clks = ARRAY_SIZE(top_aud_divs)
966
+
};
967
+
968
+
static const struct of_device_id of_match_clk_mt8196_ck[] = {
969
+
{ .compatible = "mediatek,mt8196-topckgen", .data = &topck_desc },
970
+
{ /* sentinel */ }
971
+
};
972
+
MODULE_DEVICE_TABLE(of, of_match_clk_mt8196_ck);
973
+
974
+
static struct platform_driver clk_mt8196_topck_drv = {
975
+
.probe = mtk_clk_simple_probe,
976
+
.remove = mtk_clk_simple_remove,
977
+
.driver = {
978
+
.name = "clk-mt8196-topck",
979
+
.of_match_table = of_match_clk_mt8196_ck,
980
+
},
981
+
};
982
+
983
+
MODULE_DESCRIPTION("MediaTek MT8196 top clock generators driver");
984
+
module_platform_driver(clk_mt8196_topck_drv);
985
+
MODULE_LICENSE("GPL");
+568
drivers/clk/mediatek/clk-mt8196-topckgen2.c
+568
drivers/clk/mediatek/clk-mt8196-topckgen2.c
···
1
+
// SPDX-License-Identifier: GPL-2.0-only
2
+
/*
3
+
* Copyright (c) 2025 MediaTek Inc.
4
+
* Guangjie Song <guangjie.song@mediatek.com>
5
+
* Copyright (c) 2025 Collabora Ltd.
6
+
* Laura Nao <laura.nao@collabora.com>
7
+
*/
8
+
#include <dt-bindings/clock/mediatek,mt8196-clock.h>
9
+
10
+
#include <linux/clk.h>
11
+
#include <linux/module.h>
12
+
#include <linux/of.h>
13
+
#include <linux/of_address.h>
14
+
#include <linux/of_device.h>
15
+
#include <linux/platform_device.h>
16
+
17
+
#include "clk-mtk.h"
18
+
#include "clk-mux.h"
19
+
20
+
/* MUX SEL REG */
21
+
#define CKSYS2_CLK_CFG_UPDATE 0x0004
22
+
#define CKSYS2_CLK_CFG_0 0x0010
23
+
#define CKSYS2_CLK_CFG_0_SET 0x0014
24
+
#define CKSYS2_CLK_CFG_0_CLR 0x0018
25
+
#define CKSYS2_CLK_CFG_1 0x0020
26
+
#define CKSYS2_CLK_CFG_1_SET 0x0024
27
+
#define CKSYS2_CLK_CFG_1_CLR 0x0028
28
+
#define CKSYS2_CLK_CFG_2 0x0030
29
+
#define CKSYS2_CLK_CFG_2_SET 0x0034
30
+
#define CKSYS2_CLK_CFG_2_CLR 0x0038
31
+
#define CKSYS2_CLK_CFG_3 0x0040
32
+
#define CKSYS2_CLK_CFG_3_SET 0x0044
33
+
#define CKSYS2_CLK_CFG_3_CLR 0x0048
34
+
#define CKSYS2_CLK_CFG_4 0x0050
35
+
#define CKSYS2_CLK_CFG_4_SET 0x0054
36
+
#define CKSYS2_CLK_CFG_4_CLR 0x0058
37
+
#define CKSYS2_CLK_CFG_5 0x0060
38
+
#define CKSYS2_CLK_CFG_5_SET 0x0064
39
+
#define CKSYS2_CLK_CFG_5_CLR 0x0068
40
+
#define CKSYS2_CLK_CFG_6 0x0070
41
+
#define CKSYS2_CLK_CFG_6_SET 0x0074
42
+
#define CKSYS2_CLK_CFG_6_CLR 0x0078
43
+
#define CKSYS2_CLK_FENC_STATUS_MON_0 0x0174
44
+
45
+
/* MUX SHIFT */
46
+
#define TOP_MUX_SENINF0_SHIFT 0
47
+
#define TOP_MUX_SENINF1_SHIFT 1
48
+
#define TOP_MUX_SENINF2_SHIFT 2
49
+
#define TOP_MUX_SENINF3_SHIFT 3
50
+
#define TOP_MUX_SENINF4_SHIFT 4
51
+
#define TOP_MUX_SENINF5_SHIFT 5
52
+
#define TOP_MUX_IMG1_SHIFT 6
53
+
#define TOP_MUX_IPE_SHIFT 7
54
+
#define TOP_MUX_CAM_SHIFT 8
55
+
#define TOP_MUX_CAMTM_SHIFT 9
56
+
#define TOP_MUX_DPE_SHIFT 10
57
+
#define TOP_MUX_VDEC_SHIFT 11
58
+
#define TOP_MUX_CCUSYS_SHIFT 12
59
+
#define TOP_MUX_CCUTM_SHIFT 13
60
+
#define TOP_MUX_VENC_SHIFT 14
61
+
#define TOP_MUX_DVO_SHIFT 15
62
+
#define TOP_MUX_DVO_FAVT_SHIFT 16
63
+
#define TOP_MUX_DP1_SHIFT 17
64
+
#define TOP_MUX_DP0_SHIFT 18
65
+
#define TOP_MUX_DISP_SHIFT 19
66
+
#define TOP_MUX_MDP_SHIFT 20
67
+
#define TOP_MUX_MMINFRA_SHIFT 21
68
+
#define TOP_MUX_MMINFRA_SNOC_SHIFT 22
69
+
#define TOP_MUX_MMUP_SHIFT 23
70
+
#define TOP_MUX_MMINFRA_AO_SHIFT 26
71
+
72
+
/* HW Voter REG */
73
+
#define HWV_CG_30_SET 0x0058
74
+
#define HWV_CG_30_CLR 0x005c
75
+
#define HWV_CG_30_DONE 0x2c2c
76
+
77
+
#define MM_HWV_CG_30_SET 0x00f0
78
+
#define MM_HWV_CG_30_CLR 0x00f4
79
+
#define MM_HWV_CG_30_DONE 0x2c78
80
+
#define MM_HWV_CG_31_SET 0x00f8
81
+
#define MM_HWV_CG_31_CLR 0x00fc
82
+
#define MM_HWV_CG_31_DONE 0x2c7c
83
+
#define MM_HWV_CG_32_SET 0x0100
84
+
#define MM_HWV_CG_32_CLR 0x0104
85
+
#define MM_HWV_CG_32_DONE 0x2c80
86
+
#define MM_HWV_CG_33_SET 0x0108
87
+
#define MM_HWV_CG_33_CLR 0x010c
88
+
#define MM_HWV_CG_33_DONE 0x2c84
89
+
#define MM_HWV_CG_34_SET 0x0110
90
+
#define MM_HWV_CG_34_CLR 0x0114
91
+
#define MM_HWV_CG_34_DONE 0x2c88
92
+
#define MM_HWV_CG_35_SET 0x0118
93
+
#define MM_HWV_CG_35_CLR 0x011c
94
+
#define MM_HWV_CG_35_DONE 0x2c8c
95
+
#define MM_HWV_CG_36_SET 0x0120
96
+
#define MM_HWV_CG_36_CLR 0x0124
97
+
#define MM_HWV_CG_36_DONE 0x2c90
98
+
#define MM_HWV_MUX_UPDATE_31_0 0x0240
99
+
100
+
static const struct mtk_fixed_factor top_divs[] = {
101
+
FACTOR(CLK_TOP2_MAINPLL2_D2, "mainpll2_d2", "mainpll2", 1, 2),
102
+
FACTOR(CLK_TOP2_MAINPLL2_D3, "mainpll2_d3", "mainpll2", 1, 3),
103
+
FACTOR(CLK_TOP2_MAINPLL2_D4, "mainpll2_d4", "mainpll2", 1, 4),
104
+
FACTOR(CLK_TOP2_MAINPLL2_D4_D2, "mainpll2_d4_d2", "mainpll2", 1, 8),
105
+
FACTOR(CLK_TOP2_MAINPLL2_D4_D4, "mainpll2_d4_d4", "mainpll2", 1, 16),
106
+
FACTOR(CLK_TOP2_MAINPLL2_D5, "mainpll2_d5", "mainpll2", 1, 5),
107
+
FACTOR(CLK_TOP2_MAINPLL2_D5_D2, "mainpll2_d5_d2", "mainpll2", 1, 10),
108
+
FACTOR(CLK_TOP2_MAINPLL2_D6, "mainpll2_d6", "mainpll2", 1, 6),
109
+
FACTOR(CLK_TOP2_MAINPLL2_D6_D2, "mainpll2_d6_d2", "mainpll2", 1, 12),
110
+
FACTOR(CLK_TOP2_MAINPLL2_D7, "mainpll2_d7", "mainpll2", 1, 7),
111
+
FACTOR(CLK_TOP2_MAINPLL2_D7_D2, "mainpll2_d7_d2", "mainpll2", 1, 14),
112
+
FACTOR(CLK_TOP2_MAINPLL2_D9, "mainpll2_d9", "mainpll2", 1, 9),
113
+
FACTOR(CLK_TOP2_UNIVPLL2_D3, "univpll2_d3", "univpll2", 1, 3),
114
+
FACTOR(CLK_TOP2_UNIVPLL2_D4, "univpll2_d4", "univpll2", 1, 4),
115
+
FACTOR(CLK_TOP2_UNIVPLL2_D4_D2, "univpll2_d4_d2", "univpll2", 1, 8),
116
+
FACTOR(CLK_TOP2_UNIVPLL2_D5, "univpll2_d5", "univpll2", 1, 5),
117
+
FACTOR(CLK_TOP2_UNIVPLL2_D5_D2, "univpll2_d5_d2", "univpll2", 1, 10),
118
+
FACTOR(CLK_TOP2_UNIVPLL2_D6, "univpll2_d6", "univpll2", 1, 6),
119
+
FACTOR(CLK_TOP2_UNIVPLL2_D6_D2, "univpll2_d6_d2", "univpll2", 1, 12),
120
+
FACTOR(CLK_TOP2_UNIVPLL2_D6_D4, "univpll2_d6_d4", "univpll2", 1, 24),
121
+
FACTOR(CLK_TOP2_UNIVPLL2_D7, "univpll2_d7", "univpll2", 1, 7),
122
+
FACTOR(CLK_TOP2_IMGPLL_D2, "imgpll_d2", "imgpll", 1, 2),
123
+
FACTOR(CLK_TOP2_IMGPLL_D4, "imgpll_d4", "imgpll", 1, 4),
124
+
FACTOR(CLK_TOP2_IMGPLL_D5, "imgpll_d5", "imgpll", 1, 5),
125
+
FACTOR(CLK_TOP2_IMGPLL_D5_D2, "imgpll_d5_d2", "imgpll", 1, 10),
126
+
FACTOR(CLK_TOP2_MMPLL2_D3, "mmpll2_d3", "mmpll2", 1, 3),
127
+
FACTOR(CLK_TOP2_MMPLL2_D4, "mmpll2_d4", "mmpll2", 1, 4),
128
+
FACTOR(CLK_TOP2_MMPLL2_D4_D2, "mmpll2_d4_d2", "mmpll2", 1, 8),
129
+
FACTOR(CLK_TOP2_MMPLL2_D5, "mmpll2_d5", "mmpll2", 1, 5),
130
+
FACTOR(CLK_TOP2_MMPLL2_D5_D2, "mmpll2_d5_d2", "mmpll2", 1, 10),
131
+
FACTOR(CLK_TOP2_MMPLL2_D6, "mmpll2_d6", "mmpll2", 1, 6),
132
+
FACTOR(CLK_TOP2_MMPLL2_D6_D2, "mmpll2_d6_d2", "mmpll2", 1, 12),
133
+
FACTOR(CLK_TOP2_MMPLL2_D7, "mmpll2_d7", "mmpll2", 1, 7),
134
+
FACTOR(CLK_TOP2_MMPLL2_D9, "mmpll2_d9", "mmpll2", 1, 9),
135
+
FACTOR(CLK_TOP2_TVDPLL1_D4, "tvdpll1_d4", "tvdpll1", 1, 4),
136
+
FACTOR(CLK_TOP2_TVDPLL1_D8, "tvdpll1_d8", "tvdpll1", 1, 8),
137
+
FACTOR(CLK_TOP2_TVDPLL1_D16, "tvdpll1_d16", "tvdpll1", 1, 16),
138
+
FACTOR(CLK_TOP2_TVDPLL2_D2, "tvdpll2_d2", "tvdpll2", 1, 2),
139
+
FACTOR(CLK_TOP2_TVDPLL2_D4, "tvdpll2_d4", "tvdpll2", 1, 4),
140
+
FACTOR(CLK_TOP2_TVDPLL2_D8, "tvdpll2_d8", "tvdpll2", 1, 8),
141
+
FACTOR(CLK_TOP2_TVDPLL2_D16, "tvdpll2_d16", "tvdpll2", 92, 1473),
142
+
FACTOR(CLK_TOP2_TVDPLL3_D2, "tvdpll3_d2", "tvdpll3", 1, 2),
143
+
FACTOR(CLK_TOP2_TVDPLL3_D4, "tvdpll3_d4", "tvdpll3", 1, 4),
144
+
FACTOR(CLK_TOP2_TVDPLL3_D8, "tvdpll3_d8", "tvdpll3", 1, 8),
145
+
FACTOR(CLK_TOP2_TVDPLL3_D16, "tvdpll3_d16", "tvdpll3", 92, 1473),
146
+
};
147
+
148
+
static const char * const seninf_parents[] = {
149
+
"clk26m",
150
+
"ck_osc_d10",
151
+
"ck_osc_d8",
152
+
"ck_osc_d5",
153
+
"ck_osc_d4",
154
+
"univpll2_d6_d2",
155
+
"mainpll2_d9",
156
+
"ck_osc_d2",
157
+
"mainpll2_d4_d2",
158
+
"univpll2_d4_d2",
159
+
"mmpll2_d4_d2",
160
+
"univpll2_d7",
161
+
"mainpll2_d6",
162
+
"mmpll2_d7",
163
+
"univpll2_d6",
164
+
"univpll2_d5"
165
+
};
166
+
167
+
static const char * const img1_parents[] = {
168
+
"clk26m",
169
+
"ck_osc_d4",
170
+
"ck_osc_d3",
171
+
"mmpll2_d6_d2",
172
+
"ck_osc_d2",
173
+
"imgpll_d5_d2",
174
+
"mmpll2_d5_d2",
175
+
"univpll2_d4_d2",
176
+
"mmpll2_d4_d2",
177
+
"mmpll2_d7",
178
+
"univpll2_d6",
179
+
"mmpll2_d6",
180
+
"univpll2_d5",
181
+
"mmpll2_d5",
182
+
"univpll2_d4",
183
+
"imgpll_d4"
184
+
};
185
+
186
+
static const char * const ipe_parents[] = {
187
+
"clk26m",
188
+
"ck_osc_d4",
189
+
"ck_osc_d3",
190
+
"ck_osc_d2",
191
+
"univpll2_d6",
192
+
"mmpll2_d6",
193
+
"univpll2_d5",
194
+
"imgpll_d5",
195
+
"ck_mainpll_d4",
196
+
"mmpll2_d5",
197
+
"imgpll_d4"
198
+
};
199
+
200
+
static const char * const cam_parents[] = {
201
+
"clk26m",
202
+
"ck_osc_d10",
203
+
"ck_osc_d4",
204
+
"ck_osc_d3",
205
+
"ck_osc_d2",
206
+
"mmpll2_d5_d2",
207
+
"univpll2_d4_d2",
208
+
"univpll2_d7",
209
+
"mmpll2_d7",
210
+
"univpll2_d6",
211
+
"mmpll2_d6",
212
+
"univpll2_d5",
213
+
"mmpll2_d5",
214
+
"univpll2_d4",
215
+
"imgpll_d4",
216
+
"mmpll2_d4"
217
+
};
218
+
219
+
static const char * const camtm_parents[] = {
220
+
"clk26m",
221
+
"univpll2_d6_d4",
222
+
"ck_osc_d4",
223
+
"ck_osc_d3",
224
+
"univpll2_d6_d2"
225
+
};
226
+
227
+
static const char * const dpe_parents[] = {
228
+
"clk26m",
229
+
"mmpll2_d5_d2",
230
+
"univpll2_d4_d2",
231
+
"mmpll2_d7",
232
+
"univpll2_d6",
233
+
"mmpll2_d6",
234
+
"univpll2_d5",
235
+
"mmpll2_d5",
236
+
"imgpll_d4",
237
+
"mmpll2_d4"
238
+
};
239
+
240
+
static const char * const vdec_parents[] = {
241
+
"clk26m",
242
+
"ck_mainpll_d5_d2",
243
+
"mainpll2_d4_d4",
244
+
"mainpll2_d7_d2",
245
+
"mainpll2_d6_d2",
246
+
"mainpll2_d5_d2",
247
+
"mainpll2_d9",
248
+
"mainpll2_d4_d2",
249
+
"mainpll2_d7",
250
+
"mainpll2_d6",
251
+
"univpll2_d6",
252
+
"mainpll2_d5",
253
+
"mainpll2_d4",
254
+
"imgpll_d2"
255
+
};
256
+
257
+
static const char * const ccusys_parents[] = {
258
+
"clk26m",
259
+
"ck_osc_d4",
260
+
"ck_osc_d3",
261
+
"ck_osc_d2",
262
+
"mmpll2_d5_d2",
263
+
"univpll2_d4_d2",
264
+
"mmpll2_d7",
265
+
"univpll2_d6",
266
+
"mmpll2_d6",
267
+
"univpll2_d5",
268
+
"mainpll2_d4",
269
+
"mainpll2_d3",
270
+
"univpll2_d3"
271
+
};
272
+
273
+
static const char * const ccutm_parents[] = {
274
+
"clk26m",
275
+
"univpll2_d6_d4",
276
+
"ck_osc_d4",
277
+
"ck_osc_d3",
278
+
"univpll2_d6_d2"
279
+
};
280
+
281
+
static const char * const venc_parents[] = {
282
+
"clk26m",
283
+
"mainpll2_d5_d2",
284
+
"univpll2_d5_d2",
285
+
"mainpll2_d4_d2",
286
+
"mmpll2_d9",
287
+
"univpll2_d4_d2",
288
+
"mmpll2_d4_d2",
289
+
"mainpll2_d6",
290
+
"univpll2_d6",
291
+
"mainpll2_d5",
292
+
"mmpll2_d6",
293
+
"univpll2_d5",
294
+
"mainpll2_d4",
295
+
"univpll2_d4",
296
+
"univpll2_d3"
297
+
};
298
+
299
+
static const char * const dp1_parents[] = {
300
+
"clk26m",
301
+
"tvdpll2_d16",
302
+
"tvdpll2_d8",
303
+
"tvdpll2_d4",
304
+
"tvdpll2_d2"
305
+
};
306
+
307
+
static const char * const dp0_parents[] = {
308
+
"clk26m",
309
+
"tvdpll1_d16",
310
+
"tvdpll1_d8",
311
+
"tvdpll1_d4",
312
+
"ck_tvdpll1_d2"
313
+
};
314
+
315
+
static const char * const disp_parents[] = {
316
+
"clk26m",
317
+
"ck_mainpll_d5_d2",
318
+
"ck_mainpll_d4_d2",
319
+
"ck_mainpll_d6",
320
+
"mainpll2_d5",
321
+
"mmpll2_d6",
322
+
"mainpll2_d4",
323
+
"univpll2_d4",
324
+
"mainpll2_d3"
325
+
};
326
+
327
+
static const char * const mdp_parents[] = {
328
+
"clk26m",
329
+
"ck_mainpll_d5_d2",
330
+
"mainpll2_d5_d2",
331
+
"mmpll2_d6_d2",
332
+
"mainpll2_d9",
333
+
"mainpll2_d4_d2",
334
+
"mainpll2_d7",
335
+
"mainpll2_d6",
336
+
"mainpll2_d5",
337
+
"mmpll2_d6",
338
+
"mainpll2_d4",
339
+
"univpll2_d4",
340
+
"mainpll2_d3"
341
+
};
342
+
343
+
static const char * const mminfra_parents[] = {
344
+
"clk26m",
345
+
"ck_osc_d4",
346
+
"ck_mainpll_d7_d2",
347
+
"ck_mainpll_d5_d2",
348
+
"ck_mainpll_d9",
349
+
"mmpll2_d6_d2",
350
+
"mainpll2_d4_d2",
351
+
"ck_mainpll_d6",
352
+
"univpll2_d6",
353
+
"mainpll2_d5",
354
+
"mmpll2_d6",
355
+
"univpll2_d5",
356
+
"mainpll2_d4",
357
+
"univpll2_d4",
358
+
"mainpll2_d3",
359
+
"univpll2_d3"
360
+
};
361
+
362
+
static const char * const mminfra_snoc_parents[] = {
363
+
"clk26m",
364
+
"ck_osc_d4",
365
+
"ck_mainpll_d7_d2",
366
+
"ck_mainpll_d9",
367
+
"ck_mainpll_d7",
368
+
"ck_mainpll_d6",
369
+
"mmpll2_d4_d2",
370
+
"ck_mainpll_d5",
371
+
"ck_mainpll_d4",
372
+
"univpll2_d4",
373
+
"mmpll2_d4",
374
+
"mainpll2_d3",
375
+
"univpll2_d3",
376
+
"mmpll2_d3",
377
+
"mainpll2_d2"
378
+
};
379
+
380
+
static const char * const mmup_parents[] = {
381
+
"clk26m",
382
+
"mainpll2_d6",
383
+
"mainpll2_d5",
384
+
"ck_osc_d2",
385
+
"ck_osc",
386
+
"ck_mainpll_d4",
387
+
"univpll2_d4",
388
+
"mainpll2_d3"
389
+
};
390
+
391
+
static const char * const mminfra_ao_parents[] = {
392
+
"clk26m",
393
+
"ck_osc_d4",
394
+
"ck_mainpll_d3"
395
+
};
396
+
397
+
static const char * const dvo_parents[] = {
398
+
"clk26m",
399
+
"tvdpll3_d16",
400
+
"tvdpll3_d8",
401
+
"tvdpll3_d4",
402
+
"tvdpll3_d2"
403
+
};
404
+
405
+
static const char * const dvo_favt_parents[] = {
406
+
"clk26m",
407
+
"tvdpll3_d16",
408
+
"tvdpll3_d8",
409
+
"tvdpll3_d4",
410
+
"vlp_apll1",
411
+
"vlp_apll2",
412
+
"tvdpll3_d2"
413
+
};
414
+
415
+
static const struct mtk_mux top_muxes[] = {
416
+
/* CKSYS2_CLK_CFG_0 */
417
+
MUX_GATE_HWV_FENC_CLR_SET_UPD(CLK_TOP2_SENINF0, "seninf0", seninf_parents,
418
+
CKSYS2_CLK_CFG_0, CKSYS2_CLK_CFG_0_SET, CKSYS2_CLK_CFG_0_CLR,
419
+
MM_HWV_CG_30_DONE, MM_HWV_CG_30_SET, MM_HWV_CG_30_CLR,
420
+
0, 4, 7, CKSYS2_CLK_CFG_UPDATE, TOP_MUX_SENINF0_SHIFT,
421
+
CKSYS2_CLK_FENC_STATUS_MON_0, 31),
422
+
MUX_GATE_HWV_FENC_CLR_SET_UPD(CLK_TOP2_SENINF1, "seninf1", seninf_parents,
423
+
CKSYS2_CLK_CFG_0, CKSYS2_CLK_CFG_0_SET, CKSYS2_CLK_CFG_0_CLR,
424
+
MM_HWV_CG_30_DONE, MM_HWV_CG_30_SET, MM_HWV_CG_30_CLR,
425
+
8, 4, 15, CKSYS2_CLK_CFG_UPDATE, TOP_MUX_SENINF1_SHIFT,
426
+
CKSYS2_CLK_FENC_STATUS_MON_0, 30),
427
+
MUX_GATE_HWV_FENC_CLR_SET_UPD(CLK_TOP2_SENINF2, "seninf2", seninf_parents,
428
+
CKSYS2_CLK_CFG_0, CKSYS2_CLK_CFG_0_SET, CKSYS2_CLK_CFG_0_CLR,
429
+
MM_HWV_CG_30_DONE, MM_HWV_CG_30_SET, MM_HWV_CG_30_CLR,
430
+
16, 4, 23, CKSYS2_CLK_CFG_UPDATE, TOP_MUX_SENINF2_SHIFT,
431
+
CKSYS2_CLK_FENC_STATUS_MON_0, 29),
432
+
MUX_GATE_HWV_FENC_CLR_SET_UPD(CLK_TOP2_SENINF3, "seninf3", seninf_parents,
433
+
CKSYS2_CLK_CFG_0, CKSYS2_CLK_CFG_0_SET, CKSYS2_CLK_CFG_0_CLR,
434
+
MM_HWV_CG_30_DONE, MM_HWV_CG_30_SET, MM_HWV_CG_30_CLR,
435
+
24, 4, 31, CKSYS2_CLK_CFG_UPDATE, TOP_MUX_SENINF3_SHIFT,
436
+
CKSYS2_CLK_FENC_STATUS_MON_0, 28),
437
+
/* CKSYS2_CLK_CFG_1 */
438
+
MUX_GATE_HWV_FENC_CLR_SET_UPD(CLK_TOP2_SENINF4, "seninf4", seninf_parents,
439
+
CKSYS2_CLK_CFG_1, CKSYS2_CLK_CFG_1_SET, CKSYS2_CLK_CFG_1_CLR,
440
+
MM_HWV_CG_31_DONE, MM_HWV_CG_31_SET, MM_HWV_CG_31_CLR,
441
+
0, 4, 7, CKSYS2_CLK_CFG_UPDATE, TOP_MUX_SENINF4_SHIFT,
442
+
CKSYS2_CLK_FENC_STATUS_MON_0, 27),
443
+
MUX_GATE_HWV_FENC_CLR_SET_UPD(CLK_TOP2_SENINF5, "seninf5", seninf_parents,
444
+
CKSYS2_CLK_CFG_1, CKSYS2_CLK_CFG_1_SET, CKSYS2_CLK_CFG_1_CLR,
445
+
MM_HWV_CG_31_DONE, MM_HWV_CG_31_SET, MM_HWV_CG_31_CLR,
446
+
8, 4, 15, CKSYS2_CLK_CFG_UPDATE, TOP_MUX_SENINF5_SHIFT,
447
+
CKSYS2_CLK_FENC_STATUS_MON_0, 26),
448
+
MUX_GATE_HWV_FENC_CLR_SET_UPD(CLK_TOP2_IMG1, "img1", img1_parents,
449
+
CKSYS2_CLK_CFG_1, CKSYS2_CLK_CFG_1_SET, CKSYS2_CLK_CFG_1_CLR,
450
+
MM_HWV_CG_31_DONE, MM_HWV_CG_31_SET, MM_HWV_CG_31_CLR,
451
+
16, 4, 23, CKSYS2_CLK_CFG_UPDATE, TOP_MUX_IMG1_SHIFT,
452
+
CKSYS2_CLK_FENC_STATUS_MON_0, 25),
453
+
MUX_GATE_HWV_FENC_CLR_SET_UPD(CLK_TOP2_IPE, "ipe", ipe_parents,
454
+
CKSYS2_CLK_CFG_1, CKSYS2_CLK_CFG_1_SET, CKSYS2_CLK_CFG_1_CLR,
455
+
MM_HWV_CG_31_DONE, MM_HWV_CG_31_SET, MM_HWV_CG_31_CLR,
456
+
24, 4, 31, CKSYS2_CLK_CFG_UPDATE, TOP_MUX_IPE_SHIFT,
457
+
CKSYS2_CLK_FENC_STATUS_MON_0, 24),
458
+
/* CKSYS2_CLK_CFG_2 */
459
+
MUX_GATE_HWV_FENC_CLR_SET_UPD(CLK_TOP2_CAM, "cam", cam_parents,
460
+
CKSYS2_CLK_CFG_2, CKSYS2_CLK_CFG_2_SET, CKSYS2_CLK_CFG_2_CLR,
461
+
MM_HWV_CG_32_DONE, MM_HWV_CG_32_SET, MM_HWV_CG_32_CLR,
462
+
0, 4, 7, CKSYS2_CLK_CFG_UPDATE, TOP_MUX_CAM_SHIFT,
463
+
CKSYS2_CLK_FENC_STATUS_MON_0, 23),
464
+
MUX_GATE_HWV_FENC_CLR_SET_UPD(CLK_TOP2_CAMTM, "camtm", camtm_parents,
465
+
CKSYS2_CLK_CFG_2, CKSYS2_CLK_CFG_2_SET, CKSYS2_CLK_CFG_2_CLR,
466
+
MM_HWV_CG_32_DONE, MM_HWV_CG_32_SET, MM_HWV_CG_32_CLR,
467
+
8, 3, 15, CKSYS2_CLK_CFG_UPDATE, TOP_MUX_CAMTM_SHIFT,
468
+
CKSYS2_CLK_FENC_STATUS_MON_0, 22),
469
+
MUX_GATE_HWV_FENC_CLR_SET_UPD(CLK_TOP2_DPE, "dpe", dpe_parents,
470
+
CKSYS2_CLK_CFG_2, CKSYS2_CLK_CFG_2_SET, CKSYS2_CLK_CFG_2_CLR,
471
+
MM_HWV_CG_32_DONE, MM_HWV_CG_32_SET, MM_HWV_CG_32_CLR,
472
+
16, 4, 23, CKSYS2_CLK_CFG_UPDATE, TOP_MUX_DPE_SHIFT,
473
+
CKSYS2_CLK_FENC_STATUS_MON_0, 21),
474
+
MUX_GATE_HWV_FENC_CLR_SET_UPD(CLK_TOP2_VDEC, "vdec", vdec_parents,
475
+
CKSYS2_CLK_CFG_2, CKSYS2_CLK_CFG_2_SET, CKSYS2_CLK_CFG_2_CLR,
476
+
MM_HWV_CG_32_DONE, MM_HWV_CG_32_SET, MM_HWV_CG_32_CLR,
477
+
24, 4, 31, CKSYS2_CLK_CFG_UPDATE, TOP_MUX_VDEC_SHIFT,
478
+
CKSYS2_CLK_FENC_STATUS_MON_0, 20),
479
+
/* CKSYS2_CLK_CFG_3 */
480
+
MUX_GATE_HWV_FENC_CLR_SET_UPD(CLK_TOP2_CCUSYS, "ccusys", ccusys_parents,
481
+
CKSYS2_CLK_CFG_3, CKSYS2_CLK_CFG_3_SET, CKSYS2_CLK_CFG_3_CLR,
482
+
MM_HWV_CG_33_DONE, MM_HWV_CG_33_SET, MM_HWV_CG_33_CLR,
483
+
0, 4, 7, CKSYS2_CLK_CFG_UPDATE, TOP_MUX_CCUSYS_SHIFT,
484
+
CKSYS2_CLK_FENC_STATUS_MON_0, 19),
485
+
MUX_GATE_HWV_FENC_CLR_SET_UPD(CLK_TOP2_CCUTM, "ccutm", ccutm_parents,
486
+
CKSYS2_CLK_CFG_3, CKSYS2_CLK_CFG_3_SET, CKSYS2_CLK_CFG_3_CLR,
487
+
MM_HWV_CG_33_DONE, MM_HWV_CG_33_SET, MM_HWV_CG_33_CLR,
488
+
8, 3, 15, CKSYS2_CLK_CFG_UPDATE, TOP_MUX_CCUTM_SHIFT,
489
+
CKSYS2_CLK_FENC_STATUS_MON_0, 18),
490
+
MUX_GATE_HWV_FENC_CLR_SET_UPD(CLK_TOP2_VENC, "venc", venc_parents,
491
+
CKSYS2_CLK_CFG_3, CKSYS2_CLK_CFG_3_SET, CKSYS2_CLK_CFG_3_CLR,
492
+
MM_HWV_CG_33_DONE, MM_HWV_CG_33_SET, MM_HWV_CG_33_CLR,
493
+
16, 4, 23, CKSYS2_CLK_CFG_UPDATE, TOP_MUX_VENC_SHIFT,
494
+
CKSYS2_CLK_FENC_STATUS_MON_0, 17),
495
+
MUX_GATE_FENC_CLR_SET_UPD(CLK_TOP2_DVO, "dvo", dvo_parents,
496
+
CKSYS2_CLK_CFG_3, CKSYS2_CLK_CFG_3_SET, CKSYS2_CLK_CFG_3_CLR,
497
+
24, 3, 31, CKSYS2_CLK_CFG_UPDATE, TOP_MUX_DVO_SHIFT,
498
+
CKSYS2_CLK_FENC_STATUS_MON_0, 16),
499
+
MUX_GATE_FENC_CLR_SET_UPD(CLK_TOP2_DVO_FAVT, "dvo_favt", dvo_favt_parents,
500
+
CKSYS2_CLK_CFG_4, CKSYS2_CLK_CFG_4_SET, CKSYS2_CLK_CFG_4_CLR,
501
+
0, 3, 7, CKSYS2_CLK_CFG_UPDATE, TOP_MUX_DVO_FAVT_SHIFT,
502
+
CKSYS2_CLK_FENC_STATUS_MON_0, 15),
503
+
MUX_GATE_FENC_CLR_SET_UPD(CLK_TOP2_DP1, "dp1", dp1_parents,
504
+
CKSYS2_CLK_CFG_4, CKSYS2_CLK_CFG_4_SET, CKSYS2_CLK_CFG_4_CLR,
505
+
8, 3, 15, CKSYS2_CLK_CFG_UPDATE, TOP_MUX_DP1_SHIFT,
506
+
CKSYS2_CLK_FENC_STATUS_MON_0, 14),
507
+
MUX_GATE_FENC_CLR_SET_UPD(CLK_TOP2_DP0, "dp0", dp0_parents,
508
+
CKSYS2_CLK_CFG_4, CKSYS2_CLK_CFG_4_SET, CKSYS2_CLK_CFG_4_CLR,
509
+
16, 3, 23, CKSYS2_CLK_CFG_UPDATE, TOP_MUX_DP0_SHIFT,
510
+
CKSYS2_CLK_FENC_STATUS_MON_0, 13),
511
+
MUX_GATE_HWV_FENC_CLR_SET_UPD(CLK_TOP2_DISP, "disp", disp_parents,
512
+
CKSYS2_CLK_CFG_4, CKSYS2_CLK_CFG_4_SET, CKSYS2_CLK_CFG_4_CLR,
513
+
MM_HWV_CG_34_DONE, MM_HWV_CG_34_SET, MM_HWV_CG_34_CLR,
514
+
24, 4, 31, CKSYS2_CLK_CFG_UPDATE, TOP_MUX_DISP_SHIFT,
515
+
CKSYS2_CLK_FENC_STATUS_MON_0, 12),
516
+
/* CKSYS2_CLK_CFG_5 */
517
+
MUX_GATE_HWV_FENC_CLR_SET_UPD(CLK_TOP2_MDP, "mdp", mdp_parents,
518
+
CKSYS2_CLK_CFG_5, CKSYS2_CLK_CFG_5_SET, CKSYS2_CLK_CFG_5_CLR,
519
+
MM_HWV_CG_35_DONE, MM_HWV_CG_35_SET, MM_HWV_CG_35_CLR,
520
+
0, 4, 7, CKSYS2_CLK_CFG_UPDATE, TOP_MUX_MDP_SHIFT,
521
+
CKSYS2_CLK_FENC_STATUS_MON_0, 11),
522
+
MUX_GATE_HWV_FENC_CLR_SET_UPD(CLK_TOP2_MMINFRA, "mminfra", mminfra_parents,
523
+
CKSYS2_CLK_CFG_5, CKSYS2_CLK_CFG_5_SET, CKSYS2_CLK_CFG_5_CLR,
524
+
MM_HWV_CG_35_DONE, MM_HWV_CG_35_SET, MM_HWV_CG_35_CLR,
525
+
8, 4, 15, CKSYS2_CLK_CFG_UPDATE, TOP_MUX_MMINFRA_SHIFT,
526
+
CKSYS2_CLK_FENC_STATUS_MON_0, 10),
527
+
MUX_GATE_HWV_FENC_CLR_SET_UPD(CLK_TOP2_MMINFRA_SNOC, "mminfra_snoc", mminfra_snoc_parents,
528
+
CKSYS2_CLK_CFG_5, CKSYS2_CLK_CFG_5_SET, CKSYS2_CLK_CFG_5_CLR,
529
+
MM_HWV_CG_35_DONE, MM_HWV_CG_35_SET, MM_HWV_CG_35_CLR,
530
+
16, 4, 23, CKSYS2_CLK_CFG_UPDATE, TOP_MUX_MMINFRA_SNOC_SHIFT,
531
+
CKSYS2_CLK_FENC_STATUS_MON_0, 9),
532
+
MUX_GATE_FENC_CLR_SET_UPD(CLK_TOP2_MMUP, "mmup", mmup_parents,
533
+
CKSYS2_CLK_CFG_5, CKSYS2_CLK_CFG_5_SET, CKSYS2_CLK_CFG_5_CLR,
534
+
24, 3, 31, CKSYS2_CLK_CFG_UPDATE, TOP_MUX_MMUP_SHIFT,
535
+
CKSYS2_CLK_FENC_STATUS_MON_0, 8),
536
+
/* CKSYS2_CLK_CFG_6 */
537
+
MUX_GATE_HWV_FENC_CLR_SET_UPD(CLK_TOP2_MMINFRA_AO, "mminfra_ao", mminfra_ao_parents,
538
+
CKSYS2_CLK_CFG_6, CKSYS2_CLK_CFG_6_SET, CKSYS2_CLK_CFG_6_CLR,
539
+
MM_HWV_CG_36_DONE, MM_HWV_CG_36_SET, MM_HWV_CG_36_CLR,
540
+
16, 2, 7, CKSYS2_CLK_CFG_UPDATE, TOP_MUX_MMINFRA_AO_SHIFT,
541
+
CKSYS2_CLK_FENC_STATUS_MON_0, 5),
542
+
};
543
+
544
+
static const struct mtk_clk_desc topck_desc = {
545
+
.factor_clks = top_divs,
546
+
.num_factor_clks = ARRAY_SIZE(top_divs),
547
+
.mux_clks = top_muxes,
548
+
.num_mux_clks = ARRAY_SIZE(top_muxes),
549
+
};
550
+
551
+
static const struct of_device_id of_match_clk_mt8196_ck[] = {
552
+
{ .compatible = "mediatek,mt8196-topckgen-gp2", .data = &topck_desc },
553
+
{ /* sentinel */ }
554
+
};
555
+
MODULE_DEVICE_TABLE(of, of_match_clk_mt8196_ck);
556
+
557
+
static struct platform_driver clk_mt8196_topck_drv = {
558
+
.probe = mtk_clk_simple_probe,
559
+
.remove = mtk_clk_simple_remove,
560
+
.driver = {
561
+
.name = "clk-mt8196-topck2",
562
+
.of_match_table = of_match_clk_mt8196_ck,
563
+
},
564
+
};
565
+
566
+
MODULE_DESCRIPTION("MediaTek MT8196 GP2 top clock generators driver");
567
+
module_platform_driver(clk_mt8196_topck_drv);
568
+
MODULE_LICENSE("GPL");
+108
drivers/clk/mediatek/clk-mt8196-ufs_ao.c
+108
drivers/clk/mediatek/clk-mt8196-ufs_ao.c
···
1
+
// SPDX-License-Identifier: GPL-2.0-only
2
+
/*
3
+
* Copyright (c) 2025 MediaTek Inc.
4
+
* Guangjie Song <guangjie.song@mediatek.com>
5
+
* Copyright (c) 2025 Collabora Ltd.
6
+
* Laura Nao <laura.nao@collabora.com>
7
+
*/
8
+
#include <dt-bindings/clock/mediatek,mt8196-clock.h>
9
+
#include <dt-bindings/reset/mediatek,mt8196-resets.h>
10
+
11
+
#include <linux/clk-provider.h>
12
+
#include <linux/module.h>
13
+
#include <linux/of_device.h>
14
+
#include <linux/platform_device.h>
15
+
16
+
#include "clk-gate.h"
17
+
#include "clk-mtk.h"
18
+
19
+
#define MT8196_UFSAO_RST0_SET_OFFSET 0x48
20
+
#define MT8196_UFSAO_RST1_SET_OFFSET 0x148
21
+
22
+
static const struct mtk_gate_regs ufsao0_cg_regs = {
23
+
.set_ofs = 0x108,
24
+
.clr_ofs = 0x10c,
25
+
.sta_ofs = 0x104,
26
+
};
27
+
28
+
static const struct mtk_gate_regs ufsao1_cg_regs = {
29
+
.set_ofs = 0x8,
30
+
.clr_ofs = 0xc,
31
+
.sta_ofs = 0x4,
32
+
};
33
+
34
+
#define GATE_UFSAO0(_id, _name, _parent, _shift) { \
35
+
.id = _id, \
36
+
.name = _name, \
37
+
.parent_name = _parent, \
38
+
.regs = &ufsao0_cg_regs, \
39
+
.shift = _shift, \
40
+
.ops = &mtk_clk_gate_ops_setclr, \
41
+
}
42
+
43
+
#define GATE_UFSAO1(_id, _name, _parent, _shift) { \
44
+
.id = _id, \
45
+
.name = _name, \
46
+
.parent_name = _parent, \
47
+
.regs = &ufsao1_cg_regs, \
48
+
.shift = _shift, \
49
+
.ops = &mtk_clk_gate_ops_setclr, \
50
+
}
51
+
52
+
static const struct mtk_gate ufsao_clks[] = {
53
+
/* UFSAO0 */
54
+
GATE_UFSAO0(CLK_UFSAO_UFSHCI_UFS, "ufsao_ufshci_ufs", "ufs", 0),
55
+
GATE_UFSAO0(CLK_UFSAO_UFSHCI_AES, "ufsao_ufshci_aes", "aes_ufsfde", 1),
56
+
/* UFSAO1 */
57
+
GATE_UFSAO1(CLK_UFSAO_UNIPRO_TX_SYM, "ufsao_unipro_tx_sym", "clk26m", 0),
58
+
GATE_UFSAO1(CLK_UFSAO_UNIPRO_RX_SYM0, "ufsao_unipro_rx_sym0", "clk26m", 1),
59
+
GATE_UFSAO1(CLK_UFSAO_UNIPRO_RX_SYM1, "ufsao_unipro_rx_sym1", "clk26m", 2),
60
+
GATE_UFSAO1(CLK_UFSAO_UNIPRO_SYS, "ufsao_unipro_sys", "ufs", 3),
61
+
GATE_UFSAO1(CLK_UFSAO_UNIPRO_SAP, "ufsao_unipro_sap", "clk26m", 4),
62
+
GATE_UFSAO1(CLK_UFSAO_PHY_SAP, "ufsao_phy_sap", "clk26m", 8),
63
+
};
64
+
65
+
static u16 ufsao_rst_ofs[] = {
66
+
MT8196_UFSAO_RST0_SET_OFFSET,
67
+
MT8196_UFSAO_RST1_SET_OFFSET
68
+
};
69
+
70
+
static u16 ufsao_rst_idx_map[] = {
71
+
[MT8196_UFSAO_RST0_UFS_MPHY] = 8,
72
+
[MT8196_UFSAO_RST1_UFS_UNIPRO] = 1 * RST_NR_PER_BANK + 0,
73
+
[MT8196_UFSAO_RST1_UFS_CRYPTO] = 1 * RST_NR_PER_BANK + 1,
74
+
[MT8196_UFSAO_RST1_UFSHCI] = 1 * RST_NR_PER_BANK + 2,
75
+
};
76
+
77
+
static const struct mtk_clk_rst_desc ufsao_rst_desc = {
78
+
.version = MTK_RST_SET_CLR,
79
+
.rst_bank_ofs = ufsao_rst_ofs,
80
+
.rst_bank_nr = ARRAY_SIZE(ufsao_rst_ofs),
81
+
.rst_idx_map = ufsao_rst_idx_map,
82
+
.rst_idx_map_nr = ARRAY_SIZE(ufsao_rst_idx_map),
83
+
};
84
+
85
+
static const struct mtk_clk_desc ufsao_mcd = {
86
+
.clks = ufsao_clks,
87
+
.num_clks = ARRAY_SIZE(ufsao_clks),
88
+
.rst_desc = &ufsao_rst_desc,
89
+
};
90
+
91
+
static const struct of_device_id of_match_clk_mt8196_ufs_ao[] = {
92
+
{ .compatible = "mediatek,mt8196-ufscfg-ao", .data = &ufsao_mcd },
93
+
{ /* sentinel */ }
94
+
};
95
+
MODULE_DEVICE_TABLE(of, of_match_clk_mt8196_ufs_ao);
96
+
97
+
static struct platform_driver clk_mt8196_ufs_ao_drv = {
98
+
.probe = mtk_clk_simple_probe,
99
+
.remove = mtk_clk_simple_remove,
100
+
.driver = {
101
+
.name = "clk-mt8196-ufs-ao",
102
+
.of_match_table = of_match_clk_mt8196_ufs_ao,
103
+
},
104
+
};
105
+
106
+
module_platform_driver(clk_mt8196_ufs_ao_drv);
107
+
MODULE_DESCRIPTION("MediaTek MT8196 ufs_ao clocks driver");
108
+
MODULE_LICENSE("GPL");
+253
drivers/clk/mediatek/clk-mt8196-vdec.c
+253
drivers/clk/mediatek/clk-mt8196-vdec.c
···
1
+
// SPDX-License-Identifier: GPL-2.0-only
2
+
/*
3
+
* Copyright (c) 2025 MediaTek Inc.
4
+
* Guangjie Song <guangjie.song@mediatek.com>
5
+
* Copyright (c) 2025 Collabora Ltd.
6
+
* Laura Nao <laura.nao@collabora.com>
7
+
*/
8
+
#include <dt-bindings/clock/mediatek,mt8196-clock.h>
9
+
10
+
#include <linux/clk-provider.h>
11
+
#include <linux/module.h>
12
+
#include <linux/of_device.h>
13
+
#include <linux/platform_device.h>
14
+
15
+
#include "clk-gate.h"
16
+
#include "clk-mtk.h"
17
+
18
+
static const struct mtk_gate_regs vde20_cg_regs = {
19
+
.set_ofs = 0x0,
20
+
.clr_ofs = 0x4,
21
+
.sta_ofs = 0x0,
22
+
};
23
+
24
+
static const struct mtk_gate_regs vde20_hwv_regs = {
25
+
.set_ofs = 0x0088,
26
+
.clr_ofs = 0x008c,
27
+
.sta_ofs = 0x2c44,
28
+
};
29
+
30
+
static const struct mtk_gate_regs vde21_cg_regs = {
31
+
.set_ofs = 0x200,
32
+
.clr_ofs = 0x204,
33
+
.sta_ofs = 0x200,
34
+
};
35
+
36
+
static const struct mtk_gate_regs vde21_hwv_regs = {
37
+
.set_ofs = 0x0080,
38
+
.clr_ofs = 0x0084,
39
+
.sta_ofs = 0x2c40,
40
+
};
41
+
42
+
static const struct mtk_gate_regs vde22_cg_regs = {
43
+
.set_ofs = 0x8,
44
+
.clr_ofs = 0xc,
45
+
.sta_ofs = 0x8,
46
+
};
47
+
48
+
static const struct mtk_gate_regs vde22_hwv_regs = {
49
+
.set_ofs = 0x0078,
50
+
.clr_ofs = 0x007c,
51
+
.sta_ofs = 0x2c3c,
52
+
};
53
+
54
+
#define GATE_HWV_VDE20(_id, _name, _parent, _shift) { \
55
+
.id = _id, \
56
+
.name = _name, \
57
+
.parent_name = _parent, \
58
+
.regs = &vde20_cg_regs, \
59
+
.hwv_regs = &vde20_hwv_regs, \
60
+
.shift = _shift, \
61
+
.ops = &mtk_clk_gate_hwv_ops_setclr_inv,\
62
+
.flags = CLK_OPS_PARENT_ENABLE, \
63
+
}
64
+
65
+
#define GATE_HWV_VDE21(_id, _name, _parent, _shift) { \
66
+
.id = _id, \
67
+
.name = _name, \
68
+
.parent_name = _parent, \
69
+
.regs = &vde21_cg_regs, \
70
+
.hwv_regs = &vde21_hwv_regs, \
71
+
.shift = _shift, \
72
+
.ops = &mtk_clk_gate_hwv_ops_setclr_inv,\
73
+
.flags = CLK_OPS_PARENT_ENABLE, \
74
+
}
75
+
76
+
#define GATE_HWV_VDE22(_id, _name, _parent, _shift) { \
77
+
.id = _id, \
78
+
.name = _name, \
79
+
.parent_name = _parent, \
80
+
.regs = &vde22_cg_regs, \
81
+
.hwv_regs = &vde22_hwv_regs, \
82
+
.shift = _shift, \
83
+
.ops = &mtk_clk_gate_hwv_ops_setclr_inv,\
84
+
.flags = CLK_OPS_PARENT_ENABLE | \
85
+
CLK_IGNORE_UNUSED, \
86
+
}
87
+
88
+
static const struct mtk_gate vde2_clks[] = {
89
+
/* VDE20 */
90
+
GATE_HWV_VDE20(CLK_VDE2_VDEC_CKEN, "vde2_vdec_cken", "vdec", 0),
91
+
GATE_HWV_VDE20(CLK_VDE2_VDEC_ACTIVE, "vde2_vdec_active", "vdec", 4),
92
+
GATE_HWV_VDE20(CLK_VDE2_VDEC_CKEN_ENG, "vde2_vdec_cken_eng", "vdec", 8),
93
+
/* VDE21 */
94
+
GATE_HWV_VDE21(CLK_VDE2_LAT_CKEN, "vde2_lat_cken", "vdec", 0),
95
+
GATE_HWV_VDE21(CLK_VDE2_LAT_ACTIVE, "vde2_lat_active", "vdec", 4),
96
+
GATE_HWV_VDE21(CLK_VDE2_LAT_CKEN_ENG, "vde2_lat_cken_eng", "vdec", 8),
97
+
/* VDE22 */
98
+
GATE_HWV_VDE22(CLK_VDE2_LARB1_CKEN, "vde2_larb1_cken", "vdec", 0),
99
+
};
100
+
101
+
static const struct mtk_clk_desc vde2_mcd = {
102
+
.clks = vde2_clks,
103
+
.num_clks = ARRAY_SIZE(vde2_clks),
104
+
.need_runtime_pm = true,
105
+
};
106
+
107
+
static const struct mtk_gate_regs vde10_hwv_regs = {
108
+
.set_ofs = 0x00a0,
109
+
.clr_ofs = 0x00a4,
110
+
.sta_ofs = 0x2c50,
111
+
};
112
+
113
+
static const struct mtk_gate_regs vde11_cg_regs = {
114
+
.set_ofs = 0x1e0,
115
+
.clr_ofs = 0x1e0,
116
+
.sta_ofs = 0x1e0,
117
+
};
118
+
119
+
static const struct mtk_gate_regs vde11_hwv_regs = {
120
+
.set_ofs = 0x00b0,
121
+
.clr_ofs = 0x00b4,
122
+
.sta_ofs = 0x2c58,
123
+
};
124
+
125
+
static const struct mtk_gate_regs vde12_cg_regs = {
126
+
.set_ofs = 0x1ec,
127
+
.clr_ofs = 0x1ec,
128
+
.sta_ofs = 0x1ec,
129
+
};
130
+
131
+
static const struct mtk_gate_regs vde12_hwv_regs = {
132
+
.set_ofs = 0x00a8,
133
+
.clr_ofs = 0x00ac,
134
+
.sta_ofs = 0x2c54,
135
+
};
136
+
137
+
static const struct mtk_gate_regs vde13_cg_regs = {
138
+
.set_ofs = 0x200,
139
+
.clr_ofs = 0x204,
140
+
.sta_ofs = 0x200,
141
+
};
142
+
143
+
static const struct mtk_gate_regs vde13_hwv_regs = {
144
+
.set_ofs = 0x0098,
145
+
.clr_ofs = 0x009c,
146
+
.sta_ofs = 0x2c4c,
147
+
};
148
+
149
+
static const struct mtk_gate_regs vde14_hwv_regs = {
150
+
.set_ofs = 0x0090,
151
+
.clr_ofs = 0x0094,
152
+
.sta_ofs = 0x2c48,
153
+
};
154
+
155
+
#define GATE_HWV_VDE10(_id, _name, _parent, _shift) { \
156
+
.id = _id, \
157
+
.name = _name, \
158
+
.parent_name = _parent, \
159
+
.regs = &vde20_cg_regs, \
160
+
.hwv_regs = &vde10_hwv_regs, \
161
+
.shift = _shift, \
162
+
.ops = &mtk_clk_gate_hwv_ops_setclr_inv,\
163
+
.flags = CLK_OPS_PARENT_ENABLE, \
164
+
}
165
+
166
+
#define GATE_HWV_VDE11(_id, _name, _parent, _shift) { \
167
+
.id = _id, \
168
+
.name = _name, \
169
+
.parent_name = _parent, \
170
+
.regs = &vde11_cg_regs, \
171
+
.hwv_regs = &vde11_hwv_regs, \
172
+
.shift = _shift, \
173
+
.ops = &mtk_clk_gate_hwv_ops_setclr_inv, \
174
+
.flags = CLK_OPS_PARENT_ENABLE, \
175
+
}
176
+
177
+
#define GATE_HWV_VDE12(_id, _name, _parent, _shift) { \
178
+
.id = _id, \
179
+
.name = _name, \
180
+
.parent_name = _parent, \
181
+
.regs = &vde12_cg_regs, \
182
+
.hwv_regs = &vde12_hwv_regs, \
183
+
.shift = _shift, \
184
+
.ops = &mtk_clk_gate_hwv_ops_setclr_inv, \
185
+
.flags = CLK_OPS_PARENT_ENABLE \
186
+
}
187
+
188
+
#define GATE_HWV_VDE13(_id, _name, _parent, _shift) { \
189
+
.id = _id, \
190
+
.name = _name, \
191
+
.parent_name = _parent, \
192
+
.regs = &vde13_cg_regs, \
193
+
.hwv_regs = &vde13_hwv_regs, \
194
+
.shift = _shift, \
195
+
.ops = &mtk_clk_gate_hwv_ops_setclr_inv,\
196
+
.flags = CLK_OPS_PARENT_ENABLE, \
197
+
}
198
+
199
+
#define GATE_HWV_VDE14(_id, _name, _parent, _shift) { \
200
+
.id = _id, \
201
+
.name = _name, \
202
+
.parent_name = _parent, \
203
+
.regs = &vde22_cg_regs, \
204
+
.hwv_regs = &vde14_hwv_regs, \
205
+
.shift = _shift, \
206
+
.ops = &mtk_clk_gate_hwv_ops_setclr_inv,\
207
+
.flags = CLK_OPS_PARENT_ENABLE | \
208
+
CLK_IGNORE_UNUSED, \
209
+
}
210
+
211
+
static const struct mtk_gate vde1_clks[] = {
212
+
/* VDE10 */
213
+
GATE_HWV_VDE10(CLK_VDE1_VDEC_CKEN, "vde1_vdec_cken", "vdec", 0),
214
+
GATE_HWV_VDE10(CLK_VDE1_VDEC_ACTIVE, "vde1_vdec_active", "vdec", 4),
215
+
GATE_HWV_VDE10(CLK_VDE1_VDEC_CKEN_ENG, "vde1_vdec_cken_eng", "vdec", 8),
216
+
/* VDE11 */
217
+
GATE_HWV_VDE11(CLK_VDE1_VDEC_SOC_IPS_EN, "vde1_vdec_soc_ips_en", "vdec", 0),
218
+
/* VDE12 */
219
+
GATE_HWV_VDE12(CLK_VDE1_VDEC_SOC_APTV_EN, "vde1_aptv_en", "ck_tck_26m_mx9_ck", 0),
220
+
GATE_HWV_VDE12(CLK_VDE1_VDEC_SOC_APTV_TOP_EN, "vde1_aptv_topen", "ck_tck_26m_mx9_ck", 1),
221
+
/* VDE13 */
222
+
GATE_HWV_VDE13(CLK_VDE1_LAT_CKEN, "vde1_lat_cken", "vdec", 0),
223
+
GATE_HWV_VDE13(CLK_VDE1_LAT_ACTIVE, "vde1_lat_active", "vdec", 4),
224
+
GATE_HWV_VDE13(CLK_VDE1_LAT_CKEN_ENG, "vde1_lat_cken_eng", "vdec", 8),
225
+
/* VDE14 */
226
+
GATE_HWV_VDE14(CLK_VDE1_LARB1_CKEN, "vde1_larb1_cken", "vdec", 0),
227
+
};
228
+
229
+
static const struct mtk_clk_desc vde1_mcd = {
230
+
.clks = vde1_clks,
231
+
.num_clks = ARRAY_SIZE(vde1_clks),
232
+
.need_runtime_pm = true,
233
+
};
234
+
235
+
static const struct of_device_id of_match_clk_mt8196_vdec[] = {
236
+
{ .compatible = "mediatek,mt8196-vdecsys", .data = &vde2_mcd },
237
+
{ .compatible = "mediatek,mt8196-vdecsys-soc", .data = &vde1_mcd },
238
+
{ /* sentinel */ }
239
+
};
240
+
MODULE_DEVICE_TABLE(of, of_match_clk_mt8196_vdec);
241
+
242
+
static struct platform_driver clk_mt8196_vdec_drv = {
243
+
.probe = mtk_clk_simple_probe,
244
+
.remove = mtk_clk_simple_remove,
245
+
.driver = {
246
+
.name = "clk-mt8196-vdec",
247
+
.of_match_table = of_match_clk_mt8196_vdec,
248
+
},
249
+
};
250
+
module_platform_driver(clk_mt8196_vdec_drv);
251
+
252
+
MODULE_DESCRIPTION("MediaTek MT8196 Video Decoders clocks driver");
253
+
MODULE_LICENSE("GPL");
+80
drivers/clk/mediatek/clk-mt8196-vdisp_ao.c
+80
drivers/clk/mediatek/clk-mt8196-vdisp_ao.c
···
1
+
// SPDX-License-Identifier: GPL-2.0-only
2
+
/*
3
+
* Copyright (c) 2025 MediaTek Inc.
4
+
* Guangjie Song <guangjie.song@mediatek.com>
5
+
* Copyright (c) 2025 Collabora Ltd.
6
+
* Laura Nao <laura.nao@collabora.com>
7
+
*/
8
+
#include <dt-bindings/clock/mediatek,mt8196-clock.h>
9
+
10
+
#include <linux/clk-provider.h>
11
+
#include <linux/module.h>
12
+
#include <linux/of_device.h>
13
+
#include <linux/platform_device.h>
14
+
15
+
#include "clk-gate.h"
16
+
#include "clk-mtk.h"
17
+
18
+
static const struct mtk_gate_regs mm_v_cg_regs = {
19
+
.set_ofs = 0x104,
20
+
.clr_ofs = 0x108,
21
+
.sta_ofs = 0x100,
22
+
};
23
+
24
+
static const struct mtk_gate_regs mm_v_hwv_regs = {
25
+
.set_ofs = 0x0030,
26
+
.clr_ofs = 0x0034,
27
+
.sta_ofs = 0x2c18,
28
+
};
29
+
30
+
#define GATE_MM_AO_V(_id, _name, _parent, _shift) { \
31
+
.id = _id, \
32
+
.name = _name, \
33
+
.parent_name = _parent, \
34
+
.regs = &mm_v_cg_regs, \
35
+
.shift = _shift, \
36
+
.ops = &mtk_clk_gate_ops_setclr, \
37
+
.flags = CLK_OPS_PARENT_ENABLE | \
38
+
CLK_IS_CRITICAL, \
39
+
}
40
+
41
+
#define GATE_HWV_MM_V(_id, _name, _parent, _shift) { \
42
+
.id = _id, \
43
+
.name = _name, \
44
+
.parent_name = _parent, \
45
+
.regs = &mm_v_cg_regs, \
46
+
.hwv_regs = &mm_v_hwv_regs, \
47
+
.shift = _shift, \
48
+
.ops = &mtk_clk_gate_hwv_ops_setclr, \
49
+
.flags = CLK_OPS_PARENT_ENABLE, \
50
+
}
51
+
52
+
static const struct mtk_gate mm_v_clks[] = {
53
+
GATE_HWV_MM_V(CLK_MM_V_DISP_VDISP_AO_CONFIG, "mm_v_disp_vdisp_ao_config", "disp", 0),
54
+
GATE_HWV_MM_V(CLK_MM_V_DISP_DPC, "mm_v_disp_dpc", "disp", 16),
55
+
GATE_MM_AO_V(CLK_MM_V_SMI_SUB_SOMM0, "mm_v_smi_sub_somm0", "disp", 2),
56
+
};
57
+
58
+
static const struct mtk_clk_desc mm_v_mcd = {
59
+
.clks = mm_v_clks,
60
+
.num_clks = ARRAY_SIZE(mm_v_clks),
61
+
};
62
+
63
+
static const struct of_device_id of_match_clk_mt8196_vdisp_ao[] = {
64
+
{ .compatible = "mediatek,mt8196-vdisp-ao", .data = &mm_v_mcd },
65
+
{ /* sentinel */ }
66
+
};
67
+
MODULE_DEVICE_TABLE(of, of_match_clk_mt8196_vdisp_ao);
68
+
69
+
static struct platform_driver clk_mt8196_vdisp_ao_drv = {
70
+
.probe = mtk_clk_pdev_probe,
71
+
.remove = mtk_clk_pdev_remove,
72
+
.driver = {
73
+
.name = "clk-mt8196-vdisp-ao",
74
+
.of_match_table = of_match_clk_mt8196_vdisp_ao,
75
+
},
76
+
};
77
+
module_platform_driver(clk_mt8196_vdisp_ao_drv);
78
+
79
+
MODULE_DESCRIPTION("MediaTek MT8196 vdisp_ao clocks driver");
80
+
MODULE_LICENSE("GPL");
+236
drivers/clk/mediatek/clk-mt8196-venc.c
+236
drivers/clk/mediatek/clk-mt8196-venc.c
···
1
+
// SPDX-License-Identifier: GPL-2.0-only
2
+
/*
3
+
* Copyright (c) 2025 MediaTek Inc.
4
+
* Guangjie Song <guangjie.song@mediatek.com>
5
+
* Copyright (c) 2025 Collabora Ltd.
6
+
* Laura Nao <laura.nao@collabora.com>
7
+
*/
8
+
#include <dt-bindings/clock/mediatek,mt8196-clock.h>
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+
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+
#include <linux/clk-provider.h>
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#include <linux/module.h>
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#include <linux/of_device.h>
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#include <linux/platform_device.h>
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+
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#include "clk-gate.h"
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#include "clk-mtk.h"
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+
18
+
static const struct mtk_gate_regs ven10_cg_regs = {
19
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.set_ofs = 0x4,
20
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.clr_ofs = 0x8,
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.sta_ofs = 0x0,
22
+
};
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+
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static const struct mtk_gate_regs ven10_hwv_regs = {
25
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.set_ofs = 0x00b8,
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.clr_ofs = 0x00bc,
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.sta_ofs = 0x2c5c,
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+
};
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+
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static const struct mtk_gate_regs ven11_cg_regs = {
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.set_ofs = 0x10,
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.clr_ofs = 0x14,
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.sta_ofs = 0x10,
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+
};
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static const struct mtk_gate_regs ven11_hwv_regs = {
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.set_ofs = 0x00c0,
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.clr_ofs = 0x00c4,
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.sta_ofs = 0x2c60,
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};
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+
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#define GATE_VEN10(_id, _name, _parent, _shift) { \
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.id = _id, \
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.name = _name, \
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.parent_name = _parent, \
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.regs = &ven10_cg_regs, \
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.shift = _shift, \
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.flags = CLK_OPS_PARENT_ENABLE, \
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.ops = &mtk_clk_gate_ops_setclr_inv, \
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}
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+
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#define GATE_HWV_VEN10_FLAGS(_id, _name, _parent, _shift, _flags) { \
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.id = _id, \
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.name = _name, \
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.parent_name = _parent, \
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.regs = &ven10_cg_regs, \
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.hwv_regs = &ven10_hwv_regs, \
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.shift = _shift, \
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.ops = &mtk_clk_gate_hwv_ops_setclr_inv, \
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.flags = (_flags) | \
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CLK_OPS_PARENT_ENABLE, \
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}
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#define GATE_HWV_VEN10(_id, _name, _parent, _shift) \
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GATE_HWV_VEN10_FLAGS(_id, _name, _parent, _shift, 0)
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+
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#define GATE_HWV_VEN11(_id, _name, _parent, _shift) { \
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.id = _id, \
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.name = _name, \
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.parent_name = _parent, \
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.regs = &ven11_cg_regs, \
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.hwv_regs = &ven11_hwv_regs, \
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.shift = _shift, \
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.ops = &mtk_clk_gate_hwv_ops_setclr_inv,\
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.flags = CLK_OPS_PARENT_ENABLE \
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}
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static const struct mtk_gate ven1_clks[] = {
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/* VEN10 */
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GATE_HWV_VEN10(CLK_VEN1_CKE0_LARB, "ven1_larb", "venc", 0),
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GATE_HWV_VEN10(CLK_VEN1_CKE1_VENC, "ven1_venc", "venc", 4),
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GATE_VEN10(CLK_VEN1_CKE2_JPGENC, "ven1_jpgenc", "venc", 8),
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GATE_VEN10(CLK_VEN1_CKE3_JPGDEC, "ven1_jpgdec", "venc", 12),
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GATE_VEN10(CLK_VEN1_CKE4_JPGDEC_C1, "ven1_jpgdec_c1", "venc", 16),
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GATE_HWV_VEN10(CLK_VEN1_CKE5_GALS, "ven1_gals", "venc", 28),
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GATE_HWV_VEN10(CLK_VEN1_CKE29_VENC_ADAB_CTRL, "ven1_venc_adab_ctrl",
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"venc", 29),
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GATE_HWV_VEN10_FLAGS(CLK_VEN1_CKE29_VENC_XPC_CTRL,
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"ven1_venc_xpc_ctrl", "venc", 30,
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CLK_IGNORE_UNUSED),
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GATE_HWV_VEN10(CLK_VEN1_CKE6_GALS_SRAM, "ven1_gals_sram", "venc", 31),
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/* VEN11 */
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GATE_HWV_VEN11(CLK_VEN1_RES_FLAT, "ven1_res_flat", "venc", 0),
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};
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static const struct mtk_clk_desc ven1_mcd = {
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.clks = ven1_clks,
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.num_clks = ARRAY_SIZE(ven1_clks),
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.need_runtime_pm = true,
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};
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static const struct mtk_gate_regs ven20_hwv_regs = {
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.set_ofs = 0x00c8,
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.clr_ofs = 0x00cc,
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.sta_ofs = 0x2c64,
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};
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static const struct mtk_gate_regs ven21_hwv_regs = {
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.set_ofs = 0x00d0,
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.clr_ofs = 0x00d4,
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.sta_ofs = 0x2c68,
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};
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#define GATE_VEN20(_id, _name, _parent, _shift) { \
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.id = _id, \
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.name = _name, \
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.parent_name = _parent, \
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.regs = &ven10_cg_regs, \
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.shift = _shift, \
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.flags = CLK_OPS_PARENT_ENABLE, \
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.ops = &mtk_clk_gate_ops_setclr_inv, \
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}
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#define GATE_HWV_VEN20(_id, _name, _parent, _shift) { \
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.id = _id, \
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.name = _name, \
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.parent_name = _parent, \
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.regs = &ven10_cg_regs, \
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.hwv_regs = &ven20_hwv_regs, \
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.shift = _shift, \
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.ops = &mtk_clk_gate_hwv_ops_setclr_inv,\
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.flags = CLK_OPS_PARENT_ENABLE, \
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}
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#define GATE_HWV_VEN21(_id, _name, _parent, _shift) { \
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.id = _id, \
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.name = _name, \
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.parent_name = _parent, \
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.regs = &ven11_cg_regs, \
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.hwv_regs = &ven21_hwv_regs, \
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.shift = _shift, \
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.ops = &mtk_clk_gate_hwv_ops_setclr, \
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.flags = CLK_OPS_PARENT_ENABLE \
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}
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static const struct mtk_gate ven2_clks[] = {
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/* VEN20 */
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GATE_HWV_VEN20(CLK_VEN2_CKE0_LARB, "ven2_larb", "venc", 0),
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GATE_HWV_VEN20(CLK_VEN2_CKE1_VENC, "ven2_venc", "venc", 4),
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GATE_VEN20(CLK_VEN2_CKE2_JPGENC, "ven2_jpgenc", "venc", 8),
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GATE_VEN20(CLK_VEN2_CKE3_JPGDEC, "ven2_jpgdec", "venc", 12),
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GATE_HWV_VEN20(CLK_VEN2_CKE5_GALS, "ven2_gals", "venc", 28),
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GATE_HWV_VEN20(CLK_VEN2_CKE29_VENC_XPC_CTRL, "ven2_venc_xpc_ctrl", "venc", 30),
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GATE_HWV_VEN20(CLK_VEN2_CKE6_GALS_SRAM, "ven2_gals_sram", "venc", 31),
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/* VEN21 */
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GATE_HWV_VEN21(CLK_VEN2_RES_FLAT, "ven2_res_flat", "venc", 0),
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};
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static const struct mtk_clk_desc ven2_mcd = {
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.clks = ven2_clks,
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.num_clks = ARRAY_SIZE(ven2_clks),
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.need_runtime_pm = true,
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};
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static const struct mtk_gate_regs ven_c20_hwv_regs = {
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.set_ofs = 0x00d8,
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.clr_ofs = 0x00dc,
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.sta_ofs = 0x2c6c,
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};
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static const struct mtk_gate_regs ven_c21_hwv_regs = {
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.set_ofs = 0x00e0,
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.clr_ofs = 0x00e4,
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.sta_ofs = 0x2c70,
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};
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+
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#define GATE_HWV_VEN_C20(_id, _name, _parent, _shift) {\
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.id = _id, \
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.name = _name, \
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.parent_name = _parent, \
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.regs = &ven10_cg_regs, \
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.hwv_regs = &ven_c20_hwv_regs, \
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.shift = _shift, \
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.ops = &mtk_clk_gate_hwv_ops_setclr_inv,\
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.flags = CLK_OPS_PARENT_ENABLE, \
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}
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#define GATE_HWV_VEN_C21(_id, _name, _parent, _shift) {\
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.id = _id, \
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.name = _name, \
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.parent_name = _parent, \
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.regs = &ven11_cg_regs, \
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.hwv_regs = &ven_c21_hwv_regs, \
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.shift = _shift, \
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.ops = &mtk_clk_gate_hwv_ops_setclr, \
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.flags = CLK_OPS_PARENT_ENABLE, \
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}
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static const struct mtk_gate ven_c2_clks[] = {
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/* VEN_C20 */
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GATE_HWV_VEN_C20(CLK_VEN_C2_CKE0_LARB, "ven_c2_larb", "venc", 0),
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GATE_HWV_VEN_C20(CLK_VEN_C2_CKE1_VENC, "ven_c2_venc", "venc", 4),
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GATE_HWV_VEN_C20(CLK_VEN_C2_CKE5_GALS, "ven_c2_gals", "venc", 28),
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GATE_HWV_VEN_C20(CLK_VEN_C2_CKE29_VENC_XPC_CTRL, "ven_c2_venc_xpc_ctrl",
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"venc", 30),
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GATE_HWV_VEN_C20(CLK_VEN_C2_CKE6_GALS_SRAM, "ven_c2_gals_sram", "venc", 31),
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/* VEN_C21 */
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GATE_HWV_VEN_C21(CLK_VEN_C2_RES_FLAT, "ven_c2_res_flat", "venc", 0),
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};
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+
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static const struct mtk_clk_desc ven_c2_mcd = {
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.clks = ven_c2_clks,
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.num_clks = ARRAY_SIZE(ven_c2_clks),
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.need_runtime_pm = true,
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};
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+
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static const struct of_device_id of_match_clk_mt8196_venc[] = {
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{ .compatible = "mediatek,mt8196-vencsys", .data = &ven1_mcd },
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{ .compatible = "mediatek,mt8196-vencsys-c1", .data = &ven2_mcd },
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{ .compatible = "mediatek,mt8196-vencsys-c2", .data = &ven_c2_mcd },
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{ /* sentinel */ }
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};
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MODULE_DEVICE_TABLE(of, of_match_clk_mt8196_venc);
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+
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static struct platform_driver clk_mt8196_venc_drv = {
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.probe = mtk_clk_simple_probe,
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.remove = mtk_clk_simple_remove,
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.driver = {
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.name = "clk-mt8196-venc",
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.of_match_table = of_match_clk_mt8196_venc,
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},
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};
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module_platform_driver(clk_mt8196_venc_drv);
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+
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MODULE_DESCRIPTION("MediaTek MT8196 Video Encoders clocks driver");
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MODULE_LICENSE("GPL");
+725
drivers/clk/mediatek/clk-mt8196-vlpckgen.c
+725
drivers/clk/mediatek/clk-mt8196-vlpckgen.c
···
1
+
// SPDX-License-Identifier: GPL-2.0-only
2
+
/*
3
+
* Copyright (c) 2025 MediaTek Inc.
4
+
* Guangjie Song <guangjie.song@mediatek.com>
5
+
* Copyright (c) 2025 Collabora Ltd.
6
+
* Laura Nao <laura.nao@collabora.com>
7
+
*/
8
+
#include <dt-bindings/clock/mediatek,mt8196-clock.h>
9
+
10
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#include <linux/clk.h>
11
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#include <linux/module.h>
12
+
#include <linux/of.h>
13
+
#include <linux/of_address.h>
14
+
#include <linux/of_device.h>
15
+
#include <linux/platform_device.h>
16
+
#include <linux/regmap.h>
17
+
18
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#include "clk-mtk.h"
19
+
#include "clk-mux.h"
20
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#include "clk-pll.h"
21
+
22
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/* MUX SEL REG */
23
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#define VLP_CLK_CFG_UPDATE 0x0004
24
+
#define VLP_CLK_CFG_UPDATE1 0x0008
25
+
#define VLP_CLK_CFG_0 0x0010
26
+
#define VLP_CLK_CFG_0_SET 0x0014
27
+
#define VLP_CLK_CFG_0_CLR 0x0018
28
+
#define VLP_CLK_CFG_1 0x0020
29
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#define VLP_CLK_CFG_1_SET 0x0024
30
+
#define VLP_CLK_CFG_1_CLR 0x0028
31
+
#define VLP_CLK_CFG_2 0x0030
32
+
#define VLP_CLK_CFG_2_SET 0x0034
33
+
#define VLP_CLK_CFG_2_CLR 0x0038
34
+
#define VLP_CLK_CFG_3 0x0040
35
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#define VLP_CLK_CFG_3_SET 0x0044
36
+
#define VLP_CLK_CFG_3_CLR 0x0048
37
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#define VLP_CLK_CFG_4 0x0050
38
+
#define VLP_CLK_CFG_4_SET 0x0054
39
+
#define VLP_CLK_CFG_4_CLR 0x0058
40
+
#define VLP_CLK_CFG_5 0x0060
41
+
#define VLP_CLK_CFG_5_SET 0x0064
42
+
#define VLP_CLK_CFG_5_CLR 0x0068
43
+
#define VLP_CLK_CFG_6 0x0070
44
+
#define VLP_CLK_CFG_6_SET 0x0074
45
+
#define VLP_CLK_CFG_6_CLR 0x0078
46
+
#define VLP_CLK_CFG_7 0x0080
47
+
#define VLP_CLK_CFG_7_SET 0x0084
48
+
#define VLP_CLK_CFG_7_CLR 0x0088
49
+
#define VLP_CLK_CFG_8 0x0090
50
+
#define VLP_CLK_CFG_8_SET 0x0094
51
+
#define VLP_CLK_CFG_8_CLR 0x0098
52
+
#define VLP_CLK_CFG_9 0x00a0
53
+
#define VLP_CLK_CFG_9_SET 0x00a4
54
+
#define VLP_CLK_CFG_9_CLR 0x00a8
55
+
#define VLP_CLK_CFG_10 0x00b0
56
+
#define VLP_CLK_CFG_10_SET 0x00b4
57
+
#define VLP_CLK_CFG_10_CLR 0x00b8
58
+
#define VLP_OCIC_FENC_STATUS_MON_0 0x039c
59
+
#define VLP_OCIC_FENC_STATUS_MON_1 0x03a0
60
+
61
+
/* MUX SHIFT */
62
+
#define TOP_MUX_SCP_SHIFT 0
63
+
#define TOP_MUX_SCP_SPI_SHIFT 1
64
+
#define TOP_MUX_SCP_IIC_SHIFT 2
65
+
#define TOP_MUX_SCP_IIC_HS_SHIFT 3
66
+
#define TOP_MUX_PWRAP_ULPOSC_SHIFT 4
67
+
#define TOP_MUX_SPMI_M_TIA_32K_SHIFT 5
68
+
#define TOP_MUX_APXGPT_26M_B_SHIFT 6
69
+
#define TOP_MUX_DPSW_SHIFT 7
70
+
#define TOP_MUX_DPSW_CENTRAL_SHIFT 8
71
+
#define TOP_MUX_SPMI_M_MST_SHIFT 9
72
+
#define TOP_MUX_DVFSRC_SHIFT 10
73
+
#define TOP_MUX_PWM_VLP_SHIFT 11
74
+
#define TOP_MUX_AXI_VLP_SHIFT 12
75
+
#define TOP_MUX_SYSTIMER_26M_SHIFT 13
76
+
#define TOP_MUX_SSPM_SHIFT 14
77
+
#define TOP_MUX_SRCK_SHIFT 15
78
+
#define TOP_MUX_CAMTG0_SHIFT 16
79
+
#define TOP_MUX_CAMTG1_SHIFT 17
80
+
#define TOP_MUX_CAMTG2_SHIFT 18
81
+
#define TOP_MUX_CAMTG3_SHIFT 19
82
+
#define TOP_MUX_CAMTG4_SHIFT 20
83
+
#define TOP_MUX_CAMTG5_SHIFT 21
84
+
#define TOP_MUX_CAMTG6_SHIFT 22
85
+
#define TOP_MUX_CAMTG7_SHIFT 23
86
+
#define TOP_MUX_SSPM_26M_SHIFT 25
87
+
#define TOP_MUX_ULPOSC_SSPM_SHIFT 26
88
+
#define TOP_MUX_VLP_PBUS_26M_SHIFT 27
89
+
#define TOP_MUX_DEBUG_ERR_FLAG_VLP_26M_SHIFT 28
90
+
#define TOP_MUX_DPMSRDMA_SHIFT 29
91
+
#define TOP_MUX_VLP_PBUS_156M_SHIFT 30
92
+
#define TOP_MUX_SPM_SHIFT 0
93
+
#define TOP_MUX_MMINFRA_VLP_SHIFT 1
94
+
#define TOP_MUX_USB_TOP_SHIFT 2
95
+
#define TOP_MUX_SSUSB_XHCI_SHIFT 3
96
+
#define TOP_MUX_NOC_VLP_SHIFT 4
97
+
#define TOP_MUX_AUDIO_H_SHIFT 5
98
+
#define TOP_MUX_AUD_ENGEN1_SHIFT 6
99
+
#define TOP_MUX_AUD_ENGEN2_SHIFT 7
100
+
#define TOP_MUX_AUD_INTBUS_SHIFT 8
101
+
#define TOP_MUX_SPU_VLP_26M_SHIFT 9
102
+
#define TOP_MUX_SPU0_VLP_SHIFT 10
103
+
#define TOP_MUX_SPU1_VLP_SHIFT 11
104
+
105
+
/* CKSTA REG */
106
+
#define VLP_CKSTA_REG0 0x0250
107
+
#define VLP_CKSTA_REG1 0x0254
108
+
109
+
/* HW Voter REG */
110
+
#define HWV_CG_9_SET 0x0048
111
+
#define HWV_CG_9_CLR 0x004c
112
+
#define HWV_CG_9_DONE 0x2c24
113
+
#define HWV_CG_10_SET 0x0050
114
+
#define HWV_CG_10_CLR 0x0054
115
+
#define HWV_CG_10_DONE 0x2c28
116
+
117
+
/* PLL REG */
118
+
#define VLP_AP_PLL_CON3 0x264
119
+
#define VLP_APLL1_TUNER_CON0 0x2a4
120
+
#define VLP_APLL2_TUNER_CON0 0x2a8
121
+
#define VLP_APLL1_CON0 0x274
122
+
#define VLP_APLL1_CON1 0x278
123
+
#define VLP_APLL1_CON2 0x27c
124
+
#define VLP_APLL1_CON3 0x280
125
+
#define VLP_APLL2_CON0 0x28c
126
+
#define VLP_APLL2_CON1 0x290
127
+
#define VLP_APLL2_CON2 0x294
128
+
#define VLP_APLL2_CON3 0x298
129
+
130
+
/* vlp apll1 tuner default value*/
131
+
#define VLP_APLL1_TUNER_CON0_VALUE 0x6f28bd4d
132
+
/* vlp apll2 tuner default value + 1*/
133
+
#define VLP_APLL2_TUNER_CON0_VALUE 0x78fd5265
134
+
135
+
#define VLP_PLLEN_ALL 0x080
136
+
#define VLP_PLLEN_ALL_SET 0x084
137
+
#define VLP_PLLEN_ALL_CLR 0x088
138
+
139
+
#define MT8196_PLL_FMAX (3800UL * MHZ)
140
+
#define MT8196_PLL_FMIN (1500UL * MHZ)
141
+
#define MT8196_INTEGER_BITS 8
142
+
143
+
#define PLL_FENC(_id, _name, _reg, _fenc_sta_ofs, _fenc_sta_bit,\
144
+
_flags, _pd_reg, _pd_shift, \
145
+
_pcw_reg, _pcw_shift, _pcwbits, \
146
+
_pll_en_bit) { \
147
+
.id = _id, \
148
+
.name = _name, \
149
+
.reg = _reg, \
150
+
.fenc_sta_ofs = _fenc_sta_ofs, \
151
+
.fenc_sta_bit = _fenc_sta_bit, \
152
+
.flags = _flags, \
153
+
.fmax = MT8196_PLL_FMAX, \
154
+
.fmin = MT8196_PLL_FMIN, \
155
+
.pd_reg = _pd_reg, \
156
+
.pd_shift = _pd_shift, \
157
+
.pcw_reg = _pcw_reg, \
158
+
.pcw_shift = _pcw_shift, \
159
+
.pcwbits = _pcwbits, \
160
+
.pcwibits = MT8196_INTEGER_BITS, \
161
+
.en_reg = VLP_PLLEN_ALL, \
162
+
.en_set_reg = VLP_PLLEN_ALL_SET, \
163
+
.en_clr_reg = VLP_PLLEN_ALL_CLR, \
164
+
.pll_en_bit = _pll_en_bit, \
165
+
.ops = &mtk_pll_fenc_clr_set_ops, \
166
+
}
167
+
168
+
static DEFINE_SPINLOCK(mt8196_clk_vlp_lock);
169
+
170
+
static const struct mtk_fixed_factor vlp_divs[] = {
171
+
FACTOR(CLK_VLP_CLK26M, "vlp_clk26m", "clk26m", 1, 1),
172
+
FACTOR(CLK_VLP_APLL1_D4, "apll1_d4", "vlp_apll1", 1, 4),
173
+
FACTOR(CLK_VLP_APLL1_D8, "apll1_d8", "vlp_apll1", 1, 8),
174
+
FACTOR(CLK_VLP_APLL2_D4, "apll2_d4", "vlp_apll2", 1, 4),
175
+
FACTOR(CLK_VLP_APLL2_D8, "apll2_d8", "vlp_apll2", 1, 8),
176
+
};
177
+
178
+
static const char * const vlp_scp_parents[] = {
179
+
"clk26m",
180
+
"osc_d20",
181
+
"mainpll_d6",
182
+
"mainpll_d4",
183
+
"mainpll_d3",
184
+
"vlp_apll1"
185
+
};
186
+
187
+
static const char * const vlp_scp_spi_parents[] = {
188
+
"clk26m",
189
+
"osc_d20",
190
+
"mainpll_d7_d2",
191
+
"mainpll_d5_d2"
192
+
};
193
+
194
+
static const char * const vlp_scp_iic_parents[] = {
195
+
"clk26m",
196
+
"osc_d20",
197
+
"mainpll_d5_d4",
198
+
"mainpll_d7_d2"
199
+
};
200
+
201
+
static const char * const vlp_scp_iic_hs_parents[] = {
202
+
"clk26m",
203
+
"osc_d20",
204
+
"mainpll_d5_d4",
205
+
"mainpll_d7_d2",
206
+
"mainpll_d7"
207
+
};
208
+
209
+
static const char * const vlp_pwrap_ulposc_parents[] = {
210
+
"clk26m",
211
+
"osc_d20",
212
+
"osc_d14",
213
+
"osc_d10"
214
+
};
215
+
216
+
static const char * const vlp_spmi_32k_parents[] = {
217
+
"clk26m",
218
+
"clk32k",
219
+
"osc_d20",
220
+
"osc_d14",
221
+
"osc_d10"
222
+
};
223
+
224
+
static const char * const vlp_apxgpt_26m_b_parents[] = {
225
+
"clk26m",
226
+
"osc_d20"
227
+
};
228
+
229
+
static const char * const vlp_dpsw_parents[] = {
230
+
"clk26m",
231
+
"osc_d10",
232
+
"osc_d7",
233
+
"mainpll_d7_d4"
234
+
};
235
+
236
+
static const char * const vlp_dpsw_central_parents[] = {
237
+
"clk26m",
238
+
"osc_d10",
239
+
"osc_d7",
240
+
"mainpll_d7_d4"
241
+
};
242
+
243
+
static const char * const vlp_spmi_m_parents[] = {
244
+
"clk26m",
245
+
"osc_d20",
246
+
"osc_d14",
247
+
"osc_d10"
248
+
};
249
+
250
+
static const char * const vlp_dvfsrc_parents[] = {
251
+
"clk26m",
252
+
"osc_d20"
253
+
};
254
+
255
+
static const char * const vlp_pwm_vlp_parents[] = {
256
+
"clk26m",
257
+
"clk32k",
258
+
"osc_d20",
259
+
"osc_d8",
260
+
"mainpll_d4_d8"
261
+
};
262
+
263
+
static const char * const vlp_axi_vlp_parents[] = {
264
+
"clk26m",
265
+
"osc_d20",
266
+
"mainpll_d7_d4",
267
+
"osc_d4",
268
+
"mainpll_d7_d2"
269
+
};
270
+
271
+
static const char * const vlp_systimer_26m_parents[] = {
272
+
"clk26m",
273
+
"osc_d20"
274
+
};
275
+
276
+
static const char * const vlp_sspm_parents[] = {
277
+
"clk26m",
278
+
"osc_d20",
279
+
"mainpll_d5_d2",
280
+
"osc_d2",
281
+
"mainpll_d6"
282
+
};
283
+
284
+
static const char * const vlp_srck_parents[] = {
285
+
"clk26m",
286
+
"osc_d20"
287
+
};
288
+
289
+
static const char * const vlp_camtg0_1_parents[] = {
290
+
"clk26m",
291
+
"univpll_192m_d32",
292
+
"univpll_192m_d16",
293
+
"clk13m",
294
+
"osc_d40",
295
+
"osc_d32",
296
+
"univpll_192m_d10",
297
+
"univpll_192m_d8",
298
+
"univpll_d6_d16",
299
+
"ulposc3",
300
+
"osc_d20",
301
+
"ck2_tvdpll1_d16",
302
+
"univpll_d6_d8"
303
+
};
304
+
305
+
static const char * const vlp_camtg2_7_parents[] = {
306
+
"clk26m",
307
+
"univpll_192m_d32",
308
+
"univpll_192m_d16",
309
+
"clk13m",
310
+
"osc_d40",
311
+
"osc_d32",
312
+
"univpll_192m_d10",
313
+
"univpll_192m_d8",
314
+
"univpll_d6_d16",
315
+
"osc_d20",
316
+
"ck2_tvdpll1_d16",
317
+
"univpll_d6_d8"
318
+
};
319
+
320
+
static const char * const vlp_sspm_26m_parents[] = {
321
+
"clk26m",
322
+
"osc_d20"
323
+
};
324
+
325
+
static const char * const vlp_ulposc_sspm_parents[] = {
326
+
"clk26m",
327
+
"osc_d2",
328
+
"mainpll_d4_d2"
329
+
};
330
+
331
+
static const char * const vlp_vlp_pbus_26m_parents[] = {
332
+
"clk26m",
333
+
"osc_d20"
334
+
};
335
+
336
+
static const char * const vlp_debug_err_flag_parents[] = {
337
+
"clk26m",
338
+
"osc_d20"
339
+
};
340
+
341
+
static const char * const vlp_dpmsrdma_parents[] = {
342
+
"clk26m",
343
+
"mainpll_d7_d2"
344
+
};
345
+
346
+
static const char * const vlp_vlp_pbus_156m_parents[] = {
347
+
"clk26m",
348
+
"osc_d2",
349
+
"mainpll_d7_d2",
350
+
"mainpll_d7"
351
+
};
352
+
353
+
static const char * const vlp_spm_parents[] = {
354
+
"clk26m",
355
+
"mainpll_d7_d4"
356
+
};
357
+
358
+
static const char * const vlp_mminfra_parents[] = {
359
+
"clk26m",
360
+
"osc_d4",
361
+
"mainpll_d3"
362
+
};
363
+
364
+
static const char * const vlp_usb_parents[] = {
365
+
"clk26m",
366
+
"mainpll_d9"
367
+
};
368
+
369
+
static const char * const vlp_noc_vlp_parents[] = {
370
+
"clk26m",
371
+
"osc_d20",
372
+
"mainpll_d9"
373
+
};
374
+
375
+
static const char * const vlp_audio_h_parents[] = {
376
+
"vlp_clk26m",
377
+
"vlp_apll1",
378
+
"vlp_apll2"
379
+
};
380
+
381
+
static const char * const vlp_aud_engen1_parents[] = {
382
+
"vlp_clk26m",
383
+
"apll1_d8",
384
+
"apll1_d4"
385
+
};
386
+
387
+
static const char * const vlp_aud_engen2_parents[] = {
388
+
"vlp_clk26m",
389
+
"apll2_d8",
390
+
"apll2_d4"
391
+
};
392
+
393
+
static const char * const vlp_aud_intbus_parents[] = {
394
+
"vlp_clk26m",
395
+
"mainpll_d7_d4",
396
+
"mainpll_d4_d4"
397
+
};
398
+
399
+
static const u8 vlp_aud_parent_index[] = { 1, 2, 3 };
400
+
401
+
static const char * const vlp_spvlp_26m_parents[] = {
402
+
"clk26m",
403
+
"osc_d20"
404
+
};
405
+
406
+
static const char * const vlp_spu0_vlp_parents[] = {
407
+
"clk26m",
408
+
"osc_d20",
409
+
"mainpll_d4_d4",
410
+
"mainpll_d4_d2",
411
+
"mainpll_d7",
412
+
"mainpll_d6",
413
+
"mainpll_d5"
414
+
};
415
+
416
+
static const char * const vlp_spu1_vlp_parents[] = {
417
+
"clk26m",
418
+
"osc_d20",
419
+
"mainpll_d4_d4",
420
+
"mainpll_d4_d2",
421
+
"mainpll_d7",
422
+
"mainpll_d6",
423
+
"mainpll_d5"
424
+
};
425
+
426
+
static const struct mtk_mux vlp_muxes[] = {
427
+
/* VLP_CLK_CFG_0 */
428
+
MUX_GATE_FENC_CLR_SET_UPD(CLK_VLP_SCP, "vlp_scp", vlp_scp_parents,
429
+
VLP_CLK_CFG_0, VLP_CLK_CFG_0_SET, VLP_CLK_CFG_0_CLR,
430
+
0, 3, 7, VLP_CLK_CFG_UPDATE, TOP_MUX_SCP_SHIFT,
431
+
VLP_OCIC_FENC_STATUS_MON_0, 31),
432
+
MUX_CLR_SET_UPD(CLK_VLP_SCP_SPI, "vlp_scp_spi",
433
+
vlp_scp_spi_parents, VLP_CLK_CFG_0, VLP_CLK_CFG_0_SET,
434
+
VLP_CLK_CFG_0_CLR, 8, 2,
435
+
VLP_CLK_CFG_UPDATE, TOP_MUX_SCP_SPI_SHIFT),
436
+
MUX_CLR_SET_UPD(CLK_VLP_SCP_IIC, "vlp_scp_iic",
437
+
vlp_scp_iic_parents, VLP_CLK_CFG_0, VLP_CLK_CFG_0_SET,
438
+
VLP_CLK_CFG_0_CLR, 16, 2,
439
+
VLP_CLK_CFG_UPDATE, TOP_MUX_SCP_IIC_SHIFT),
440
+
MUX_CLR_SET_UPD(CLK_VLP_SCP_IIC_HS, "vlp_scp_iic_hs",
441
+
vlp_scp_iic_hs_parents, VLP_CLK_CFG_0, VLP_CLK_CFG_0_SET,
442
+
VLP_CLK_CFG_0_CLR, 24, 3,
443
+
VLP_CLK_CFG_UPDATE, TOP_MUX_SCP_IIC_HS_SHIFT),
444
+
/* VLP_CLK_CFG_1 */
445
+
MUX_CLR_SET_UPD(CLK_VLP_PWRAP_ULPOSC, "vlp_pwrap_ulposc",
446
+
vlp_pwrap_ulposc_parents, VLP_CLK_CFG_1, VLP_CLK_CFG_1_SET,
447
+
VLP_CLK_CFG_1_CLR, 0, 2,
448
+
VLP_CLK_CFG_UPDATE, TOP_MUX_PWRAP_ULPOSC_SHIFT),
449
+
MUX_CLR_SET_UPD(CLK_VLP_SPMI_M_TIA_32K, "vlp_spmi_32k",
450
+
vlp_spmi_32k_parents, VLP_CLK_CFG_1, VLP_CLK_CFG_1_SET,
451
+
VLP_CLK_CFG_1_CLR, 8, 3,
452
+
VLP_CLK_CFG_UPDATE, TOP_MUX_SPMI_M_TIA_32K_SHIFT),
453
+
MUX_CLR_SET_UPD(CLK_VLP_APXGPT_26M_B, "vlp_apxgpt_26m_b",
454
+
vlp_apxgpt_26m_b_parents, VLP_CLK_CFG_1, VLP_CLK_CFG_1_SET,
455
+
VLP_CLK_CFG_1_CLR, 16, 1,
456
+
VLP_CLK_CFG_UPDATE, TOP_MUX_APXGPT_26M_B_SHIFT),
457
+
MUX_CLR_SET_UPD(CLK_VLP_DPSW, "vlp_dpsw",
458
+
vlp_dpsw_parents, VLP_CLK_CFG_1, VLP_CLK_CFG_1_SET,
459
+
VLP_CLK_CFG_1_CLR, 24, 2,
460
+
VLP_CLK_CFG_UPDATE, TOP_MUX_DPSW_SHIFT),
461
+
/* VLP_CLK_CFG_2 */
462
+
MUX_CLR_SET_UPD(CLK_VLP_DPSW_CENTRAL, "vlp_dpsw_central",
463
+
vlp_dpsw_central_parents, VLP_CLK_CFG_2, VLP_CLK_CFG_2_SET,
464
+
VLP_CLK_CFG_2_CLR, 0, 2,
465
+
VLP_CLK_CFG_UPDATE, TOP_MUX_DPSW_CENTRAL_SHIFT),
466
+
MUX_CLR_SET_UPD(CLK_VLP_SPMI_M_MST, "vlp_spmi_m",
467
+
vlp_spmi_m_parents, VLP_CLK_CFG_2, VLP_CLK_CFG_2_SET,
468
+
VLP_CLK_CFG_2_CLR, 8, 2,
469
+
VLP_CLK_CFG_UPDATE, TOP_MUX_SPMI_M_MST_SHIFT),
470
+
MUX_CLR_SET_UPD(CLK_VLP_DVFSRC, "vlp_dvfsrc",
471
+
vlp_dvfsrc_parents, VLP_CLK_CFG_2, VLP_CLK_CFG_2_SET,
472
+
VLP_CLK_CFG_2_CLR, 16, 1,
473
+
VLP_CLK_CFG_UPDATE, TOP_MUX_DVFSRC_SHIFT),
474
+
MUX_GATE_FENC_CLR_SET_UPD(CLK_VLP_PWM_VLP, "vlp_pwm_vlp", vlp_pwm_vlp_parents,
475
+
VLP_CLK_CFG_2, VLP_CLK_CFG_2_SET, VLP_CLK_CFG_2_CLR,
476
+
24, 3, 31, VLP_CLK_CFG_UPDATE, TOP_MUX_PWM_VLP_SHIFT,
477
+
VLP_OCIC_FENC_STATUS_MON_0, 20),
478
+
/* VLP_CLK_CFG_3 */
479
+
MUX_CLR_SET_UPD(CLK_VLP_AXI_VLP, "vlp_axi_vlp",
480
+
vlp_axi_vlp_parents, VLP_CLK_CFG_3, VLP_CLK_CFG_3_SET,
481
+
VLP_CLK_CFG_3_CLR, 0, 3,
482
+
VLP_CLK_CFG_UPDATE, TOP_MUX_AXI_VLP_SHIFT),
483
+
MUX_CLR_SET_UPD(CLK_VLP_SYSTIMER_26M, "vlp_systimer_26m",
484
+
vlp_systimer_26m_parents, VLP_CLK_CFG_3, VLP_CLK_CFG_3_SET,
485
+
VLP_CLK_CFG_3_CLR, 8, 1,
486
+
VLP_CLK_CFG_UPDATE, TOP_MUX_SYSTIMER_26M_SHIFT),
487
+
MUX_CLR_SET_UPD(CLK_VLP_SSPM, "vlp_sspm",
488
+
vlp_sspm_parents, VLP_CLK_CFG_3, VLP_CLK_CFG_3_SET,
489
+
VLP_CLK_CFG_3_CLR, 16, 3,
490
+
VLP_CLK_CFG_UPDATE, TOP_MUX_SSPM_SHIFT),
491
+
MUX_CLR_SET_UPD(CLK_VLP_SRCK, "vlp_srck",
492
+
vlp_srck_parents, VLP_CLK_CFG_3, VLP_CLK_CFG_3_SET,
493
+
VLP_CLK_CFG_3_CLR, 24, 1,
494
+
VLP_CLK_CFG_UPDATE, TOP_MUX_SRCK_SHIFT),
495
+
/* VLP_CLK_CFG_4 */
496
+
MUX_GATE_HWV_FENC_CLR_SET_UPD(CLK_VLP_CAMTG0, "vlp_camtg0", vlp_camtg0_1_parents,
497
+
VLP_CLK_CFG_4, VLP_CLK_CFG_4_SET, VLP_CLK_CFG_4_CLR,
498
+
HWV_CG_9_DONE, HWV_CG_9_SET, HWV_CG_9_CLR,
499
+
0, 4, 7, VLP_CLK_CFG_UPDATE, TOP_MUX_CAMTG0_SHIFT,
500
+
VLP_OCIC_FENC_STATUS_MON_0, 15),
501
+
MUX_GATE_HWV_FENC_CLR_SET_UPD(CLK_VLP_CAMTG1, "vlp_camtg1", vlp_camtg0_1_parents,
502
+
VLP_CLK_CFG_4, VLP_CLK_CFG_4_SET, VLP_CLK_CFG_4_CLR,
503
+
HWV_CG_9_DONE, HWV_CG_9_SET, HWV_CG_9_CLR,
504
+
8, 4, 15, VLP_CLK_CFG_UPDATE, TOP_MUX_CAMTG1_SHIFT,
505
+
VLP_OCIC_FENC_STATUS_MON_0, 14),
506
+
MUX_GATE_HWV_FENC_CLR_SET_UPD(CLK_VLP_CAMTG2, "vlp_camtg2", vlp_camtg2_7_parents,
507
+
VLP_CLK_CFG_4, VLP_CLK_CFG_4_SET, VLP_CLK_CFG_4_CLR,
508
+
HWV_CG_9_DONE, HWV_CG_9_SET, HWV_CG_9_CLR,
509
+
16, 4, 23, VLP_CLK_CFG_UPDATE, TOP_MUX_CAMTG2_SHIFT,
510
+
VLP_OCIC_FENC_STATUS_MON_0, 13),
511
+
MUX_GATE_HWV_FENC_CLR_SET_UPD(CLK_VLP_CAMTG3, "vlp_camtg3", vlp_camtg2_7_parents,
512
+
VLP_CLK_CFG_4, VLP_CLK_CFG_4_SET, VLP_CLK_CFG_4_CLR,
513
+
HWV_CG_9_DONE, HWV_CG_9_SET, HWV_CG_9_CLR,
514
+
24, 4, 31, VLP_CLK_CFG_UPDATE, TOP_MUX_CAMTG3_SHIFT,
515
+
VLP_OCIC_FENC_STATUS_MON_0, 12),
516
+
/* VLP_CLK_CFG_5 */
517
+
MUX_GATE_HWV_FENC_CLR_SET_UPD(CLK_VLP_CAMTG4, "vlp_camtg4", vlp_camtg2_7_parents,
518
+
VLP_CLK_CFG_5, VLP_CLK_CFG_5_SET, VLP_CLK_CFG_5_CLR,
519
+
HWV_CG_10_DONE, HWV_CG_10_SET, HWV_CG_10_CLR,
520
+
0, 4, 7, VLP_CLK_CFG_UPDATE, TOP_MUX_CAMTG4_SHIFT,
521
+
VLP_OCIC_FENC_STATUS_MON_0, 11),
522
+
MUX_GATE_HWV_FENC_CLR_SET_UPD(CLK_VLP_CAMTG5, "vlp_camtg5", vlp_camtg2_7_parents,
523
+
VLP_CLK_CFG_5, VLP_CLK_CFG_5_SET, VLP_CLK_CFG_5_CLR,
524
+
HWV_CG_10_DONE, HWV_CG_10_SET, HWV_CG_10_CLR,
525
+
8, 4, 15, VLP_CLK_CFG_UPDATE, TOP_MUX_CAMTG5_SHIFT,
526
+
VLP_OCIC_FENC_STATUS_MON_0, 10),
527
+
MUX_GATE_HWV_FENC_CLR_SET_UPD(CLK_VLP_CAMTG6, "vlp_camtg6", vlp_camtg2_7_parents,
528
+
VLP_CLK_CFG_5, VLP_CLK_CFG_5_SET, VLP_CLK_CFG_5_CLR,
529
+
HWV_CG_10_DONE, HWV_CG_10_SET, HWV_CG_10_CLR,
530
+
16, 4, 23, VLP_CLK_CFG_UPDATE, TOP_MUX_CAMTG6_SHIFT,
531
+
VLP_OCIC_FENC_STATUS_MON_0, 9),
532
+
MUX_GATE_HWV_FENC_CLR_SET_UPD(CLK_VLP_CAMTG7, "vlp_camtg7", vlp_camtg2_7_parents,
533
+
VLP_CLK_CFG_5, VLP_CLK_CFG_5_SET, VLP_CLK_CFG_5_CLR,
534
+
HWV_CG_10_DONE, HWV_CG_10_SET, HWV_CG_10_CLR,
535
+
24, 4, 31, VLP_CLK_CFG_UPDATE, TOP_MUX_CAMTG7_SHIFT,
536
+
VLP_OCIC_FENC_STATUS_MON_0, 8),
537
+
/* VLP_CLK_CFG_6 */
538
+
MUX_CLR_SET_UPD(CLK_VLP_SSPM_26M, "vlp_sspm_26m",
539
+
vlp_sspm_26m_parents, VLP_CLK_CFG_6, VLP_CLK_CFG_6_SET,
540
+
VLP_CLK_CFG_6_CLR, 8, 1,
541
+
VLP_CLK_CFG_UPDATE, TOP_MUX_SSPM_26M_SHIFT),
542
+
MUX_CLR_SET_UPD(CLK_VLP_ULPOSC_SSPM, "vlp_ulposc_sspm",
543
+
vlp_ulposc_sspm_parents, VLP_CLK_CFG_6, VLP_CLK_CFG_6_SET,
544
+
VLP_CLK_CFG_6_CLR, 16, 2,
545
+
VLP_CLK_CFG_UPDATE, TOP_MUX_ULPOSC_SSPM_SHIFT),
546
+
MUX_CLR_SET_UPD(CLK_VLP_VLP_PBUS_26M, "vlp_vlp_pbus_26m",
547
+
vlp_vlp_pbus_26m_parents, VLP_CLK_CFG_6, VLP_CLK_CFG_6_SET,
548
+
VLP_CLK_CFG_6_CLR, 24, 1,
549
+
VLP_CLK_CFG_UPDATE, TOP_MUX_VLP_PBUS_26M_SHIFT),
550
+
/* VLP_CLK_CFG_7 */
551
+
MUX_CLR_SET_UPD(CLK_VLP_DEBUG_ERR_FLAG, "vlp_debug_err_flag",
552
+
vlp_debug_err_flag_parents, VLP_CLK_CFG_7, VLP_CLK_CFG_7_SET,
553
+
VLP_CLK_CFG_7_CLR, 0, 1,
554
+
VLP_CLK_CFG_UPDATE, TOP_MUX_DEBUG_ERR_FLAG_VLP_26M_SHIFT),
555
+
MUX_CLR_SET_UPD(CLK_VLP_DPMSRDMA, "vlp_dpmsrdma",
556
+
vlp_dpmsrdma_parents, VLP_CLK_CFG_7, VLP_CLK_CFG_7_SET,
557
+
VLP_CLK_CFG_7_CLR, 8, 1,
558
+
VLP_CLK_CFG_UPDATE, TOP_MUX_DPMSRDMA_SHIFT),
559
+
MUX_CLR_SET_UPD(CLK_VLP_VLP_PBUS_156M, "vlp_vlp_pbus_156m",
560
+
vlp_vlp_pbus_156m_parents, VLP_CLK_CFG_7, VLP_CLK_CFG_7_SET,
561
+
VLP_CLK_CFG_7_CLR, 16, 2,
562
+
VLP_CLK_CFG_UPDATE, TOP_MUX_VLP_PBUS_156M_SHIFT),
563
+
MUX_CLR_SET_UPD(CLK_VLP_SPM, "vlp_spm",
564
+
vlp_spm_parents, VLP_CLK_CFG_7, VLP_CLK_CFG_7_SET,
565
+
VLP_CLK_CFG_7_CLR, 24, 1,
566
+
VLP_CLK_CFG_UPDATE1, TOP_MUX_SPM_SHIFT),
567
+
/* VLP_CLK_CFG_8 */
568
+
MUX_GATE_FENC_CLR_SET_UPD(CLK_VLP_MMINFRA, "vlp_mminfra", vlp_mminfra_parents,
569
+
VLP_CLK_CFG_8, VLP_CLK_CFG_8_SET, VLP_CLK_CFG_8_CLR,
570
+
0, 2, 7, VLP_CLK_CFG_UPDATE1, TOP_MUX_MMINFRA_VLP_SHIFT,
571
+
VLP_OCIC_FENC_STATUS_MON_1, 31),
572
+
MUX_GATE_FENC_CLR_SET_UPD(CLK_VLP_USB_TOP, "vlp_usb", vlp_usb_parents,
573
+
VLP_CLK_CFG_8, VLP_CLK_CFG_8_SET, VLP_CLK_CFG_8_CLR,
574
+
8, 1, 15, VLP_CLK_CFG_UPDATE1, TOP_MUX_USB_TOP_SHIFT,
575
+
VLP_OCIC_FENC_STATUS_MON_1, 30),
576
+
MUX_GATE_FENC_CLR_SET_UPD(CLK_VLP_USB_XHCI, "vlp_usb_xhci", vlp_usb_parents,
577
+
VLP_CLK_CFG_8, VLP_CLK_CFG_8_SET, VLP_CLK_CFG_8_CLR,
578
+
16, 1, 23, VLP_CLK_CFG_UPDATE1, TOP_MUX_SSUSB_XHCI_SHIFT,
579
+
VLP_OCIC_FENC_STATUS_MON_1, 29),
580
+
MUX_CLR_SET_UPD(CLK_VLP_NOC_VLP, "vlp_noc_vlp",
581
+
vlp_noc_vlp_parents, VLP_CLK_CFG_8, VLP_CLK_CFG_8_SET,
582
+
VLP_CLK_CFG_8_CLR, 24, 2,
583
+
VLP_CLK_CFG_UPDATE1, TOP_MUX_NOC_VLP_SHIFT),
584
+
/* VLP_CLK_CFG_9 */
585
+
MUX_GATE_FENC_CLR_SET_UPD_INDEXED(CLK_VLP_AUDIO_H, "vlp_audio_h",
586
+
vlp_audio_h_parents, vlp_aud_parent_index,
587
+
VLP_CLK_CFG_9, VLP_CLK_CFG_9_SET, VLP_CLK_CFG_9_CLR,
588
+
0, 2, 7, VLP_CLK_CFG_UPDATE1, TOP_MUX_AUDIO_H_SHIFT,
589
+
VLP_OCIC_FENC_STATUS_MON_1, 27),
590
+
MUX_GATE_FENC_CLR_SET_UPD_INDEXED(CLK_VLP_AUD_ENGEN1, "vlp_aud_engen1",
591
+
vlp_aud_engen1_parents, vlp_aud_parent_index,
592
+
VLP_CLK_CFG_9, VLP_CLK_CFG_9_SET, VLP_CLK_CFG_9_CLR,
593
+
8, 2, 15, VLP_CLK_CFG_UPDATE1, TOP_MUX_AUD_ENGEN1_SHIFT,
594
+
VLP_OCIC_FENC_STATUS_MON_1, 26),
595
+
MUX_GATE_FENC_CLR_SET_UPD_INDEXED(CLK_VLP_AUD_ENGEN2, "vlp_aud_engen2",
596
+
vlp_aud_engen2_parents, vlp_aud_parent_index,
597
+
VLP_CLK_CFG_9, VLP_CLK_CFG_9_SET, VLP_CLK_CFG_9_CLR,
598
+
16, 2, 23, VLP_CLK_CFG_UPDATE1, TOP_MUX_AUD_ENGEN2_SHIFT,
599
+
VLP_OCIC_FENC_STATUS_MON_1, 25),
600
+
MUX_GATE_FENC_CLR_SET_UPD_INDEXED(CLK_VLP_AUD_INTBUS, "vlp_aud_intbus",
601
+
vlp_aud_intbus_parents, vlp_aud_parent_index,
602
+
VLP_CLK_CFG_9, VLP_CLK_CFG_9_SET, VLP_CLK_CFG_9_CLR,
603
+
24, 2, 31, VLP_CLK_CFG_UPDATE1, TOP_MUX_AUD_INTBUS_SHIFT,
604
+
VLP_OCIC_FENC_STATUS_MON_1, 24),
605
+
/* VLP_CLK_CFG_10 */
606
+
MUX_CLR_SET_UPD(CLK_VLP_SPVLP_26M, "vlp_spvlp_26m",
607
+
vlp_spvlp_26m_parents, VLP_CLK_CFG_10, VLP_CLK_CFG_10_SET,
608
+
VLP_CLK_CFG_10_CLR, 0, 1,
609
+
VLP_CLK_CFG_UPDATE1, TOP_MUX_SPU_VLP_26M_SHIFT),
610
+
MUX_CLR_SET_UPD(CLK_VLP_SPU0_VLP, "vlp_spu0_vlp",
611
+
vlp_spu0_vlp_parents, VLP_CLK_CFG_10, VLP_CLK_CFG_10_SET,
612
+
VLP_CLK_CFG_10_CLR, 8, 3,
613
+
VLP_CLK_CFG_UPDATE1, TOP_MUX_SPU0_VLP_SHIFT),
614
+
MUX_CLR_SET_UPD(CLK_VLP_SPU1_VLP, "vlp_spu1_vlp",
615
+
vlp_spu1_vlp_parents, VLP_CLK_CFG_10, VLP_CLK_CFG_10_SET,
616
+
VLP_CLK_CFG_10_CLR, 16, 3,
617
+
VLP_CLK_CFG_UPDATE1, TOP_MUX_SPU1_VLP_SHIFT),
618
+
};
619
+
620
+
static const struct mtk_pll_data vlp_plls[] = {
621
+
PLL_FENC(CLK_VLP_APLL1, "vlp_apll1", VLP_APLL1_CON0, 0x0358, 1, 0,
622
+
VLP_APLL1_CON1, 24, VLP_APLL1_CON2, 0, 32, 0),
623
+
PLL_FENC(CLK_VLP_APLL2, "vlp_apll2", VLP_APLL2_CON0, 0x0358, 0, 0,
624
+
VLP_APLL2_CON1, 24, VLP_APLL2_CON2, 0, 32, 1),
625
+
};
626
+
627
+
static const struct regmap_config vlpckgen_regmap_config = {
628
+
.reg_bits = 32,
629
+
.val_bits = 32,
630
+
.reg_stride = 4,
631
+
.max_register = 0x1000,
632
+
.fast_io = true,
633
+
};
634
+
635
+
static int clk_mt8196_vlp_probe(struct platform_device *pdev)
636
+
{
637
+
static void __iomem *base;
638
+
struct clk_hw_onecell_data *clk_data;
639
+
int r;
640
+
struct device_node *node = pdev->dev.of_node;
641
+
struct device *dev = &pdev->dev;
642
+
struct regmap *regmap;
643
+
644
+
clk_data = mtk_alloc_clk_data(ARRAY_SIZE(vlp_muxes) +
645
+
ARRAY_SIZE(vlp_plls) +
646
+
ARRAY_SIZE(vlp_divs));
647
+
if (!clk_data)
648
+
return -ENOMEM;
649
+
650
+
base = devm_platform_ioremap_resource(pdev, 0);
651
+
if (IS_ERR(base))
652
+
return PTR_ERR(base);
653
+
654
+
regmap = devm_regmap_init_mmio(dev, base, &vlpckgen_regmap_config);
655
+
if (IS_ERR(regmap))
656
+
return PTR_ERR(regmap);
657
+
658
+
r = mtk_clk_register_factors(vlp_divs, ARRAY_SIZE(vlp_divs), clk_data);
659
+
if (r)
660
+
goto free_clk_data;
661
+
662
+
r = mtk_clk_register_muxes(&pdev->dev, vlp_muxes, ARRAY_SIZE(vlp_muxes),
663
+
node, &mt8196_clk_vlp_lock, clk_data);
664
+
if (r)
665
+
goto unregister_factors;
666
+
667
+
r = mtk_clk_register_plls(node, vlp_plls, ARRAY_SIZE(vlp_plls),
668
+
clk_data);
669
+
if (r)
670
+
goto unregister_muxes;
671
+
672
+
r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data);
673
+
if (r)
674
+
goto unregister_plls;
675
+
676
+
platform_set_drvdata(pdev, clk_data);
677
+
678
+
/* Initialize APLL tuner registers */
679
+
regmap_write(regmap, VLP_APLL1_TUNER_CON0, VLP_APLL1_TUNER_CON0_VALUE);
680
+
regmap_write(regmap, VLP_APLL2_TUNER_CON0, VLP_APLL2_TUNER_CON0_VALUE);
681
+
682
+
return r;
683
+
684
+
unregister_plls:
685
+
mtk_clk_unregister_plls(vlp_plls, ARRAY_SIZE(vlp_plls), clk_data);
686
+
unregister_muxes:
687
+
mtk_clk_unregister_muxes(vlp_muxes, ARRAY_SIZE(vlp_muxes), clk_data);
688
+
unregister_factors:
689
+
mtk_clk_unregister_factors(vlp_divs, ARRAY_SIZE(vlp_divs), clk_data);
690
+
free_clk_data:
691
+
mtk_free_clk_data(clk_data);
692
+
693
+
return r;
694
+
}
695
+
696
+
static void clk_mt8196_vlp_remove(struct platform_device *pdev)
697
+
{
698
+
struct clk_hw_onecell_data *clk_data = platform_get_drvdata(pdev);
699
+
struct device_node *node = pdev->dev.of_node;
700
+
701
+
of_clk_del_provider(node);
702
+
mtk_clk_unregister_plls(vlp_plls, ARRAY_SIZE(vlp_plls), clk_data);
703
+
mtk_clk_unregister_muxes(vlp_muxes, ARRAY_SIZE(vlp_muxes), clk_data);
704
+
mtk_clk_unregister_factors(vlp_divs, ARRAY_SIZE(vlp_divs), clk_data);
705
+
mtk_free_clk_data(clk_data);
706
+
}
707
+
708
+
static const struct of_device_id of_match_clk_mt8196_vlp_ck[] = {
709
+
{ .compatible = "mediatek,mt8196-vlpckgen" },
710
+
{ /* sentinel */ }
711
+
};
712
+
MODULE_DEVICE_TABLE(of, of_match_clk_mt8196_vlp_ck);
713
+
714
+
static struct platform_driver clk_mt8196_vlp_drv = {
715
+
.probe = clk_mt8196_vlp_probe,
716
+
.remove = clk_mt8196_vlp_remove,
717
+
.driver = {
718
+
.name = "clk-mt8196-vlpck",
719
+
.of_match_table = of_match_clk_mt8196_vlp_ck,
720
+
},
721
+
};
722
+
723
+
MODULE_DESCRIPTION("MediaTek MT8196 VLP clock generator driver");
724
+
module_platform_driver(clk_mt8196_vlp_drv);
725
+
MODULE_LICENSE("GPL");
+16
drivers/clk/mediatek/clk-mtk.c
+16
drivers/clk/mediatek/clk-mtk.c
···
685
685
}
686
686
EXPORT_SYMBOL_GPL(mtk_clk_simple_remove);
687
687
688
+
struct regmap *mtk_clk_get_hwv_regmap(struct device_node *node)
689
+
{
690
+
struct device_node *hwv_node;
691
+
struct regmap *regmap_hwv;
692
+
693
+
hwv_node = of_parse_phandle(node, "mediatek,hardware-voter", 0);
694
+
if (!hwv_node)
695
+
return NULL;
696
+
697
+
regmap_hwv = device_node_to_regmap(hwv_node);
698
+
of_node_put(hwv_node);
699
+
700
+
return regmap_hwv;
701
+
}
702
+
EXPORT_SYMBOL_GPL(mtk_clk_get_hwv_regmap);
703
+
688
704
MODULE_LICENSE("GPL");
+22
drivers/clk/mediatek/clk-mtk.h
+22
drivers/clk/mediatek/clk-mtk.h
···
20
20
21
21
#define MHZ (1000 * 1000)
22
22
23
+
#define MTK_WAIT_HWV_DONE_US 30
24
+
23
25
struct platform_device;
24
26
25
27
/*
···
175
173
.flags = 0, \
176
174
}
177
175
176
+
#define MUX_DIV_GATE(_id, _name, _parents, \
177
+
_mux_reg, _mux_shift, _mux_width, \
178
+
_div_reg, _div_shift, _div_width, \
179
+
_gate_reg, _gate_shift) { \
180
+
.id = _id, \
181
+
.name = _name, \
182
+
.parent_names = _parents, \
183
+
.num_parents = ARRAY_SIZE(_parents), \
184
+
.mux_reg = _mux_reg, \
185
+
.mux_shift = _mux_shift, \
186
+
.mux_width = _mux_width, \
187
+
.divider_reg = _div_reg, \
188
+
.divider_shift = _div_shift, \
189
+
.divider_width = _div_width, \
190
+
.gate_reg = _gate_reg, \
191
+
.gate_shift = _gate_shift, \
192
+
.flags = CLK_SET_RATE_PARENT, \
193
+
}
194
+
178
195
int mtk_clk_register_composites(struct device *dev,
179
196
const struct mtk_composite *mcs, int num,
180
197
void __iomem *base, spinlock_t *lock,
···
266
245
void mtk_clk_pdev_remove(struct platform_device *pdev);
267
246
int mtk_clk_simple_probe(struct platform_device *pdev);
268
247
void mtk_clk_simple_remove(struct platform_device *pdev);
248
+
struct regmap *mtk_clk_get_hwv_regmap(struct device_node *node);
269
249
270
250
#endif /* __DRV_CLK_MTK_H */
+119
-3
drivers/clk/mediatek/clk-mux.c
+119
-3
drivers/clk/mediatek/clk-mux.c
···
8
8
#include <linux/clk-provider.h>
9
9
#include <linux/compiler_types.h>
10
10
#include <linux/container_of.h>
11
+
#include <linux/dev_printk.h>
11
12
#include <linux/err.h>
12
13
#include <linux/mfd/syscon.h>
13
14
#include <linux/module.h>
···
16
15
#include <linux/spinlock.h>
17
16
#include <linux/slab.h>
18
17
18
+
#include "clk-mtk.h"
19
19
#include "clk-mux.h"
20
+
21
+
#define MTK_WAIT_FENC_DONE_US 30
20
22
21
23
struct mtk_clk_mux {
22
24
struct clk_hw hw;
23
25
struct regmap *regmap;
26
+
struct regmap *regmap_hwv;
24
27
const struct mtk_mux *data;
25
28
spinlock_t *lock;
26
29
bool reparent;
···
33
28
static inline struct mtk_clk_mux *to_mtk_clk_mux(struct clk_hw *hw)
34
29
{
35
30
return container_of(hw, struct mtk_clk_mux, hw);
31
+
}
32
+
33
+
static int mtk_clk_mux_fenc_enable_setclr(struct clk_hw *hw)
34
+
{
35
+
struct mtk_clk_mux *mux = to_mtk_clk_mux(hw);
36
+
unsigned long flags;
37
+
u32 val;
38
+
int ret;
39
+
40
+
if (mux->lock)
41
+
spin_lock_irqsave(mux->lock, flags);
42
+
else
43
+
__acquire(mux->lock);
44
+
45
+
regmap_write(mux->regmap, mux->data->clr_ofs,
46
+
BIT(mux->data->gate_shift));
47
+
48
+
ret = regmap_read_poll_timeout_atomic(mux->regmap, mux->data->fenc_sta_mon_ofs,
49
+
val, val & BIT(mux->data->fenc_shift), 1,
50
+
MTK_WAIT_FENC_DONE_US);
51
+
52
+
if (mux->lock)
53
+
spin_unlock_irqrestore(mux->lock, flags);
54
+
else
55
+
__release(mux->lock);
56
+
57
+
return ret;
36
58
}
37
59
38
60
static int mtk_clk_mux_enable_setclr(struct clk_hw *hw)
···
102
70
BIT(mux->data->gate_shift));
103
71
}
104
72
73
+
static int mtk_clk_mux_fenc_is_enabled(struct clk_hw *hw)
74
+
{
75
+
struct mtk_clk_mux *mux = to_mtk_clk_mux(hw);
76
+
u32 val;
77
+
78
+
regmap_read(mux->regmap, mux->data->fenc_sta_mon_ofs, &val);
79
+
80
+
return !!(val & BIT(mux->data->fenc_shift));
81
+
}
82
+
105
83
static int mtk_clk_mux_is_enabled(struct clk_hw *hw)
106
84
{
107
85
struct mtk_clk_mux *mux = to_mtk_clk_mux(hw);
···
120
78
regmap_read(mux->regmap, mux->data->mux_ofs, &val);
121
79
122
80
return (val & BIT(mux->data->gate_shift)) == 0;
81
+
}
82
+
83
+
static int mtk_clk_mux_hwv_fenc_enable(struct clk_hw *hw)
84
+
{
85
+
struct mtk_clk_mux *mux = to_mtk_clk_mux(hw);
86
+
u32 val;
87
+
int ret;
88
+
89
+
regmap_write(mux->regmap_hwv, mux->data->hwv_set_ofs,
90
+
BIT(mux->data->gate_shift));
91
+
92
+
ret = regmap_read_poll_timeout_atomic(mux->regmap_hwv, mux->data->hwv_sta_ofs,
93
+
val, val & BIT(mux->data->gate_shift), 0,
94
+
MTK_WAIT_HWV_DONE_US);
95
+
if (ret)
96
+
return ret;
97
+
98
+
ret = regmap_read_poll_timeout_atomic(mux->regmap, mux->data->fenc_sta_mon_ofs,
99
+
val, val & BIT(mux->data->fenc_shift), 1,
100
+
MTK_WAIT_FENC_DONE_US);
101
+
102
+
return ret;
103
+
}
104
+
105
+
static void mtk_clk_mux_hwv_disable(struct clk_hw *hw)
106
+
{
107
+
struct mtk_clk_mux *mux = to_mtk_clk_mux(hw);
108
+
u32 val;
109
+
110
+
regmap_write(mux->regmap_hwv, mux->data->hwv_clr_ofs,
111
+
BIT(mux->data->gate_shift));
112
+
113
+
regmap_read_poll_timeout_atomic(mux->regmap_hwv, mux->data->hwv_sta_ofs,
114
+
val, (val & BIT(mux->data->gate_shift)),
115
+
0, MTK_WAIT_HWV_DONE_US);
123
116
}
124
117
125
118
static u8 mtk_clk_mux_get_parent(struct clk_hw *hw)
···
223
146
static int mtk_clk_mux_determine_rate(struct clk_hw *hw,
224
147
struct clk_rate_request *req)
225
148
{
226
-
struct mtk_clk_mux *mux = to_mtk_clk_mux(hw);
149
+
return clk_mux_determine_rate_flags(hw, req, 0);
150
+
}
227
151
228
-
return clk_mux_determine_rate_flags(hw, req, mux->data->flags);
152
+
static bool mtk_clk_mux_uses_hwv(const struct clk_ops *ops)
153
+
{
154
+
if (ops == &mtk_mux_gate_hwv_fenc_clr_set_upd_ops)
155
+
return true;
156
+
157
+
return false;
229
158
}
230
159
231
160
const struct clk_ops mtk_mux_clr_set_upd_ops = {
···
251
168
};
252
169
EXPORT_SYMBOL_GPL(mtk_mux_gate_clr_set_upd_ops);
253
170
171
+
const struct clk_ops mtk_mux_gate_fenc_clr_set_upd_ops = {
172
+
.enable = mtk_clk_mux_fenc_enable_setclr,
173
+
.disable = mtk_clk_mux_disable_setclr,
174
+
.is_enabled = mtk_clk_mux_fenc_is_enabled,
175
+
.get_parent = mtk_clk_mux_get_parent,
176
+
.set_parent = mtk_clk_mux_set_parent_setclr_lock,
177
+
.determine_rate = mtk_clk_mux_determine_rate,
178
+
};
179
+
EXPORT_SYMBOL_GPL(mtk_mux_gate_fenc_clr_set_upd_ops);
180
+
181
+
const struct clk_ops mtk_mux_gate_hwv_fenc_clr_set_upd_ops = {
182
+
.enable = mtk_clk_mux_hwv_fenc_enable,
183
+
.disable = mtk_clk_mux_hwv_disable,
184
+
.is_enabled = mtk_clk_mux_fenc_is_enabled,
185
+
.get_parent = mtk_clk_mux_get_parent,
186
+
.set_parent = mtk_clk_mux_set_parent_setclr_lock,
187
+
.determine_rate = mtk_clk_mux_determine_rate,
188
+
};
189
+
EXPORT_SYMBOL_GPL(mtk_mux_gate_hwv_fenc_clr_set_upd_ops);
190
+
254
191
static struct clk_hw *mtk_clk_register_mux(struct device *dev,
255
192
const struct mtk_mux *mux,
256
193
struct regmap *regmap,
194
+
struct regmap *regmap_hwv,
257
195
spinlock_t *lock)
258
196
{
259
197
struct mtk_clk_mux *clk_mux;
···
290
186
init.parent_names = mux->parent_names;
291
187
init.num_parents = mux->num_parents;
292
188
init.ops = mux->ops;
189
+
if (mtk_clk_mux_uses_hwv(init.ops) && !regmap_hwv)
190
+
return dev_err_ptr_probe(
191
+
dev, -ENXIO,
192
+
"regmap not found for hardware voter clocks\n");
293
193
294
194
clk_mux->regmap = regmap;
195
+
clk_mux->regmap_hwv = regmap_hwv;
295
196
clk_mux->data = mux;
296
197
clk_mux->lock = lock;
297
198
clk_mux->hw.init = &init;
···
329
220
struct clk_hw_onecell_data *clk_data)
330
221
{
331
222
struct regmap *regmap;
223
+
struct regmap *regmap_hwv;
332
224
struct clk_hw *hw;
333
225
int i;
334
226
···
338
228
pr_err("Cannot find regmap for %pOF: %pe\n", node, regmap);
339
229
return PTR_ERR(regmap);
340
230
}
231
+
232
+
regmap_hwv = mtk_clk_get_hwv_regmap(node);
233
+
if (IS_ERR(regmap_hwv))
234
+
return dev_err_probe(
235
+
dev, PTR_ERR(regmap_hwv),
236
+
"Cannot find hardware voter regmap for %pOF\n", node);
341
237
342
238
for (i = 0; i < num; i++) {
343
239
const struct mtk_mux *mux = &muxes[i];
···
354
238
continue;
355
239
}
356
240
357
-
hw = mtk_clk_register_mux(dev, mux, regmap, lock);
241
+
hw = mtk_clk_register_mux(dev, mux, regmap, regmap_hwv, lock);
358
242
359
243
if (IS_ERR(hw)) {
360
244
pr_err("Failed to register clk %s: %pe\n", mux->name,
+87
drivers/clk/mediatek/clk-mux.h
+87
drivers/clk/mediatek/clk-mux.h
···
29
29
u32 clr_ofs;
30
30
u32 upd_ofs;
31
31
32
+
u32 hwv_set_ofs;
33
+
u32 hwv_clr_ofs;
34
+
u32 hwv_sta_ofs;
35
+
u32 fenc_sta_mon_ofs;
36
+
32
37
u8 mux_shift;
33
38
u8 mux_width;
34
39
u8 gate_shift;
35
40
s8 upd_shift;
41
+
u8 fenc_shift;
36
42
37
43
const struct clk_ops *ops;
38
44
signed char num_parents;
···
83
77
84
78
extern const struct clk_ops mtk_mux_clr_set_upd_ops;
85
79
extern const struct clk_ops mtk_mux_gate_clr_set_upd_ops;
80
+
extern const struct clk_ops mtk_mux_gate_fenc_clr_set_upd_ops;
81
+
extern const struct clk_ops mtk_mux_gate_hwv_fenc_clr_set_upd_ops;
86
82
87
83
#define MUX_GATE_CLR_SET_UPD_FLAGS(_id, _name, _parents, _mux_ofs, \
88
84
_mux_set_ofs, _mux_clr_ofs, _shift, _width, \
···
125
117
_mux_set_ofs, _mux_clr_ofs, _shift, _width, \
126
118
0, _upd_ofs, _upd, CLK_SET_RATE_PARENT, \
127
119
mtk_mux_clr_set_upd_ops)
120
+
121
+
#define MUX_GATE_HWV_FENC_CLR_SET_UPD_FLAGS(_id, _name, _parents, \
122
+
_mux_ofs, _mux_set_ofs, _mux_clr_ofs, \
123
+
_hwv_sta_ofs, _hwv_set_ofs, _hwv_clr_ofs, \
124
+
_shift, _width, _gate, _upd_ofs, _upd, \
125
+
_fenc_sta_mon_ofs, _fenc, _flags) { \
126
+
.id = _id, \
127
+
.name = _name, \
128
+
.mux_ofs = _mux_ofs, \
129
+
.set_ofs = _mux_set_ofs, \
130
+
.clr_ofs = _mux_clr_ofs, \
131
+
.hwv_sta_ofs = _hwv_sta_ofs, \
132
+
.hwv_set_ofs = _hwv_set_ofs, \
133
+
.hwv_clr_ofs = _hwv_clr_ofs, \
134
+
.upd_ofs = _upd_ofs, \
135
+
.fenc_sta_mon_ofs = _fenc_sta_mon_ofs, \
136
+
.mux_shift = _shift, \
137
+
.mux_width = _width, \
138
+
.gate_shift = _gate, \
139
+
.upd_shift = _upd, \
140
+
.fenc_shift = _fenc, \
141
+
.parent_names = _parents, \
142
+
.num_parents = ARRAY_SIZE(_parents), \
143
+
.flags = _flags, \
144
+
.ops = &mtk_mux_gate_hwv_fenc_clr_set_upd_ops, \
145
+
}
146
+
147
+
#define MUX_GATE_HWV_FENC_CLR_SET_UPD(_id, _name, _parents, \
148
+
_mux_ofs, _mux_set_ofs, _mux_clr_ofs, \
149
+
_hwv_sta_ofs, _hwv_set_ofs, _hwv_clr_ofs, \
150
+
_shift, _width, _gate, _upd_ofs, _upd, \
151
+
_fenc_sta_mon_ofs, _fenc) \
152
+
MUX_GATE_HWV_FENC_CLR_SET_UPD_FLAGS(_id, _name, _parents, \
153
+
_mux_ofs, _mux_set_ofs, _mux_clr_ofs, \
154
+
_hwv_sta_ofs, _hwv_set_ofs, _hwv_clr_ofs, \
155
+
_shift, _width, _gate, _upd_ofs, _upd, \
156
+
_fenc_sta_mon_ofs, _fenc, 0)
157
+
158
+
#define MUX_GATE_FENC_CLR_SET_UPD_FLAGS(_id, _name, _parents, _paridx, \
159
+
_num_parents, _mux_ofs, _mux_set_ofs, _mux_clr_ofs, \
160
+
_shift, _width, _gate, _upd_ofs, _upd, \
161
+
_fenc_sta_mon_ofs, _fenc, _flags) { \
162
+
.id = _id, \
163
+
.name = _name, \
164
+
.mux_ofs = _mux_ofs, \
165
+
.set_ofs = _mux_set_ofs, \
166
+
.clr_ofs = _mux_clr_ofs, \
167
+
.upd_ofs = _upd_ofs, \
168
+
.fenc_sta_mon_ofs = _fenc_sta_mon_ofs, \
169
+
.mux_shift = _shift, \
170
+
.mux_width = _width, \
171
+
.gate_shift = _gate, \
172
+
.upd_shift = _upd, \
173
+
.fenc_shift = _fenc, \
174
+
.parent_names = _parents, \
175
+
.parent_index = _paridx, \
176
+
.num_parents = _num_parents, \
177
+
.flags = _flags, \
178
+
.ops = &mtk_mux_gate_fenc_clr_set_upd_ops, \
179
+
}
180
+
181
+
#define MUX_GATE_FENC_CLR_SET_UPD(_id, _name, _parents, \
182
+
_mux_ofs, _mux_set_ofs, _mux_clr_ofs, \
183
+
_shift, _width, _gate, _upd_ofs, _upd, \
184
+
_fenc_sta_mon_ofs, _fenc) \
185
+
MUX_GATE_FENC_CLR_SET_UPD_FLAGS(_id, _name, _parents, \
186
+
NULL, ARRAY_SIZE(_parents), _mux_ofs, \
187
+
_mux_set_ofs, _mux_clr_ofs, _shift, \
188
+
_width, _gate, _upd_ofs, _upd, \
189
+
_fenc_sta_mon_ofs, _fenc, 0)
190
+
191
+
#define MUX_GATE_FENC_CLR_SET_UPD_INDEXED(_id, _name, _parents, _paridx, \
192
+
_mux_ofs, _mux_set_ofs, _mux_clr_ofs, \
193
+
_shift, _width, _gate, _upd_ofs, _upd, \
194
+
_fenc_sta_mon_ofs, _fenc) \
195
+
MUX_GATE_FENC_CLR_SET_UPD_FLAGS(_id, _name, _parents, _paridx, \
196
+
ARRAY_SIZE(_paridx), _mux_ofs, _mux_set_ofs, \
197
+
_mux_clr_ofs, _shift, _width, _gate, _upd_ofs, _upd, \
198
+
_fenc_sta_mon_ofs, _fenc, 0)
128
199
129
200
int mtk_clk_register_muxes(struct device *dev,
130
201
const struct mtk_mux *muxes,
+44
-1
drivers/clk/mediatek/clk-pll.c
+44
-1
drivers/clk/mediatek/clk-pll.c
···
37
37
return (readl(pll->en_addr) & BIT(pll->data->pll_en_bit)) != 0;
38
38
}
39
39
40
+
static int mtk_pll_fenc_is_prepared(struct clk_hw *hw)
41
+
{
42
+
struct mtk_clk_pll *pll = to_mtk_clk_pll(hw);
43
+
44
+
return !!(readl(pll->fenc_addr) & BIT(pll->data->fenc_sta_bit));
45
+
}
46
+
40
47
static unsigned long __mtk_pll_recalc_rate(struct mtk_clk_pll *pll, u32 fin,
41
48
u32 pcw, int postdiv)
42
49
{
···
281
274
writel(r, pll->pwr_addr);
282
275
}
283
276
277
+
static int mtk_pll_prepare_setclr(struct clk_hw *hw)
278
+
{
279
+
struct mtk_clk_pll *pll = to_mtk_clk_pll(hw);
280
+
281
+
writel(BIT(pll->data->pll_en_bit), pll->en_set_addr);
282
+
283
+
/* Wait 20us after enable for the PLL to stabilize */
284
+
udelay(20);
285
+
286
+
return 0;
287
+
}
288
+
289
+
static void mtk_pll_unprepare_setclr(struct clk_hw *hw)
290
+
{
291
+
struct mtk_clk_pll *pll = to_mtk_clk_pll(hw);
292
+
293
+
writel(BIT(pll->data->pll_en_bit), pll->en_clr_addr);
294
+
}
295
+
284
296
const struct clk_ops mtk_pll_ops = {
285
297
.is_prepared = mtk_pll_is_prepared,
286
298
.prepare = mtk_pll_prepare,
···
308
282
.round_rate = mtk_pll_round_rate,
309
283
.set_rate = mtk_pll_set_rate,
310
284
};
285
+
286
+
const struct clk_ops mtk_pll_fenc_clr_set_ops = {
287
+
.is_prepared = mtk_pll_fenc_is_prepared,
288
+
.prepare = mtk_pll_prepare_setclr,
289
+
.unprepare = mtk_pll_unprepare_setclr,
290
+
.recalc_rate = mtk_pll_recalc_rate,
291
+
.round_rate = mtk_pll_round_rate,
292
+
.set_rate = mtk_pll_set_rate,
293
+
};
294
+
EXPORT_SYMBOL_GPL(mtk_pll_fenc_clr_set_ops);
311
295
312
296
struct clk_hw *mtk_clk_register_pll_ops(struct mtk_clk_pll *pll,
313
297
const struct mtk_pll_data *data,
···
344
308
pll->en_addr = base + data->en_reg;
345
309
else
346
310
pll->en_addr = pll->base_addr + REG_CON0;
311
+
if (data->en_set_reg)
312
+
pll->en_set_addr = base + data->en_set_reg;
313
+
if (data->en_clr_reg)
314
+
pll->en_clr_addr = base + data->en_clr_reg;
347
315
pll->hw.init = &init;
348
316
pll->data = data;
317
+
318
+
pll->fenc_addr = base + data->fenc_sta_ofs;
349
319
350
320
init.name = data->name;
351
321
init.flags = (data->flags & PLL_AO) ? CLK_IS_CRITICAL : 0;
···
375
333
{
376
334
struct mtk_clk_pll *pll;
377
335
struct clk_hw *hw;
336
+
const struct clk_ops *pll_ops = data->ops ? data->ops : &mtk_pll_ops;
378
337
379
338
pll = kzalloc(sizeof(*pll), GFP_KERNEL);
380
339
if (!pll)
381
340
return ERR_PTR(-ENOMEM);
382
341
383
-
hw = mtk_clk_register_pll_ops(pll, data, base, &mtk_pll_ops);
342
+
hw = mtk_clk_register_pll_ops(pll, data, base, pll_ops);
384
343
if (IS_ERR(hw))
385
344
kfree(pll);
386
345
+8
drivers/clk/mediatek/clk-pll.h
+8
drivers/clk/mediatek/clk-pll.h
···
29
29
u32 reg;
30
30
u32 pwr_reg;
31
31
u32 en_mask;
32
+
u32 fenc_sta_ofs;
32
33
u32 pd_reg;
33
34
u32 tuner_reg;
34
35
u32 tuner_en_reg;
···
48
47
const struct mtk_pll_div_table *div_table;
49
48
const char *parent_name;
50
49
u32 en_reg;
50
+
u32 en_set_reg;
51
+
u32 en_clr_reg;
51
52
u8 pll_en_bit; /* Assume 0, indicates BIT(0) by default */
52
53
u8 pcw_chg_bit;
54
+
u8 fenc_sta_bit;
53
55
};
54
56
55
57
/*
···
72
68
void __iomem *pcw_addr;
73
69
void __iomem *pcw_chg_addr;
74
70
void __iomem *en_addr;
71
+
void __iomem *en_set_addr;
72
+
void __iomem *en_clr_addr;
73
+
void __iomem *fenc_addr;
75
74
const struct mtk_pll_data *data;
76
75
};
77
76
···
85
78
struct clk_hw_onecell_data *clk_data);
86
79
87
80
extern const struct clk_ops mtk_pll_ops;
81
+
extern const struct clk_ops mtk_pll_fenc_clr_set_ops;
88
82
89
83
static inline struct mtk_clk_pll *to_mtk_clk_pll(struct clk_hw *hw)
90
84
{
+10
drivers/clk/mmp/Kconfig
+10
drivers/clk/mmp/Kconfig
···
1
+
# SPDX-License-Identifier: GPL-2.0-only
2
+
3
+
config COMMON_CLK_PXA1908
4
+
bool "Clock driver for Marvell PXA1908"
5
+
depends on ARCH_MMP || COMPILE_TEST
6
+
depends on OF
7
+
default y if ARCH_MMP && ARM64
8
+
select AUXILIARY_BUS
9
+
help
10
+
This driver supports the Marvell PXA1908 SoC clocks.
+4
-1
drivers/clk/mmp/Makefile
+4
-1
drivers/clk/mmp/Makefile
···
11
11
obj-$(CONFIG_COMMON_CLK_MMP2) += clk-of-mmp2.o clk-pll.o pwr-island.o
12
12
obj-$(CONFIG_COMMON_CLK_MMP2_AUDIO) += clk-audio.o
13
13
14
-
obj-$(CONFIG_ARCH_MMP) += clk-of-pxa1928.o clk-pxa1908-apbc.o clk-pxa1908-apbcp.o clk-pxa1908-apmu.o clk-pxa1908-mpmu.o
14
+
obj-$(CONFIG_COMMON_CLK_PXA1908) += clk-pxa1908-apbc.o clk-pxa1908-apbcp.o \
15
+
clk-pxa1908-mpmu.o clk-pxa1908-apmu.o
16
+
17
+
obj-$(CONFIG_ARCH_MMP) += clk-of-pxa1928.o
+7
drivers/clk/mmp/clk-pxa1908-apmu.c
+7
drivers/clk/mmp/clk-pxa1908-apmu.c
···
1
1
// SPDX-License-Identifier: GPL-2.0-only
2
+
#include <linux/auxiliary_bus.h>
2
3
#include <linux/clk-provider.h>
3
4
#include <linux/module.h>
4
5
#include <linux/platform_device.h>
···
86
85
static int pxa1908_apmu_probe(struct platform_device *pdev)
87
86
{
88
87
struct pxa1908_clk_unit *pxa_unit;
88
+
struct auxiliary_device *adev;
89
89
90
90
pxa_unit = devm_kzalloc(&pdev->dev, sizeof(*pxa_unit), GFP_KERNEL);
91
91
if (!pxa_unit)
···
95
93
pxa_unit->base = devm_platform_ioremap_resource(pdev, 0);
96
94
if (IS_ERR(pxa_unit->base))
97
95
return PTR_ERR(pxa_unit->base);
96
+
97
+
adev = devm_auxiliary_device_create(&pdev->dev, "power", NULL);
98
+
if (IS_ERR(adev))
99
+
return dev_err_probe(&pdev->dev, PTR_ERR(adev),
100
+
"Failed to register power controller\n");
98
101
99
102
mmp_clk_init(pdev->dev.of_node, &pxa_unit->unit, APMU_NR_CLKS);
100
103
+18
-14
drivers/clk/xilinx/clk-xlnx-clock-wizard.c
+18
-14
drivers/clk/xilinx/clk-xlnx-clock-wizard.c
···
340
340
unsigned long parent_rate)
341
341
{
342
342
struct clk_wzrd_divider *divider = to_clk_wzrd_divider(hw);
343
-
u64 vco_freq, freq, diff, vcomin, vcomax;
343
+
u64 vco_freq, freq, diff, vcomin, vcomax, best_diff = -1ULL;
344
344
u32 m, d, o;
345
345
u32 mmin, mmax, dmin, dmax, omin, omax;
346
346
···
356
356
for (m = mmin; m <= mmax; m++) {
357
357
for (d = dmin; d <= dmax; d++) {
358
358
vco_freq = DIV_ROUND_CLOSEST((parent_rate * m), d);
359
-
if (vco_freq >= vcomin && vco_freq <= vcomax) {
360
-
for (o = omin; o <= omax; o++) {
361
-
freq = DIV_ROUND_CLOSEST_ULL(vco_freq, o);
362
-
diff = abs(freq - rate);
359
+
if (vco_freq < vcomin || vco_freq > vcomax)
360
+
continue;
363
361
364
-
if (diff < WZRD_MIN_ERR) {
365
-
divider->m = m;
366
-
divider->d = d;
367
-
divider->o = o;
368
-
return 0;
369
-
}
370
-
}
362
+
o = DIV_ROUND_CLOSEST_ULL(vco_freq, rate);
363
+
if (o < omin || o > omax)
364
+
continue;
365
+
freq = DIV_ROUND_CLOSEST_ULL(vco_freq, o);
366
+
diff = abs(freq - rate);
367
+
368
+
if (diff < best_diff) {
369
+
best_diff = diff;
370
+
divider->m = m;
371
+
divider->d = d;
372
+
divider->o = o;
373
+
if (!diff)
374
+
return 0;
371
375
}
372
376
}
373
377
}
374
-
return -EBUSY;
378
+
return 0;
375
379
}
376
380
377
381
static int clk_wzrd_get_divisors(struct clk_hw *hw, unsigned long rate,
···
1112
1108
(dev,
1113
1109
clkout_name, clk_name, 0,
1114
1110
clk_wzrd->base,
1115
-
(WZRD_CLK_CFG_REG(is_versal, 3) + i * 8),
1111
+
(WZRD_CLK_CFG_REG(is_versal, 2) + i * 8),
1116
1112
WZRD_CLKOUT_DIVIDE_SHIFT,
1117
1113
WZRD_CLKOUT_DIVIDE_WIDTH,
1118
1114
CLK_DIVIDER_ONE_BASED |
+36
include/dt-bindings/clock/loongson,ls2k-clk.h
+36
include/dt-bindings/clock/loongson,ls2k-clk.h
···
43
43
#define LOONGSON2_I2S_CLK 33
44
44
#define LOONGSON2_MISC_CLK 34
45
45
46
+
#define LS2K0300_CLK_STABLE 0
47
+
#define LS2K0300_NODE_PLL 1
48
+
#define LS2K0300_DDR_PLL 2
49
+
#define LS2K0300_PIX_PLL 3
50
+
#define LS2K0300_CLK_THSENS 4
51
+
#define LS2K0300_CLK_NODE_DIV 5
52
+
#define LS2K0300_CLK_NODE_PLL_GATE 6
53
+
#define LS2K0300_CLK_NODE_SCALE 7
54
+
#define LS2K0300_CLK_NODE_GATE 8
55
+
#define LS2K0300_CLK_GMAC_DIV 9
56
+
#define LS2K0300_CLK_GMAC_GATE 10
57
+
#define LS2K0300_CLK_I2S_DIV 11
58
+
#define LS2K0300_CLK_I2S_SCALE 12
59
+
#define LS2K0300_CLK_I2S_GATE 13
60
+
#define LS2K0300_CLK_DDR_DIV 14
61
+
#define LS2K0300_CLK_DDR_GATE 15
62
+
#define LS2K0300_CLK_NET_DIV 16
63
+
#define LS2K0300_CLK_NET_GATE 17
64
+
#define LS2K0300_CLK_DEV_DIV 18
65
+
#define LS2K0300_CLK_DEV_GATE 19
66
+
#define LS2K0300_CLK_PIX_DIV 20
67
+
#define LS2K0300_CLK_PIX_PLL_GATE 21
68
+
#define LS2K0300_CLK_PIX_SCALE 22
69
+
#define LS2K0300_CLK_PIX_GATE 23
70
+
#define LS2K0300_CLK_GMACBP_DIV 24
71
+
#define LS2K0300_CLK_GMACBP_GATE 25
72
+
#define LS2K0300_CLK_USB_SCALE 26
73
+
#define LS2K0300_CLK_USB_GATE 27
74
+
#define LS2K0300_CLK_APB_SCALE 28
75
+
#define LS2K0300_CLK_APB_GATE 29
76
+
#define LS2K0300_CLK_BOOT_SCALE 30
77
+
#define LS2K0300_CLK_BOOT_GATE 31
78
+
#define LS2K0300_CLK_SDIO_SCALE 32
79
+
#define LS2K0300_CLK_SDIO_GATE 33
80
+
#define LS2K0300_CLK_GMAC_IN 34
81
+
46
82
#endif
+803
include/dt-bindings/clock/mediatek,mt8196-clock.h
+803
include/dt-bindings/clock/mediatek,mt8196-clock.h
···
1
+
/* SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause */
2
+
/*
3
+
* Copyright (c) 2025 MediaTek Inc.
4
+
* Guangjie Song <guangjie.song@mediatek.com>
5
+
* Copyright (c) 2025 Collabora Ltd.
6
+
* Laura Nao <laura.nao@collabora.com>
7
+
*/
8
+
9
+
#ifndef _DT_BINDINGS_CLK_MT8196_H
10
+
#define _DT_BINDINGS_CLK_MT8196_H
11
+
12
+
/* CKSYS */
13
+
#define CLK_TOP_AXI 0
14
+
#define CLK_TOP_MEM_SUB 1
15
+
#define CLK_TOP_IO_NOC 2
16
+
#define CLK_TOP_P_AXI 3
17
+
#define CLK_TOP_UFS_PEXTP0_AXI 4
18
+
#define CLK_TOP_PEXTP1_USB_AXI 5
19
+
#define CLK_TOP_P_FMEM_SUB 6
20
+
#define CLK_TOP_PEXPT0_MEM_SUB 7
21
+
#define CLK_TOP_PEXTP1_USB_MEM_SUB 8
22
+
#define CLK_TOP_P_NOC 9
23
+
#define CLK_TOP_EMI_N 10
24
+
#define CLK_TOP_EMI_S 11
25
+
#define CLK_TOP_AP2CONN_HOST 12
26
+
#define CLK_TOP_ATB 13
27
+
#define CLK_TOP_CIRQ 14
28
+
#define CLK_TOP_PBUS_156M 15
29
+
#define CLK_TOP_EFUSE 16
30
+
#define CLK_TOP_MCL3GIC 17
31
+
#define CLK_TOP_MCINFRA 18
32
+
#define CLK_TOP_DSP 19
33
+
#define CLK_TOP_MFG_REF 20
34
+
#define CLK_TOP_MFG_EB 21
35
+
#define CLK_TOP_UART 22
36
+
#define CLK_TOP_SPI0_BCLK 23
37
+
#define CLK_TOP_SPI1_BCLK 24
38
+
#define CLK_TOP_SPI2_BCLK 25
39
+
#define CLK_TOP_SPI3_BCLK 26
40
+
#define CLK_TOP_SPI4_BCLK 27
41
+
#define CLK_TOP_SPI5_BCLK 28
42
+
#define CLK_TOP_SPI6_BCLK 29
43
+
#define CLK_TOP_SPI7_BCLK 30
44
+
#define CLK_TOP_MSDC30_1 31
45
+
#define CLK_TOP_MSDC30_2 32
46
+
#define CLK_TOP_DISP_PWM 33
47
+
#define CLK_TOP_USB_TOP_1P 34
48
+
#define CLK_TOP_USB_XHCI_1P 35
49
+
#define CLK_TOP_USB_FMCNT_P1 36
50
+
#define CLK_TOP_I2C_P 37
51
+
#define CLK_TOP_I2C_EAST 38
52
+
#define CLK_TOP_I2C_WEST 39
53
+
#define CLK_TOP_I2C_NORTH 40
54
+
#define CLK_TOP_AES_UFSFDE 41
55
+
#define CLK_TOP_UFS 42
56
+
#define CLK_TOP_AUD_1 43
57
+
#define CLK_TOP_AUD_2 44
58
+
#define CLK_TOP_ADSP 45
59
+
#define CLK_TOP_ADSP_UARTHUB_B 46
60
+
#define CLK_TOP_DPMAIF_MAIN 47
61
+
#define CLK_TOP_PWM 48
62
+
#define CLK_TOP_MCUPM 49
63
+
#define CLK_TOP_IPSEAST 50
64
+
#define CLK_TOP_TL 51
65
+
#define CLK_TOP_TL_P1 52
66
+
#define CLK_TOP_TL_P2 53
67
+
#define CLK_TOP_EMI_INTERFACE_546 54
68
+
#define CLK_TOP_SDF 55
69
+
#define CLK_TOP_UARTHUB_BCLK 56
70
+
#define CLK_TOP_DPSW_CMP_26M 57
71
+
#define CLK_TOP_SMAP 58
72
+
#define CLK_TOP_SSR_PKA 59
73
+
#define CLK_TOP_SSR_DMA 60
74
+
#define CLK_TOP_SSR_KDF 61
75
+
#define CLK_TOP_SSR_RNG 62
76
+
#define CLK_TOP_SPU0 63
77
+
#define CLK_TOP_SPU1 64
78
+
#define CLK_TOP_DXCC 65
79
+
#define CLK_TOP_APLL_I2SIN0 66
80
+
#define CLK_TOP_APLL_I2SIN1 67
81
+
#define CLK_TOP_APLL_I2SIN2 68
82
+
#define CLK_TOP_APLL_I2SIN3 69
83
+
#define CLK_TOP_APLL_I2SIN4 70
84
+
#define CLK_TOP_APLL_I2SIN6 71
85
+
#define CLK_TOP_APLL_I2SOUT0 72
86
+
#define CLK_TOP_APLL_I2SOUT1 73
87
+
#define CLK_TOP_APLL_I2SOUT2 74
88
+
#define CLK_TOP_APLL_I2SOUT3 75
89
+
#define CLK_TOP_APLL_I2SOUT4 76
90
+
#define CLK_TOP_APLL_I2SOUT6 77
91
+
#define CLK_TOP_APLL_FMI2S 78
92
+
#define CLK_TOP_APLL_TDMOUT 79
93
+
#define CLK_TOP_APLL12_DIV_TDMOUT_M 80
94
+
#define CLK_TOP_APLL12_DIV_TDMOUT_B 81
95
+
#define CLK_TOP_MAINPLL_D3 82
96
+
#define CLK_TOP_MAINPLL_D4 83
97
+
#define CLK_TOP_MAINPLL_D4_D2 84
98
+
#define CLK_TOP_MAINPLL_D4_D4 85
99
+
#define CLK_TOP_MAINPLL_D4_D8 86
100
+
#define CLK_TOP_MAINPLL_D5 87
101
+
#define CLK_TOP_MAINPLL_D5_D2 88
102
+
#define CLK_TOP_MAINPLL_D5_D4 89
103
+
#define CLK_TOP_MAINPLL_D5_D8 90
104
+
#define CLK_TOP_MAINPLL_D6 91
105
+
#define CLK_TOP_MAINPLL_D6_D2 92
106
+
#define CLK_TOP_MAINPLL_D7 93
107
+
#define CLK_TOP_MAINPLL_D7_D2 94
108
+
#define CLK_TOP_MAINPLL_D7_D4 95
109
+
#define CLK_TOP_MAINPLL_D7_D8 96
110
+
#define CLK_TOP_MAINPLL_D9 97
111
+
#define CLK_TOP_UNIVPLL_D4 98
112
+
#define CLK_TOP_UNIVPLL_D4_D2 99
113
+
#define CLK_TOP_UNIVPLL_D4_D4 100
114
+
#define CLK_TOP_UNIVPLL_D4_D8 101
115
+
#define CLK_TOP_UNIVPLL_D5 102
116
+
#define CLK_TOP_UNIVPLL_D5_D2 103
117
+
#define CLK_TOP_UNIVPLL_D5_D4 104
118
+
#define CLK_TOP_UNIVPLL_D6 105
119
+
#define CLK_TOP_UNIVPLL_D6_D2 106
120
+
#define CLK_TOP_UNIVPLL_D6_D4 107
121
+
#define CLK_TOP_UNIVPLL_D6_D8 108
122
+
#define CLK_TOP_UNIVPLL_D6_D16 109
123
+
#define CLK_TOP_UNIVPLL_192M 110
124
+
#define CLK_TOP_UNIVPLL_192M_D4 111
125
+
#define CLK_TOP_UNIVPLL_192M_D8 112
126
+
#define CLK_TOP_UNIVPLL_192M_D16 113
127
+
#define CLK_TOP_UNIVPLL_192M_D32 114
128
+
#define CLK_TOP_UNIVPLL_192M_D10 115
129
+
#define CLK_TOP_TVDPLL1_D2 116
130
+
#define CLK_TOP_MSDCPLL_D2 117
131
+
#define CLK_TOP_OSC_D2 118
132
+
#define CLK_TOP_OSC_D3 119
133
+
#define CLK_TOP_OSC_D4 120
134
+
#define CLK_TOP_OSC_D5 121
135
+
#define CLK_TOP_OSC_D7 122
136
+
#define CLK_TOP_OSC_D8 123
137
+
#define CLK_TOP_OSC_D10 124
138
+
#define CLK_TOP_OSC_D14 125
139
+
#define CLK_TOP_OSC_D20 126
140
+
#define CLK_TOP_OSC_D32 127
141
+
#define CLK_TOP_OSC_D40 128
142
+
#define CLK_TOP_SFLASH 129
143
+
144
+
/* APMIXEDSYS */
145
+
#define CLK_APMIXED_MAINPLL 0
146
+
#define CLK_APMIXED_UNIVPLL 1
147
+
#define CLK_APMIXED_MSDCPLL 2
148
+
#define CLK_APMIXED_ADSPPLL 3
149
+
#define CLK_APMIXED_EMIPLL 4
150
+
#define CLK_APMIXED_EMIPLL2 5
151
+
#define CLK_APMIXED_NET1PLL 6
152
+
#define CLK_APMIXED_SGMIIPLL 7
153
+
154
+
/* CKSYS_GP2 */
155
+
#define CLK_TOP2_SENINF0 0
156
+
#define CLK_TOP2_SENINF1 1
157
+
#define CLK_TOP2_SENINF2 2
158
+
#define CLK_TOP2_SENINF3 3
159
+
#define CLK_TOP2_SENINF4 4
160
+
#define CLK_TOP2_SENINF5 5
161
+
#define CLK_TOP2_IMG1 6
162
+
#define CLK_TOP2_IPE 7
163
+
#define CLK_TOP2_CAM 8
164
+
#define CLK_TOP2_CAMTM 9
165
+
#define CLK_TOP2_DPE 10
166
+
#define CLK_TOP2_VDEC 11
167
+
#define CLK_TOP2_CCUSYS 12
168
+
#define CLK_TOP2_CCUTM 13
169
+
#define CLK_TOP2_VENC 14
170
+
#define CLK_TOP2_DP1 15
171
+
#define CLK_TOP2_DP0 16
172
+
#define CLK_TOP2_DISP 17
173
+
#define CLK_TOP2_MDP 18
174
+
#define CLK_TOP2_MMINFRA 19
175
+
#define CLK_TOP2_MMINFRA_SNOC 20
176
+
#define CLK_TOP2_MMUP 21
177
+
#define CLK_TOP2_MMINFRA_AO 22
178
+
#define CLK_TOP2_MAINPLL2_D2 23
179
+
#define CLK_TOP2_MAINPLL2_D3 24
180
+
#define CLK_TOP2_MAINPLL2_D4 25
181
+
#define CLK_TOP2_MAINPLL2_D4_D2 26
182
+
#define CLK_TOP2_MAINPLL2_D4_D4 27
183
+
#define CLK_TOP2_MAINPLL2_D5 28
184
+
#define CLK_TOP2_MAINPLL2_D5_D2 29
185
+
#define CLK_TOP2_MAINPLL2_D6 30
186
+
#define CLK_TOP2_MAINPLL2_D6_D2 31
187
+
#define CLK_TOP2_MAINPLL2_D7 32
188
+
#define CLK_TOP2_MAINPLL2_D7_D2 33
189
+
#define CLK_TOP2_MAINPLL2_D9 34
190
+
#define CLK_TOP2_UNIVPLL2_D3 35
191
+
#define CLK_TOP2_UNIVPLL2_D4 36
192
+
#define CLK_TOP2_UNIVPLL2_D4_D2 37
193
+
#define CLK_TOP2_UNIVPLL2_D5 38
194
+
#define CLK_TOP2_UNIVPLL2_D5_D2 39
195
+
#define CLK_TOP2_UNIVPLL2_D6 40
196
+
#define CLK_TOP2_UNIVPLL2_D6_D2 41
197
+
#define CLK_TOP2_UNIVPLL2_D6_D4 42
198
+
#define CLK_TOP2_UNIVPLL2_D7 43
199
+
#define CLK_TOP2_IMGPLL_D2 44
200
+
#define CLK_TOP2_IMGPLL_D4 45
201
+
#define CLK_TOP2_IMGPLL_D5 46
202
+
#define CLK_TOP2_IMGPLL_D5_D2 47
203
+
#define CLK_TOP2_MMPLL2_D3 48
204
+
#define CLK_TOP2_MMPLL2_D4 49
205
+
#define CLK_TOP2_MMPLL2_D4_D2 50
206
+
#define CLK_TOP2_MMPLL2_D5 51
207
+
#define CLK_TOP2_MMPLL2_D5_D2 52
208
+
#define CLK_TOP2_MMPLL2_D6 53
209
+
#define CLK_TOP2_MMPLL2_D6_D2 54
210
+
#define CLK_TOP2_MMPLL2_D7 55
211
+
#define CLK_TOP2_MMPLL2_D9 56
212
+
#define CLK_TOP2_TVDPLL1_D4 57
213
+
#define CLK_TOP2_TVDPLL1_D8 58
214
+
#define CLK_TOP2_TVDPLL1_D16 59
215
+
#define CLK_TOP2_TVDPLL2_D2 60
216
+
#define CLK_TOP2_TVDPLL2_D4 61
217
+
#define CLK_TOP2_TVDPLL2_D8 62
218
+
#define CLK_TOP2_TVDPLL2_D16 63
219
+
#define CLK_TOP2_DVO 64
220
+
#define CLK_TOP2_DVO_FAVT 65
221
+
#define CLK_TOP2_TVDPLL3_D2 66
222
+
#define CLK_TOP2_TVDPLL3_D4 67
223
+
#define CLK_TOP2_TVDPLL3_D8 68
224
+
#define CLK_TOP2_TVDPLL3_D16 69
225
+
226
+
/* APMIXEDSYS_GP2 */
227
+
#define CLK_APMIXED2_MAINPLL2 0
228
+
#define CLK_APMIXED2_UNIVPLL2 1
229
+
#define CLK_APMIXED2_MMPLL2 2
230
+
#define CLK_APMIXED2_IMGPLL 3
231
+
#define CLK_APMIXED2_TVDPLL1 4
232
+
#define CLK_APMIXED2_TVDPLL2 5
233
+
#define CLK_APMIXED2_TVDPLL3 6
234
+
235
+
/* IMP_IIC_WRAP_E */
236
+
#define CLK_IMPE_I2C5 0
237
+
238
+
/* IMP_IIC_WRAP_W */
239
+
#define CLK_IMPW_I2C0 0
240
+
#define CLK_IMPW_I2C3 1
241
+
#define CLK_IMPW_I2C6 2
242
+
#define CLK_IMPW_I2C10 3
243
+
244
+
/* IMP_IIC_WRAP_N */
245
+
#define CLK_IMPN_I2C1 0
246
+
#define CLK_IMPN_I2C2 1
247
+
#define CLK_IMPN_I2C4 2
248
+
#define CLK_IMPN_I2C7 3
249
+
#define CLK_IMPN_I2C8 4
250
+
#define CLK_IMPN_I2C9 5
251
+
252
+
/* IMP_IIC_WRAP_C */
253
+
#define CLK_IMPC_I2C11 0
254
+
#define CLK_IMPC_I2C12 1
255
+
#define CLK_IMPC_I2C13 2
256
+
#define CLK_IMPC_I2C14 3
257
+
258
+
/* PERICFG_AO */
259
+
#define CLK_PERI_AO_UART0_BCLK 0
260
+
#define CLK_PERI_AO_UART1_BCLK 1
261
+
#define CLK_PERI_AO_UART2_BCLK 2
262
+
#define CLK_PERI_AO_UART3_BCLK 3
263
+
#define CLK_PERI_AO_UART4_BCLK 4
264
+
#define CLK_PERI_AO_UART5_BCLK 5
265
+
#define CLK_PERI_AO_PWM_X16W_HCLK 6
266
+
#define CLK_PERI_AO_PWM_X16W_BCLK 7
267
+
#define CLK_PERI_AO_PWM_PWM_BCLK0 8
268
+
#define CLK_PERI_AO_PWM_PWM_BCLK1 9
269
+
#define CLK_PERI_AO_PWM_PWM_BCLK2 10
270
+
#define CLK_PERI_AO_PWM_PWM_BCLK3 11
271
+
#define CLK_PERI_AO_SPI0_BCLK 12
272
+
#define CLK_PERI_AO_SPI1_BCLK 13
273
+
#define CLK_PERI_AO_SPI2_BCLK 14
274
+
#define CLK_PERI_AO_SPI3_BCLK 15
275
+
#define CLK_PERI_AO_SPI4_BCLK 16
276
+
#define CLK_PERI_AO_SPI5_BCLK 17
277
+
#define CLK_PERI_AO_SPI6_BCLK 18
278
+
#define CLK_PERI_AO_SPI7_BCLK 19
279
+
#define CLK_PERI_AO_AP_DMA_X32W_BCLK 20
280
+
#define CLK_PERI_AO_MSDC1_MSDC_SRC 21
281
+
#define CLK_PERI_AO_MSDC1_HCLK 22
282
+
#define CLK_PERI_AO_MSDC1_AXI 23
283
+
#define CLK_PERI_AO_MSDC1_HCLK_WRAP 24
284
+
#define CLK_PERI_AO_MSDC2_MSDC_SRC 25
285
+
#define CLK_PERI_AO_MSDC2_HCLK 26
286
+
#define CLK_PERI_AO_MSDC2_AXI 27
287
+
#define CLK_PERI_AO_MSDC2_HCLK_WRAP 28
288
+
#define CLK_PERI_AO_FLASHIF_FLASH 29
289
+
#define CLK_PERI_AO_FLASHIF_27M 30
290
+
#define CLK_PERI_AO_FLASHIF_DRAM 31
291
+
#define CLK_PERI_AO_FLASHIF_AXI 32
292
+
#define CLK_PERI_AO_FLASHIF_BCLK 33
293
+
294
+
/* UFSCFG_AO */
295
+
#define CLK_UFSAO_UNIPRO_TX_SYM 0
296
+
#define CLK_UFSAO_UNIPRO_RX_SYM0 1
297
+
#define CLK_UFSAO_UNIPRO_RX_SYM1 2
298
+
#define CLK_UFSAO_UNIPRO_SYS 3
299
+
#define CLK_UFSAO_UNIPRO_SAP 4
300
+
#define CLK_UFSAO_PHY_SAP 5
301
+
#define CLK_UFSAO_UFSHCI_UFS 6
302
+
#define CLK_UFSAO_UFSHCI_AES 7
303
+
304
+
/* PEXTP0CFG_AO */
305
+
#define CLK_PEXT_PEXTP_MAC_P0_TL 0
306
+
#define CLK_PEXT_PEXTP_MAC_P0_REF 1
307
+
#define CLK_PEXT_PEXTP_PHY_P0_MCU_BUS 2
308
+
#define CLK_PEXT_PEXTP_PHY_P0_PEXTP_REF 3
309
+
#define CLK_PEXT_PEXTP_MAC_P0_AXI_250 4
310
+
#define CLK_PEXT_PEXTP_MAC_P0_AHB_APB 5
311
+
#define CLK_PEXT_PEXTP_MAC_P0_PL_P 6
312
+
#define CLK_PEXT_PEXTP_VLP_AO_P0_LP 7
313
+
314
+
/* PEXTP1CFG_AO */
315
+
#define CLK_PEXT1_PEXTP_MAC_P1_TL 0
316
+
#define CLK_PEXT1_PEXTP_MAC_P1_REF 1
317
+
#define CLK_PEXT1_PEXTP_MAC_P2_TL 2
318
+
#define CLK_PEXT1_PEXTP_MAC_P2_REF 3
319
+
#define CLK_PEXT1_PEXTP_PHY_P1_MCU_BUS 4
320
+
#define CLK_PEXT1_PEXTP_PHY_P1_PEXTP_REF 5
321
+
#define CLK_PEXT1_PEXTP_PHY_P2_MCU_BUS 6
322
+
#define CLK_PEXT1_PEXTP_PHY_P2_PEXTP_REF 7
323
+
#define CLK_PEXT1_PEXTP_MAC_P1_AXI_250 8
324
+
#define CLK_PEXT1_PEXTP_MAC_P1_AHB_APB 9
325
+
#define CLK_PEXT1_PEXTP_MAC_P1_PL_P 10
326
+
#define CLK_PEXT1_PEXTP_MAC_P2_AXI_250 11
327
+
#define CLK_PEXT1_PEXTP_MAC_P2_AHB_APB 12
328
+
#define CLK_PEXT1_PEXTP_MAC_P2_PL_P 13
329
+
#define CLK_PEXT1_PEXTP_VLP_AO_P1_LP 14
330
+
#define CLK_PEXT1_PEXTP_VLP_AO_P2_LP 15
331
+
332
+
/* VLP_CKSYS */
333
+
#define CLK_VLP_APLL1 0
334
+
#define CLK_VLP_APLL2 1
335
+
#define CLK_VLP_SCP 2
336
+
#define CLK_VLP_SCP_SPI 3
337
+
#define CLK_VLP_SCP_IIC 4
338
+
#define CLK_VLP_SCP_IIC_HS 5
339
+
#define CLK_VLP_PWRAP_ULPOSC 6
340
+
#define CLK_VLP_SPMI_M_TIA_32K 7
341
+
#define CLK_VLP_APXGPT_26M_B 8
342
+
#define CLK_VLP_DPSW 9
343
+
#define CLK_VLP_DPSW_CENTRAL 10
344
+
#define CLK_VLP_SPMI_M_MST 11
345
+
#define CLK_VLP_DVFSRC 12
346
+
#define CLK_VLP_PWM_VLP 13
347
+
#define CLK_VLP_AXI_VLP 14
348
+
#define CLK_VLP_SYSTIMER_26M 15
349
+
#define CLK_VLP_SSPM 16
350
+
#define CLK_VLP_SRCK 17
351
+
#define CLK_VLP_CAMTG0 18
352
+
#define CLK_VLP_CAMTG1 19
353
+
#define CLK_VLP_CAMTG2 20
354
+
#define CLK_VLP_CAMTG3 21
355
+
#define CLK_VLP_CAMTG4 22
356
+
#define CLK_VLP_CAMTG5 23
357
+
#define CLK_VLP_CAMTG6 24
358
+
#define CLK_VLP_CAMTG7 25
359
+
#define CLK_VLP_SSPM_26M 26
360
+
#define CLK_VLP_ULPOSC_SSPM 27
361
+
#define CLK_VLP_VLP_PBUS_26M 28
362
+
#define CLK_VLP_DEBUG_ERR_FLAG 29
363
+
#define CLK_VLP_DPMSRDMA 30
364
+
#define CLK_VLP_VLP_PBUS_156M 31
365
+
#define CLK_VLP_SPM 32
366
+
#define CLK_VLP_MMINFRA 33
367
+
#define CLK_VLP_USB_TOP 34
368
+
#define CLK_VLP_USB_XHCI 35
369
+
#define CLK_VLP_NOC_VLP 36
370
+
#define CLK_VLP_AUDIO_H 37
371
+
#define CLK_VLP_AUD_ENGEN1 38
372
+
#define CLK_VLP_AUD_ENGEN2 39
373
+
#define CLK_VLP_AUD_INTBUS 40
374
+
#define CLK_VLP_SPVLP_26M 41
375
+
#define CLK_VLP_SPU0_VLP 42
376
+
#define CLK_VLP_SPU1_VLP 43
377
+
#define CLK_VLP_CLK26M 44
378
+
#define CLK_VLP_APLL1_D4 45
379
+
#define CLK_VLP_APLL1_D8 46
380
+
#define CLK_VLP_APLL2_D4 47
381
+
#define CLK_VLP_APLL2_D8 48
382
+
383
+
/* DISPSYS_CONFIG */
384
+
#define CLK_MM_CONFIG 0
385
+
#define CLK_MM_DISP_MUTEX0 1
386
+
#define CLK_MM_DISP_AAL0 2
387
+
#define CLK_MM_DISP_AAL1 3
388
+
#define CLK_MM_DISP_C3D0 4
389
+
#define CLK_MM_DISP_C3D1 5
390
+
#define CLK_MM_DISP_C3D2 6
391
+
#define CLK_MM_DISP_C3D3 7
392
+
#define CLK_MM_DISP_CCORR0 8
393
+
#define CLK_MM_DISP_CCORR1 9
394
+
#define CLK_MM_DISP_CCORR2 10
395
+
#define CLK_MM_DISP_CCORR3 11
396
+
#define CLK_MM_DISP_CHIST0 12
397
+
#define CLK_MM_DISP_CHIST1 13
398
+
#define CLK_MM_DISP_COLOR0 14
399
+
#define CLK_MM_DISP_COLOR1 15
400
+
#define CLK_MM_DISP_DITHER0 16
401
+
#define CLK_MM_DISP_DITHER1 17
402
+
#define CLK_MM_DISP_DLI_ASYNC0 18
403
+
#define CLK_MM_DISP_DLI_ASYNC1 19
404
+
#define CLK_MM_DISP_DLI_ASYNC2 20
405
+
#define CLK_MM_DISP_DLI_ASYNC3 21
406
+
#define CLK_MM_DISP_DLI_ASYNC4 22
407
+
#define CLK_MM_DISP_DLI_ASYNC5 23
408
+
#define CLK_MM_DISP_DLI_ASYNC6 24
409
+
#define CLK_MM_DISP_DLI_ASYNC7 25
410
+
#define CLK_MM_DISP_DLI_ASYNC8 26
411
+
#define CLK_MM_DISP_DLI_ASYNC9 27
412
+
#define CLK_MM_DISP_DLI_ASYNC10 28
413
+
#define CLK_MM_DISP_DLI_ASYNC11 29
414
+
#define CLK_MM_DISP_DLI_ASYNC12 30
415
+
#define CLK_MM_DISP_DLI_ASYNC13 31
416
+
#define CLK_MM_DISP_DLI_ASYNC14 32
417
+
#define CLK_MM_DISP_DLI_ASYNC15 33
418
+
#define CLK_MM_DISP_DLO_ASYNC0 34
419
+
#define CLK_MM_DISP_DLO_ASYNC1 35
420
+
#define CLK_MM_DISP_DLO_ASYNC2 36
421
+
#define CLK_MM_DISP_DLO_ASYNC3 37
422
+
#define CLK_MM_DISP_DLO_ASYNC4 38
423
+
#define CLK_MM_DISP_DLO_ASYNC5 39
424
+
#define CLK_MM_DISP_DLO_ASYNC6 40
425
+
#define CLK_MM_DISP_DLO_ASYNC7 41
426
+
#define CLK_MM_DISP_DLO_ASYNC8 42
427
+
#define CLK_MM_DISP_GAMMA0 43
428
+
#define CLK_MM_DISP_GAMMA1 44
429
+
#define CLK_MM_MDP_AAL0 45
430
+
#define CLK_MM_MDP_AAL1 46
431
+
#define CLK_MM_MDP_RDMA0 47
432
+
#define CLK_MM_DISP_POSTMASK0 48
433
+
#define CLK_MM_DISP_POSTMASK1 49
434
+
#define CLK_MM_MDP_RSZ0 50
435
+
#define CLK_MM_MDP_RSZ1 51
436
+
#define CLK_MM_DISP_SPR0 52
437
+
#define CLK_MM_DISP_TDSHP0 53
438
+
#define CLK_MM_DISP_TDSHP1 54
439
+
#define CLK_MM_DISP_WDMA0 55
440
+
#define CLK_MM_DISP_Y2R0 56
441
+
#define CLK_MM_SMI_SUB_COMM0 57
442
+
#define CLK_MM_DISP_FAKE_ENG0 58
443
+
444
+
/* DISPSYS1_CONFIG */
445
+
#define CLK_MM1_DISPSYS1_CONFIG 0
446
+
#define CLK_MM1_DISPSYS1_S_CONFIG 1
447
+
#define CLK_MM1_DISP_MUTEX0 2
448
+
#define CLK_MM1_DISP_DLI_ASYNC20 3
449
+
#define CLK_MM1_DISP_DLI_ASYNC21 4
450
+
#define CLK_MM1_DISP_DLI_ASYNC22 5
451
+
#define CLK_MM1_DISP_DLI_ASYNC23 6
452
+
#define CLK_MM1_DISP_DLI_ASYNC24 7
453
+
#define CLK_MM1_DISP_DLI_ASYNC25 8
454
+
#define CLK_MM1_DISP_DLI_ASYNC26 9
455
+
#define CLK_MM1_DISP_DLI_ASYNC27 10
456
+
#define CLK_MM1_DISP_DLI_ASYNC28 11
457
+
#define CLK_MM1_DISP_RELAY0 12
458
+
#define CLK_MM1_DISP_RELAY1 13
459
+
#define CLK_MM1_DISP_RELAY2 14
460
+
#define CLK_MM1_DISP_RELAY3 15
461
+
#define CLK_MM1_DISP_DP_INTF0 16
462
+
#define CLK_MM1_DISP_DP_INTF1 17
463
+
#define CLK_MM1_DISP_DSC_WRAP0 18
464
+
#define CLK_MM1_DISP_DSC_WRAP1 19
465
+
#define CLK_MM1_DISP_DSC_WRAP2 20
466
+
#define CLK_MM1_DISP_DSC_WRAP3 21
467
+
#define CLK_MM1_DISP_DSI0 22
468
+
#define CLK_MM1_DISP_DSI1 23
469
+
#define CLK_MM1_DISP_DSI2 24
470
+
#define CLK_MM1_DISP_DVO0 25
471
+
#define CLK_MM1_DISP_GDMA0 26
472
+
#define CLK_MM1_DISP_MERGE0 27
473
+
#define CLK_MM1_DISP_MERGE1 28
474
+
#define CLK_MM1_DISP_MERGE2 29
475
+
#define CLK_MM1_DISP_ODDMR0 30
476
+
#define CLK_MM1_DISP_POSTALIGN0 31
477
+
#define CLK_MM1_DISP_DITHER2 32
478
+
#define CLK_MM1_DISP_R2Y0 33
479
+
#define CLK_MM1_DISP_SPLITTER0 34
480
+
#define CLK_MM1_DISP_SPLITTER1 35
481
+
#define CLK_MM1_DISP_SPLITTER2 36
482
+
#define CLK_MM1_DISP_SPLITTER3 37
483
+
#define CLK_MM1_DISP_VDCM0 38
484
+
#define CLK_MM1_DISP_WDMA1 39
485
+
#define CLK_MM1_DISP_WDMA2 40
486
+
#define CLK_MM1_DISP_WDMA3 41
487
+
#define CLK_MM1_DISP_WDMA4 42
488
+
#define CLK_MM1_MDP_RDMA1 43
489
+
#define CLK_MM1_SMI_LARB0 44
490
+
#define CLK_MM1_MOD1 45
491
+
#define CLK_MM1_MOD2 46
492
+
#define CLK_MM1_MOD3 47
493
+
#define CLK_MM1_MOD4 48
494
+
#define CLK_MM1_MOD5 49
495
+
#define CLK_MM1_MOD6 50
496
+
#define CLK_MM1_CG0 51
497
+
#define CLK_MM1_CG1 52
498
+
#define CLK_MM1_CG2 53
499
+
#define CLK_MM1_CG3 54
500
+
#define CLK_MM1_CG4 55
501
+
#define CLK_MM1_CG5 56
502
+
#define CLK_MM1_CG6 57
503
+
#define CLK_MM1_CG7 58
504
+
#define CLK_MM1_F26M 59
505
+
506
+
/* OVLSYS_CONFIG */
507
+
#define CLK_OVLSYS_CONFIG 0
508
+
#define CLK_OVL_FAKE_ENG0 1
509
+
#define CLK_OVL_FAKE_ENG1 2
510
+
#define CLK_OVL_MUTEX0 3
511
+
#define CLK_OVL_EXDMA0 4
512
+
#define CLK_OVL_EXDMA1 5
513
+
#define CLK_OVL_EXDMA2 6
514
+
#define CLK_OVL_EXDMA3 7
515
+
#define CLK_OVL_EXDMA4 8
516
+
#define CLK_OVL_EXDMA5 9
517
+
#define CLK_OVL_EXDMA6 10
518
+
#define CLK_OVL_EXDMA7 11
519
+
#define CLK_OVL_EXDMA8 12
520
+
#define CLK_OVL_EXDMA9 13
521
+
#define CLK_OVL_BLENDER0 14
522
+
#define CLK_OVL_BLENDER1 15
523
+
#define CLK_OVL_BLENDER2 16
524
+
#define CLK_OVL_BLENDER3 17
525
+
#define CLK_OVL_BLENDER4 18
526
+
#define CLK_OVL_BLENDER5 19
527
+
#define CLK_OVL_BLENDER6 20
528
+
#define CLK_OVL_BLENDER7 21
529
+
#define CLK_OVL_BLENDER8 22
530
+
#define CLK_OVL_BLENDER9 23
531
+
#define CLK_OVL_OUTPROC0 24
532
+
#define CLK_OVL_OUTPROC1 25
533
+
#define CLK_OVL_OUTPROC2 26
534
+
#define CLK_OVL_OUTPROC3 27
535
+
#define CLK_OVL_OUTPROC4 28
536
+
#define CLK_OVL_OUTPROC5 29
537
+
#define CLK_OVL_MDP_RSZ0 30
538
+
#define CLK_OVL_MDP_RSZ1 31
539
+
#define CLK_OVL_DISP_WDMA0 32
540
+
#define CLK_OVL_DISP_WDMA1 33
541
+
#define CLK_OVL_UFBC_WDMA0 34
542
+
#define CLK_OVL_MDP_RDMA0 35
543
+
#define CLK_OVL_MDP_RDMA1 36
544
+
#define CLK_OVL_BWM0 37
545
+
#define CLK_OVL_DLI0 38
546
+
#define CLK_OVL_DLI1 39
547
+
#define CLK_OVL_DLI2 40
548
+
#define CLK_OVL_DLI3 41
549
+
#define CLK_OVL_DLI4 42
550
+
#define CLK_OVL_DLI5 43
551
+
#define CLK_OVL_DLI6 44
552
+
#define CLK_OVL_DLI7 45
553
+
#define CLK_OVL_DLI8 46
554
+
#define CLK_OVL_DLO0 47
555
+
#define CLK_OVL_DLO1 48
556
+
#define CLK_OVL_DLO2 49
557
+
#define CLK_OVL_DLO3 50
558
+
#define CLK_OVL_DLO4 51
559
+
#define CLK_OVL_DLO5 52
560
+
#define CLK_OVL_DLO6 53
561
+
#define CLK_OVL_DLO7 54
562
+
#define CLK_OVL_DLO8 55
563
+
#define CLK_OVL_DLO9 56
564
+
#define CLK_OVL_DLO10 57
565
+
#define CLK_OVL_DLO11 58
566
+
#define CLK_OVL_DLO12 59
567
+
#define CLK_OVLSYS_RELAY0 60
568
+
#define CLK_OVL_INLINEROT0 61
569
+
#define CLK_OVL_SMI 62
570
+
#define CLK_OVL_SMI_SMI 63
571
+
572
+
573
+
/* OVLSYS1_CONFIG */
574
+
#define CLK_OVL1_OVLSYS_CONFIG 0
575
+
#define CLK_OVL1_OVL_FAKE_ENG0 1
576
+
#define CLK_OVL1_OVL_FAKE_ENG1 2
577
+
#define CLK_OVL1_OVL_MUTEX0 3
578
+
#define CLK_OVL1_OVL_EXDMA0 4
579
+
#define CLK_OVL1_OVL_EXDMA1 5
580
+
#define CLK_OVL1_OVL_EXDMA2 6
581
+
#define CLK_OVL1_OVL_EXDMA3 7
582
+
#define CLK_OVL1_OVL_EXDMA4 8
583
+
#define CLK_OVL1_OVL_EXDMA5 9
584
+
#define CLK_OVL1_OVL_EXDMA6 10
585
+
#define CLK_OVL1_OVL_EXDMA7 11
586
+
#define CLK_OVL1_OVL_EXDMA8 12
587
+
#define CLK_OVL1_OVL_EXDMA9 13
588
+
#define CLK_OVL1_OVL_BLENDER0 14
589
+
#define CLK_OVL1_OVL_BLENDER1 15
590
+
#define CLK_OVL1_OVL_BLENDER2 16
591
+
#define CLK_OVL1_OVL_BLENDER3 17
592
+
#define CLK_OVL1_OVL_BLENDER4 18
593
+
#define CLK_OVL1_OVL_BLENDER5 19
594
+
#define CLK_OVL1_OVL_BLENDER6 20
595
+
#define CLK_OVL1_OVL_BLENDER7 21
596
+
#define CLK_OVL1_OVL_BLENDER8 22
597
+
#define CLK_OVL1_OVL_BLENDER9 23
598
+
#define CLK_OVL1_OVL_OUTPROC0 24
599
+
#define CLK_OVL1_OVL_OUTPROC1 25
600
+
#define CLK_OVL1_OVL_OUTPROC2 26
601
+
#define CLK_OVL1_OVL_OUTPROC3 27
602
+
#define CLK_OVL1_OVL_OUTPROC4 28
603
+
#define CLK_OVL1_OVL_OUTPROC5 29
604
+
#define CLK_OVL1_OVL_MDP_RSZ0 30
605
+
#define CLK_OVL1_OVL_MDP_RSZ1 31
606
+
#define CLK_OVL1_OVL_DISP_WDMA0 32
607
+
#define CLK_OVL1_OVL_DISP_WDMA1 33
608
+
#define CLK_OVL1_OVL_UFBC_WDMA0 34
609
+
#define CLK_OVL1_OVL_MDP_RDMA0 35
610
+
#define CLK_OVL1_OVL_MDP_RDMA1 36
611
+
#define CLK_OVL1_OVL_BWM0 37
612
+
#define CLK_OVL1_DLI0 38
613
+
#define CLK_OVL1_DLI1 39
614
+
#define CLK_OVL1_DLI2 40
615
+
#define CLK_OVL1_DLI3 41
616
+
#define CLK_OVL1_DLI4 42
617
+
#define CLK_OVL1_DLI5 43
618
+
#define CLK_OVL1_DLI6 44
619
+
#define CLK_OVL1_DLI7 45
620
+
#define CLK_OVL1_DLI8 46
621
+
#define CLK_OVL1_DLO0 47
622
+
#define CLK_OVL1_DLO1 48
623
+
#define CLK_OVL1_DLO2 49
624
+
#define CLK_OVL1_DLO3 50
625
+
#define CLK_OVL1_DLO4 51
626
+
#define CLK_OVL1_DLO5 52
627
+
#define CLK_OVL1_DLO6 53
628
+
#define CLK_OVL1_DLO7 54
629
+
#define CLK_OVL1_DLO8 55
630
+
#define CLK_OVL1_DLO9 56
631
+
#define CLK_OVL1_DLO10 57
632
+
#define CLK_OVL1_DLO11 58
633
+
#define CLK_OVL1_DLO12 59
634
+
#define CLK_OVL1_OVLSYS_RELAY0 60
635
+
#define CLK_OVL1_OVL_INLINEROT0 61
636
+
#define CLK_OVL1_SMI 62
637
+
638
+
639
+
/* VDEC_SOC_GCON_BASE */
640
+
#define CLK_VDE1_LARB1_CKEN 0
641
+
#define CLK_VDE1_LAT_CKEN 1
642
+
#define CLK_VDE1_LAT_ACTIVE 2
643
+
#define CLK_VDE1_LAT_CKEN_ENG 3
644
+
#define CLK_VDE1_VDEC_CKEN 4
645
+
#define CLK_VDE1_VDEC_ACTIVE 5
646
+
#define CLK_VDE1_VDEC_CKEN_ENG 6
647
+
#define CLK_VDE1_VDEC_SOC_APTV_EN 7
648
+
#define CLK_VDE1_VDEC_SOC_APTV_TOP_EN 8
649
+
#define CLK_VDE1_VDEC_SOC_IPS_EN 9
650
+
651
+
/* VDEC_GCON_BASE */
652
+
#define CLK_VDE2_LARB1_CKEN 0
653
+
#define CLK_VDE2_LAT_CKEN 1
654
+
#define CLK_VDE2_LAT_ACTIVE 2
655
+
#define CLK_VDE2_LAT_CKEN_ENG 3
656
+
#define CLK_VDE2_VDEC_CKEN 4
657
+
#define CLK_VDE2_VDEC_ACTIVE 5
658
+
#define CLK_VDE2_VDEC_CKEN_ENG 6
659
+
660
+
/* VENC_GCON */
661
+
#define CLK_VEN1_CKE0_LARB 0
662
+
#define CLK_VEN1_CKE1_VENC 1
663
+
#define CLK_VEN1_CKE2_JPGENC 2
664
+
#define CLK_VEN1_CKE3_JPGDEC 3
665
+
#define CLK_VEN1_CKE4_JPGDEC_C1 4
666
+
#define CLK_VEN1_CKE5_GALS 5
667
+
#define CLK_VEN1_CKE29_VENC_ADAB_CTRL 6
668
+
#define CLK_VEN1_CKE29_VENC_XPC_CTRL 7
669
+
#define CLK_VEN1_CKE6_GALS_SRAM 8
670
+
#define CLK_VEN1_RES_FLAT 9
671
+
672
+
/* VENC_GCON_CORE1 */
673
+
#define CLK_VEN2_CKE0_LARB 0
674
+
#define CLK_VEN2_CKE1_VENC 1
675
+
#define CLK_VEN2_CKE2_JPGENC 2
676
+
#define CLK_VEN2_CKE3_JPGDEC 3
677
+
#define CLK_VEN2_CKE5_GALS 4
678
+
#define CLK_VEN2_CKE29_VENC_XPC_CTRL 5
679
+
#define CLK_VEN2_CKE6_GALS_SRAM 6
680
+
#define CLK_VEN2_RES_FLAT 7
681
+
682
+
/* VENC_GCON_CORE2 */
683
+
#define CLK_VEN_C2_CKE0_LARB 0
684
+
#define CLK_VEN_C2_CKE1_VENC 1
685
+
#define CLK_VEN_C2_CKE5_GALS 2
686
+
#define CLK_VEN_C2_CKE29_VENC_XPC_CTRL 3
687
+
#define CLK_VEN_C2_CKE6_GALS_SRAM 4
688
+
#define CLK_VEN_C2_RES_FLAT 5
689
+
690
+
/* MDPSYS_CONFIG */
691
+
#define CLK_MDP_MDP_MUTEX0 0
692
+
#define CLK_MDP_SMI0 1
693
+
#define CLK_MDP_SMI0_SMI 2
694
+
#define CLK_MDP_APB_BUS 3
695
+
#define CLK_MDP_MDP_RDMA0 4
696
+
#define CLK_MDP_MDP_RDMA1 5
697
+
#define CLK_MDP_MDP_RDMA2 6
698
+
#define CLK_MDP_MDP_BIRSZ0 7
699
+
#define CLK_MDP_MDP_HDR0 8
700
+
#define CLK_MDP_MDP_AAL0 9
701
+
#define CLK_MDP_MDP_RSZ0 10
702
+
#define CLK_MDP_MDP_RSZ2 11
703
+
#define CLK_MDP_MDP_TDSHP0 12
704
+
#define CLK_MDP_MDP_COLOR0 13
705
+
#define CLK_MDP_MDP_WROT0 14
706
+
#define CLK_MDP_MDP_WROT1 15
707
+
#define CLK_MDP_MDP_WROT2 16
708
+
#define CLK_MDP_MDP_FAKE_ENG0 17
709
+
#define CLK_MDP_APB_DB 18
710
+
#define CLK_MDP_MDP_DLI_ASYNC0 19
711
+
#define CLK_MDP_MDP_DLI_ASYNC1 20
712
+
#define CLK_MDP_MDP_DLO_ASYNC0 21
713
+
#define CLK_MDP_MDP_DLO_ASYNC1 22
714
+
#define CLK_MDP_MDP_DLI_ASYNC2 23
715
+
#define CLK_MDP_MDP_DLO_ASYNC2 24
716
+
#define CLK_MDP_MDP_DLO_ASYNC3 25
717
+
#define CLK_MDP_IMG_DL_ASYNC0 26
718
+
#define CLK_MDP_MDP_RROT0 27
719
+
#define CLK_MDP_MDP_MERGE0 28
720
+
#define CLK_MDP_MDP_C3D0 29
721
+
#define CLK_MDP_MDP_FG0 30
722
+
#define CLK_MDP_MDP_CLA2 31
723
+
#define CLK_MDP_MDP_DLO_ASYNC4 32
724
+
#define CLK_MDP_VPP_RSZ0 33
725
+
#define CLK_MDP_VPP_RSZ1 34
726
+
#define CLK_MDP_MDP_DLO_ASYNC5 35
727
+
#define CLK_MDP_IMG0 36
728
+
#define CLK_MDP_F26M 37
729
+
#define CLK_MDP_IMG_DL_RELAY0 38
730
+
#define CLK_MDP_IMG_DL_RELAY1 39
731
+
732
+
/* MDPSYS1_CONFIG */
733
+
#define CLK_MDP1_MDP_MUTEX0 0
734
+
#define CLK_MDP1_SMI0 1
735
+
#define CLK_MDP1_SMI0_SMI 2
736
+
#define CLK_MDP1_APB_BUS 3
737
+
#define CLK_MDP1_MDP_RDMA0 4
738
+
#define CLK_MDP1_MDP_RDMA1 5
739
+
#define CLK_MDP1_MDP_RDMA2 6
740
+
#define CLK_MDP1_MDP_BIRSZ0 7
741
+
#define CLK_MDP1_MDP_HDR0 8
742
+
#define CLK_MDP1_MDP_AAL0 9
743
+
#define CLK_MDP1_MDP_RSZ0 10
744
+
#define CLK_MDP1_MDP_RSZ2 11
745
+
#define CLK_MDP1_MDP_TDSHP0 12
746
+
#define CLK_MDP1_MDP_COLOR0 13
747
+
#define CLK_MDP1_MDP_WROT0 14
748
+
#define CLK_MDP1_MDP_WROT1 15
749
+
#define CLK_MDP1_MDP_WROT2 16
750
+
#define CLK_MDP1_MDP_FAKE_ENG0 17
751
+
#define CLK_MDP1_APB_DB 18
752
+
#define CLK_MDP1_MDP_DLI_ASYNC0 19
753
+
#define CLK_MDP1_MDP_DLI_ASYNC1 20
754
+
#define CLK_MDP1_MDP_DLO_ASYNC0 21
755
+
#define CLK_MDP1_MDP_DLO_ASYNC1 22
756
+
#define CLK_MDP1_MDP_DLI_ASYNC2 23
757
+
#define CLK_MDP1_MDP_DLO_ASYNC2 24
758
+
#define CLK_MDP1_MDP_DLO_ASYNC3 25
759
+
#define CLK_MDP1_IMG_DL_ASYNC0 26
760
+
#define CLK_MDP1_MDP_RROT0 27
761
+
#define CLK_MDP1_MDP_MERGE0 28
762
+
#define CLK_MDP1_MDP_C3D0 29
763
+
#define CLK_MDP1_MDP_FG0 30
764
+
#define CLK_MDP1_MDP_CLA2 31
765
+
#define CLK_MDP1_MDP_DLO_ASYNC4 32
766
+
#define CLK_MDP1_VPP_RSZ0 33
767
+
#define CLK_MDP1_VPP_RSZ1 34
768
+
#define CLK_MDP1_MDP_DLO_ASYNC5 35
769
+
#define CLK_MDP1_IMG0 36
770
+
#define CLK_MDP1_F26M 37
771
+
#define CLK_MDP1_IMG_DL_RELAY0 38
772
+
#define CLK_MDP1_IMG_DL_RELAY1 39
773
+
774
+
/* DISP_VDISP_AO_CONFIG */
775
+
#define CLK_MM_V_DISP_VDISP_AO_CONFIG 0
776
+
#define CLK_MM_V_DISP_DPC 1
777
+
#define CLK_MM_V_SMI_SUB_SOMM0 2
778
+
779
+
/* MFGPLL_PLL_CTRL */
780
+
#define CLK_MFG_AO_MFGPLL 0
781
+
782
+
/* MFGPLL_SC0_PLL_CTRL */
783
+
#define CLK_MFGSC0_AO_MFGPLL_SC0 0
784
+
785
+
/* MFGPLL_SC1_PLL_CTRL */
786
+
#define CLK_MFGSC1_AO_MFGPLL_SC1 0
787
+
788
+
/* CCIPLL_PLL_CTRL */
789
+
#define CLK_CCIPLL 0
790
+
791
+
/* ARMPLL_LL_PLL_CTRL */
792
+
#define CLK_CPLL_ARMPLL_LL 0
793
+
794
+
/* ARMPLL_BL_PLL_CTRL */
795
+
#define CLK_CPBL_ARMPLL_BL 0
796
+
797
+
/* ARMPLL_B_PLL_CTRL */
798
+
#define CLK_CPB_ARMPLL_B 0
799
+
800
+
/* PTPPLL_PLL_CTRL */
801
+
#define CLK_PTPPLL 0
802
+
803
+
#endif /* _DT_BINDINGS_CLK_MT8196_H */
+1
-1
include/dt-bindings/clock/mt7622-clk.h
+1
-1
include/dt-bindings/clock/mt7622-clk.h
+26
include/dt-bindings/reset/mediatek,mt8196-resets.h
+26
include/dt-bindings/reset/mediatek,mt8196-resets.h
···
1
+
/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
2
+
/*
3
+
* Copyright (c) 2025 Collabora Ltd.
4
+
* Author: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
5
+
*/
6
+
7
+
#ifndef _DT_BINDINGS_RESET_CONTROLLER_MT8196
8
+
#define _DT_BINDINGS_RESET_CONTROLLER_MT8196
9
+
10
+
/* PEXTP0 resets */
11
+
#define MT8196_PEXTP0_RST0_PCIE0_MAC 0
12
+
#define MT8196_PEXTP0_RST0_PCIE0_PHY 1
13
+
14
+
/* PEXTP1 resets */
15
+
#define MT8196_PEXTP1_RST0_PCIE1_MAC 0
16
+
#define MT8196_PEXTP1_RST0_PCIE1_PHY 1
17
+
#define MT8196_PEXTP1_RST0_PCIE2_MAC 2
18
+
#define MT8196_PEXTP1_RST0_PCIE2_PHY 3
19
+
20
+
/* UFS resets */
21
+
#define MT8196_UFSAO_RST0_UFS_MPHY 0
22
+
#define MT8196_UFSAO_RST1_UFS_UNIPRO 1
23
+
#define MT8196_UFSAO_RST1_UFS_CRYPTO 2
24
+
#define MT8196_UFSAO_RST1_UFSHCI 3
25
+
26
+
#endif /* _DT_BINDINGS_RESET_CONTROLLER_MT8196 */