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drm/amd/display: Fix Silence Conversion Warnings in Dmub

Fix Conversion that might result in a loss of data warnings in dmub/src/:

- dmub_dcn20/31/32/35/42/60/401.c: Add ASSERT(value <= 0xFF) and
explicit (uint8_t) cast when storing REG_GET results into uint8_t
debug struct fields. Add != 0 for bool assignments from uint32_t
bitfield reads.
- dmub_reg.c: Cast va_arg shift value to uint8_t with ASSERT guard
before passing to set_reg_field_value_masks().
- dmub_srv.c: Widen num_pending to uint64_t to match uint64_t
arithmetic; use != 0 for bool assignments from unsigned expressions.

No functional change intended.

Reviewed-by: Dillon Varone <dillon.varone@amd.com>
Signed-off-by: Gaghik Khachatrian <gaghik.khachatrian@amd.com>
Signed-off-by: Chuanyu Tseng <chuanyu.tseng@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

authored by

Gaghik Khachatrian and committed by
Alex Deucher d77ff733 4c3aeb11

+82 -44
+12 -6
drivers/gpu/drm/amd/display/dmub/src/dmub_dcn20.c
··· 460 460 dmub->debug.inbox0_size = REG_READ(DMCUB_INBOX0_SIZE); 461 461 462 462 REG_GET(DMCUB_CNTL, DMCUB_ENABLE, &is_dmub_enabled); 463 - dmub->debug.is_dmcub_enabled = is_dmub_enabled; 463 + ASSERT(is_dmub_enabled <= 0xFF); 464 + dmub->debug.is_dmcub_enabled = (uint8_t)is_dmub_enabled; 464 465 465 466 REG_GET(DMCUB_CNTL, DMCUB_SOFT_RESET, &is_soft_reset); 466 - dmub->debug.is_dmcub_soft_reset = is_soft_reset; 467 + ASSERT(is_soft_reset <= 0xFF); 468 + dmub->debug.is_dmcub_soft_reset = (uint8_t)is_soft_reset; 467 469 468 470 REG_GET(DMCUB_SEC_CNTL, DMCUB_SEC_RESET_STATUS, &is_sec_reset); 469 - dmub->debug.is_dmcub_secure_reset = is_sec_reset; 471 + ASSERT(is_sec_reset <= 0xFF); 472 + dmub->debug.is_dmcub_secure_reset = (uint8_t)is_sec_reset; 470 473 471 474 REG_GET(DMCUB_CNTL, DMCUB_TRACEPORT_EN, &is_traceport_enabled); 472 - dmub->debug.is_traceport_en = is_traceport_enabled; 475 + ASSERT(is_traceport_enabled <= 0xFF); 476 + dmub->debug.is_traceport_en = (uint8_t)is_traceport_enabled; 473 477 474 478 REG_GET(DMCUB_REGION3_CW0_TOP_ADDRESS, DMCUB_REGION3_CW0_ENABLE, &is_cw0_enabled); 475 - dmub->debug.is_cw0_enabled = is_cw0_enabled; 479 + ASSERT(is_cw0_enabled <= 0xFF); 480 + dmub->debug.is_cw0_enabled = (uint8_t)is_cw0_enabled; 476 481 477 482 REG_GET(DMCUB_REGION3_CW6_TOP_ADDRESS, DMCUB_REGION3_CW6_ENABLE, &is_cw6_enabled); 478 - dmub->debug.is_cw6_enabled = is_cw6_enabled; 483 + ASSERT(is_cw6_enabled <= 0xFF); 484 + dmub->debug.is_cw6_enabled = (uint8_t)is_cw6_enabled; 479 485 }
+14 -7
drivers/gpu/drm/amd/display/dmub/src/dmub_dcn31.c
··· 466 466 dmub->debug.outbox1_size = REG_READ(DMCUB_OUTBOX1_SIZE); 467 467 468 468 REG_GET(DMCUB_CNTL, DMCUB_ENABLE, &is_dmub_enabled); 469 - dmub->debug.is_dmcub_enabled = is_dmub_enabled; 469 + ASSERT(is_dmub_enabled <= 0xFF); 470 + dmub->debug.is_dmcub_enabled = (uint8_t)is_dmub_enabled; 470 471 471 472 REG_GET(DMCUB_CNTL, DMCUB_PWAIT_MODE_STATUS, &is_pwait); 472 - dmub->debug.is_pwait = is_pwait; 473 + ASSERT(is_pwait <= 0xFF); 474 + dmub->debug.is_pwait = (uint8_t)is_pwait; 473 475 474 476 REG_GET(DMCUB_CNTL2, DMCUB_SOFT_RESET, &is_soft_reset); 475 - dmub->debug.is_dmcub_soft_reset = is_soft_reset; 477 + ASSERT(is_soft_reset <= 0xFF); 478 + dmub->debug.is_dmcub_soft_reset = (uint8_t)is_soft_reset; 476 479 477 480 REG_GET(DMCUB_SEC_CNTL, DMCUB_SEC_RESET_STATUS, &is_sec_reset); 478 - dmub->debug.is_dmcub_secure_reset = is_sec_reset; 481 + ASSERT(is_sec_reset <= 0xFF); 482 + dmub->debug.is_dmcub_secure_reset = (uint8_t)is_sec_reset; 479 483 480 484 REG_GET(DMCUB_CNTL, DMCUB_TRACEPORT_EN, &is_traceport_enabled); 481 - dmub->debug.is_traceport_en = is_traceport_enabled; 485 + ASSERT(is_traceport_enabled <= 0xFF); 486 + dmub->debug.is_traceport_en = (uint8_t)is_traceport_enabled; 482 487 483 488 REG_GET(DMCUB_REGION3_CW0_TOP_ADDRESS, DMCUB_REGION3_CW0_ENABLE, &is_cw0_enabled); 484 - dmub->debug.is_cw0_enabled = is_cw0_enabled; 489 + ASSERT(is_cw0_enabled <= 0xFF); 490 + dmub->debug.is_cw0_enabled = (uint8_t)is_cw0_enabled; 485 491 486 492 REG_GET(DMCUB_REGION3_CW6_TOP_ADDRESS, DMCUB_REGION3_CW6_ENABLE, &is_cw6_enabled); 487 - dmub->debug.is_cw6_enabled = is_cw6_enabled; 493 + ASSERT(is_cw6_enabled <= 0xFF); 494 + dmub->debug.is_cw6_enabled = (uint8_t)is_cw6_enabled; 488 495 } 489 496 490 497 bool dmub_dcn31_should_detect(struct dmub_srv *dmub)
+10 -5
drivers/gpu/drm/amd/display/dmub/src/dmub_dcn32.c
··· 486 486 dmub->debug.outbox1_size = REG_READ(DMCUB_OUTBOX1_SIZE); 487 487 488 488 REG_GET(DMCUB_CNTL, DMCUB_ENABLE, &is_dmub_enabled); 489 - dmub->debug.is_dmcub_enabled = is_dmub_enabled; 489 + ASSERT(is_dmub_enabled <= 0xFF); 490 + dmub->debug.is_dmcub_enabled = (uint8_t)is_dmub_enabled; 490 491 491 492 REG_GET(DMCUB_CNTL, DMCUB_PWAIT_MODE_STATUS, &is_pwait); 492 - dmub->debug.is_pwait = is_pwait; 493 + ASSERT(is_pwait <= 0xFF); 494 + dmub->debug.is_pwait = (uint8_t)is_pwait; 493 495 494 496 REG_GET(DMCUB_CNTL2, DMCUB_SOFT_RESET, &is_soft_reset); 495 - dmub->debug.is_dmcub_soft_reset = is_soft_reset; 497 + ASSERT(is_soft_reset <= 0xFF); 498 + dmub->debug.is_dmcub_soft_reset = (uint8_t)is_soft_reset; 496 499 497 500 REG_GET(DMCUB_CNTL, DMCUB_TRACEPORT_EN, &is_traceport_enabled); 498 - dmub->debug.is_traceport_en = is_traceport_enabled; 501 + ASSERT(is_traceport_enabled <= 0xFF); 502 + dmub->debug.is_traceport_en = (uint8_t)is_traceport_enabled; 499 503 500 504 REG_GET(DMCUB_REGION3_CW6_TOP_ADDRESS, DMCUB_REGION3_CW6_ENABLE, &is_cw6_enabled); 501 - dmub->debug.is_cw6_enabled = is_cw6_enabled; 505 + ASSERT(is_cw6_enabled <= 0xFF); 506 + dmub->debug.is_cw6_enabled = (uint8_t)is_cw6_enabled; 502 507 503 508 dmub->debug.gpint_datain0 = REG_READ(DMCUB_GPINT_DATAIN0); 504 509 }
+11 -6
drivers/gpu/drm/amd/display/dmub/src/dmub_dcn35.c
··· 402 402 union dmub_fw_boot_options boot_options = {0}; 403 403 404 404 if (!dmub->dpia_supported) { 405 - dmub->dpia_supported = dmub_dcn35_get_fw_boot_option(dmub).bits.enable_dpia; 405 + dmub->dpia_supported = dmub_dcn35_get_fw_boot_option(dmub).bits.enable_dpia != 0; 406 406 } 407 407 408 408 boot_options.bits.z10_disable = params->disable_z10; ··· 508 508 dmub->debug.outbox1_size = REG_READ(DMCUB_OUTBOX1_SIZE); 509 509 510 510 REG_GET(DMCUB_CNTL, DMCUB_ENABLE, &is_dmub_enabled); 511 - dmub->debug.is_dmcub_enabled = is_dmub_enabled; 511 + ASSERT(is_dmub_enabled <= 0xFF); 512 + dmub->debug.is_dmcub_enabled = (uint8_t)is_dmub_enabled; 512 513 513 514 REG_GET(DMCUB_CNTL, DMCUB_PWAIT_MODE_STATUS, &is_pwait); 514 - dmub->debug.is_pwait = is_pwait; 515 + ASSERT(is_pwait <= 0xFF); 516 + dmub->debug.is_pwait = (uint8_t)is_pwait; 515 517 516 518 REG_GET(DMCUB_CNTL2, DMCUB_SOFT_RESET, &is_soft_reset); 517 - dmub->debug.is_dmcub_soft_reset = is_soft_reset; 519 + ASSERT(is_soft_reset <= 0xFF); 520 + dmub->debug.is_dmcub_soft_reset = (uint8_t)is_soft_reset; 518 521 519 522 REG_GET(DMCUB_CNTL, DMCUB_TRACEPORT_EN, &is_traceport_enabled); 520 - dmub->debug.is_traceport_en = is_traceport_enabled; 523 + ASSERT(is_traceport_enabled <= 0xFF); 524 + dmub->debug.is_traceport_en = (uint8_t)is_traceport_enabled; 521 525 522 526 REG_GET(DMCUB_REGION3_CW6_TOP_ADDRESS, DMCUB_REGION3_CW6_ENABLE, &is_cw6_enabled); 523 - dmub->debug.is_cw6_enabled = is_cw6_enabled; 527 + ASSERT(is_cw6_enabled <= 0xFF); 528 + dmub->debug.is_cw6_enabled = (uint8_t)is_cw6_enabled; 524 529 525 530 dmub->debug.gpint_datain0 = REG_READ(DMCUB_GPINT_DATAIN0); 526 531 }
+14 -7
drivers/gpu/drm/amd/display/dmub/src/dmub_dcn401.c
··· 473 473 dmub->debug.outbox1_size = REG_READ(DMCUB_OUTBOX1_SIZE); 474 474 475 475 REG_GET(DMCUB_CNTL, DMCUB_ENABLE, &is_dmub_enabled); 476 - dmub->debug.is_dmcub_enabled = is_dmub_enabled; 476 + ASSERT(is_dmub_enabled <= 0xFF); 477 + dmub->debug.is_dmcub_enabled = (uint8_t)is_dmub_enabled; 477 478 478 479 REG_GET(DMCUB_CNTL, DMCUB_PWAIT_MODE_STATUS, &is_pwait); 479 - dmub->debug.is_pwait = is_pwait; 480 + ASSERT(is_pwait <= 0xFF); 481 + dmub->debug.is_pwait = (uint8_t)is_pwait; 480 482 481 483 REG_GET(DMCUB_CNTL2, DMCUB_SOFT_RESET, &is_soft_reset); 482 - dmub->debug.is_dmcub_soft_reset = is_soft_reset; 484 + ASSERT(is_soft_reset <= 0xFF); 485 + dmub->debug.is_dmcub_soft_reset = (uint8_t)is_soft_reset; 483 486 484 487 REG_GET(DMCUB_SEC_CNTL, DMCUB_SEC_RESET_STATUS, &is_sec_reset); 485 - dmub->debug.is_dmcub_secure_reset = is_sec_reset; 488 + ASSERT(is_sec_reset <= 0xFF); 489 + dmub->debug.is_dmcub_secure_reset = (uint8_t)is_sec_reset; 486 490 487 491 REG_GET(DMCUB_CNTL, DMCUB_TRACEPORT_EN, &is_traceport_enabled); 488 - dmub->debug.is_traceport_en = is_traceport_enabled; 492 + ASSERT(is_traceport_enabled <= 0xFF); 493 + dmub->debug.is_traceport_en = (uint8_t)is_traceport_enabled; 489 494 490 495 REG_GET(DMCUB_REGION3_CW0_TOP_ADDRESS, DMCUB_REGION3_CW0_ENABLE, &is_cw0_enabled); 491 - dmub->debug.is_cw0_enabled = is_cw0_enabled; 496 + ASSERT(is_cw0_enabled <= 0xFF); 497 + dmub->debug.is_cw0_enabled = (uint8_t)is_cw0_enabled; 492 498 493 499 REG_GET(DMCUB_REGION3_CW6_TOP_ADDRESS, DMCUB_REGION3_CW6_ENABLE, &is_cw6_enabled); 494 - dmub->debug.is_cw6_enabled = is_cw6_enabled; 500 + ASSERT(is_cw6_enabled <= 0xFF); 501 + dmub->debug.is_cw6_enabled = (uint8_t)is_cw6_enabled; 495 502 496 503 dmub->debug.gpint_datain0 = REG_READ(DMCUB_GPINT_DATAIN0); 497 504 }
+15 -8
drivers/gpu/drm/amd/display/dmub/src/dmub_dcn42.c
··· 41 41 union dmub_fw_boot_options boot_options = {0}; 42 42 43 43 if (!dmub->dpia_supported) { 44 - dmub->dpia_supported = dmub_dcn42_get_fw_boot_option(dmub).bits.enable_dpia; 44 + dmub->dpia_supported = dmub_dcn42_get_fw_boot_option(dmub).bits.enable_dpia != 0; 45 45 } 46 46 47 47 boot_options.bits.z10_disable = params->disable_z10; ··· 676 676 dmub->debug.outbox1_size = REG_READ(DMCUB_OUTBOX1_SIZE); 677 677 678 678 REG_GET(DMCUB_CNTL, DMCUB_ENABLE, &is_dmub_enabled); 679 - dmub->debug.is_dmcub_enabled = is_dmub_enabled; 679 + ASSERT(is_dmub_enabled <= 0xFF); 680 + dmub->debug.is_dmcub_enabled = (uint8_t)is_dmub_enabled; 680 681 681 682 REG_GET(DMCUB_CNTL, DMCUB_PWAIT_MODE_STATUS, &is_pwait); 682 - dmub->debug.is_pwait = is_pwait; 683 + ASSERT(is_pwait <= 0xFF); 684 + dmub->debug.is_pwait = (uint8_t)is_pwait; 683 685 684 686 REG_GET(DMCUB_CNTL2, DMCUB_SOFT_RESET, &is_soft_reset); 685 - dmub->debug.is_dmcub_soft_reset = is_soft_reset; 687 + ASSERT(is_soft_reset <= 0xFF); 688 + dmub->debug.is_dmcub_soft_reset = (uint8_t)is_soft_reset; 686 689 687 690 REG_GET(DMCUB_SEC_CNTL, DMCUB_SEC_RESET_STATUS, &is_sec_reset); 688 - dmub->debug.is_dmcub_secure_reset = is_sec_reset; 691 + ASSERT(is_sec_reset <= 0xFF); 692 + dmub->debug.is_dmcub_secure_reset = (uint8_t)is_sec_reset; 689 693 690 694 REG_GET(DMCUB_CNTL, DMCUB_TRACEPORT_EN, &is_traceport_enabled); 691 - dmub->debug.is_traceport_en = is_traceport_enabled; 695 + ASSERT(is_traceport_enabled <= 0xFF); 696 + dmub->debug.is_traceport_en = (uint8_t)is_traceport_enabled; 692 697 693 698 REG_GET(DMCUB_REGION3_CW0_TOP_ADDRESS, DMCUB_REGION3_CW0_ENABLE, &is_cw0_enabled); 694 - dmub->debug.is_cw0_enabled = is_cw0_enabled; 699 + ASSERT(is_cw0_enabled <= 0xFF); 700 + dmub->debug.is_cw0_enabled = (uint8_t)is_cw0_enabled; 695 701 696 702 REG_GET(DMCUB_REGION3_CW6_TOP_ADDRESS, DMCUB_REGION3_CW6_ENABLE, &is_cw6_enabled); 697 - dmub->debug.is_cw6_enabled = is_cw6_enabled; 703 + ASSERT(is_cw6_enabled <= 0xFF); 704 + dmub->debug.is_cw6_enabled = (uint8_t)is_cw6_enabled; 698 705 699 706 dmub->debug.gpint_datain0 = REG_READ(DMCUB_GPINT_DATAIN0); 700 707 }
+2 -1
drivers/gpu/drm/amd/display/dmub/src/dmub_reg.c
··· 57 57 mask = va_arg(ap, uint32_t); 58 58 field_value = va_arg(ap, uint32_t); 59 59 60 + ASSERT(shift <= 0xFF); 60 61 set_reg_field_value_masks(field_value_mask, field_value, mask, 61 - shift); 62 + (uint8_t)shift); 62 63 i++; 63 64 } 64 65 }
+4 -4
drivers/gpu/drm/amd/display/dmub/src/dmub_srv.c
··· 1034 1034 static void dmub_srv_update_reg_inbox0_status(struct dmub_srv *dmub) 1035 1035 { 1036 1036 if (dmub->reg_inbox0.is_pending) { 1037 - dmub->reg_inbox0.is_pending = dmub->hw_funcs.read_reg_inbox0_rsp_int_status && 1038 - !dmub->hw_funcs.read_reg_inbox0_rsp_int_status(dmub); 1037 + dmub->reg_inbox0.is_pending = (dmub->hw_funcs.read_reg_inbox0_rsp_int_status && 1038 + !dmub->hw_funcs.read_reg_inbox0_rsp_int_status(dmub)) != 0; 1039 1039 1040 1040 if (!dmub->reg_inbox0.is_pending) { 1041 1041 /* ack the rsp interrupt */ ··· 1320 1320 1321 1321 enum dmub_status dmub_srv_reg_cmd_execute(struct dmub_srv *dmub, union dmub_rb_cmd *cmd) 1322 1322 { 1323 - uint32_t num_pending = 0; 1323 + uint64_t num_pending = 0; 1324 1324 1325 1325 if (!dmub->hw_init) 1326 1326 return DMUB_STATUS_INVALID; ··· 1348 1348 1349 1349 dmub->reg_inbox0.num_submitted++; 1350 1350 dmub->reg_inbox0.is_pending = true; 1351 - dmub->reg_inbox0.is_multi_pending = cmd->cmd_common.header.multi_cmd_pending; 1351 + dmub->reg_inbox0.is_multi_pending = cmd->cmd_common.header.multi_cmd_pending != 0; 1352 1352 1353 1353 return DMUB_STATUS_OK; 1354 1354 }