clk: renesas: r9a09g056: Add support for PLLVDO, CRU clocks, and resets

Add support for the PLLVDO clock and its related CRU clocks and reset
entries in the R9A09G056 CPG driver. Introduce `CLK_PLLVDO` and associated
clocks like `CLK_PLLVDO_CRU0` and `CLK_PLLVDO_CRU1`, along with their
corresponding dividers.

Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://patch.msgid.link/20251023210724.666476-3-prabhakar.mahadev-lad.rj@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>

authored by

Lad Prabhakar and committed by

Geert Uytterhoeven 7 months ago 861df879 d64522b5

+31

1 changed file

expand all

drivers

clk

renesas

r9a09g056-cpg.c

+31

drivers/clk/renesas/r9a09g056-cpg.c

··· 29 29 CLK_PLLCLN, 30 30 CLK_PLLDTY, 31 31 CLK_PLLCA55, 32 + CLK_PLLVDO, 32 33 CLK_PLLETH, 33 34 CLK_PLLDSI, 34 35 CLK_PLLGPU, ··· 51 50 CLK_PLLDTY_ACPU_DIV4, 52 51 CLK_PLLDTY_DIV8, 53 52 CLK_PLLDTY_DIV16, 53 + CLK_PLLVDO_CRU0, 54 + CLK_PLLVDO_CRU1, 54 55 CLK_PLLETH_DIV_250_FIX, 55 56 CLK_PLLETH_DIV_125_FIX, 56 57 CLK_CSDIV_PLLETH_GBE0, ··· 75 72 {1, 2}, 76 73 {2, 4}, 77 74 {3, 8}, 75 + {0, 0}, 76 + }; 77 + 78 + static const struct clk_div_table dtable_2_4[] = { 79 + {0, 2}, 80 + {1, 4}, 78 81 {0, 0}, 79 82 }; 80 83 ··· 158 149 DEF_FIXED(".pllcln", CLK_PLLCLN, CLK_QEXTAL, 200, 3), 159 150 DEF_FIXED(".plldty", CLK_PLLDTY, CLK_QEXTAL, 200, 3), 160 151 DEF_PLL(".pllca55", CLK_PLLCA55, CLK_QEXTAL, PLLCA55), 152 + DEF_FIXED(".pllvdo", CLK_PLLVDO, CLK_QEXTAL, 105, 2), 161 153 DEF_FIXED(".plleth", CLK_PLLETH, CLK_QEXTAL, 125, 3), 162 154 DEF_PLLDSI(".plldsi", CLK_PLLDSI, CLK_QEXTAL, PLLDSI), 163 155 DEF_PLL(".pllgpu", CLK_PLLGPU, CLK_QEXTAL, PLLGPU), ··· 183 173 DEF_FIXED(".plldty_acpu_div4", CLK_PLLDTY_ACPU_DIV4, CLK_PLLDTY_ACPU, 1, 4), 184 174 DEF_FIXED(".plldty_div8", CLK_PLLDTY_DIV8, CLK_PLLDTY, 1, 8), 185 175 DEF_FIXED(".plldty_div16", CLK_PLLDTY_DIV16, CLK_PLLDTY, 1, 16), 176 + 177 + DEF_DDIV(".pllvdo_cru0", CLK_PLLVDO_CRU0, CLK_PLLVDO, CDDIV3_DIVCTL3, dtable_2_4), 178 + DEF_DDIV(".pllvdo_cru1", CLK_PLLVDO_CRU1, CLK_PLLVDO, CDDIV4_DIVCTL0, dtable_2_4), 186 179 187 180 DEF_FIXED(".plleth_250_fix", CLK_PLLETH_DIV_250_FIX, CLK_PLLETH, 1, 4), 188 181 DEF_FIXED(".plleth_125_fix", CLK_PLLETH_DIV_125_FIX, CLK_PLLETH_DIV_250_FIX, 1, 2), ··· 347 334 BUS_MSTOP(8, BIT(6))), 348 335 DEF_MOD("gbeth_1_aclk_i", CLK_PLLDTY_DIV8, 12, 3, 6, 3, 349 336 BUS_MSTOP(8, BIT(6))), 337 + DEF_MOD("cru_0_aclk", CLK_PLLDTY_ACPU_DIV2, 13, 2, 6, 18, 338 + BUS_MSTOP(9, BIT(4))), 339 + DEF_MOD_NO_PM("cru_0_vclk", CLK_PLLVDO_CRU0, 13, 3, 6, 19, 340 + BUS_MSTOP(9, BIT(4))), 341 + DEF_MOD("cru_0_pclk", CLK_PLLDTY_DIV16, 13, 4, 6, 20, 342 + BUS_MSTOP(9, BIT(4))), 343 + DEF_MOD("cru_1_aclk", CLK_PLLDTY_ACPU_DIV2, 13, 5, 6, 21, 344 + BUS_MSTOP(9, BIT(5))), 345 + DEF_MOD_NO_PM("cru_1_vclk", CLK_PLLVDO_CRU1, 13, 6, 6, 22, 346 + BUS_MSTOP(9, BIT(5))), 347 + DEF_MOD("cru_1_pclk", CLK_PLLDTY_DIV16, 13, 7, 6, 23, 348 + BUS_MSTOP(9, BIT(5))), 350 349 DEF_MOD("dsi_0_pclk", CLK_PLLDTY_DIV16, 14, 8, 7, 8, 351 350 BUS_MSTOP(9, BIT(14) | BIT(15))), 352 351 DEF_MOD("dsi_0_aclk", CLK_PLLDTY_ACPU_DIV2, 14, 9, 7, 9, ··· 421 396 DEF_RST(10, 15, 5, 0), /* USB2_0_PRESETN */ 422 397 DEF_RST(11, 0, 5, 1), /* GBETH_0_ARESETN_I */ 423 398 DEF_RST(11, 1, 5, 2), /* GBETH_1_ARESETN_I */ 399 + DEF_RST(12, 5, 5, 22), /* CRU_0_PRESETN */ 400 + DEF_RST(12, 6, 5, 23), /* CRU_0_ARESETN */ 401 + DEF_RST(12, 7, 5, 24), /* CRU_0_S_RESETN */ 402 + DEF_RST(12, 8, 5, 25), /* CRU_1_PRESETN */ 403 + DEF_RST(12, 9, 5, 26), /* CRU_1_ARESETN */ 404 + DEF_RST(12, 10, 5, 27), /* CRU_1_S_RESETN */ 424 405 DEF_RST(13, 7, 6, 8), /* DSI_0_PRESETN */ 425 406 DEF_RST(13, 8, 6, 9), /* DSI_0_ARESETN */ 426 407 DEF_RST(13, 12, 6, 13), /* LCDC_0_RESET_N */

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