Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
clk: renesas: r9a09g056: Add clocks and resets for DSI and LCDC modules
Add clock and reset definitions required to support the DSI and LCDC
hardware blocks on the RZ/V2N SoC. This includes new core clocks, clock
dividers, module clocks, and reset entries, as well as PLL and divider
configurations specific to these peripherals.
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://patch.msgid.link/20251023210724.666476-2-prabhakar.mahadev-lad.rj@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
authored by
Lad Prabhakar
and committed by
Geert Uytterhoeven
d64522b5
79276fb0
+64
+64
drivers/clk/renesas/r9a09g056-cpg.c
+64
drivers/clk/renesas/r9a09g056-cpg.c
···
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*/
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#include <linux/clk-provider.h>
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#include <linux/clk/renesas.h>
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#include <linux/device.h>
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#include <linux/init.h>
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#include <linux/kernel.h>
···
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CLK_PLLDTY,
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CLK_PLLCA55,
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CLK_PLLETH,
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CLK_PLLDSI,
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CLK_PLLGPU,
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/* Internal Core Clocks */
···
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CLK_PLLDTY_ACPU_DIV2,
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CLK_PLLDTY_ACPU_DIV4,
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CLK_PLLDTY_DIV8,
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CLK_PLLDTY_DIV16,
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CLK_PLLETH_DIV_250_FIX,
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CLK_PLLETH_DIV_125_FIX,
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CLK_CSDIV_PLLETH_GBE0,
···
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CLK_SMUX2_GBE0_RXCLK,
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CLK_SMUX2_GBE1_TXCLK,
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CLK_SMUX2_GBE1_RXCLK,
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CLK_CDIV4_PLLETH_LPCLK,
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CLK_PLLETH_LPCLK_GEAR,
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CLK_PLLDSI_GEAR,
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CLK_PLLGPU_GEAR,
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/* Module Clocks */
···
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{0, 0},
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};
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static const struct clk_div_table dtable_2_32[] = {
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{0, 2},
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{1, 4},
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{2, 6},
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{3, 8},
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{4, 10},
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{5, 12},
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{6, 14},
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{7, 16},
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{8, 18},
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{9, 20},
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{10, 22},
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{11, 24},
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{12, 26},
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{13, 28},
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{14, 30},
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{15, 32},
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{0, 0},
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};
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static const struct clk_div_table dtable_2_64[] = {
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{0, 2},
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{1, 4},
···
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{2, 100},
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{0, 0},
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};
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static const struct clk_div_table dtable_16_128[] = {
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{0, 16},
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{1, 32},
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{2, 64},
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{3, 128},
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{0, 0},
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};
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RZV2H_CPG_PLL_DSI_LIMITS(rzv2n_cpg_pll_dsi_limits);
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#define PLLDSI PLL_PACK_LIMITS(0xc0, 1, 0, &rzv2n_cpg_pll_dsi_limits)
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/* Mux clock tables */
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static const char * const smux2_gbe0_rxclk[] = { ".plleth_gbe0", "et0_rxclk" };
···
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DEF_FIXED(".plldty", CLK_PLLDTY, CLK_QEXTAL, 200, 3),
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DEF_PLL(".pllca55", CLK_PLLCA55, CLK_QEXTAL, PLLCA55),
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DEF_FIXED(".plleth", CLK_PLLETH, CLK_QEXTAL, 125, 3),
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DEF_PLLDSI(".plldsi", CLK_PLLDSI, CLK_QEXTAL, PLLDSI),
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DEF_PLL(".pllgpu", CLK_PLLGPU, CLK_QEXTAL, PLLGPU),
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/* Internal Core Clocks */
···
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DEF_FIXED(".plldty_acpu_div2", CLK_PLLDTY_ACPU_DIV2, CLK_PLLDTY_ACPU, 1, 2),
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DEF_FIXED(".plldty_acpu_div4", CLK_PLLDTY_ACPU_DIV4, CLK_PLLDTY_ACPU, 1, 4),
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DEF_FIXED(".plldty_div8", CLK_PLLDTY_DIV8, CLK_PLLDTY, 1, 8),
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DEF_FIXED(".plldty_div16", CLK_PLLDTY_DIV16, CLK_PLLDTY, 1, 16),
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DEF_FIXED(".plleth_250_fix", CLK_PLLETH_DIV_250_FIX, CLK_PLLETH, 1, 4),
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DEF_FIXED(".plleth_125_fix", CLK_PLLETH_DIV_125_FIX, CLK_PLLETH_DIV_250_FIX, 1, 2),
···
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DEF_SMUX(".smux2_gbe0_rxclk", CLK_SMUX2_GBE0_RXCLK, SSEL0_SELCTL3, smux2_gbe0_rxclk),
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DEF_SMUX(".smux2_gbe1_txclk", CLK_SMUX2_GBE1_TXCLK, SSEL1_SELCTL0, smux2_gbe1_txclk),
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DEF_SMUX(".smux2_gbe1_rxclk", CLK_SMUX2_GBE1_RXCLK, SSEL1_SELCTL1, smux2_gbe1_rxclk),
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DEF_FIXED(".cdiv4_plleth_lpclk", CLK_CDIV4_PLLETH_LPCLK, CLK_PLLETH, 1, 4),
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DEF_CSDIV(".plleth_lpclk_gear", CLK_PLLETH_LPCLK_GEAR, CLK_CDIV4_PLLETH_LPCLK,
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CSDIV0_DIVCTL2, dtable_16_128),
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+
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DEF_PLLDSI_DIV(".plldsi_gear", CLK_PLLDSI_GEAR, CLK_PLLDSI,
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CSDIV1_DIVCTL2, dtable_2_32),
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DEF_DDIV(".pllgpu_gear", CLK_PLLGPU_GEAR, CLK_PLLGPU, CDDIV3_DIVCTL1, dtable_2_64),
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···
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BUS_MSTOP(8, BIT(6))),
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DEF_MOD("gbeth_1_aclk_i", CLK_PLLDTY_DIV8, 12, 3, 6, 3,
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BUS_MSTOP(8, BIT(6))),
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DEF_MOD("dsi_0_pclk", CLK_PLLDTY_DIV16, 14, 8, 7, 8,
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BUS_MSTOP(9, BIT(14) | BIT(15))),
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DEF_MOD("dsi_0_aclk", CLK_PLLDTY_ACPU_DIV2, 14, 9, 7, 9,
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BUS_MSTOP(9, BIT(14) | BIT(15))),
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DEF_MOD("dsi_0_vclk1", CLK_PLLDSI_GEAR, 14, 10, 7, 10,
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BUS_MSTOP(9, BIT(14) | BIT(15))),
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DEF_MOD("dsi_0_lpclk", CLK_PLLETH_LPCLK_GEAR, 14, 11, 7, 11,
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BUS_MSTOP(9, BIT(14) | BIT(15))),
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DEF_MOD("dsi_0_pllref_clk", CLK_QEXTAL, 14, 12, 7, 12,
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BUS_MSTOP(9, BIT(14) | BIT(15))),
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DEF_MOD("lcdc_0_clk_a", CLK_PLLDTY_ACPU_DIV2, 14, 13, 7, 13,
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BUS_MSTOP(10, BIT(1) | BIT(2) | BIT(3))),
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DEF_MOD("lcdc_0_clk_p", CLK_PLLDTY_DIV16, 14, 14, 7, 14,
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BUS_MSTOP(10, BIT(1) | BIT(2) | BIT(3))),
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DEF_MOD("lcdc_0_clk_d", CLK_PLLDSI_GEAR, 14, 15, 7, 15,
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BUS_MSTOP(10, BIT(1) | BIT(2) | BIT(3))),
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DEF_MOD("gpu_0_clk", CLK_PLLGPU_GEAR, 15, 0, 7, 16,
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BUS_MSTOP(3, BIT(4))),
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DEF_MOD("gpu_0_axi_clk", CLK_PLLDTY_ACPU_DIV2, 15, 1, 7, 17,
···
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DEF_RST(10, 15, 5, 0), /* USB2_0_PRESETN */
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DEF_RST(11, 0, 5, 1), /* GBETH_0_ARESETN_I */
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DEF_RST(11, 1, 5, 2), /* GBETH_1_ARESETN_I */
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DEF_RST(13, 7, 6, 8), /* DSI_0_PRESETN */
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DEF_RST(13, 8, 6, 9), /* DSI_0_ARESETN */
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DEF_RST(13, 12, 6, 13), /* LCDC_0_RESET_N */
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DEF_RST(13, 13, 6, 14), /* GPU_0_RESETN */
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DEF_RST(13, 14, 6, 15), /* GPU_0_AXI_RESETN */
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DEF_RST(13, 15, 6, 16), /* GPU_0_ACE_RESETN */