-46

drivers/gpu/drm/msm/disp/dpu1/dpu_core_irq.h

reviewed

··· 8 8 #include "dpu_kms.h" 9 9 #include "dpu_hw_interrupts.h" 10 10 11 11 - /** 12 12 - * dpu_core_irq_preinstall - perform pre-installation of core IRQ handler 13 13 - * @kms: MSM KMS handle 14 14 - * @return: none 15 15 - */ 16 11 void dpu_core_irq_preinstall(struct msm_kms *kms); 17 12 18 18 - /** 19 19 - * dpu_core_irq_uninstall - uninstall core IRQ handler 20 20 - * @kms: MSM KMS handle 21 21 - * @return: none 22 22 - */ 23 13 void dpu_core_irq_uninstall(struct msm_kms *kms); 24 14 25 25 - /** 26 26 - * dpu_core_irq - core IRQ handler 27 27 - * @kms: MSM KMS handle 28 28 - * @return: interrupt handling status 29 29 - */ 30 15 irqreturn_t dpu_core_irq(struct msm_kms *kms); 31 16 32 32 - /** 33 33 - * dpu_core_irq_read - IRQ helper function for reading IRQ status 34 34 - * @dpu_kms: DPU handle 35 35 - * @irq_idx: irq index 36 36 - * @return: non-zero if irq detected; otherwise no irq detected 37 37 - */ 38 17 u32 dpu_core_irq_read( 39 18 struct dpu_kms *dpu_kms, 40 19 unsigned int irq_idx); 41 20 42 42 - /** 43 43 - * dpu_core_irq_register_callback - For registering callback function on IRQ 44 44 - * interrupt 45 45 - * @dpu_kms: DPU handle 46 46 - * @irq_idx: irq index 47 47 - * @irq_cb: IRQ callback funcion. 48 48 - * @irq_arg: IRQ callback argument. 49 49 - * @return: 0 for success registering callback, otherwise failure 50 50 - * 51 51 - * This function supports registration of multiple callbacks for each interrupt. 52 52 - */ 53 21 int dpu_core_irq_register_callback( 54 22 struct dpu_kms *dpu_kms, 55 23 unsigned int irq_idx, 56 24 void (*irq_cb)(void *arg), 57 25 void *irq_arg); 58 26 59 59 - /** 60 60 - * dpu_core_irq_unregister_callback - For unregistering callback function on IRQ 61 61 - * interrupt 62 62 - * @dpu_kms: DPU handle 63 63 - * @irq_idx: irq index 64 64 - * @return: 0 for success registering callback, otherwise failure 65 65 - * 66 66 - * This function supports registration of multiple callbacks for each interrupt. 67 67 - */ 68 27 int dpu_core_irq_unregister_callback( 69 28 struct dpu_kms *dpu_kms, 70 29 unsigned int irq_idx); 71 30 72 72 - /** 73 73 - * dpu_debugfs_core_irq_init - register core irq debugfs 74 74 - * @dpu_kms: pointer to kms 75 75 - * @parent: debugfs directory root 76 76 - */ 77 31 void dpu_debugfs_core_irq_init(struct dpu_kms *dpu_kms, 78 32 struct dentry *parent); 79 33

+23

drivers/gpu/drm/msm/disp/dpu1/dpu_core_perf.c

reviewed

··· 140 140 perf->max_per_pipe_ib, perf->bw_ctl); 141 141 } 142 142 143 143 + /** 144 144 + * dpu_core_perf_crtc_check - validate performance of the given crtc state 145 145 + * @crtc: Pointer to crtc 146 146 + * @state: Pointer to new crtc state 147 147 + * return: zero if success, or error code otherwise 148 148 + */ 143 149 int dpu_core_perf_crtc_check(struct drm_crtc *crtc, 144 150 struct drm_crtc_state *state) 145 151 { ··· 307 301 return clk_rate; 308 302 } 309 303 304 304 + /** 305 305 + * dpu_core_perf_crtc_update - update performance of the given crtc 306 306 + * @crtc: Pointer to crtc 307 307 + * @params_changed: true if crtc parameters are modified 308 308 + * return: zero if success, or error code otherwise 309 309 + */ 310 310 int dpu_core_perf_crtc_update(struct drm_crtc *crtc, 311 311 int params_changed) 312 312 { ··· 458 446 .write = _dpu_core_perf_mode_write, 459 447 }; 460 448 449 449 + /** 450 450 + * dpu_core_perf_debugfs_init - initialize debugfs for core performance context 451 451 + * @dpu_kms: Pointer to the dpu_kms struct 452 452 + * @parent: Pointer to parent debugfs 453 453 + */ 461 454 int dpu_core_perf_debugfs_init(struct dpu_kms *dpu_kms, struct dentry *parent) 462 455 { 463 456 struct dpu_core_perf *perf = &dpu_kms->perf; ··· 499 482 } 500 483 #endif 501 484 485 485 + /** 486 486 + * dpu_core_perf_init - initialize the given core performance context 487 487 + * @perf: Pointer to core performance context 488 488 + * @perf_cfg: Pointer to platform performance configuration 489 489 + * @max_core_clk_rate: Maximum core clock rate 490 490 + */ 502 491 int dpu_core_perf_init(struct dpu_core_perf *perf, 503 492 const struct dpu_perf_cfg *perf_cfg, 504 493 unsigned long max_core_clk_rate)

-27

drivers/gpu/drm/msm/disp/dpu1/dpu_core_perf.h

reviewed

··· 54 54 u64 fix_core_ab_vote; 55 55 }; 56 56 57 57 - /** 58 58 - * dpu_core_perf_crtc_check - validate performance of the given crtc state 59 59 - * @crtc: Pointer to crtc 60 60 - * @state: Pointer to new crtc state 61 61 - * return: zero if success, or error code otherwise 62 62 - */ 63 57 int dpu_core_perf_crtc_check(struct drm_crtc *crtc, 64 58 struct drm_crtc_state *state); 65 59 66 66 - /** 67 67 - * dpu_core_perf_crtc_update - update performance of the given crtc 68 68 - * @crtc: Pointer to crtc 69 69 - * @params_changed: true if crtc parameters are modified 70 70 - * return: zero if success, or error code otherwise 71 71 - */ 72 60 int dpu_core_perf_crtc_update(struct drm_crtc *crtc, 73 61 int params_changed); 74 62 75 75 - /** 76 76 - * dpu_core_perf_crtc_release_bw - release bandwidth of the given crtc 77 77 - * @crtc: Pointer to crtc 78 78 - */ 79 63 void dpu_core_perf_crtc_release_bw(struct drm_crtc *crtc); 80 64 81 81 - /** 82 82 - * dpu_core_perf_init - initialize the given core performance context 83 83 - * @perf: Pointer to core performance context 84 84 - * @perf_cfg: Pointer to platform performance configuration 85 85 - * @max_core_clk_rate: Maximum core clock rate 86 86 - */ 87 65 int dpu_core_perf_init(struct dpu_core_perf *perf, 88 66 const struct dpu_perf_cfg *perf_cfg, 89 67 unsigned long max_core_clk_rate); 90 68 91 69 struct dpu_kms; 92 70 93 93 - /** 94 94 - * dpu_core_perf_debugfs_init - initialize debugfs for core performance context 95 95 - * @dpu_kms: Pointer to the dpu_kms struct 96 96 - * @debugfs_parent: Pointer to parent debugfs 97 97 - */ 98 71 int dpu_core_perf_debugfs_init(struct dpu_kms *dpu_kms, struct dentry *parent); 99 72 100 73 #endif /* _DPU_CORE_PERF_H_ */

+30 -1

drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c

reviewed

··· 572 572 spin_unlock_irqrestore(&dev->event_lock, flags); 573 573 } 574 574 575 575 + /** 576 576 + * dpu_crtc_get_intf_mode - get interface mode of the given crtc 577 577 + * @crtc: Pointert to crtc 578 578 + */ 575 579 enum dpu_intf_mode dpu_crtc_get_intf_mode(struct drm_crtc *crtc) 576 580 { 577 581 struct drm_encoder *encoder; ··· 598 594 return INTF_MODE_NONE; 599 595 } 600 596 597 597 + /** 598 598 + * dpu_crtc_vblank_callback - called on vblank irq, issues completion events 599 599 + * @crtc: Pointer to drm crtc object 600 600 + */ 601 601 void dpu_crtc_vblank_callback(struct drm_crtc *crtc) 602 602 { 603 603 struct dpu_crtc *dpu_crtc = to_dpu_crtc(crtc); ··· 712 704 kthread_queue_work(priv->event_thread[crtc_id].worker, &fevent->work); 713 705 } 714 706 707 707 + /** 708 708 + * dpu_crtc_complete_commit - callback signalling completion of current commit 709 709 + * @crtc: Pointer to drm crtc object 710 710 + */ 715 711 void dpu_crtc_complete_commit(struct drm_crtc *crtc) 716 712 { 717 713 trace_dpu_crtc_complete_commit(DRMID(crtc)); ··· 946 934 return rc; 947 935 } 948 936 937 937 + /** 938 938 + * dpu_crtc_commit_kickoff - trigger kickoff of the commit for this crtc 939 939 + * @crtc: Pointer to drm crtc object 940 940 + */ 949 941 void dpu_crtc_commit_kickoff(struct drm_crtc *crtc) 950 942 { 951 943 struct drm_encoder *encoder; ··· 1259 1243 4096); 1260 1244 } 1261 1245 1246 1246 + /** 1247 1247 + * dpu_crtc_vblank - enable or disable vblanks for this crtc 1248 1248 + * @crtc: Pointer to drm crtc object 1249 1249 + * @en: true to enable vblanks, false to disable 1250 1250 + */ 1262 1251 int dpu_crtc_vblank(struct drm_crtc *crtc, bool en) 1263 1252 { 1264 1253 struct dpu_crtc *dpu_crtc = to_dpu_crtc(crtc); ··· 1483 1462 .get_scanout_position = dpu_crtc_get_scanout_position, 1484 1463 }; 1485 1464 1486 1486 - /* initialize crtc */ 1465 1465 + /** 1466 1466 + * dpu_crtc_init - create a new crtc object 1467 1467 + * @dev: dpu device 1468 1468 + * @plane: base plane 1469 1469 + * @cursor: cursor plane 1470 1470 + * @return: new crtc object or error 1471 1471 + * 1472 1472 + * initialize CRTC 1473 1473 + */ 1487 1474 struct drm_crtc *dpu_crtc_init(struct drm_device *dev, struct drm_plane *plane, 1488 1475 struct drm_plane *cursor) 1489 1476 {

-38

drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.h

reviewed

··· 239 239 return crtc ? atomic_read(&to_dpu_crtc(crtc)->frame_pending) : -EINVAL; 240 240 } 241 241 242 242 - /** 243 243 - * dpu_crtc_vblank - enable or disable vblanks for this crtc 244 244 - * @crtc: Pointer to drm crtc object 245 245 - * @en: true to enable vblanks, false to disable 246 246 - */ 247 242 int dpu_crtc_vblank(struct drm_crtc *crtc, bool en); 248 243 249 249 - /** 250 250 - * dpu_crtc_vblank_callback - called on vblank irq, issues completion events 251 251 - * @crtc: Pointer to drm crtc object 252 252 - */ 253 244 void dpu_crtc_vblank_callback(struct drm_crtc *crtc); 254 245 255 255 - /** 256 256 - * dpu_crtc_commit_kickoff - trigger kickoff of the commit for this crtc 257 257 - * @crtc: Pointer to drm crtc object 258 258 - */ 259 246 void dpu_crtc_commit_kickoff(struct drm_crtc *crtc); 260 247 261 261 - /** 262 262 - * dpu_crtc_complete_commit - callback signalling completion of current commit 263 263 - * @crtc: Pointer to drm crtc object 264 264 - */ 265 248 void dpu_crtc_complete_commit(struct drm_crtc *crtc); 266 249 267 267 - /** 268 268 - * dpu_crtc_init - create a new crtc object 269 269 - * @dev: dpu device 270 270 - * @plane: base plane 271 271 - * @cursor: cursor plane 272 272 - * @Return: new crtc object or error 273 273 - */ 274 250 struct drm_crtc *dpu_crtc_init(struct drm_device *dev, struct drm_plane *plane, 275 251 struct drm_plane *cursor); 276 252 277 277 - /** 278 278 - * dpu_crtc_register_custom_event - api for enabling/disabling crtc event 279 279 - * @kms: Pointer to dpu_kms 280 280 - * @crtc_drm: Pointer to crtc object 281 281 - * @event: Event that client is interested 282 282 - * @en: Flag to enable/disable the event 283 283 - */ 284 284 - int dpu_crtc_register_custom_event(struct dpu_kms *kms, 285 285 - struct drm_crtc *crtc_drm, u32 event, bool en); 286 286 - 287 287 - /** 288 288 - * dpu_crtc_get_intf_mode - get interface mode of the given crtc 289 289 - * @crtc: Pointert to crtc 290 290 - */ 291 253 enum dpu_intf_mode dpu_crtc_get_intf_mode(struct drm_crtc *crtc); 292 254 293 255 /**

+179

drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c

reviewed

··· 217 217 15, 7, 13, 5, 3, 11, 1, 9, 12, 4, 14, 6, 0, 8, 2, 10 218 218 }; 219 219 220 220 + /** 221 221 + * dpu_encoder_get_drm_fmt - return DRM fourcc format 222 222 + * @phys_enc: Pointer to physical encoder structure 223 223 + */ 220 224 u32 dpu_encoder_get_drm_fmt(struct dpu_encoder_phys *phys_enc) 221 225 { 222 226 struct drm_encoder *drm_enc; ··· 239 235 return DRM_FORMAT_RGB888; 240 236 } 241 237 238 238 + /** 239 239 + * dpu_encoder_needs_periph_flush - return true if physical encoder requires 240 240 + * peripheral flush 241 241 + * @phys_enc: Pointer to physical encoder structure 242 242 + */ 242 243 bool dpu_encoder_needs_periph_flush(struct dpu_encoder_phys *phys_enc) 243 244 { 244 245 struct drm_encoder *drm_enc; ··· 262 253 msm_dp_needs_periph_flush(priv->dp[disp_info->h_tile_instance[0]], mode); 263 254 } 264 255 256 256 + /** 257 257 + * dpu_encoder_is_widebus_enabled - return bool value if widebus is enabled 258 258 + * @drm_enc: Pointer to previously created drm encoder structure 259 259 + */ 265 260 bool dpu_encoder_is_widebus_enabled(const struct drm_encoder *drm_enc) 266 261 { 267 262 const struct dpu_encoder_virt *dpu_enc; ··· 285 272 return false; 286 273 } 287 274 275 275 + /** 276 276 + * dpu_encoder_is_dsc_enabled - indicate whether dsc is enabled 277 277 + * for the encoder. 278 278 + * @drm_enc: Pointer to previously created drm encoder structure 279 279 + */ 288 280 bool dpu_encoder_is_dsc_enabled(const struct drm_encoder *drm_enc) 289 281 { 290 282 const struct dpu_encoder_virt *dpu_enc = to_dpu_encoder_virt(drm_enc); ··· 297 279 return dpu_enc->dsc ? true : false; 298 280 } 299 281 282 282 + /** 283 283 + * dpu_encoder_get_crc_values_cnt - get number of physical encoders contained 284 284 + * in virtual encoder that can collect CRC values 285 285 + * @drm_enc: Pointer to previously created drm encoder structure 286 286 + * Returns: Number of physical encoders for given drm encoder 287 287 + */ 300 288 int dpu_encoder_get_crc_values_cnt(const struct drm_encoder *drm_enc) 301 289 { 302 290 struct dpu_encoder_virt *dpu_enc; ··· 321 297 return num_intf; 322 298 } 323 299 300 300 + /** 301 301 + * dpu_encoder_setup_misr - enable misr calculations 302 302 + * @drm_enc: Pointer to previously created drm encoder structure 303 303 + */ 324 304 void dpu_encoder_setup_misr(const struct drm_encoder *drm_enc) 325 305 { 326 306 struct dpu_encoder_virt *dpu_enc; ··· 343 315 } 344 316 } 345 317 318 318 + /** 319 319 + * dpu_encoder_get_crc - get the crc value from interface blocks 320 320 + * @drm_enc: Pointer to previously created drm encoder structure 321 321 + * @crcs: array to fill with CRC data 322 322 + * @pos: offset into the @crcs array 323 323 + * Returns: 0 on success, error otherwise 324 324 + */ 346 325 int dpu_encoder_get_crc(const struct drm_encoder *drm_enc, u32 *crcs, int pos) 347 326 { 348 327 struct dpu_encoder_virt *dpu_enc; ··· 420 385 } 421 386 } 422 387 388 388 + /** 389 389 + * dpu_encoder_helper_report_irq_timeout - utility to report error that irq has 390 390 + * timed out, including reporting frame error event to crtc and debug dump 391 391 + * @phys_enc: Pointer to physical encoder structure 392 392 + * @intr_idx: Failing interrupt index 393 393 + */ 423 394 void dpu_encoder_helper_report_irq_timeout(struct dpu_encoder_phys *phys_enc, 424 395 enum dpu_intr_idx intr_idx) 425 396 { ··· 443 402 static int dpu_encoder_helper_wait_event_timeout(int32_t drm_id, 444 403 u32 irq_idx, struct dpu_encoder_wait_info *info); 445 404 405 405 + /** 406 406 + * dpu_encoder_helper_wait_for_irq - utility to wait on an irq. 407 407 + * note: will call dpu_encoder_helper_wait_for_irq on timeout 408 408 + * @phys_enc: Pointer to physical encoder structure 409 409 + * @irq_idx: IRQ index 410 410 + * @func: IRQ callback to be called in case of timeout 411 411 + * @wait_info: wait info struct 412 412 + * @return: 0 or -ERROR 413 413 + */ 446 414 int dpu_encoder_helper_wait_for_irq(struct dpu_encoder_phys *phys_enc, 447 415 unsigned int irq_idx, 448 416 void (*func)(void *arg), ··· 523 473 return ret; 524 474 } 525 475 476 476 + /** 477 477 + * dpu_encoder_get_vsync_count - get vsync count for the encoder. 478 478 + * @drm_enc: Pointer to previously created drm encoder structure 479 479 + */ 526 480 int dpu_encoder_get_vsync_count(struct drm_encoder *drm_enc) 527 481 { 528 482 struct dpu_encoder_virt *dpu_enc = to_dpu_encoder_virt(drm_enc); ··· 534 480 return phys ? atomic_read(&phys->vsync_cnt) : 0; 535 481 } 536 482 483 483 + /** 484 484 + * dpu_encoder_get_linecount - get interface line count for the encoder. 485 485 + * @drm_enc: Pointer to previously created drm encoder structure 486 486 + */ 537 487 int dpu_encoder_get_linecount(struct drm_encoder *drm_enc) 538 488 { 539 489 struct dpu_encoder_virt *dpu_enc; ··· 553 495 return linecount; 554 496 } 555 497 498 498 + /** 499 499 + * dpu_encoder_helper_split_config - split display configuration helper function 500 500 + * This helper function may be used by physical encoders to configure 501 501 + * the split display related registers. 502 502 + * @phys_enc: Pointer to physical encoder structure 503 503 + * @interface: enum dpu_intf setting 504 504 + */ 556 505 void dpu_encoder_helper_split_config( 557 506 struct dpu_encoder_phys *phys_enc, 558 507 enum dpu_intf interface) ··· 609 544 } 610 545 } 611 546 547 547 + /** 548 548 + * dpu_encoder_use_dsc_merge - returns true if the encoder uses DSC merge topology. 549 549 + * @drm_enc: Pointer to previously created drm encoder structure 550 550 + */ 612 551 bool dpu_encoder_use_dsc_merge(struct drm_encoder *drm_enc) 613 552 { 614 553 struct dpu_encoder_virt *dpu_enc = to_dpu_encoder_virt(drm_enc); ··· 629 560 return (num_dsc > 0) && (num_dsc > intf_count); 630 561 } 631 562 563 563 + /** 564 564 + * dpu_encoder_get_dsc_config - get DSC config for the DPU encoder 565 565 + * This helper function is used by physical encoder to get DSC config 566 566 + * used for this encoder. 567 567 + * @drm_enc: Pointer to encoder structure 568 568 + */ 632 569 struct drm_dsc_config *dpu_encoder_get_dsc_config(struct drm_encoder *drm_enc) 633 570 { 634 571 struct msm_drm_private *priv = drm_enc->dev->dev_private; ··· 1164 1089 return 0; 1165 1090 } 1166 1091 1092 1092 + /** 1093 1093 + * dpu_encoder_prepare_wb_job - prepare writeback job for the encoder. 1094 1094 + * @drm_enc: Pointer to previously created drm encoder structure 1095 1095 + * @job: Pointer to the current drm writeback job 1096 1096 + */ 1167 1097 void dpu_encoder_prepare_wb_job(struct drm_encoder *drm_enc, 1168 1098 struct drm_writeback_job *job) 1169 1099 { ··· 1186 1106 } 1187 1107 } 1188 1108 1109 1109 + /** 1110 1110 + * dpu_encoder_cleanup_wb_job - cleanup writeback job for the encoder. 1111 1111 + * @drm_enc: Pointer to previously created drm encoder structure 1112 1112 + * @job: Pointer to the current drm writeback job 1113 1113 + */ 1189 1114 void dpu_encoder_cleanup_wb_job(struct drm_encoder *drm_enc, 1190 1115 struct drm_writeback_job *job) 1191 1116 { ··· 1333 1248 } 1334 1249 } 1335 1250 1251 1251 + /** 1252 1252 + * dpu_encoder_virt_runtime_resume - pm runtime resume the encoder configs 1253 1253 + * @drm_enc: encoder pointer 1254 1254 + */ 1336 1255 void dpu_encoder_virt_runtime_resume(struct drm_encoder *drm_enc) 1337 1256 { 1338 1257 struct dpu_encoder_virt *dpu_enc = to_dpu_encoder_virt(drm_enc); ··· 1478 1389 return NULL; 1479 1390 } 1480 1391 1392 1392 + /** 1393 1393 + * dpu_encoder_vblank_callback - Notify virtual encoder of vblank IRQ reception 1394 1394 + * @drm_enc: Pointer to drm encoder structure 1395 1395 + * @phy_enc: Pointer to physical encoder 1396 1396 + * Note: This is called from IRQ handler context. 1397 1397 + */ 1481 1398 void dpu_encoder_vblank_callback(struct drm_encoder *drm_enc, 1482 1399 struct dpu_encoder_phys *phy_enc) 1483 1400 { ··· 1506 1411 DPU_ATRACE_END("encoder_vblank_callback"); 1507 1412 } 1508 1413 1414 1414 + /** 1415 1415 + * dpu_encoder_underrun_callback - Notify virtual encoder of underrun IRQ reception 1416 1416 + * @drm_enc: Pointer to drm encoder structure 1417 1417 + * @phy_enc: Pointer to physical encoder 1418 1418 + * Note: This is called from IRQ handler context. 1419 1419 + */ 1509 1420 void dpu_encoder_underrun_callback(struct drm_encoder *drm_enc, 1510 1421 struct dpu_encoder_phys *phy_enc) 1511 1422 { ··· 1530 1429 DPU_ATRACE_END("encoder_underrun_callback"); 1531 1430 } 1532 1431 1432 1432 + /** 1433 1433 + * dpu_encoder_assign_crtc - Link the encoder to the crtc it's assigned to 1434 1434 + * @drm_enc: encoder pointer 1435 1435 + * @crtc: crtc pointer 1436 1436 + */ 1533 1437 void dpu_encoder_assign_crtc(struct drm_encoder *drm_enc, struct drm_crtc *crtc) 1534 1438 { 1535 1439 struct dpu_encoder_virt *dpu_enc = to_dpu_encoder_virt(drm_enc); ··· 1547 1441 spin_unlock_irqrestore(&dpu_enc->enc_spinlock, lock_flags); 1548 1442 } 1549 1443 1444 1444 + /** 1445 1445 + * dpu_encoder_toggle_vblank_for_crtc - Toggles vblank interrupts on or off if 1446 1446 + * the encoder is assigned to the given crtc 1447 1447 + * @drm_enc: encoder pointer 1448 1448 + * @crtc: crtc pointer 1449 1449 + * @enable: true if vblank should be enabled 1450 1450 + */ 1550 1451 void dpu_encoder_toggle_vblank_for_crtc(struct drm_encoder *drm_enc, 1551 1452 struct drm_crtc *crtc, bool enable) 1552 1453 { ··· 1578 1465 } 1579 1466 } 1580 1467 1468 1468 + /** 1469 1469 + * dpu_encoder_frame_done_callback - Notify virtual encoder that this phys 1470 1470 + * encoder completes last request frame 1471 1471 + * @drm_enc: Pointer to drm encoder structure 1472 1472 + * @ready_phys: Pointer to physical encoder 1473 1473 + * @event: Event to process 1474 1474 + */ 1581 1475 void dpu_encoder_frame_done_callback( 1582 1476 struct drm_encoder *drm_enc, 1583 1477 struct dpu_encoder_phys *ready_phys, u32 event) ··· 1707 1587 phys->ops.trigger_start(phys); 1708 1588 } 1709 1589 1590 1590 + /** 1591 1591 + * dpu_encoder_helper_trigger_start - control start helper function 1592 1592 + * This helper function may be optionally specified by physical 1593 1593 + * encoders if they require ctl_start triggering. 1594 1594 + * @phys_enc: Pointer to physical encoder structure 1595 1595 + */ 1710 1596 void dpu_encoder_helper_trigger_start(struct dpu_encoder_phys *phys_enc) 1711 1597 { 1712 1598 struct dpu_hw_ctl *ctl; ··· 1834 1708 spin_unlock_irqrestore(&dpu_enc->enc_spinlock, lock_flags); 1835 1709 } 1836 1710 1711 1711 + /** 1712 1712 + * dpu_encoder_trigger_kickoff_pending - Clear the flush bits from previous 1713 1713 + * kickoff and trigger the ctl prepare progress for command mode display. 1714 1714 + * @drm_enc: encoder pointer 1715 1715 + */ 1837 1716 void dpu_encoder_trigger_kickoff_pending(struct drm_encoder *drm_enc) 1838 1717 { 1839 1718 struct dpu_encoder_virt *dpu_enc; ··· 1915 1784 return line_time; 1916 1785 } 1917 1786 1787 1787 + /** 1788 1788 + * dpu_encoder_vsync_time - get the time of the next vsync 1789 1789 + * @drm_enc: encoder pointer 1790 1790 + * @wakeup_time: pointer to ktime_t to write the vsync time to 1791 1791 + */ 1918 1792 int dpu_encoder_vsync_time(struct drm_encoder *drm_enc, ktime_t *wakeup_time) 1919 1793 { 1920 1794 struct drm_display_mode *mode; ··· 2066 1930 dsc, dsc_common_mode, initial_lines); 2067 1931 } 2068 1932 1933 1933 + /** 1934 1934 + * dpu_encoder_prepare_for_kickoff - schedule double buffer flip of the ctl 1935 1935 + * path (i.e. ctl flush and start) at next appropriate time. 1936 1936 + * Immediately: if no previous commit is outstanding. 1937 1937 + * Delayed: Block until next trigger can be issued. 1938 1938 + * @drm_enc: encoder pointer 1939 1939 + */ 2069 1940 void dpu_encoder_prepare_for_kickoff(struct drm_encoder *drm_enc) 2070 1941 { 2071 1942 struct dpu_encoder_virt *dpu_enc; ··· 2109 1966 dpu_encoder_prep_dsc(dpu_enc, dpu_enc->dsc); 2110 1967 } 2111 1968 1969 1969 + /** 1970 1970 + * dpu_encoder_is_valid_for_commit - check if encode has valid parameters for commit. 1971 1971 + * @drm_enc: Pointer to drm encoder structure 1972 1972 + */ 2112 1973 bool dpu_encoder_is_valid_for_commit(struct drm_encoder *drm_enc) 2113 1974 { 2114 1975 struct dpu_encoder_virt *dpu_enc; ··· 2134 1987 return true; 2135 1988 } 2136 1989 1990 1990 + /** 1991 1991 + * dpu_encoder_kickoff - trigger a double buffer flip of the ctl path 1992 1992 + * (i.e. ctl flush and start) immediately. 1993 1993 + * @drm_enc: encoder pointer 1994 1994 + */ 2137 1995 void dpu_encoder_kickoff(struct drm_encoder *drm_enc) 2138 1996 { 2139 1997 struct dpu_encoder_virt *dpu_enc; ··· 2237 2085 } 2238 2086 } 2239 2087 2088 2088 + /** 2089 2089 + * dpu_encoder_helper_phys_cleanup - helper to cleanup dpu pipeline 2090 2090 + * @phys_enc: Pointer to physical encoder structure 2091 2091 + */ 2240 2092 void dpu_encoder_helper_phys_cleanup(struct dpu_encoder_phys *phys_enc) 2241 2093 { 2242 2094 struct dpu_hw_ctl *ctl = phys_enc->hw_ctl; ··· 2324 2168 ctl->ops.clear_pending_flush(ctl); 2325 2169 } 2326 2170 2171 2171 + /** 2172 2172 + * dpu_encoder_helper_phys_setup_cdm - setup chroma down sampling block 2173 2173 + * @phys_enc: Pointer to physical encoder 2174 2174 + * @dpu_fmt: Pinter to the format description 2175 2175 + * @output_type: HDMI/WB 2176 2176 + */ 2327 2177 void dpu_encoder_helper_phys_setup_cdm(struct dpu_encoder_phys *phys_enc, 2328 2178 const struct msm_format *dpu_fmt, 2329 2179 u32 output_type) ··· 2634 2472 .debugfs_init = dpu_encoder_debugfs_init, 2635 2473 }; 2636 2474 2475 2475 + /** 2476 2476 + * dpu_encoder_init - initialize virtual encoder object 2477 2477 + * @dev: Pointer to drm device structure 2478 2478 + * @drm_enc_mode: corresponding DRM_MODE_ENCODER_* constant 2479 2479 + * @disp_info: Pointer to display information structure 2480 2480 + * Returns: Pointer to newly created drm encoder 2481 2481 + */ 2637 2482 struct drm_encoder *dpu_encoder_init(struct drm_device *dev, 2638 2483 int drm_enc_mode, 2639 2484 struct msm_display_info *disp_info) ··· 2762 2593 return ret; 2763 2594 } 2764 2595 2596 2596 + /** 2597 2597 + * dpu_encoder_get_intf_mode - get interface mode of the given encoder 2598 2598 + * @encoder: Pointer to drm encoder object 2599 2599 + */ 2765 2600 enum dpu_intf_mode dpu_encoder_get_intf_mode(struct drm_encoder *encoder) 2766 2601 { 2767 2602 struct dpu_encoder_virt *dpu_enc = NULL; ··· 2785 2612 return INTF_MODE_NONE; 2786 2613 } 2787 2614 2615 2615 + /** 2616 2616 + * dpu_encoder_helper_get_dsc - get DSC blocks mask for the DPU encoder 2617 2617 + * This helper function is used by physical encoder to get DSC blocks mask 2618 2618 + * used for this encoder. 2619 2619 + * @phys_enc: Pointer to physical encoder structure 2620 2620 + */ 2788 2621 unsigned int dpu_encoder_helper_get_dsc(struct dpu_encoder_phys *phys_enc) 2789 2622 { 2790 2623 struct drm_encoder *encoder = phys_enc->parent;

-105

drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.h

reviewed

··· 38 38 enum dpu_vsync_source vsync_source; 39 39 }; 40 40 41 41 - /** 42 42 - * dpu_encoder_assign_crtc - Link the encoder to the crtc it's assigned to 43 43 - * @encoder: encoder pointer 44 44 - * @crtc: crtc pointer 45 45 - */ 46 41 void dpu_encoder_assign_crtc(struct drm_encoder *encoder, 47 42 struct drm_crtc *crtc); 48 43 49 49 - /** 50 50 - * dpu_encoder_toggle_vblank_for_crtc - Toggles vblank interrupts on or off if 51 51 - * the encoder is assigned to the given crtc 52 52 - * @encoder: encoder pointer 53 53 - * @crtc: crtc pointer 54 54 - * @enable: true if vblank should be enabled 55 55 - */ 56 44 void dpu_encoder_toggle_vblank_for_crtc(struct drm_encoder *encoder, 57 45 struct drm_crtc *crtc, bool enable); 58 46 59 59 - /** 60 60 - * dpu_encoder_prepare_for_kickoff - schedule double buffer flip of the ctl 61 61 - * path (i.e. ctl flush and start) at next appropriate time. 62 62 - * Immediately: if no previous commit is outstanding. 63 63 - * Delayed: Block until next trigger can be issued. 64 64 - * @encoder: encoder pointer 65 65 - */ 66 47 void dpu_encoder_prepare_for_kickoff(struct drm_encoder *encoder); 67 48 68 68 - /** 69 69 - * dpu_encoder_trigger_kickoff_pending - Clear the flush bits from previous 70 70 - * kickoff and trigger the ctl prepare progress for command mode display. 71 71 - * @encoder: encoder pointer 72 72 - */ 73 49 void dpu_encoder_trigger_kickoff_pending(struct drm_encoder *encoder); 74 50 75 75 - /** 76 76 - * dpu_encoder_kickoff - trigger a double buffer flip of the ctl path 77 77 - * (i.e. ctl flush and start) immediately. 78 78 - * @encoder: encoder pointer 79 79 - */ 80 51 void dpu_encoder_kickoff(struct drm_encoder *encoder); 81 52 82 82 - /** 83 83 - * dpu_encoder_wakeup_time - get the time of the next vsync 84 84 - */ 85 53 int dpu_encoder_vsync_time(struct drm_encoder *drm_enc, ktime_t *wakeup_time); 86 54 87 55 int dpu_encoder_wait_for_commit_done(struct drm_encoder *drm_encoder); 88 56 89 57 int dpu_encoder_wait_for_tx_complete(struct drm_encoder *drm_encoder); 90 58 91 91 - /* 92 92 - * dpu_encoder_get_intf_mode - get interface mode of the given encoder 93 93 - * @encoder: Pointer to drm encoder object 94 94 - */ 95 59 enum dpu_intf_mode dpu_encoder_get_intf_mode(struct drm_encoder *encoder); 96 60 97 97 - /** 98 98 - * dpu_encoder_virt_runtime_resume - pm runtime resume the encoder configs 99 99 - * @encoder: encoder pointer 100 100 - */ 101 61 void dpu_encoder_virt_runtime_resume(struct drm_encoder *encoder); 102 62 103 103 - /** 104 104 - * dpu_encoder_init - initialize virtual encoder object 105 105 - * @dev: Pointer to drm device structure 106 106 - * @drm_enc_mode: corresponding DRM_MODE_ENCODER_* constant 107 107 - * @disp_info: Pointer to display information structure 108 108 - * Returns: Pointer to newly created drm encoder 109 109 - */ 110 63 struct drm_encoder *dpu_encoder_init(struct drm_device *dev, 111 64 int drm_enc_mode, 112 65 struct msm_display_info *disp_info); 113 66 114 114 - /** 115 115 - * dpu_encoder_set_idle_timeout - set the idle timeout for video 116 116 - * and command mode encoders. 117 117 - * @drm_enc: Pointer to previously created drm encoder structure 118 118 - * @idle_timeout: idle timeout duration in milliseconds 119 119 - */ 120 120 - void dpu_encoder_set_idle_timeout(struct drm_encoder *drm_enc, 121 121 - u32 idle_timeout); 122 122 - /** 123 123 - * dpu_encoder_get_linecount - get interface line count for the encoder. 124 124 - * @drm_enc: Pointer to previously created drm encoder structure 125 125 - */ 126 67 int dpu_encoder_get_linecount(struct drm_encoder *drm_enc); 127 68 128 128 - /** 129 129 - * dpu_encoder_get_vsync_count - get vsync count for the encoder. 130 130 - * @drm_enc: Pointer to previously created drm encoder structure 131 131 - */ 132 69 int dpu_encoder_get_vsync_count(struct drm_encoder *drm_enc); 133 70 134 134 - /** 135 135 - * dpu_encoder_is_widebus_enabled - return bool value if widebus is enabled 136 136 - * @drm_enc: Pointer to previously created drm encoder structure 137 137 - */ 138 71 bool dpu_encoder_is_widebus_enabled(const struct drm_encoder *drm_enc); 139 72 140 140 - /** 141 141 - * dpu_encoder_is_dsc_enabled - indicate whether dsc is enabled 142 142 - * for the encoder. 143 143 - * @drm_enc: Pointer to previously created drm encoder structure 144 144 - */ 145 73 bool dpu_encoder_is_dsc_enabled(const struct drm_encoder *drm_enc); 146 74 147 147 - /** 148 148 - * dpu_encoder_get_crc_values_cnt - get number of physical encoders contained 149 149 - * in virtual encoder that can collect CRC values 150 150 - * @drm_enc: Pointer to previously created drm encoder structure 151 151 - * Returns: Number of physical encoders for given drm encoder 152 152 - */ 153 75 int dpu_encoder_get_crc_values_cnt(const struct drm_encoder *drm_enc); 154 76 155 155 - /** 156 156 - * dpu_encoder_setup_misr - enable misr calculations 157 157 - * @drm_enc: Pointer to previously created drm encoder structure 158 158 - */ 159 77 void dpu_encoder_setup_misr(const struct drm_encoder *drm_encoder); 160 78 161 161 - /** 162 162 - * dpu_encoder_get_crc - get the crc value from interface blocks 163 163 - * @drm_enc: Pointer to previously created drm encoder structure 164 164 - * Returns: 0 on success, error otherwise 165 165 - */ 166 79 int dpu_encoder_get_crc(const struct drm_encoder *drm_enc, u32 *crcs, int pos); 167 80 168 168 - /** 169 169 - * dpu_encoder_use_dsc_merge - returns true if the encoder uses DSC merge topology. 170 170 - * @drm_enc: Pointer to previously created drm encoder structure 171 171 - */ 172 81 bool dpu_encoder_use_dsc_merge(struct drm_encoder *drm_enc); 173 82 174 174 - /** 175 175 - * dpu_encoder_prepare_wb_job - prepare writeback job for the encoder. 176 176 - * @drm_enc: Pointer to previously created drm encoder structure 177 177 - * @job: Pointer to the current drm writeback job 178 178 - */ 179 83 void dpu_encoder_prepare_wb_job(struct drm_encoder *drm_enc, 180 84 struct drm_writeback_job *job); 181 85 182 182 - /** 183 183 - * dpu_encoder_cleanup_wb_job - cleanup writeback job for the encoder. 184 184 - * @drm_enc: Pointer to previously created drm encoder structure 185 185 - * @job: Pointer to the current drm writeback job 186 186 - */ 187 86 void dpu_encoder_cleanup_wb_job(struct drm_encoder *drm_enc, 188 87 struct drm_writeback_job *job); 189 88 190 190 - /** 191 191 - * dpu_encoder_is_valid_for_commit - check if encode has valid parameters for commit. 192 192 - * @drm_enc: Pointer to drm encoder structure 193 193 - */ 194 89 bool dpu_encoder_is_valid_for_commit(struct drm_encoder *drm_enc); 195 90 196 91 #endif /* __DPU_ENCODER_H__ */

-90

drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys.h

reviewed

··· 279 279 s64 timeout_ms; 280 280 }; 281 281 282 282 - /** 283 283 - * dpu_encoder_phys_vid_init - Construct a new video mode physical encoder 284 284 - * @p: Pointer to init params structure 285 285 - * Return: Error code or newly allocated encoder 286 286 - */ 287 282 struct dpu_encoder_phys *dpu_encoder_phys_vid_init(struct drm_device *dev, 288 283 struct dpu_enc_phys_init_params *p); 289 284 290 290 - /** 291 291 - * dpu_encoder_phys_cmd_init - Construct a new command mode physical encoder 292 292 - * @dev: Corresponding device for devres management 293 293 - * @p: Pointer to init params structure 294 294 - * Return: Error code or newly allocated encoder 295 295 - */ 296 285 struct dpu_encoder_phys *dpu_encoder_phys_cmd_init(struct drm_device *dev, 297 286 struct dpu_enc_phys_init_params *p); 298 287 299 299 - /** 300 300 - * dpu_encoder_phys_wb_init - initialize writeback encoder 301 301 - * @dev: Corresponding device for devres management 302 302 - * @init: Pointer to init info structure with initialization params 303 303 - */ 304 288 struct dpu_encoder_phys *dpu_encoder_phys_wb_init(struct drm_device *dev, 305 289 struct dpu_enc_phys_init_params *p); 306 290 307 307 - /** 308 308 - * dpu_encoder_helper_trigger_start - control start helper function 309 309 - * This helper function may be optionally specified by physical 310 310 - * encoders if they require ctl_start triggering. 311 311 - * @phys_enc: Pointer to physical encoder structure 312 312 - */ 313 291 void dpu_encoder_helper_trigger_start(struct dpu_encoder_phys *phys_enc); 314 292 315 293 static inline enum dpu_3d_blend_mode dpu_encoder_helper_get_3d_blend_mode( ··· 309 331 return BLEND_3D_NONE; 310 332 } 311 333 312 312 - /** 313 313 - * dpu_encoder_helper_get_dsc - get DSC blocks mask for the DPU encoder 314 314 - * This helper function is used by physical encoder to get DSC blocks mask 315 315 - * used for this encoder. 316 316 - * @phys_enc: Pointer to physical encoder structure 317 317 - */ 318 334 unsigned int dpu_encoder_helper_get_dsc(struct dpu_encoder_phys *phys_enc); 319 335 320 320 - /** 321 321 - * dpu_encoder_get_dsc_config - get DSC config for the DPU encoder 322 322 - * This helper function is used by physical encoder to get DSC config 323 323 - * used for this encoder. 324 324 - * @drm_enc: Pointer to encoder structure 325 325 - */ 326 336 struct drm_dsc_config *dpu_encoder_get_dsc_config(struct drm_encoder *drm_enc); 327 337 328 328 - /** 329 329 - * dpu_encoder_get_drm_fmt - return DRM fourcc format 330 330 - * @phys_enc: Pointer to physical encoder structure 331 331 - */ 332 338 u32 dpu_encoder_get_drm_fmt(struct dpu_encoder_phys *phys_enc); 333 339 334 334 - /** 335 335 - * dpu_encoder_needs_periph_flush - return true if physical encoder requires 336 336 - * peripheral flush 337 337 - * @phys_enc: Pointer to physical encoder structure 338 338 - */ 339 340 bool dpu_encoder_needs_periph_flush(struct dpu_encoder_phys *phys_enc); 340 341 341 341 - /** 342 342 - * dpu_encoder_helper_split_config - split display configuration helper function 343 343 - * This helper function may be used by physical encoders to configure 344 344 - * the split display related registers. 345 345 - * @phys_enc: Pointer to physical encoder structure 346 346 - * @interface: enum dpu_intf setting 347 347 - */ 348 342 void dpu_encoder_helper_split_config( 349 343 struct dpu_encoder_phys *phys_enc, 350 344 enum dpu_intf interface); 351 345 352 352 - /** 353 353 - * dpu_encoder_helper_report_irq_timeout - utility to report error that irq has 354 354 - * timed out, including reporting frame error event to crtc and debug dump 355 355 - * @phys_enc: Pointer to physical encoder structure 356 356 - * @intr_idx: Failing interrupt index 357 357 - */ 358 346 void dpu_encoder_helper_report_irq_timeout(struct dpu_encoder_phys *phys_enc, 359 347 enum dpu_intr_idx intr_idx); 360 348 361 361 - /** 362 362 - * dpu_encoder_helper_wait_for_irq - utility to wait on an irq. 363 363 - * note: will call dpu_encoder_helper_wait_for_irq on timeout 364 364 - * @phys_enc: Pointer to physical encoder structure 365 365 - * @irq: IRQ index 366 366 - * @func: IRQ callback to be called in case of timeout 367 367 - * @wait_info: wait info struct 368 368 - * @Return: 0 or -ERROR 369 369 - */ 370 349 int dpu_encoder_helper_wait_for_irq(struct dpu_encoder_phys *phys_enc, 371 350 unsigned int irq, 372 351 void (*func)(void *arg), 373 352 struct dpu_encoder_wait_info *wait_info); 374 353 375 375 - /** 376 376 - * dpu_encoder_helper_phys_cleanup - helper to cleanup dpu pipeline 377 377 - * @phys_enc: Pointer to physical encoder structure 378 378 - */ 379 354 void dpu_encoder_helper_phys_cleanup(struct dpu_encoder_phys *phys_enc); 380 355 381 381 - /** 382 382 - * dpu_encoder_helper_phys_setup_cdm - setup chroma down sampling block 383 383 - * @phys_enc: Pointer to physical encoder 384 384 - * @output_type: HDMI/WB 385 385 - */ 386 356 void dpu_encoder_helper_phys_setup_cdm(struct dpu_encoder_phys *phys_enc, 387 357 const struct msm_format *dpu_fmt, 388 358 u32 output_type); 389 359 390 390 - /** 391 391 - * dpu_encoder_vblank_callback - Notify virtual encoder of vblank IRQ reception 392 392 - * @drm_enc: Pointer to drm encoder structure 393 393 - * @phys_enc: Pointer to physical encoder 394 394 - * Note: This is called from IRQ handler context. 395 395 - */ 396 360 void dpu_encoder_vblank_callback(struct drm_encoder *drm_enc, 397 361 struct dpu_encoder_phys *phy_enc); 398 362 399 399 - /** dpu_encoder_underrun_callback - Notify virtual encoder of underrun IRQ reception 400 400 - * @drm_enc: Pointer to drm encoder structure 401 401 - * @phys_enc: Pointer to physical encoder 402 402 - * Note: This is called from IRQ handler context. 403 403 - */ 404 363 void dpu_encoder_underrun_callback(struct drm_encoder *drm_enc, 405 364 struct dpu_encoder_phys *phy_enc); 406 365 407 407 - /** dpu_encoder_frame_done_callback -- Notify virtual encoder that this phys encoder completes last request frame 408 408 - * @drm_enc: Pointer to drm encoder structure 409 409 - * @phys_enc: Pointer to physical encoder 410 410 - * @event: Event to process 411 411 - */ 412 366 void dpu_encoder_frame_done_callback( 413 367 struct drm_encoder *drm_enc, 414 368 struct dpu_encoder_phys *ready_phys, u32 event);

+6

drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c

reviewed

··· 720 720 ops->get_line_count = dpu_encoder_phys_cmd_get_line_count; 721 721 } 722 722 723 723 + /** 724 724 + * dpu_encoder_phys_cmd_init - Construct a new command mode physical encoder 725 725 + * @dev: Corresponding device for devres management 726 726 + * @p: Pointer to init params structure 727 727 + * Return: Error code or newly allocated encoder 728 728 + */ 723 729 struct dpu_encoder_phys *dpu_encoder_phys_cmd_init(struct drm_device *dev, 724 730 struct dpu_enc_phys_init_params *p) 725 731 {

+6

drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c

reviewed

··· 746 746 ops->get_frame_count = dpu_encoder_phys_vid_get_frame_count; 747 747 } 748 748 749 749 + /** 750 750 + * dpu_encoder_phys_vid_init - Construct a new video mode physical encoder 751 751 + * @dev: Corresponding device for devres management 752 752 + * @p: Pointer to init params structure 753 753 + * Return: Error code or newly allocated encoder 754 754 + */ 749 755 struct dpu_encoder_phys *dpu_encoder_phys_vid_init(struct drm_device *dev, 750 756 struct dpu_enc_phys_init_params *p) 751 757 {

+9 -2

drivers/gpu/drm/msm/disp/dpu1/dpu_formats.c

reviewed

··· 241 241 return 0; 242 242 } 243 243 244 244 - /* 245 245 - * dpu_format_populate_addrs - populate non-address part of the layout based on 244 244 + /** 245 245 + * dpu_format_populate_plane_sizes - populate non-address part of the layout based on 246 246 * fb, and format found in the fb 247 247 * @fb: framebuffer pointer 248 248 * @layout: format layout structure to populate ··· 366 366 layout->plane_addr[i] = msm_framebuffer_iova(fb, aspace, i); 367 367 } 368 368 369 369 + /** 370 370 + * dpu_format_populate_addrs - populate buffer addresses based on 371 371 + * mmu, fb, and format found in the fb 372 372 + * @aspace: address space pointer 373 373 + * @fb: framebuffer pointer 374 374 + * @layout: format layout structure to populate 375 375 + */ 369 376 void dpu_format_populate_addrs(struct msm_gem_address_space *aspace, 370 377 struct drm_framebuffer *fb, 371 378 struct dpu_hw_fmt_layout *layout)

-7

drivers/gpu/drm/msm/disp/dpu1/dpu_formats.h

reviewed

··· 31 31 return false; 32 32 } 33 33 34 34 - /** 35 35 - * dpu_format_populate_addrs - populate buffer addresses based on 36 36 - * mmu, fb, and format found in the fb 37 37 - * @aspace: address space pointer 38 38 - * @fb: framebuffer pointer 39 39 - * @fmtl: format layout structure to populate 40 40 - */ 41 34 void dpu_format_populate_addrs(struct msm_gem_address_space *aspace, 42 35 struct drm_framebuffer *fb, 43 36 struct dpu_hw_fmt_layout *layout);

+8

drivers/gpu/drm/msm/disp/dpu1/dpu_hw_cdm.c

reviewed

··· 222 222 DPU_REG_WRITE(c, CDM_MUX, mux_cfg); 223 223 } 224 224 225 225 + /** 226 226 + * dpu_hw_cdm_init - initializes the cdm hw driver object. 227 227 + * should be called once before accessing every cdm. 228 228 + * @dev: DRM device handle 229 229 + * @cfg: CDM catalog entry for which driver object is required 230 230 + * @addr : mapped register io address of MDSS 231 231 + * @mdss_rev: mdss hw core revision 232 232 + */ 225 233 struct dpu_hw_cdm *dpu_hw_cdm_init(struct drm_device *dev, 226 234 const struct dpu_cdm_cfg *cfg, void __iomem *addr, 227 235 const struct dpu_mdss_version *mdss_rev)

-8

drivers/gpu/drm/msm/disp/dpu1/dpu_hw_cdm.h

reviewed

··· 122 122 struct dpu_hw_cdm_ops ops; 123 123 }; 124 124 125 125 - /** 126 126 - * dpu_hw_cdm_init - initializes the cdm hw driver object. 127 127 - * should be called once before accessing every cdm. 128 128 - * @dev: DRM device handle 129 129 - * @cdm: CDM catalog entry for which driver object is required 130 130 - * @addr : mapped register io address of MDSS 131 131 - * @mdss_rev: mdss hw core revision 132 132 - */ 133 125 struct dpu_hw_cdm *dpu_hw_cdm_init(struct drm_device *dev, 134 126 const struct dpu_cdm_cfg *cdm, void __iomem *addr, 135 127 const struct dpu_mdss_version *mdss_rev);

+9

drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c

reviewed

··· 736 736 ops->set_active_pipes = dpu_hw_ctl_set_fetch_pipe_active; 737 737 }; 738 738 739 739 + /** 740 740 + * dpu_hw_ctl_init() - Initializes the ctl_path hw driver object. 741 741 + * Should be called before accessing any ctl_path register. 742 742 + * @dev: Corresponding device for devres management 743 743 + * @cfg: ctl_path catalog entry for which driver object is required 744 744 + * @addr: mapped register io address of MDP 745 745 + * @mixer_count: Number of mixers in @mixer 746 746 + * @mixer: Pointer to an array of Layer Mixers defined in the catalog 747 747 + */ 739 748 struct dpu_hw_ctl *dpu_hw_ctl_init(struct drm_device *dev, 740 749 const struct dpu_ctl_cfg *cfg, 741 750 void __iomem *addr,

-9

drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.h

reviewed

··· 294 294 return container_of(hw, struct dpu_hw_ctl, base); 295 295 } 296 296 297 297 - /** 298 298 - * dpu_hw_ctl_init() - Initializes the ctl_path hw driver object. 299 299 - * Should be called before accessing any ctl_path register. 300 300 - * @dev: Corresponding device for devres management 301 301 - * @cfg: ctl_path catalog entry for which driver object is required 302 302 - * @addr: mapped register io address of MDP 303 303 - * @mixer_count: Number of mixers in @mixer 304 304 - * @mixer: Pointer to an array of Layer Mixers defined in the catalog 305 305 - */ 306 297 struct dpu_hw_ctl *dpu_hw_ctl_init(struct drm_device *dev, 307 298 const struct dpu_ctl_cfg *cfg, 308 299 void __iomem *addr,

+7

drivers/gpu/drm/msm/disp/dpu1/dpu_hw_dsc.c

reviewed

··· 190 190 ops->dsc_bind_pingpong_blk = dpu_hw_dsc_bind_pingpong_blk; 191 191 }; 192 192 193 193 + /** 194 194 + * dpu_hw_dsc_init() - Initializes the DSC hw driver object. 195 195 + * @dev: Corresponding device for devres management 196 196 + * @cfg: DSC catalog entry for which driver object is required 197 197 + * @addr: Mapped register io address of MDP 198 198 + * Return: Error code or allocated dpu_hw_dsc context 199 199 + */ 193 200 struct dpu_hw_dsc *dpu_hw_dsc_init(struct drm_device *dev, 194 201 const struct dpu_dsc_cfg *cfg, 195 202 void __iomem *addr)

-14

drivers/gpu/drm/msm/disp/dpu1/dpu_hw_dsc.h

reviewed

··· 62 62 struct dpu_hw_dsc_ops ops; 63 63 }; 64 64 65 65 - /** 66 66 - * dpu_hw_dsc_init() - Initializes the DSC hw driver object. 67 67 - * @dev: Corresponding device for devres management 68 68 - * @cfg: DSC catalog entry for which driver object is required 69 69 - * @addr: Mapped register io address of MDP 70 70 - * Return: Error code or allocated dpu_hw_dsc context 71 71 - */ 72 65 struct dpu_hw_dsc *dpu_hw_dsc_init(struct drm_device *dev, 73 66 const struct dpu_dsc_cfg *cfg, 74 67 void __iomem *addr); 75 68 76 76 - /** 77 77 - * dpu_hw_dsc_init_1_2() - initializes the v1.2 DSC hw driver object 78 78 - * @dev: Corresponding device for devres management 79 79 - * @cfg: DSC catalog entry for which driver object is required 80 80 - * @addr: Mapped register io address of MDP 81 81 - * Returns: Error code or allocated dpu_hw_dsc context 82 82 - */ 83 69 struct dpu_hw_dsc *dpu_hw_dsc_init_1_2(struct drm_device *dev, 84 70 const struct dpu_dsc_cfg *cfg, 85 71 void __iomem *addr);

+7

drivers/gpu/drm/msm/disp/dpu1/dpu_hw_dsc_1_2.c

reviewed

··· 369 369 ops->dsc_bind_pingpong_blk = dpu_hw_dsc_bind_pingpong_blk_1_2; 370 370 } 371 371 372 372 + /** 373 373 + * dpu_hw_dsc_init_1_2() - initializes the v1.2 DSC hw driver object 374 374 + * @dev: Corresponding device for devres management 375 375 + * @cfg: DSC catalog entry for which driver object is required 376 376 + * @addr: Mapped register io address of MDP 377 377 + * Returns: Error code or allocated dpu_hw_dsc context 378 378 + */ 372 379 struct dpu_hw_dsc *dpu_hw_dsc_init_1_2(struct drm_device *dev, 373 380 const struct dpu_dsc_cfg *cfg, 374 381 void __iomem *addr)

+8

drivers/gpu/drm/msm/disp/dpu1/dpu_hw_dspp.c

reviewed

··· 70 70 c->ops.setup_pcc = dpu_setup_dspp_pcc; 71 71 } 72 72 73 73 + /** 74 74 + * dpu_hw_dspp_init() - Initializes the DSPP hw driver object. 75 75 + * should be called once before accessing every DSPP. 76 76 + * @dev: Corresponding device for devres management 77 77 + * @cfg: DSPP catalog entry for which driver object is required 78 78 + * @addr: Mapped register io address of MDP 79 79 + * Return: pointer to structure or ERR_PTR 80 80 + */ 73 81 struct dpu_hw_dspp *dpu_hw_dspp_init(struct drm_device *dev, 74 82 const struct dpu_dspp_cfg *cfg, 75 83 void __iomem *addr)

-8

drivers/gpu/drm/msm/disp/dpu1/dpu_hw_dspp.h

reviewed

··· 78 78 return container_of(hw, struct dpu_hw_dspp, base); 79 79 } 80 80 81 81 - /** 82 82 - * dpu_hw_dspp_init() - Initializes the DSPP hw driver object. 83 83 - * should be called once before accessing every DSPP. 84 84 - * @dev: Corresponding device for devres management 85 85 - * @cfg: DSPP catalog entry for which driver object is required 86 86 - * @addr: Mapped register io address of MDP 87 87 - * Return: pointer to structure or ERR_PTR 88 88 - */ 89 81 struct dpu_hw_dspp *dpu_hw_dspp_init(struct drm_device *dev, 90 82 const struct dpu_dspp_cfg *cfg, 91 83 void __iomem *addr);

+52

drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.c

reviewed

··· 237 237 irq_entry->cb(irq_entry->arg); 238 238 } 239 239 240 240 + /** 241 241 + * dpu_core_irq - core IRQ handler 242 242 + * @kms: MSM KMS handle 243 243 + * @return: interrupt handling status 244 244 + */ 240 245 irqreturn_t dpu_core_irq(struct msm_kms *kms) 241 246 { 242 247 struct dpu_kms *dpu_kms = to_dpu_kms(kms); ··· 447 442 wmb(); 448 443 } 449 444 445 445 + /** 446 446 + * dpu_core_irq_read - IRQ helper function for reading IRQ status 447 447 + * @dpu_kms: DPU handle 448 448 + * @irq_idx: irq index 449 449 + * @return: non-zero if irq detected; otherwise no irq detected 450 450 + */ 450 451 u32 dpu_core_irq_read(struct dpu_kms *dpu_kms, 451 452 unsigned int irq_idx) 452 453 { ··· 487 476 return intr_status; 488 477 } 489 478 479 479 + /** 480 480 + * dpu_hw_intr_init(): Initializes the interrupts hw object 481 481 + * @dev: Corresponding device for devres management 482 482 + * @addr: mapped register io address of MDP 483 483 + * @m: pointer to MDSS catalog data 484 484 + */ 490 485 struct dpu_hw_intr *dpu_hw_intr_init(struct drm_device *dev, 491 486 void __iomem *addr, 492 487 const struct dpu_mdss_cfg *m) ··· 534 517 return intr; 535 518 } 536 519 520 520 + /** 521 521 + * dpu_core_irq_register_callback - For registering callback function on IRQ 522 522 + * interrupt 523 523 + * @dpu_kms: DPU handle 524 524 + * @irq_idx: irq index 525 525 + * @irq_cb: IRQ callback function. 526 526 + * @irq_arg: IRQ callback argument. 527 527 + * @return: 0 for success registering callback, otherwise failure 528 528 + * 529 529 + * This function supports registration of multiple callbacks for each interrupt. 530 530 + */ 537 531 int dpu_core_irq_register_callback(struct dpu_kms *dpu_kms, 538 532 unsigned int irq_idx, 539 533 void (*irq_cb)(void *arg), ··· 595 567 return 0; 596 568 } 597 569 570 570 + /** 571 571 + * dpu_core_irq_unregister_callback - For unregistering callback function on IRQ 572 572 + * interrupt 573 573 + * @dpu_kms: DPU handle 574 574 + * @irq_idx: irq index 575 575 + * @return: 0 for success registering callback, otherwise failure 576 576 + * 577 577 + * This function supports registration of multiple callbacks for each interrupt. 578 578 + */ 598 579 int dpu_core_irq_unregister_callback(struct dpu_kms *dpu_kms, 599 580 unsigned int irq_idx) 600 581 { ··· 665 628 666 629 DEFINE_SHOW_ATTRIBUTE(dpu_debugfs_core_irq); 667 630 631 631 + /** 632 632 + * dpu_debugfs_core_irq_init - register core irq debugfs 633 633 + * @dpu_kms: pointer to kms 634 634 + * @parent: debugfs directory root 635 635 + */ 668 636 void dpu_debugfs_core_irq_init(struct dpu_kms *dpu_kms, 669 637 struct dentry *parent) 670 638 { ··· 678 636 } 679 637 #endif 680 638 639 639 + /** 640 640 + * dpu_core_irq_preinstall - perform pre-installation of core IRQ handler 641 641 + * @kms: MSM KMS handle 642 642 + * @return: none 643 643 + */ 681 644 void dpu_core_irq_preinstall(struct msm_kms *kms) 682 645 { 683 646 struct dpu_kms *dpu_kms = to_dpu_kms(kms); ··· 700 653 } 701 654 } 702 655 656 656 + /** 657 657 + * dpu_core_irq_uninstall - uninstall core IRQ handler 658 658 + * @kms: MSM KMS handle 659 659 + * @return: none 660 660 + */ 703 661 void dpu_core_irq_uninstall(struct msm_kms *kms) 704 662 { 705 663 struct dpu_kms *dpu_kms = to_dpu_kms(kms);

-6

drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.h

reviewed

··· 68 68 struct dpu_hw_intr_entry irq_tbl[DPU_NUM_IRQS]; 69 69 }; 70 70 71 71 - /** 72 72 - * dpu_hw_intr_init(): Initializes the interrupts hw object 73 73 - * @dev: Corresponding device for devres management 74 74 - * @addr: mapped register io address of MDP 75 75 - * @m: pointer to MDSS catalog data 76 76 - */ 77 71 struct dpu_hw_intr *dpu_hw_intr_init(struct drm_device *dev, 78 72 void __iomem *addr, 79 73 const struct dpu_mdss_cfg *m);

+8

drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c

reviewed

··· 547 547 DPU_REG_WRITE(&intf->hw, INTF_CONFIG2, intf_cfg2); 548 548 } 549 549 550 550 + /** 551 551 + * dpu_hw_intf_init() - Initializes the INTF driver for the passed 552 552 + * interface catalog entry. 553 553 + * @dev: Corresponding device for devres management 554 554 + * @cfg: interface catalog entry for which driver object is required 555 555 + * @addr: mapped register io address of MDP 556 556 + * @mdss_rev: dpu core's major and minor versions 557 557 + */ 550 558 struct dpu_hw_intf *dpu_hw_intf_init(struct drm_device *dev, 551 559 const struct dpu_intf_cfg *cfg, 552 560 void __iomem *addr,

-8

drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.h

reviewed

··· 130 130 struct dpu_hw_intf_ops ops; 131 131 }; 132 132 133 133 - /** 134 134 - * dpu_hw_intf_init() - Initializes the INTF driver for the passed 135 135 - * interface catalog entry. 136 136 - * @dev: Corresponding device for devres management 137 137 - * @cfg: interface catalog entry for which driver object is required 138 138 - * @addr: mapped register io address of MDP 139 139 - * @mdss_rev: dpu core's major and minor versions 140 140 - */ 141 133 struct dpu_hw_intf *dpu_hw_intf_init(struct drm_device *dev, 142 134 const struct dpu_intf_cfg *cfg, 143 135 void __iomem *addr,

+7

drivers/gpu/drm/msm/disp/dpu1/dpu_hw_lm.c

reviewed

··· 158 158 ops->collect_misr = dpu_hw_lm_collect_misr; 159 159 } 160 160 161 161 + /** 162 162 + * dpu_hw_lm_init() - Initializes the mixer hw driver object. 163 163 + * should be called once before accessing every mixer. 164 164 + * @dev: Corresponding device for devres management 165 165 + * @cfg: mixer catalog entry for which driver object is required 166 166 + * @addr: mapped register io address of MDP 167 167 + */ 161 168 struct dpu_hw_mixer *dpu_hw_lm_init(struct drm_device *dev, 162 169 const struct dpu_lm_cfg *cfg, 163 170 void __iomem *addr)

-7

drivers/gpu/drm/msm/disp/dpu1/dpu_hw_lm.h

reviewed

··· 93 93 return container_of(hw, struct dpu_hw_mixer, base); 94 94 } 95 95 96 96 - /** 97 97 - * dpu_hw_lm_init() - Initializes the mixer hw driver object. 98 98 - * should be called once before accessing every mixer. 99 99 - * @dev: Corresponding device for devres management 100 100 - * @cfg: mixer catalog entry for which driver object is required 101 101 - * @addr: mapped register io address of MDP 102 102 - */ 103 96 struct dpu_hw_mixer *dpu_hw_lm_init(struct drm_device *dev, 104 97 const struct dpu_lm_cfg *cfg, 105 98 void __iomem *addr);

+8

drivers/gpu/drm/msm/disp/dpu1/dpu_hw_merge3d.c

reviewed

··· 39 39 c->ops.setup_3d_mode = dpu_hw_merge_3d_setup_3d_mode; 40 40 }; 41 41 42 42 + /** 43 43 + * dpu_hw_merge_3d_init() - Initializes the merge_3d driver for the passed 44 44 + * merge3d catalog entry. 45 45 + * @dev: Corresponding device for devres management 46 46 + * @cfg: Pingpong catalog entry for which driver object is required 47 47 + * @addr: Mapped register io address of MDP 48 48 + * Return: Error code or allocated dpu_hw_merge_3d context 49 49 + */ 42 50 struct dpu_hw_merge_3d *dpu_hw_merge_3d_init(struct drm_device *dev, 43 51 const struct dpu_merge_3d_cfg *cfg, 44 52 void __iomem *addr)

-8

drivers/gpu/drm/msm/disp/dpu1/dpu_hw_merge3d.h

reviewed

··· 45 45 return container_of(hw, struct dpu_hw_merge_3d, base); 46 46 } 47 47 48 48 - /** 49 49 - * dpu_hw_merge_3d_init() - Initializes the merge_3d driver for the passed 50 50 - * merge3d catalog entry. 51 51 - * @dev: Corresponding device for devres management 52 52 - * @cfg: Pingpong catalog entry for which driver object is required 53 53 - * @addr: Mapped register io address of MDP 54 54 - * Return: Error code or allocated dpu_hw_merge_3d context 55 55 - */ 56 48 struct dpu_hw_merge_3d *dpu_hw_merge_3d_init(struct drm_device *dev, 57 49 const struct dpu_merge_3d_cfg *cfg, 58 50 void __iomem *addr);

+9

drivers/gpu/drm/msm/disp/dpu1/dpu_hw_pingpong.c

reviewed

··· 283 283 return 0; 284 284 } 285 285 286 286 + /** 287 287 + * dpu_hw_pingpong_init() - initializes the pingpong driver for the passed 288 288 + * pingpong catalog entry. 289 289 + * @dev: Corresponding device for devres management 290 290 + * @cfg: Pingpong catalog entry for which driver object is required 291 291 + * @addr: Mapped register io address of MDP 292 292 + * @mdss_rev: dpu core's major and minor versions 293 293 + * Return: Error code or allocated dpu_hw_pingpong context 294 294 + */ 286 295 struct dpu_hw_pingpong *dpu_hw_pingpong_init(struct drm_device *dev, 287 296 const struct dpu_pingpong_cfg *cfg, 288 297 void __iomem *addr,

-9

drivers/gpu/drm/msm/disp/dpu1/dpu_hw_pingpong.h

reviewed

··· 118 118 return container_of(hw, struct dpu_hw_pingpong, base); 119 119 } 120 120 121 121 - /** 122 122 - * dpu_hw_pingpong_init() - initializes the pingpong driver for the passed 123 123 - * pingpong catalog entry. 124 124 - * @dev: Corresponding device for devres management 125 125 - * @cfg: Pingpong catalog entry for which driver object is required 126 126 - * @addr: Mapped register io address of MDP 127 127 - * @mdss_rev: dpu core's major and minor versions 128 128 - * Return: Error code or allocated dpu_hw_pingpong context 129 129 - */ 130 121 struct dpu_hw_pingpong *dpu_hw_pingpong_init(struct drm_device *dev, 131 122 const struct dpu_pingpong_cfg *cfg, 132 123 void __iomem *addr,

+9

drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c

reviewed

··· 672 672 } 673 673 #endif 674 674 675 675 + /** 676 676 + * dpu_hw_sspp_init() - Initializes the sspp hw driver object. 677 677 + * Should be called once before accessing every pipe. 678 678 + * @dev: Corresponding device for devres management 679 679 + * @cfg: Pipe catalog entry for which driver object is required 680 680 + * @addr: Mapped register io address of MDP 681 681 + * @mdss_data: UBWC / MDSS configuration data 682 682 + * @mdss_rev: dpu core's major and minor versions 683 683 + */ 675 684 struct dpu_hw_sspp *dpu_hw_sspp_init(struct drm_device *dev, 676 685 const struct dpu_sspp_cfg *cfg, 677 686 void __iomem *addr,

+1 -9

drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.h

reviewed

··· 319 319 }; 320 320 321 321 struct dpu_kms; 322 322 - /** 323 323 - * dpu_hw_sspp_init() - Initializes the sspp hw driver object. 324 324 - * Should be called once before accessing every pipe. 325 325 - * @dev: Corresponding device for devres management 326 326 - * @cfg: Pipe catalog entry for which driver object is required 327 327 - * @addr: Mapped register io address of MDP 328 328 - * @mdss_data: UBWC / MDSS configuration data 329 329 - * @mdss_rev: dpu core's major and minor versions 330 330 - */ 322 322 + 331 323 struct dpu_hw_sspp *dpu_hw_sspp_init(struct drm_device *dev, 332 324 const struct dpu_sspp_cfg *cfg, 333 325 void __iomem *addr,

+7

drivers/gpu/drm/msm/disp/dpu1/dpu_hw_top.c

reviewed

··· 284 284 ops->intf_audio_select = dpu_hw_intf_audio_select; 285 285 } 286 286 287 287 + /** 288 288 + * dpu_hw_mdptop_init - initializes the top driver for the passed config 289 289 + * @dev: Corresponding device for devres management 290 290 + * @cfg: MDP TOP configuration from catalog 291 291 + * @addr: Mapped register io address of MDP 292 292 + * @mdss_rev: dpu core's major and minor versions 293 293 + */ 287 294 struct dpu_hw_mdp *dpu_hw_mdptop_init(struct drm_device *dev, 288 295 const struct dpu_mdp_cfg *cfg, 289 296 void __iomem *addr,

-9

drivers/gpu/drm/msm/disp/dpu1/dpu_hw_top.h

reviewed

··· 157 157 struct dpu_hw_mdp_ops ops; 158 158 }; 159 159 160 160 - /** 161 161 - * dpu_hw_mdptop_init - initializes the top driver for the passed config 162 162 - * @dev: Corresponding device for devres management 163 163 - * @cfg: MDP TOP configuration from catalog 164 164 - * @addr: Mapped register io address of MDP 165 165 - * @mdss_rev: dpu core's major and minor versions 166 166 - */ 167 160 struct dpu_hw_mdp *dpu_hw_mdptop_init(struct drm_device *dev, 168 161 const struct dpu_mdp_cfg *cfg, 169 162 void __iomem *addr, 170 163 const struct dpu_mdss_version *mdss_rev); 171 171 - 172 172 - void dpu_hw_mdp_destroy(struct dpu_hw_mdp *mdp); 173 164 174 165 #endif /*_DPU_HW_TOP_H */

+7

drivers/gpu/drm/msm/disp/dpu1/dpu_hw_vbif.c

reviewed

··· 213 213 ops->set_write_gather_en = dpu_hw_set_write_gather_en; 214 214 } 215 215 216 216 + /** 217 217 + * dpu_hw_vbif_init() - Initializes the VBIF driver for the passed 218 218 + * VBIF catalog entry. 219 219 + * @dev: Corresponding device for devres management 220 220 + * @cfg: VBIF catalog entry for which driver object is required 221 221 + * @addr: Mapped register io address of MDSS 222 222 + */ 216 223 struct dpu_hw_vbif *dpu_hw_vbif_init(struct drm_device *dev, 217 224 const struct dpu_vbif_cfg *cfg, 218 225 void __iomem *addr)

-7

drivers/gpu/drm/msm/disp/dpu1/dpu_hw_vbif.h

reviewed

··· 105 105 struct dpu_hw_vbif_ops ops; 106 106 }; 107 107 108 108 - /** 109 109 - * dpu_hw_vbif_init() - Initializes the VBIF driver for the passed 110 110 - * VBIF catalog entry. 111 111 - * @dev: Corresponding device for devres management 112 112 - * @cfg: VBIF catalog entry for which driver object is required 113 113 - * @addr: Mapped register io address of MDSS 114 114 - */ 115 108 struct dpu_hw_vbif *dpu_hw_vbif_init(struct drm_device *dev, 116 109 const struct dpu_vbif_cfg *cfg, 117 110 void __iomem *addr);

+8

drivers/gpu/drm/msm/disp/dpu1/dpu_hw_wb.c

reviewed

··· 213 213 ops->setup_clk_force_ctrl = dpu_hw_wb_setup_clk_force_ctrl; 214 214 } 215 215 216 216 + /** 217 217 + * dpu_hw_wb_init() - Initializes the writeback hw driver object. 218 218 + * @dev: Corresponding device for devres management 219 219 + * @cfg: wb_path catalog entry for which driver object is required 220 220 + * @addr: mapped register io address of MDP 221 221 + * @mdss_rev: dpu core's major and minor versions 222 222 + * Return: Error code or allocated dpu_hw_wb context 223 223 + */ 216 224 struct dpu_hw_wb *dpu_hw_wb_init(struct drm_device *dev, 217 225 const struct dpu_wb_cfg *cfg, 218 226 void __iomem *addr,

-8

drivers/gpu/drm/msm/disp/dpu1/dpu_hw_wb.h

reviewed

··· 75 75 struct dpu_hw_wb_ops ops; 76 76 }; 77 77 78 78 - /** 79 79 - * dpu_hw_wb_init() - Initializes the writeback hw driver object. 80 80 - * @dev: Corresponding device for devres management 81 81 - * @cfg: wb_path catalog entry for which driver object is required 82 82 - * @addr: mapped register io address of MDP 83 83 - * @mdss_rev: dpu core's major and minor versions 84 84 - * Return: Error code or allocated dpu_hw_wb context 85 85 - */ 86 78 struct dpu_hw_wb *dpu_hw_wb_init(struct drm_device *dev, 87 79 const struct dpu_wb_cfg *cfg, 88 80 void __iomem *addr,

+22

drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c

reviewed

··· 230 230 } 231 231 DEFINE_SHOW_ATTRIBUTE(dpu_regset32); 232 232 233 233 + /** 234 234 + * dpu_debugfs_create_regset32 - Create register read back file for debugfs 235 235 + * 236 236 + * This function is almost identical to the standard debugfs_create_regset32() 237 237 + * function, with the main difference being that a list of register 238 238 + * names/offsets do not need to be provided. The 'read' function simply outputs 239 239 + * sequential register values over a specified range. 240 240 + * 241 241 + * @name: File name within debugfs 242 242 + * @mode: File mode within debugfs 243 243 + * @parent: Parent directory entry within debugfs, can be NULL 244 244 + * @offset: sub-block offset 245 245 + * @length: sub-block length, in bytes 246 246 + * @dpu_kms: pointer to dpu kms structure 247 247 + */ 233 248 void dpu_debugfs_create_regset32(const char *name, umode_t mode, 234 249 void *parent, 235 250 uint32_t offset, uint32_t length, struct dpu_kms *dpu_kms) ··· 1075 1060 return 0; 1076 1061 } 1077 1062 1063 1063 + /** 1064 1064 + * dpu_kms_get_clk_rate() - get the clock rate 1065 1065 + * @dpu_kms: pointer to dpu_kms structure 1066 1066 + * @clock_name: clock name to get the rate 1067 1067 + * 1068 1068 + * Return: current clock rate 1069 1069 + */ 1078 1070 unsigned long dpu_kms_get_clk_rate(struct dpu_kms *dpu_kms, char *clock_name) 1079 1071 { 1080 1072 struct clk *clk;

-34

drivers/gpu/drm/msm/disp/dpu1/dpu_kms.h

reviewed

··· 145 145 * @dpu_debugfs_create_regset32: Create 32-bit register dump file 146 146 */ 147 147 148 148 - /** 149 149 - * dpu_debugfs_create_regset32 - Create register read back file for debugfs 150 150 - * 151 151 - * This function is almost identical to the standard debugfs_create_regset32() 152 152 - * function, with the main difference being that a list of register 153 153 - * names/offsets do not need to be provided. The 'read' function simply outputs 154 154 - * sequential register values over a specified range. 155 155 - * 156 156 - * @name: File name within debugfs 157 157 - * @mode: File mode within debugfs 158 158 - * @parent: Parent directory entry within debugfs, can be NULL 159 159 - * @offset: sub-block offset 160 160 - * @length: sub-block length, in bytes 161 161 - * @dpu_kms: pointer to dpu kms structure 162 162 - */ 163 148 void dpu_debugfs_create_regset32(const char *name, umode_t mode, 164 149 void *parent, 165 150 uint32_t offset, uint32_t length, struct dpu_kms *dpu_kms); 166 166 - 167 167 - /** 168 168 - * dpu_debugfs_get_root - Return root directory entry for KMS's debugfs 169 169 - * 170 170 - * The return value should be passed as the 'parent' argument to subsequent 171 171 - * debugfs create calls. 172 172 - * 173 173 - * @dpu_kms: Pointer to DPU's KMS structure 174 174 - * 175 175 - * Return: dentry pointer for DPU's debugfs location 176 176 - */ 177 177 - void *dpu_debugfs_get_root(struct dpu_kms *dpu_kms); 178 151 179 152 /** 180 153 * DPU info management functions ··· 162 189 int dpu_enable_vblank(struct msm_kms *kms, struct drm_crtc *crtc); 163 190 void dpu_disable_vblank(struct msm_kms *kms, struct drm_crtc *crtc); 164 191 165 165 - /** 166 166 - * dpu_kms_get_clk_rate() - get the clock rate 167 167 - * @dpu_kms: pointer to dpu_kms structure 168 168 - * @clock_name: clock name to get the rate 169 169 - * 170 170 - * Return: current clock rate 171 171 - */ 172 192 unsigned long dpu_kms_get_clk_rate(struct dpu_kms *dpu_kms, char *clock_name); 173 193 174 194 #endif /* __dpu_kms_H__ */

+13 -1

drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c

reviewed

··· 1041 1041 1042 1042 } 1043 1043 1044 1044 + /** 1045 1045 + * dpu_plane_flush - final plane operations before commit flush 1046 1046 + * @plane: Pointer to drm plane structure 1047 1047 + */ 1044 1048 void dpu_plane_flush(struct drm_plane *plane) 1045 1049 { 1046 1050 struct dpu_plane *pdpu; ··· 1433 1429 .atomic_update = dpu_plane_atomic_update, 1434 1430 }; 1435 1431 1436 1436 - /* initialize plane */ 1432 1432 + /** 1433 1433 + * dpu_plane_init - create new dpu plane for the given pipe 1434 1434 + * @dev: Pointer to DRM device 1435 1435 + * @pipe: dpu hardware pipe identifier 1436 1436 + * @type: Plane type - PRIMARY/OVERLAY/CURSOR 1437 1437 + * @possible_crtcs: bitmask of crtc that can be attached to the given pipe 1438 1438 + * 1439 1439 + * Initialize the plane. 1440 1440 + */ 1437 1441 struct drm_plane *dpu_plane_init(struct drm_device *dev, 1438 1442 uint32_t pipe, enum drm_plane_type type, 1439 1443 unsigned long possible_crtcs)

-26

drivers/gpu/drm/msm/disp/dpu1/dpu_plane.h

reviewed

··· 54 54 #define to_dpu_plane_state(x) \ 55 55 container_of(x, struct dpu_plane_state, base) 56 56 57 57 - /** 58 58 - * dpu_plane_flush - final plane operations before commit flush 59 59 - * @plane: Pointer to drm plane structure 60 60 - */ 61 57 void dpu_plane_flush(struct drm_plane *plane); 62 58 63 63 - /** 64 64 - * dpu_plane_set_error: enable/disable error condition 65 65 - * @plane: pointer to drm_plane structure 66 66 - */ 67 59 void dpu_plane_set_error(struct drm_plane *plane, bool error); 68 60 69 69 - /** 70 70 - * dpu_plane_init - create new dpu plane for the given pipe 71 71 - * @dev: Pointer to DRM device 72 72 - * @pipe: dpu hardware pipe identifier 73 73 - * @type: Plane type - PRIMARY/OVERLAY/CURSOR 74 74 - * @possible_crtcs: bitmask of crtc that can be attached to the given pipe 75 75 - * 76 76 - */ 77 61 struct drm_plane *dpu_plane_init(struct drm_device *dev, 78 62 uint32_t pipe, enum drm_plane_type type, 79 63 unsigned long possible_crtcs); 80 80 - 81 81 - /** 82 82 - * dpu_plane_color_fill - enables color fill on plane 83 83 - * @plane: Pointer to DRM plane object 84 84 - * @color: RGB fill color value, [23..16] Blue, [15..8] Green, [7..0] Red 85 85 - * @alpha: 8-bit fill alpha value, 255 selects 100% alpha 86 86 - * Returns: 0 on success 87 87 - */ 88 88 - int dpu_plane_color_fill(struct drm_plane *plane, 89 89 - uint32_t color, uint32_t alpha); 90 64 91 65 #ifdef CONFIG_DEBUG_FS 92 66 void dpu_plane_danger_signal_ctrl(struct drm_plane *plane, bool enable);

+46

drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c

reviewed

··· 34 34 struct msm_display_topology topology; 35 35 }; 36 36 37 37 + /** 38 38 + * dpu_rm_init - Read hardware catalog and create reservation tracking objects 39 39 + * for all HW blocks. 40 40 + * @dev: Corresponding device for devres management 41 41 + * @rm: DPU Resource Manager handle 42 42 + * @cat: Pointer to hardware catalog 43 43 + * @mdss_data: Pointer to MDSS / UBWC configuration 44 44 + * @mmio: mapped register io address of MDP 45 45 + * @return: 0 on Success otherwise -ERROR 46 46 + */ 37 47 int dpu_rm_init(struct drm_device *dev, 38 48 struct dpu_rm *rm, 39 49 const struct dpu_mdss_cfg *cat, ··· 651 641 } 652 642 } 653 643 644 644 + /** 645 645 + * dpu_rm_release - Given the encoder for the display chain, release any 646 646 + * HW blocks previously reserved for that use case. 647 647 + * @global_state: resources shared across multiple kms objects 648 648 + * @enc: DRM Encoder handle 649 649 + * @return: 0 on Success otherwise -ERROR 650 650 + */ 654 651 void dpu_rm_release(struct dpu_global_state *global_state, 655 652 struct drm_encoder *enc) 656 653 { ··· 674 657 _dpu_rm_clear_mapping(&global_state->cdm_to_enc_id, 1, enc->base.id); 675 658 } 676 659 660 660 + /** 661 661 + * dpu_rm_reserve - Given a CRTC->Encoder->Connector display chain, analyze 662 662 + * the use connections and user requirements, specified through related 663 663 + * topology control properties, and reserve hardware blocks to that 664 664 + * display chain. 665 665 + * HW blocks can then be accessed through dpu_rm_get_* functions. 666 666 + * HW Reservations should be released via dpu_rm_release_hw. 667 667 + * @rm: DPU Resource Manager handle 668 668 + * @global_state: resources shared across multiple kms objects 669 669 + * @enc: DRM Encoder handle 670 670 + * @crtc_state: Proposed Atomic DRM CRTC State handle 671 671 + * @topology: Pointer to topology info for the display 672 672 + * @return: 0 on Success otherwise -ERROR 673 673 + */ 677 674 int dpu_rm_reserve( 678 675 struct dpu_rm *rm, 679 676 struct dpu_global_state *global_state, ··· 725 694 return ret; 726 695 } 727 696 697 697 + /** 698 698 + * dpu_rm_get_assigned_resources - Get hw resources of the given type that are 699 699 + * assigned to this encoder 700 700 + * @rm: DPU Resource Manager handle 701 701 + * @global_state: resources shared across multiple kms objects 702 702 + * @enc_id: encoder id requesting for allocation 703 703 + * @type: resource type to return data for 704 704 + * @blks: pointer to the array to be filled by HW resources 705 705 + * @blks_size: size of the @blks array 706 706 + */ 728 707 int dpu_rm_get_assigned_resources(struct dpu_rm *rm, 729 708 struct dpu_global_state *global_state, uint32_t enc_id, 730 709 enum dpu_hw_blk_type type, struct dpu_hw_blk **blks, int blks_size) ··· 813 772 } 814 773 815 774 775 775 + /** 776 776 + * dpu_rm_print_state - output the RM private state 777 777 + * @p: DRM printer 778 778 + * @global_state: global state 779 779 + */ 816 780 void dpu_rm_print_state(struct drm_printer *p, 817 781 const struct dpu_global_state *global_state) 818 782 {

-38

drivers/gpu/drm/msm/disp/dpu1/dpu_rm.h

reviewed

··· 53 53 bool needs_cdm; 54 54 }; 55 55 56 56 - /** 57 57 - * dpu_rm_init - Read hardware catalog and create reservation tracking objects 58 58 - * for all HW blocks. 59 59 - * @dev: Corresponding device for devres management 60 60 - * @rm: DPU Resource Manager handle 61 61 - * @cat: Pointer to hardware catalog 62 62 - * @mdss_data: Pointer to MDSS / UBWC configuration 63 63 - * @mmio: mapped register io address of MDP 64 64 - * @Return: 0 on Success otherwise -ERROR 65 65 - */ 66 56 int dpu_rm_init(struct drm_device *dev, 67 57 struct dpu_rm *rm, 68 58 const struct dpu_mdss_cfg *cat, 69 59 const struct msm_mdss_data *mdss_data, 70 60 void __iomem *mmio); 71 61 72 72 - /** 73 73 - * dpu_rm_reserve - Given a CRTC->Encoder->Connector display chain, analyze 74 74 - * the use connections and user requirements, specified through related 75 75 - * topology control properties, and reserve hardware blocks to that 76 76 - * display chain. 77 77 - * HW blocks can then be accessed through dpu_rm_get_* functions. 78 78 - * HW Reservations should be released via dpu_rm_release_hw. 79 79 - * @rm: DPU Resource Manager handle 80 80 - * @drm_enc: DRM Encoder handle 81 81 - * @crtc_state: Proposed Atomic DRM CRTC State handle 82 82 - * @topology: Pointer to topology info for the display 83 83 - * @Return: 0 on Success otherwise -ERROR 84 84 - */ 85 62 int dpu_rm_reserve(struct dpu_rm *rm, 86 63 struct dpu_global_state *global_state, 87 64 struct drm_encoder *drm_enc, 88 65 struct drm_crtc_state *crtc_state, 89 66 struct msm_display_topology topology); 90 67 91 91 - /** 92 92 - * dpu_rm_reserve - Given the encoder for the display chain, release any 93 93 - * HW blocks previously reserved for that use case. 94 94 - * @rm: DPU Resource Manager handle 95 95 - * @enc: DRM Encoder handle 96 96 - * @Return: 0 on Success otherwise -ERROR 97 97 - */ 98 68 void dpu_rm_release(struct dpu_global_state *global_state, 99 69 struct drm_encoder *enc); 100 70 101 101 - /** 102 102 - * Get hw resources of the given type that are assigned to this encoder. 103 103 - */ 104 71 int dpu_rm_get_assigned_resources(struct dpu_rm *rm, 105 72 struct dpu_global_state *global_state, uint32_t enc_id, 106 73 enum dpu_hw_blk_type type, struct dpu_hw_blk **blks, int blks_size); 107 74 108 108 - /** 109 109 - * dpu_rm_print_state - output the RM private state 110 110 - * @p: DRM printer 111 111 - * @global_state: global state 112 112 - */ 113 75 void dpu_rm_print_state(struct drm_printer *p, 114 76 const struct dpu_global_state *global_state); 115 77

+13

drivers/gpu/drm/msm/disp/dpu1/dpu_vbif.c

reviewed

··· 204 204 vbif->ops.set_halt_ctrl(vbif, params->xin_id, false); 205 205 } 206 206 207 207 + /** 208 208 + * dpu_vbif_set_qos_remap - set QoS priority level remap 209 209 + * @dpu_kms: DPU handler 210 210 + * @params: Pointer to QoS configuration parameters 211 211 + */ 207 212 void dpu_vbif_set_qos_remap(struct dpu_kms *dpu_kms, 208 213 struct dpu_vbif_set_qos_params *params) 209 214 { ··· 250 245 } 251 246 } 252 247 248 248 + /** 249 249 + * dpu_vbif_clear_errors - clear any vbif errors 250 250 + * @dpu_kms: DPU handler 251 251 + */ 253 252 void dpu_vbif_clear_errors(struct dpu_kms *dpu_kms) 254 253 { 255 254 struct dpu_hw_vbif *vbif; ··· 271 262 } 272 263 } 273 264 265 265 + /** 266 266 + * dpu_vbif_init_memtypes - initialize xin memory types for vbif 267 267 + * @dpu_kms: DPU handler 268 268 + */ 274 269 void dpu_vbif_init_memtypes(struct dpu_kms *dpu_kms) 275 270 { 276 271 struct dpu_hw_vbif *vbif;

-18

drivers/gpu/drm/msm/disp/dpu1/dpu_vbif.h

reviewed

··· 38 38 bool is_rt; 39 39 }; 40 40 41 41 - /** 42 42 - * dpu_vbif_set_ot_limit - set OT limit for vbif client 43 43 - * @dpu_kms: DPU handler 44 44 - * @params: Pointer to OT configuration parameters 45 45 - */ 46 41 void dpu_vbif_set_ot_limit(struct dpu_kms *dpu_kms, 47 42 struct dpu_vbif_set_ot_params *params); 48 43 49 49 - /** 50 50 - * dpu_vbif_set_qos_remap - set QoS priority level remap 51 51 - * @dpu_kms: DPU handler 52 52 - * @params: Pointer to QoS configuration parameters 53 53 - */ 54 44 void dpu_vbif_set_qos_remap(struct dpu_kms *dpu_kms, 55 45 struct dpu_vbif_set_qos_params *params); 56 46 57 57 - /** 58 58 - * dpu_vbif_clear_errors - clear any vbif errors 59 59 - * @dpu_kms: DPU handler 60 60 - */ 61 47 void dpu_vbif_clear_errors(struct dpu_kms *dpu_kms); 62 48 63 63 - /** 64 64 - * dpu_vbif_init_memtypes - initialize xin memory types for vbif 65 65 - * @dpu_kms: DPU handler 66 66 - */ 67 49 void dpu_vbif_init_memtypes(struct dpu_kms *dpu_kms); 68 50 69 51 void dpu_debugfs_vbif_init(struct dpu_kms *dpu_kms, struct dentry *debugfs_root);