Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
Merge tag 'mfd-next-5.15' of git://git.kernel.org/pub/scm/linux/kernel/git/lee/mfd
Pull MFD updates from Lee Jones:
"Core Frameworks:
- Add support for registering devices via MFD cells to Simple MFD (I2C)
New Drivers:
- Add support for Renesas Synchronization Management Unit (SMU)
New Device Support:
- Add support for N5010 to Intel M10 BMC
- Add support for Cannon Lake to Intel LPSS ACPI
- Add support for Samsung SSG{1,2} to ST-Ericsson's U8500 family
- Add support for TQMx110EB and TQMxE40x to TQ-Systems PLD TQMx86
New Functionality:
- Add support for GPIO to Intel LPC ICH
- Add support for Reset to Texas Instruments TPS65086
Fix-ups:
- Trivial, sorting, whitespace, renaming, etc; mt6360-core, db8500-prcmu-regs, tqmx86
- Device Tree fiddling; syscon, axp20x, qcom,pm8008, ti,tps65086, brcm,cru
- Use proper APIs for IRQ map resolution; ab8500-core, stmpe, tc3589x, wm8994-irq
- Pass 'supplied-from' property through axp288_fuel_gauge via swnode
- Remove unused file entry; MAINTAINERS
- Make interrupt line optional; tps65086
- Rename db8500-cpuidle driver symbol; db8500-prcmu
- Remove support for unused hardware; tqmx86
- Provide a standard LPC clock frequency for unknown boards; tqmx86
- Remove unused code; ti_am335x_tscadc
- Use of_iomap() instead of ioremap(); syscon
Bug Fixes:
- Clear GPIO IRQ resource flags when no IRQ is set; tqmx86
- Fix incorrect/misleading frequencies; db8500-prcmu
- Mitigate namespace clash with other GPIOBASE users"
* tag 'mfd-next-5.15' of git://git.kernel.org/pub/scm/linux/kernel/git/lee/mfd: (31 commits)
mfd: lpc_sch: Rename GPIOBASE to prevent build error
mfd: syscon: Use of_iomap() instead of ioremap()
dt-bindings: mfd: Add Broadcom CRU
mfd: ti_am335x_tscadc: Delete superfluous error message
mfd: tqmx86: Assume 24MHz LPC clock for unknown boards
mfd: tqmx86: Add support for TQ-Systems DMI IDs
mfd: tqmx86: Add support for TQMx110EB and TQMxE40x
mfd: tqmx86: Fix typo in "platform"
mfd: tqmx86: Remove incorrect TQMx90UC board ID
mfd: tqmx86: Clear GPIO IRQ resource when no IRQ is set
mfd: simple-mfd-i2c: Add support for registering devices via MFD cells
mfd/cpuidle: ux500: Rename driver symbol
mfd: tps65086: Add cell entry for reset driver
mfd: tps65086: Make interrupt line optional
dt-bindings: mfd: Convert tps65086.txt to YAML
MAINTAINERS: Adjust ARM/NOMADIK/Ux500 ARCHITECTURES to file renaming
mfd: db8500-prcmu: Handle missing FW variant
mfd: db8500-prcmu: Rename register header
mfd: axp20x: Add supplied-from property to axp288_fuel_gauge cell
mfd: Don't use irq_create_mapping() to resolve a mapping
...
+1906
-120
+2
-1
Documentation/devicetree/bindings/mfd/axp20x.txt
+2
-1
Documentation/devicetree/bindings/mfd/axp20x.txt
···
26
26
* "x-powers,axp803"
27
27
* "x-powers,axp806"
28
28
* "x-powers,axp805", "x-powers,axp806"
29
+
* "x-powers,axp305", "x-powers,axp805", "x-powers,axp806"
29
30
* "x-powers,axp809"
30
31
* "x-powers,axp813"
31
32
- reg: The I2C slave address or RSB hardware address for the AXP chip
32
-
- interrupts: SoC NMI / GPIO interrupt connected to the PMIC's IRQ pin
33
33
- interrupt-controller: The PMIC has its own internal IRQs
34
34
- #interrupt-cells: Should be set to 1
35
35
···
43
43
AXP20x/LDO3: software-based implementation
44
44
45
45
Optional properties:
46
+
- interrupts: SoC NMI / GPIO interrupt connected to the PMIC's IRQ pin
46
47
- x-powers,dcdc-freq: defines the work frequency of DC-DC in KHz
47
48
AXP152/20X: range: 750-1875, Default: 1.5 MHz
48
49
AXP22X/8XX: range: 1800-4050, Default: 3 MHz
+86
Documentation/devicetree/bindings/mfd/brcm,cru.yaml
+86
Documentation/devicetree/bindings/mfd/brcm,cru.yaml
···
1
+
# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
2
+
%YAML 1.2
3
+
---
4
+
$id: http://devicetree.org/schemas/mfd/brcm,cru.yaml#
5
+
$schema: http://devicetree.org/meta-schemas/core.yaml#
6
+
7
+
title: Broadcom CRU
8
+
9
+
maintainers:
10
+
- Rafał Miłecki <rafal@milecki.pl>
11
+
12
+
description: |
13
+
Broadcom CRU ("Clock and Reset Unit" or "Central Resource Unit") is a hardware
14
+
block grouping smaller blocks. On Broadcom Northstar platform it contains e.g.
15
+
clocks, pinctrl, USB PHY and thermal.
16
+
17
+
properties:
18
+
compatible:
19
+
items:
20
+
- enum:
21
+
- brcm,ns-cru
22
+
- const: simple-mfd
23
+
24
+
reg:
25
+
description: CRU registers
26
+
27
+
ranges: true
28
+
29
+
"#address-cells":
30
+
const: 1
31
+
32
+
"#size-cells":
33
+
const: 1
34
+
35
+
pinctrl:
36
+
$ref: ../pinctrl/brcm,ns-pinmux.yaml
37
+
38
+
patternProperties:
39
+
'^clock-controller@[a-f0-9]+$':
40
+
$ref: ../clock/brcm,iproc-clocks.yaml
41
+
42
+
'^thermal@[a-f0-9]+$':
43
+
$ref: ../thermal/brcm,ns-thermal.yaml
44
+
45
+
additionalProperties: false
46
+
47
+
required:
48
+
- reg
49
+
50
+
examples:
51
+
- |
52
+
cru-bus@1800c100 {
53
+
compatible = "brcm,ns-cru", "simple-mfd";
54
+
reg = <0x1800c100 0x1d0>;
55
+
ranges;
56
+
#address-cells = <1>;
57
+
#size-cells = <1>;
58
+
59
+
clock-controller@100 {
60
+
#clock-cells = <1>;
61
+
compatible = "brcm,nsp-lcpll0";
62
+
reg = <0x100 0x14>;
63
+
clocks = <&osc>;
64
+
clock-output-names = "lcpll0", "pcie_phy", "sdio", "ddr_phy";
65
+
};
66
+
67
+
clock-controller@140 {
68
+
#clock-cells = <1>;
69
+
compatible = "brcm,nsp-genpll";
70
+
reg = <0x140 0x24>;
71
+
clocks = <&osc>;
72
+
clock-output-names = "genpll", "phy", "ethernetclk", "usbclk",
73
+
"iprocfast", "sata1", "sata2";
74
+
};
75
+
76
+
pinctrl {
77
+
compatible = "brcm,bcm4708-pinmux";
78
+
offset = <0x1c0>;
79
+
};
80
+
81
+
thermal@2c0 {
82
+
compatible = "brcm,ns-thermal";
83
+
reg = <0x2c0 0x10>;
84
+
#thermal-sensor-cells = <0>;
85
+
};
86
+
};
+10
-3
Documentation/devicetree/bindings/mfd/qcom,pm8008.yaml
+10
-3
Documentation/devicetree/bindings/mfd/qcom,pm8008.yaml
···
53
53
54
54
properties:
55
55
compatible:
56
-
const: qcom,pm8008-gpio
56
+
items:
57
+
- const: qcom,pm8008-gpio
58
+
- const: qcom,spmi-gpio
57
59
58
60
reg:
59
61
description: Peripheral address of one of the two GPIO peripherals.
60
62
maxItems: 1
61
63
62
64
gpio-controller: true
65
+
66
+
gpio-ranges:
67
+
maxItems: 1
63
68
64
69
interrupt-controller: true
65
70
···
80
75
- gpio-controller
81
76
- interrupt-controller
82
77
- "#gpio-cells"
78
+
- gpio-ranges
83
79
- "#interrupt-cells"
84
80
85
81
additionalProperties: false
···
113
107
interrupt-parent = <&tlmm>;
114
108
interrupts = <32 IRQ_TYPE_EDGE_RISING>;
115
109
116
-
gpio@c000 {
117
-
compatible = "qcom,pm8008-gpio";
110
+
pm8008_gpios: gpio@c000 {
111
+
compatible = "qcom,pm8008-gpio", "qcom,spmi-gpio";
118
112
reg = <0xc000>;
119
113
gpio-controller;
114
+
gpio-ranges = <&pm8008_gpios 0 0 2>;
120
115
#gpio-cells = <2>;
121
116
interrupt-controller;
122
117
#interrupt-cells = <2>;
+3
Documentation/devicetree/bindings/mfd/syscon.yaml
+3
Documentation/devicetree/bindings/mfd/syscon.yaml
···
45
45
- microchip,sparx5-cpu-syscon
46
46
- mstar,msc313-pmsleep
47
47
- rockchip,px30-qos
48
+
- rockchip,rk3036-qos
48
49
- rockchip,rk3066-qos
50
+
- rockchip,rk3228-qos
49
51
- rockchip,rk3288-qos
50
52
- rockchip,rk3399-qos
53
+
- rockchip,rk3568-qos
51
54
- samsung,exynos3-sysreg
52
55
- samsung,exynos4-sysreg
53
56
- samsung,exynos5-sysreg
+124
Documentation/devicetree/bindings/mfd/ti,tps65086.yaml
+124
Documentation/devicetree/bindings/mfd/ti,tps65086.yaml
···
1
+
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2
+
%YAML 1.2
3
+
---
4
+
$id: http://devicetree.org/schemas/mfd/ti,tps65086.yaml#
5
+
$schema: http://devicetree.org/meta-schemas/core.yaml#
6
+
7
+
title: TPS65086 Power Management Integrated Circuit (PMIC)
8
+
9
+
maintainers:
10
+
- Emil Renner Berthing <kernel@esmil.dk>
11
+
12
+
properties:
13
+
compatible:
14
+
const: ti,tps65086
15
+
16
+
reg:
17
+
const: 0x5e
18
+
description: I2C slave address
19
+
20
+
interrupts:
21
+
maxItems: 1
22
+
23
+
interrupt-controller: true
24
+
25
+
'#interrupt-cells':
26
+
const: 2
27
+
description: |
28
+
The first cell is the IRQ number. The second cell is the flags,
29
+
encoded as trigger masks from ../interrupt-controller/interrupts.txt.
30
+
31
+
gpio-controller: true
32
+
33
+
'#gpio-cells':
34
+
const: 2
35
+
description: |
36
+
The first cell is the pin number and the second cell is used to specify
37
+
flags. See ../gpio/gpio.txt for more information.
38
+
39
+
regulators:
40
+
type: object
41
+
description: |
42
+
List of child nodes that specify the regulator initialization data.
43
+
Child nodes must be named after their hardware counterparts:
44
+
buck[1-6], ldoa[1-3], swa1, swb[1-2], and vtt.
45
+
Each child node is defined using the standard binding for regulators and
46
+
the optional regulator properties defined below.
47
+
48
+
patternProperties:
49
+
"^buck[1-6]$":
50
+
type: object
51
+
$ref: ../regulator/regulator.yaml
52
+
53
+
properties:
54
+
regulator-name: true
55
+
regulator-boot-on: true
56
+
regulator-always-on: true
57
+
regulator-min-microvolt: true
58
+
regulator-max-microvolt: true
59
+
ti,regulator-step-size-25mv:
60
+
type: boolean
61
+
description: |
62
+
Set this if the regulator is factory set with a 25mv step voltage
63
+
mapping.
64
+
ti,regulator-decay:
65
+
type: boolean
66
+
description: |
67
+
Set this if the output needs to decay, default is for the output
68
+
to slew down.
69
+
70
+
additionalProperties: false
71
+
72
+
"^(ldoa[1-3]|swa1|swb[1-2]|vtt)$":
73
+
type: object
74
+
$ref: ../regulator/regulator.yaml
75
+
76
+
properties:
77
+
regulator-name: true
78
+
regulator-boot-on: true
79
+
regulator-always-on: true
80
+
regulator-min-microvolt: true
81
+
regulator-max-microvolt: true
82
+
83
+
additionalProperties: false
84
+
85
+
additionalProperties: false
86
+
87
+
required:
88
+
- compatible
89
+
- reg
90
+
- gpio-controller
91
+
- '#gpio-cells'
92
+
- regulators
93
+
94
+
examples:
95
+
- |
96
+
#include <dt-bindings/interrupt-controller/irq.h>
97
+
i2c0 {
98
+
#address-cells = <1>;
99
+
#size-cells = <0>;
100
+
101
+
pmic: pmic@5e {
102
+
compatible = "ti,tps65086";
103
+
reg = <0x5e>;
104
+
interrupt-parent = <&gpio1>;
105
+
interrupts = <28 IRQ_TYPE_LEVEL_LOW>;
106
+
interrupt-controller;
107
+
#interrupt-cells = <2>;
108
+
gpio-controller;
109
+
#gpio-cells = <2>;
110
+
111
+
regulators {
112
+
buck1 {
113
+
regulator-name = "vcc1";
114
+
regulator-min-microvolt = <1600000>;
115
+
regulator-max-microvolt = <1600000>;
116
+
regulator-boot-on;
117
+
ti,regulator-decay;
118
+
ti,regulator-step-size-25mv;
119
+
};
120
+
};
121
+
};
122
+
};
123
+
124
+
...
-54
Documentation/devicetree/bindings/mfd/tps65086.txt
-54
Documentation/devicetree/bindings/mfd/tps65086.txt
···
1
-
* TPS65086 Power Management Integrated Circuit (PMIC) bindings
2
-
3
-
Required properties:
4
-
- compatible : Should be "ti,tps65086".
5
-
- reg : I2C slave address.
6
-
- interrupts : The interrupt line the device is connected to.
7
-
- interrupt-controller : Marks the device node as an interrupt controller.
8
-
- #interrupt-cells : The number of cells to describe an IRQ, should be 2.
9
-
The first cell is the IRQ number.
10
-
The second cell is the flags, encoded as trigger
11
-
masks from ../interrupt-controller/interrupts.txt.
12
-
- gpio-controller : Marks the device node as a GPIO Controller.
13
-
- #gpio-cells : Should be two. The first cell is the pin number and
14
-
the second cell is used to specify flags.
15
-
See ../gpio/gpio.txt for more information.
16
-
- regulators: : List of child nodes that specify the regulator
17
-
initialization data. Child nodes must be named
18
-
after their hardware counterparts: buck[1-6],
19
-
ldoa[1-3], swa1, swb[1-2], and vtt. Each child
20
-
node is defined using the standard binding for
21
-
regulators and the optional regulator properties
22
-
defined below.
23
-
24
-
Optional regulator properties:
25
-
- ti,regulator-step-size-25mv : This is applicable for buck[1-6], set this
26
-
if the regulator is factory set with a 25mv
27
-
step voltage mapping.
28
-
- ti,regulator-decay : This is applicable for buck[1-6], set this if
29
-
the output needs to decay, default is for
30
-
the output to slew down.
31
-
32
-
Example:
33
-
34
-
pmic: tps65086@5e {
35
-
compatible = "ti,tps65086";
36
-
reg = <0x5e>;
37
-
interrupt-parent = <&gpio1>;
38
-
interrupts = <28 IRQ_TYPE_LEVEL_LOW>;
39
-
interrupt-controller;
40
-
#interrupt-cells = <2>;
41
-
gpio-controller;
42
-
#gpio-cells = <2>;
43
-
44
-
regulators {
45
-
buck1 {
46
-
regulator-name = "vcc1";
47
-
regulator-min-microvolt = <1600000>;
48
-
regulator-max-microvolt = <1600000>;
49
-
regulator-boot-on;
50
-
ti,regulator-decay;
51
-
ti,regulator-step-size-25mv;
52
-
};
53
-
};
54
-
};
-1
MAINTAINERS
-1
MAINTAINERS
+2
-1
drivers/clk/ux500/u8500_of_clk.c
+2
-1
drivers/clk/ux500/u8500_of_clk.c
···
99
99
if (fw_version != NULL) {
100
100
switch (fw_version->project) {
101
101
case PRCMU_FW_PROJECT_U8500_C2:
102
-
case PRCMU_FW_PROJECT_U8500_MBL:
102
+
case PRCMU_FW_PROJECT_U8500_SSG1:
103
103
case PRCMU_FW_PROJECT_U8520:
104
104
case PRCMU_FW_PROJECT_U8420:
105
105
case PRCMU_FW_PROJECT_U8420_SYSCLK:
106
+
case PRCMU_FW_PROJECT_U8500_SSG2:
106
107
sgaclk_parent = "soc0_pll";
107
108
break;
108
109
default:
+1
-1
drivers/cpuidle/cpuidle-ux500.c
+1
-1
drivers/cpuidle/cpuidle-ux500.c
+28
drivers/mfd/Kconfig
+28
drivers/mfd/Kconfig
···
2199
2199
additional drivers must be enabled in order to use the functionality
2200
2200
of the device.
2201
2201
2202
+
config MFD_RSMU_I2C
2203
+
tristate "Renesas Synchronization Management Unit with I2C"
2204
+
depends on I2C && OF
2205
+
select MFD_CORE
2206
+
select REGMAP_I2C
2207
+
help
2208
+
Support for the Renesas Synchronization Management Unit, such as
2209
+
Clockmatrix and 82P33XXX series. This option supports I2C as
2210
+
the control interface.
2211
+
2212
+
This driver provides common support for accessing the device.
2213
+
Additional drivers must be enabled in order to use the functionality
2214
+
of the device.
2215
+
2216
+
config MFD_RSMU_SPI
2217
+
tristate "Renesas Synchronization Management Unit with SPI"
2218
+
depends on SPI && OF
2219
+
select MFD_CORE
2220
+
select REGMAP_SPI
2221
+
help
2222
+
Support for the Renesas Synchronization Management Unit, such as
2223
+
Clockmatrix and 82P33XXX series. This option supports SPI as
2224
+
the control interface.
2225
+
2226
+
This driver provides common support for accessing the device.
2227
+
Additional drivers must be enabled in order to use the functionality
2228
+
of the device.
2229
+
2202
2230
endmenu
2203
2231
endif
+5
drivers/mfd/Makefile
+5
drivers/mfd/Makefile
···
273
273
274
274
obj-$(CONFIG_MFD_ATC260X) += atc260x-core.o
275
275
obj-$(CONFIG_MFD_ATC260X_I2C) += atc260x-i2c.o
276
+
277
+
rsmu-i2c-objs := rsmu_core.o rsmu_i2c.o
278
+
rsmu-spi-objs := rsmu_core.o rsmu_spi.o
279
+
obj-$(CONFIG_MFD_RSMU_I2C) += rsmu-i2c.o
280
+
obj-$(CONFIG_MFD_RSMU_SPI) += rsmu-spi.o
+1
-1
drivers/mfd/ab8500-core.c
+1
-1
drivers/mfd/ab8500-core.c
+15
-1
drivers/mfd/axp20x.c
+15
-1
drivers/mfd/axp20x.c
···
125
125
126
126
static const struct regmap_range axp288_volatile_ranges[] = {
127
127
regmap_reg_range(AXP20X_PWR_INPUT_STATUS, AXP288_POWER_REASON),
128
+
regmap_reg_range(AXP22X_PWR_OUT_CTRL1, AXP22X_ALDO3_V_OUT),
128
129
regmap_reg_range(AXP288_BC_GLOBAL, AXP288_BC_GLOBAL),
129
130
regmap_reg_range(AXP288_BC_DET_STAT, AXP20X_VBUS_IPSOUT_MGMT),
130
131
regmap_reg_range(AXP20X_CHRG_BAK_CTRL, AXP20X_CHRG_BAK_CTRL),
131
132
regmap_reg_range(AXP20X_IRQ1_EN, AXP20X_IPSOUT_V_HIGH_L),
132
133
regmap_reg_range(AXP20X_TIMER_CTRL, AXP20X_TIMER_CTRL),
133
-
regmap_reg_range(AXP22X_GPIO_STATE, AXP22X_GPIO_STATE),
134
+
regmap_reg_range(AXP20X_GPIO1_CTRL, AXP22X_GPIO_STATE),
134
135
regmap_reg_range(AXP288_RT_BATT_V_H, AXP288_RT_BATT_V_L),
135
136
regmap_reg_range(AXP20X_FG_RES, AXP288_FG_CC_CAP_REG),
136
137
};
···
700
699
DEFINE_RES_IRQ(AXP288_IRQ_CBTO),
701
700
};
702
701
702
+
static const char * const axp288_fuel_gauge_suppliers[] = { "axp288_charger" };
703
+
704
+
static const struct property_entry axp288_fuel_gauge_properties[] = {
705
+
PROPERTY_ENTRY_STRING_ARRAY("supplied-from", axp288_fuel_gauge_suppliers),
706
+
{ }
707
+
};
708
+
709
+
static const struct software_node axp288_fuel_gauge_sw_node = {
710
+
.name = "axp288_fuel_gauge",
711
+
.properties = axp288_fuel_gauge_properties,
712
+
};
713
+
703
714
static const struct mfd_cell axp288_cells[] = {
704
715
{
705
716
.name = "axp288_adc",
···
729
716
.name = "axp288_fuel_gauge",
730
717
.num_resources = ARRAY_SIZE(axp288_fuel_gauge_resources),
731
718
.resources = axp288_fuel_gauge_resources,
719
+
.swnode = &axp288_fuel_gauge_sw_node,
732
720
}, {
733
721
.name = "axp221-pek",
734
722
.num_resources = ARRAY_SIZE(axp288_power_button_resources),
+12
-13
drivers/mfd/db8500-prcmu.c
+12
-13
drivers/mfd/db8500-prcmu.c
···
37
37
#include <linux/regulator/db8500-prcmu.h>
38
38
#include <linux/regulator/machine.h>
39
39
#include <linux/platform_data/ux500_wdt.h>
40
-
#include "dbx500-prcmu-regs.h"
40
+
#include "db8500-prcmu-regs.h"
41
41
42
42
/* Index of different voltages to be used when accessing AVSData */
43
43
#define PRCM_AVS_BASE 0x2FC
···
1622
1622
}
1623
1623
1624
1624
static const unsigned long db8500_armss_freqs[] = {
1625
-
200000000,
1626
-
400000000,
1627
-
800000000,
1625
+
199680000,
1626
+
399360000,
1627
+
798720000,
1628
1628
998400000
1629
1629
};
1630
1630
1631
1631
/* The DB8520 has slightly higher ARMSS max frequency */
1632
1632
static const unsigned long db8520_armss_freqs[] = {
1633
-
200000000,
1634
-
400000000,
1635
-
800000000,
1633
+
199680000,
1634
+
399360000,
1635
+
798720000,
1636
1636
1152000000
1637
1637
};
1638
-
1639
-
1640
1638
1641
1639
static long round_armss_rate(unsigned long rate)
1642
1640
{
···
2565
2567
return "U8500 C4";
2566
2568
case PRCMU_FW_PROJECT_U9500_MBL:
2567
2569
return "U9500 MBL";
2568
-
case PRCMU_FW_PROJECT_U8500_MBL:
2569
-
return "U8500 MBL";
2570
+
case PRCMU_FW_PROJECT_U8500_SSG1:
2571
+
return "U8500 Samsung 1";
2570
2572
case PRCMU_FW_PROJECT_U8500_MBL2:
2571
2573
return "U8500 MBL2";
2572
2574
case PRCMU_FW_PROJECT_U8520:
2573
2575
return "U8520 MBL";
2574
2576
case PRCMU_FW_PROJECT_U8420:
2575
2577
return "U8420";
2578
+
case PRCMU_FW_PROJECT_U8500_SSG2:
2579
+
return "U8500 Samsung 2";
2576
2580
case PRCMU_FW_PROJECT_U8420_SYSCLK:
2577
2581
return "U8420-sysclk";
2578
2582
case PRCMU_FW_PROJECT_U9540:
···
2951
2951
.pdata_size = sizeof(db8500_wdt_pdata),
2952
2952
.id = -1,
2953
2953
},
2954
+
MFD_CELL_NAME("db8500-cpuidle"),
2954
2955
};
2955
2956
2956
2957
static const struct mfd_cell db8500_prcmu_devs[] = {
2957
2958
MFD_CELL_OF("db8500-prcmu-regulators", NULL,
2958
2959
&db8500_regulators, sizeof(db8500_regulators), 0,
2959
2960
"stericsson,db8500-prcmu-regulator"),
2960
-
MFD_CELL_OF("cpuidle-dbx500",
2961
-
NULL, NULL, 0, 0, "stericsson,cpuidle-dbx500"),
2962
2961
MFD_CELL_OF("db8500-thermal",
2963
2962
NULL, NULL, 0, 0, "stericsson,db8500-thermal"),
2964
2963
};
drivers/mfd/dbx500-prcmu-regs.h
drivers/mfd/db8500-prcmu-regs.h
drivers/mfd/dbx500-prcmu-regs.h
drivers/mfd/db8500-prcmu-regs.h
+18
drivers/mfd/intel-lpss-acpi.c
+18
drivers/mfd/intel-lpss-acpi.c
···
89
89
.swnode = &apl_i2c_node,
90
90
};
91
91
92
+
static const struct intel_lpss_platform_info cnl_i2c_info = {
93
+
.clk_rate = 216000000,
94
+
.swnode = &spt_i2c_node,
95
+
};
96
+
92
97
static const struct acpi_device_id intel_lpss_acpi_ids[] = {
93
98
/* SPT */
94
99
{ "INT3440", (kernel_ulong_t)&spt_info },
···
107
102
{ "INT3448", (kernel_ulong_t)&spt_uart_info },
108
103
{ "INT3449", (kernel_ulong_t)&spt_uart_info },
109
104
{ "INT344A", (kernel_ulong_t)&spt_uart_info },
105
+
/* CNL */
106
+
{ "INT34B0", (kernel_ulong_t)&spt_info },
107
+
{ "INT34B1", (kernel_ulong_t)&spt_info },
108
+
{ "INT34B2", (kernel_ulong_t)&cnl_i2c_info },
109
+
{ "INT34B3", (kernel_ulong_t)&cnl_i2c_info },
110
+
{ "INT34B4", (kernel_ulong_t)&cnl_i2c_info },
111
+
{ "INT34B5", (kernel_ulong_t)&cnl_i2c_info },
112
+
{ "INT34B6", (kernel_ulong_t)&cnl_i2c_info },
113
+
{ "INT34B7", (kernel_ulong_t)&cnl_i2c_info },
114
+
{ "INT34B8", (kernel_ulong_t)&spt_uart_info },
115
+
{ "INT34B9", (kernel_ulong_t)&spt_uart_info },
116
+
{ "INT34BA", (kernel_ulong_t)&spt_uart_info },
117
+
{ "INT34BC", (kernel_ulong_t)&spt_info },
110
118
/* BXT */
111
119
{ "80860AAC", (kernel_ulong_t)&bxt_i2c_info },
112
120
{ "80860ABC", (kernel_ulong_t)&bxt_info },
+11
-1
drivers/mfd/intel-m10-bmc.c
+11
-1
drivers/mfd/intel-m10-bmc.c
···
15
15
16
16
enum m10bmc_type {
17
17
M10_N3000,
18
-
M10_D5005
18
+
M10_D5005,
19
+
M10_N5010,
19
20
};
20
21
21
22
static struct mfd_cell m10bmc_d5005_subdevs[] = {
···
27
26
{ .name = "n3000bmc-hwmon" },
28
27
{ .name = "n3000bmc-retimer" },
29
28
{ .name = "n3000bmc-secure" },
29
+
};
30
+
31
+
static struct mfd_cell m10bmc_n5010_subdevs[] = {
32
+
{ .name = "n5010bmc-hwmon" },
30
33
};
31
34
32
35
static const struct regmap_range m10bmc_regmap_range[] = {
···
197
192
cells = m10bmc_d5005_subdevs;
198
193
n_cell = ARRAY_SIZE(m10bmc_d5005_subdevs);
199
194
break;
195
+
case M10_N5010:
196
+
cells = m10bmc_n5010_subdevs;
197
+
n_cell = ARRAY_SIZE(m10bmc_n5010_subdevs);
198
+
break;
200
199
default:
201
200
return -ENODEV;
202
201
}
···
216
207
static const struct spi_device_id m10bmc_spi_id[] = {
217
208
{ "m10-n3000", M10_N3000 },
218
209
{ "m10-d5005", M10_D5005 },
210
+
{ "m10-n5010", M10_N5010 },
219
211
{ }
220
212
};
221
213
MODULE_DEVICE_TABLE(spi, m10bmc_spi_id);
+1
drivers/mfd/lpc_ich.c
+1
drivers/mfd/lpc_ich.c
+2
-2
drivers/mfd/lpc_sch.c
+2
-2
drivers/mfd/lpc_sch.c
···
22
22
#define SMBASE 0x40
23
23
#define SMBUS_IO_SIZE 64
24
24
25
-
#define GPIOBASE 0x44
25
+
#define GPIO_BASE 0x44
26
26
#define GPIO_IO_SIZE 64
27
27
#define GPIO_IO_SIZE_CENTERTON 128
28
28
···
145
145
if (ret == 0)
146
146
cells++;
147
147
148
-
ret = lpc_sch_populate_cell(dev, GPIOBASE, "sch_gpio",
148
+
ret = lpc_sch_populate_cell(dev, GPIO_BASE, "sch_gpio",
149
149
info->io_size_gpio,
150
150
id->device, &lpc_sch_cells[cells]);
151
151
if (ret < 0)
+4
-4
drivers/mfd/mt6360-core.c
+4
-4
drivers/mfd/mt6360-core.c
···
319
319
DEFINE_RES_IRQ_NAMED(MT6360_BUCK2_OC_EVT, "buck2_oc_evt"),
320
320
DEFINE_RES_IRQ_NAMED(MT6360_BUCK2_OV_EVT, "buck2_ov_evt"),
321
321
DEFINE_RES_IRQ_NAMED(MT6360_BUCK2_UV_EVT, "buck2_uv_evt"),
322
-
DEFINE_RES_IRQ_NAMED(MT6360_LDO6_OC_EVT, "ldo6_oc_evt"),
323
-
DEFINE_RES_IRQ_NAMED(MT6360_LDO7_OC_EVT, "ldo7_oc_evt"),
324
-
DEFINE_RES_IRQ_NAMED(MT6360_LDO6_PGB_EVT, "ldo6_pgb_evt"),
325
-
DEFINE_RES_IRQ_NAMED(MT6360_LDO7_PGB_EVT, "ldo7_pgb_evt"),
326
322
DEFINE_RES_IRQ_NAMED(MT6360_LDO1_OC_EVT, "ldo1_oc_evt"),
327
323
DEFINE_RES_IRQ_NAMED(MT6360_LDO2_OC_EVT, "ldo2_oc_evt"),
328
324
DEFINE_RES_IRQ_NAMED(MT6360_LDO3_OC_EVT, "ldo3_oc_evt"),
329
325
DEFINE_RES_IRQ_NAMED(MT6360_LDO5_OC_EVT, "ldo5_oc_evt"),
326
+
DEFINE_RES_IRQ_NAMED(MT6360_LDO6_OC_EVT, "ldo6_oc_evt"),
327
+
DEFINE_RES_IRQ_NAMED(MT6360_LDO7_OC_EVT, "ldo7_oc_evt"),
330
328
DEFINE_RES_IRQ_NAMED(MT6360_LDO1_PGB_EVT, "ldo1_pgb_evt"),
331
329
DEFINE_RES_IRQ_NAMED(MT6360_LDO2_PGB_EVT, "ldo2_pgb_evt"),
332
330
DEFINE_RES_IRQ_NAMED(MT6360_LDO3_PGB_EVT, "ldo3_pgb_evt"),
333
331
DEFINE_RES_IRQ_NAMED(MT6360_LDO5_PGB_EVT, "ldo5_pgb_evt"),
332
+
DEFINE_RES_IRQ_NAMED(MT6360_LDO6_PGB_EVT, "ldo6_pgb_evt"),
333
+
DEFINE_RES_IRQ_NAMED(MT6360_LDO7_PGB_EVT, "ldo7_pgb_evt"),
334
334
};
335
335
336
336
static const struct mfd_cell mt6360_devs[] = {
+16
drivers/mfd/rsmu.h
+16
drivers/mfd/rsmu.h
···
1
+
/* SPDX-License-Identifier: GPL-2.0+ */
2
+
/*
3
+
* Renesas Synchronization Management Unit (SMU) devices.
4
+
*
5
+
* Copyright (C) 2021 Integrated Device Technology, Inc., a Renesas Company.
6
+
*/
7
+
8
+
#ifndef __RSMU_MFD_H
9
+
#define __RSMU_MFD_H
10
+
11
+
#include <linux/mfd/rsmu.h>
12
+
13
+
int rsmu_core_init(struct rsmu_ddata *rsmu);
14
+
void rsmu_core_exit(struct rsmu_ddata *rsmu);
15
+
16
+
#endif /* __RSMU_MFD_H */
+88
drivers/mfd/rsmu_core.c
+88
drivers/mfd/rsmu_core.c
···
1
+
// SPDX-License-Identifier: GPL-2.0+
2
+
/*
3
+
* Core driver for Renesas Synchronization Management Unit (SMU) devices.
4
+
*
5
+
* Copyright (C) 2021 Integrated Device Technology, Inc., a Renesas Company.
6
+
*/
7
+
8
+
#include <linux/init.h>
9
+
#include <linux/kernel.h>
10
+
#include <linux/mfd/core.h>
11
+
#include <linux/mfd/rsmu.h>
12
+
#include <linux/module.h>
13
+
#include <linux/of.h>
14
+
#include <linux/regmap.h>
15
+
#include <linux/slab.h>
16
+
17
+
#include "rsmu.h"
18
+
19
+
enum {
20
+
RSMU_PHC = 0,
21
+
RSMU_CDEV = 1,
22
+
RSMU_N_DEVS = 2,
23
+
};
24
+
25
+
static struct mfd_cell rsmu_cm_devs[] = {
26
+
[RSMU_PHC] = {
27
+
.name = "8a3400x-phc",
28
+
},
29
+
[RSMU_CDEV] = {
30
+
.name = "8a3400x-cdev",
31
+
},
32
+
};
33
+
34
+
static struct mfd_cell rsmu_sabre_devs[] = {
35
+
[RSMU_PHC] = {
36
+
.name = "82p33x1x-phc",
37
+
},
38
+
[RSMU_CDEV] = {
39
+
.name = "82p33x1x-cdev",
40
+
},
41
+
};
42
+
43
+
static struct mfd_cell rsmu_sl_devs[] = {
44
+
[RSMU_PHC] = {
45
+
.name = "8v19n85x-phc",
46
+
},
47
+
[RSMU_CDEV] = {
48
+
.name = "8v19n85x-cdev",
49
+
},
50
+
};
51
+
52
+
int rsmu_core_init(struct rsmu_ddata *rsmu)
53
+
{
54
+
struct mfd_cell *cells;
55
+
int ret;
56
+
57
+
switch (rsmu->type) {
58
+
case RSMU_CM:
59
+
cells = rsmu_cm_devs;
60
+
break;
61
+
case RSMU_SABRE:
62
+
cells = rsmu_sabre_devs;
63
+
break;
64
+
case RSMU_SL:
65
+
cells = rsmu_sl_devs;
66
+
break;
67
+
default:
68
+
dev_err(rsmu->dev, "Unsupported RSMU device type: %d\n", rsmu->type);
69
+
return -ENODEV;
70
+
}
71
+
72
+
mutex_init(&rsmu->lock);
73
+
74
+
ret = devm_mfd_add_devices(rsmu->dev, PLATFORM_DEVID_AUTO, cells,
75
+
RSMU_N_DEVS, NULL, 0, NULL);
76
+
if (ret < 0)
77
+
dev_err(rsmu->dev, "Failed to register sub-devices: %d\n", ret);
78
+
79
+
return ret;
80
+
}
81
+
82
+
void rsmu_core_exit(struct rsmu_ddata *rsmu)
83
+
{
84
+
mutex_destroy(&rsmu->lock);
85
+
}
86
+
87
+
MODULE_DESCRIPTION("Renesas SMU core driver");
88
+
MODULE_LICENSE("GPL");
+203
drivers/mfd/rsmu_i2c.c
+203
drivers/mfd/rsmu_i2c.c
···
1
+
// SPDX-License-Identifier: GPL-2.0+
2
+
/*
3
+
* I2C driver for Renesas Synchronization Management Unit (SMU) devices.
4
+
*
5
+
* Copyright (C) 2021 Integrated Device Technology, Inc., a Renesas Company.
6
+
*/
7
+
8
+
#include <linux/i2c.h>
9
+
#include <linux/init.h>
10
+
#include <linux/kernel.h>
11
+
#include <linux/mfd/core.h>
12
+
#include <linux/mfd/rsmu.h>
13
+
#include <linux/module.h>
14
+
#include <linux/of.h>
15
+
#include <linux/regmap.h>
16
+
#include <linux/slab.h>
17
+
18
+
#include "rsmu.h"
19
+
20
+
/*
21
+
* 16-bit register address: the lower 8 bits of the register address come
22
+
* from the offset addr byte and the upper 8 bits come from the page register.
23
+
*/
24
+
#define RSMU_CM_PAGE_ADDR 0xFD
25
+
#define RSMU_CM_PAGE_WINDOW 256
26
+
27
+
/*
28
+
* 15-bit register address: the lower 7 bits of the register address come
29
+
* from the offset addr byte and the upper 8 bits come from the page register.
30
+
*/
31
+
#define RSMU_SABRE_PAGE_ADDR 0x7F
32
+
#define RSMU_SABRE_PAGE_WINDOW 128
33
+
34
+
static const struct regmap_range_cfg rsmu_cm_range_cfg[] = {
35
+
{
36
+
.range_min = 0,
37
+
.range_max = 0xD000,
38
+
.selector_reg = RSMU_CM_PAGE_ADDR,
39
+
.selector_mask = 0xFF,
40
+
.selector_shift = 0,
41
+
.window_start = 0,
42
+
.window_len = RSMU_CM_PAGE_WINDOW,
43
+
}
44
+
};
45
+
46
+
static const struct regmap_range_cfg rsmu_sabre_range_cfg[] = {
47
+
{
48
+
.range_min = 0,
49
+
.range_max = 0x400,
50
+
.selector_reg = RSMU_SABRE_PAGE_ADDR,
51
+
.selector_mask = 0xFF,
52
+
.selector_shift = 0,
53
+
.window_start = 0,
54
+
.window_len = RSMU_SABRE_PAGE_WINDOW,
55
+
}
56
+
};
57
+
58
+
static bool rsmu_cm_volatile_reg(struct device *dev, unsigned int reg)
59
+
{
60
+
switch (reg) {
61
+
case RSMU_CM_PAGE_ADDR:
62
+
return false;
63
+
default:
64
+
return true;
65
+
}
66
+
}
67
+
68
+
static bool rsmu_sabre_volatile_reg(struct device *dev, unsigned int reg)
69
+
{
70
+
switch (reg) {
71
+
case RSMU_SABRE_PAGE_ADDR:
72
+
return false;
73
+
default:
74
+
return true;
75
+
}
76
+
}
77
+
78
+
static const struct regmap_config rsmu_cm_regmap_config = {
79
+
.reg_bits = 8,
80
+
.val_bits = 8,
81
+
.max_register = 0xD000,
82
+
.ranges = rsmu_cm_range_cfg,
83
+
.num_ranges = ARRAY_SIZE(rsmu_cm_range_cfg),
84
+
.volatile_reg = rsmu_cm_volatile_reg,
85
+
.cache_type = REGCACHE_RBTREE,
86
+
.can_multi_write = true,
87
+
};
88
+
89
+
static const struct regmap_config rsmu_sabre_regmap_config = {
90
+
.reg_bits = 8,
91
+
.val_bits = 8,
92
+
.max_register = 0x400,
93
+
.ranges = rsmu_sabre_range_cfg,
94
+
.num_ranges = ARRAY_SIZE(rsmu_sabre_range_cfg),
95
+
.volatile_reg = rsmu_sabre_volatile_reg,
96
+
.cache_type = REGCACHE_RBTREE,
97
+
.can_multi_write = true,
98
+
};
99
+
100
+
static const struct regmap_config rsmu_sl_regmap_config = {
101
+
.reg_bits = 16,
102
+
.val_bits = 8,
103
+
.reg_format_endian = REGMAP_ENDIAN_BIG,
104
+
.max_register = 0x339,
105
+
.cache_type = REGCACHE_NONE,
106
+
.can_multi_write = true,
107
+
};
108
+
109
+
static int rsmu_i2c_probe(struct i2c_client *client,
110
+
const struct i2c_device_id *id)
111
+
{
112
+
const struct regmap_config *cfg;
113
+
struct rsmu_ddata *rsmu;
114
+
int ret;
115
+
116
+
rsmu = devm_kzalloc(&client->dev, sizeof(*rsmu), GFP_KERNEL);
117
+
if (!rsmu)
118
+
return -ENOMEM;
119
+
120
+
i2c_set_clientdata(client, rsmu);
121
+
122
+
rsmu->dev = &client->dev;
123
+
rsmu->type = (enum rsmu_type)id->driver_data;
124
+
125
+
switch (rsmu->type) {
126
+
case RSMU_CM:
127
+
cfg = &rsmu_cm_regmap_config;
128
+
break;
129
+
case RSMU_SABRE:
130
+
cfg = &rsmu_sabre_regmap_config;
131
+
break;
132
+
case RSMU_SL:
133
+
cfg = &rsmu_sl_regmap_config;
134
+
break;
135
+
default:
136
+
dev_err(rsmu->dev, "Unsupported RSMU device type: %d\n", rsmu->type);
137
+
return -ENODEV;
138
+
}
139
+
rsmu->regmap = devm_regmap_init_i2c(client, cfg);
140
+
if (IS_ERR(rsmu->regmap)) {
141
+
ret = PTR_ERR(rsmu->regmap);
142
+
dev_err(rsmu->dev, "Failed to allocate register map: %d\n", ret);
143
+
return ret;
144
+
}
145
+
146
+
return rsmu_core_init(rsmu);
147
+
}
148
+
149
+
static int rsmu_i2c_remove(struct i2c_client *client)
150
+
{
151
+
struct rsmu_ddata *rsmu = i2c_get_clientdata(client);
152
+
153
+
rsmu_core_exit(rsmu);
154
+
155
+
return 0;
156
+
}
157
+
158
+
static const struct i2c_device_id rsmu_i2c_id[] = {
159
+
{ "8a34000", RSMU_CM },
160
+
{ "8a34001", RSMU_CM },
161
+
{ "82p33810", RSMU_SABRE },
162
+
{ "82p33811", RSMU_SABRE },
163
+
{ "8v19n850", RSMU_SL },
164
+
{ "8v19n851", RSMU_SL },
165
+
{}
166
+
};
167
+
MODULE_DEVICE_TABLE(i2c, rsmu_i2c_id);
168
+
169
+
static const struct of_device_id rsmu_i2c_of_match[] = {
170
+
{ .compatible = "idt,8a34000", .data = (void *)RSMU_CM },
171
+
{ .compatible = "idt,8a34001", .data = (void *)RSMU_CM },
172
+
{ .compatible = "idt,82p33810", .data = (void *)RSMU_SABRE },
173
+
{ .compatible = "idt,82p33811", .data = (void *)RSMU_SABRE },
174
+
{ .compatible = "idt,8v19n850", .data = (void *)RSMU_SL },
175
+
{ .compatible = "idt,8v19n851", .data = (void *)RSMU_SL },
176
+
{}
177
+
};
178
+
MODULE_DEVICE_TABLE(of, rsmu_i2c_of_match);
179
+
180
+
static struct i2c_driver rsmu_i2c_driver = {
181
+
.driver = {
182
+
.name = "rsmu-i2c",
183
+
.of_match_table = of_match_ptr(rsmu_i2c_of_match),
184
+
},
185
+
.probe = rsmu_i2c_probe,
186
+
.remove = rsmu_i2c_remove,
187
+
.id_table = rsmu_i2c_id,
188
+
};
189
+
190
+
static int __init rsmu_i2c_init(void)
191
+
{
192
+
return i2c_add_driver(&rsmu_i2c_driver);
193
+
}
194
+
subsys_initcall(rsmu_i2c_init);
195
+
196
+
static void __exit rsmu_i2c_exit(void)
197
+
{
198
+
i2c_del_driver(&rsmu_i2c_driver);
199
+
}
200
+
module_exit(rsmu_i2c_exit);
201
+
202
+
MODULE_DESCRIPTION("Renesas SMU I2C driver");
203
+
MODULE_LICENSE("GPL");
+273
drivers/mfd/rsmu_spi.c
+273
drivers/mfd/rsmu_spi.c
···
1
+
// SPDX-License-Identifier: GPL-2.0+
2
+
/*
3
+
* SPI driver for Renesas Synchronization Management Unit (SMU) devices.
4
+
*
5
+
* Copyright (C) 2021 Integrated Device Technology, Inc., a Renesas Company.
6
+
*/
7
+
8
+
#include <linux/init.h>
9
+
#include <linux/kernel.h>
10
+
#include <linux/mfd/core.h>
11
+
#include <linux/mfd/rsmu.h>
12
+
#include <linux/module.h>
13
+
#include <linux/of.h>
14
+
#include <linux/regmap.h>
15
+
#include <linux/slab.h>
16
+
#include <linux/spi/spi.h>
17
+
18
+
#include "rsmu.h"
19
+
20
+
#define RSMU_CM_PAGE_ADDR 0x7C
21
+
#define RSMU_SABRE_PAGE_ADDR 0x7F
22
+
#define RSMU_HIGHER_ADDR_MASK 0xFF80
23
+
#define RSMU_HIGHER_ADDR_SHIFT 7
24
+
#define RSMU_LOWER_ADDR_MASK 0x7F
25
+
26
+
static int rsmu_read_device(struct rsmu_ddata *rsmu, u8 reg, u8 *buf, u16 bytes)
27
+
{
28
+
struct spi_device *client = to_spi_device(rsmu->dev);
29
+
struct spi_transfer xfer = {0};
30
+
struct spi_message msg;
31
+
u8 cmd[256] = {0};
32
+
u8 rsp[256] = {0};
33
+
int ret;
34
+
35
+
cmd[0] = reg | 0x80;
36
+
xfer.rx_buf = rsp;
37
+
xfer.len = bytes + 1;
38
+
xfer.tx_buf = cmd;
39
+
xfer.bits_per_word = client->bits_per_word;
40
+
xfer.speed_hz = client->max_speed_hz;
41
+
42
+
spi_message_init(&msg);
43
+
spi_message_add_tail(&xfer, &msg);
44
+
45
+
/*
46
+
* 4-wire SPI is a shift register, so for every byte you send,
47
+
* you get one back at the same time. Example read from 0xC024,
48
+
* which has value of 0x2D
49
+
*
50
+
* MOSI:
51
+
* 7C 00 C0 #Set page register
52
+
* A4 00 #MSB is set, so this is read command
53
+
* MISO:
54
+
* XX 2D #XX is a dummy byte from sending A4 and we
55
+
* need to throw it away
56
+
*/
57
+
ret = spi_sync(client, &msg);
58
+
if (ret >= 0)
59
+
memcpy(buf, &rsp[1], xfer.len-1);
60
+
61
+
return ret;
62
+
}
63
+
64
+
static int rsmu_write_device(struct rsmu_ddata *rsmu, u8 reg, u8 *buf, u16 bytes)
65
+
{
66
+
struct spi_device *client = to_spi_device(rsmu->dev);
67
+
struct spi_transfer xfer = {0};
68
+
struct spi_message msg;
69
+
u8 cmd[256] = {0};
70
+
71
+
cmd[0] = reg;
72
+
memcpy(&cmd[1], buf, bytes);
73
+
74
+
xfer.len = bytes + 1;
75
+
xfer.tx_buf = cmd;
76
+
xfer.bits_per_word = client->bits_per_word;
77
+
xfer.speed_hz = client->max_speed_hz;
78
+
spi_message_init(&msg);
79
+
spi_message_add_tail(&xfer, &msg);
80
+
81
+
return spi_sync(client, &msg);
82
+
}
83
+
84
+
/*
85
+
* 1-byte (1B) offset addressing:
86
+
* 16-bit register address: the lower 7 bits of the register address come
87
+
* from the offset addr byte and the upper 9 bits come from the page register.
88
+
*/
89
+
static int rsmu_write_page_register(struct rsmu_ddata *rsmu, u16 reg)
90
+
{
91
+
u8 page_reg;
92
+
u8 buf[2];
93
+
u16 bytes;
94
+
u16 page;
95
+
int err;
96
+
97
+
switch (rsmu->type) {
98
+
case RSMU_CM:
99
+
page_reg = RSMU_CM_PAGE_ADDR;
100
+
page = reg & RSMU_HIGHER_ADDR_MASK;
101
+
buf[0] = (u8)(page & 0xff);
102
+
buf[1] = (u8)((page >> 8) & 0xff);
103
+
bytes = 2;
104
+
break;
105
+
case RSMU_SABRE:
106
+
page_reg = RSMU_SABRE_PAGE_ADDR;
107
+
page = reg >> RSMU_HIGHER_ADDR_SHIFT;
108
+
buf[0] = (u8)(page & 0xff);
109
+
bytes = 1;
110
+
break;
111
+
default:
112
+
dev_err(rsmu->dev, "Unsupported RSMU device type: %d\n", rsmu->type);
113
+
return -ENODEV;
114
+
}
115
+
116
+
/* Simply return if we are on the same page */
117
+
if (rsmu->page == page)
118
+
return 0;
119
+
120
+
err = rsmu_write_device(rsmu, page_reg, buf, bytes);
121
+
if (err)
122
+
dev_err(rsmu->dev, "Failed to set page offset 0x%x\n", page);
123
+
else
124
+
/* Remember the last page */
125
+
rsmu->page = page;
126
+
127
+
return err;
128
+
}
129
+
130
+
static int rsmu_reg_read(void *context, unsigned int reg, unsigned int *val)
131
+
{
132
+
struct rsmu_ddata *rsmu = spi_get_drvdata((struct spi_device *)context);
133
+
u8 addr = (u8)(reg & RSMU_LOWER_ADDR_MASK);
134
+
int err;
135
+
136
+
err = rsmu_write_page_register(rsmu, reg);
137
+
if (err)
138
+
return err;
139
+
140
+
err = rsmu_read_device(rsmu, addr, (u8 *)val, 1);
141
+
if (err)
142
+
dev_err(rsmu->dev, "Failed to read offset address 0x%x\n", addr);
143
+
144
+
return err;
145
+
}
146
+
147
+
static int rsmu_reg_write(void *context, unsigned int reg, unsigned int val)
148
+
{
149
+
struct rsmu_ddata *rsmu = spi_get_drvdata((struct spi_device *)context);
150
+
u8 addr = (u8)(reg & RSMU_LOWER_ADDR_MASK);
151
+
u8 data = (u8)val;
152
+
int err;
153
+
154
+
err = rsmu_write_page_register(rsmu, reg);
155
+
if (err)
156
+
return err;
157
+
158
+
err = rsmu_write_device(rsmu, addr, &data, 1);
159
+
if (err)
160
+
dev_err(rsmu->dev,
161
+
"Failed to write offset address 0x%x\n", addr);
162
+
163
+
return err;
164
+
}
165
+
166
+
static const struct regmap_config rsmu_cm_regmap_config = {
167
+
.reg_bits = 16,
168
+
.val_bits = 8,
169
+
.max_register = 0xD000,
170
+
.reg_read = rsmu_reg_read,
171
+
.reg_write = rsmu_reg_write,
172
+
.cache_type = REGCACHE_NONE,
173
+
};
174
+
175
+
static const struct regmap_config rsmu_sabre_regmap_config = {
176
+
.reg_bits = 16,
177
+
.val_bits = 8,
178
+
.max_register = 0x400,
179
+
.reg_read = rsmu_reg_read,
180
+
.reg_write = rsmu_reg_write,
181
+
.cache_type = REGCACHE_NONE,
182
+
};
183
+
184
+
static int rsmu_spi_probe(struct spi_device *client)
185
+
{
186
+
const struct spi_device_id *id = spi_get_device_id(client);
187
+
const struct regmap_config *cfg;
188
+
struct rsmu_ddata *rsmu;
189
+
int ret;
190
+
191
+
rsmu = devm_kzalloc(&client->dev, sizeof(*rsmu), GFP_KERNEL);
192
+
if (!rsmu)
193
+
return -ENOMEM;
194
+
195
+
spi_set_drvdata(client, rsmu);
196
+
197
+
rsmu->dev = &client->dev;
198
+
rsmu->type = (enum rsmu_type)id->driver_data;
199
+
200
+
/* Initialize regmap */
201
+
switch (rsmu->type) {
202
+
case RSMU_CM:
203
+
cfg = &rsmu_cm_regmap_config;
204
+
break;
205
+
case RSMU_SABRE:
206
+
cfg = &rsmu_sabre_regmap_config;
207
+
break;
208
+
default:
209
+
dev_err(rsmu->dev, "Unsupported RSMU device type: %d\n", rsmu->type);
210
+
return -ENODEV;
211
+
}
212
+
213
+
rsmu->regmap = devm_regmap_init(&client->dev, NULL, client, cfg);
214
+
if (IS_ERR(rsmu->regmap)) {
215
+
ret = PTR_ERR(rsmu->regmap);
216
+
dev_err(rsmu->dev, "Failed to allocate register map: %d\n", ret);
217
+
return ret;
218
+
}
219
+
220
+
return rsmu_core_init(rsmu);
221
+
}
222
+
223
+
static int rsmu_spi_remove(struct spi_device *client)
224
+
{
225
+
struct rsmu_ddata *rsmu = spi_get_drvdata(client);
226
+
227
+
rsmu_core_exit(rsmu);
228
+
229
+
return 0;
230
+
}
231
+
232
+
static const struct spi_device_id rsmu_spi_id[] = {
233
+
{ "8a34000", RSMU_CM },
234
+
{ "8a34001", RSMU_CM },
235
+
{ "82p33810", RSMU_SABRE },
236
+
{ "82p33811", RSMU_SABRE },
237
+
{}
238
+
};
239
+
MODULE_DEVICE_TABLE(spi, rsmu_spi_id);
240
+
241
+
static const struct of_device_id rsmu_spi_of_match[] = {
242
+
{ .compatible = "idt,8a34000", .data = (void *)RSMU_CM },
243
+
{ .compatible = "idt,8a34001", .data = (void *)RSMU_CM },
244
+
{ .compatible = "idt,82p33810", .data = (void *)RSMU_SABRE },
245
+
{ .compatible = "idt,82p33811", .data = (void *)RSMU_SABRE },
246
+
{}
247
+
};
248
+
MODULE_DEVICE_TABLE(of, rsmu_spi_of_match);
249
+
250
+
static struct spi_driver rsmu_spi_driver = {
251
+
.driver = {
252
+
.name = "rsmu-spi",
253
+
.of_match_table = of_match_ptr(rsmu_spi_of_match),
254
+
},
255
+
.probe = rsmu_spi_probe,
256
+
.remove = rsmu_spi_remove,
257
+
.id_table = rsmu_spi_id,
258
+
};
259
+
260
+
static int __init rsmu_spi_init(void)
261
+
{
262
+
return spi_register_driver(&rsmu_spi_driver);
263
+
}
264
+
subsys_initcall(rsmu_spi_init);
265
+
266
+
static void __exit rsmu_spi_exit(void)
267
+
{
268
+
spi_unregister_driver(&rsmu_spi_driver);
269
+
}
270
+
module_exit(rsmu_spi_exit);
271
+
272
+
MODULE_DESCRIPTION("Renesas SMU SPI driver");
273
+
MODULE_LICENSE("GPL");
+33
-8
drivers/mfd/simple-mfd-i2c.c
+33
-8
drivers/mfd/simple-mfd-i2c.c
···
2
2
/*
3
3
* Simple MFD - I2C
4
4
*
5
+
* Author(s):
6
+
* Michael Walle <michael@walle.cc>
7
+
* Lee Jones <lee.jones@linaro.org>
8
+
*
5
9
* This driver creates a single register map with the intention for it to be
6
10
* shared by all sub-devices. Children can use their parent's device structure
7
11
* (dev.parent) in order to reference it.
8
12
*
9
13
* Once the register map has been successfully initialised, any sub-devices
10
-
* represented by child nodes in Device Tree will be subsequently registered.
14
+
* represented by child nodes in Device Tree or via the MFD cells in this file
15
+
* will be subsequently registered.
11
16
*/
12
17
13
18
#include <linux/i2c.h>
14
19
#include <linux/kernel.h>
20
+
#include <linux/mfd/core.h>
15
21
#include <linux/module.h>
16
22
#include <linux/of_platform.h>
17
23
#include <linux/regmap.h>
18
24
19
-
static const struct regmap_config simple_regmap_config = {
25
+
#include "simple-mfd-i2c.h"
26
+
27
+
static const struct regmap_config regmap_config_8r_8v = {
20
28
.reg_bits = 8,
21
29
.val_bits = 8,
22
30
};
23
31
24
32
static int simple_mfd_i2c_probe(struct i2c_client *i2c)
25
33
{
26
-
const struct regmap_config *config;
34
+
const struct simple_mfd_data *simple_mfd_data;
35
+
const struct regmap_config *regmap_config;
27
36
struct regmap *regmap;
37
+
int ret;
28
38
29
-
config = device_get_match_data(&i2c->dev);
30
-
if (!config)
31
-
config = &simple_regmap_config;
39
+
simple_mfd_data = device_get_match_data(&i2c->dev);
32
40
33
-
regmap = devm_regmap_init_i2c(i2c, config);
41
+
/* If no regmap_config is specified, use the default 8reg and 8val bits */
42
+
if (!simple_mfd_data || !simple_mfd_data->regmap_config)
43
+
regmap_config = ®map_config_8r_8v;
44
+
else
45
+
regmap_config = simple_mfd_data->regmap_config;
46
+
47
+
regmap = devm_regmap_init_i2c(i2c, regmap_config);
34
48
if (IS_ERR(regmap))
35
49
return PTR_ERR(regmap);
36
50
37
-
return devm_of_platform_populate(&i2c->dev);
51
+
/* If no MFD cells are spedified, use register the DT child nodes instead */
52
+
if (!simple_mfd_data || !simple_mfd_data->mfd_cell)
53
+
return devm_of_platform_populate(&i2c->dev);
54
+
55
+
ret = devm_mfd_add_devices(&i2c->dev, PLATFORM_DEVID_AUTO,
56
+
simple_mfd_data->mfd_cell,
57
+
simple_mfd_data->mfd_cell_size,
58
+
NULL, 0, NULL);
59
+
if (ret)
60
+
dev_err(&i2c->dev, "Failed to add child devices\n");
61
+
62
+
return ret;
38
63
}
39
64
40
65
static const struct of_device_id simple_mfd_i2c_of_match[] = {
+32
drivers/mfd/simple-mfd-i2c.h
+32
drivers/mfd/simple-mfd-i2c.h
···
1
+
// SPDX-License-Identifier: GPL-2.0-only
2
+
/*
3
+
* Simple MFD - I2C
4
+
*
5
+
* Author: Lee Jones <lee.jones@linaro.org>
6
+
*
7
+
* This driver creates a single register map with the intention for it to be
8
+
* shared by all sub-devices. Children can use their parent's device structure
9
+
* (dev.parent) in order to reference it.
10
+
*
11
+
* This driver creates a single register map with the intention for it to be
12
+
* shared by all sub-devices. Children can use their parent's device structure
13
+
* (dev.parent) in order to reference it.
14
+
*
15
+
* Once the register map has been successfully initialised, any sub-devices
16
+
* represented by child nodes in Device Tree or via the MFD cells in the
17
+
* associated C file will be subsequently registered.
18
+
*/
19
+
20
+
#ifndef __MFD_SIMPLE_MFD_I2C_H
21
+
#define __MFD_SIMPLE_MFD_I2C_H
22
+
23
+
#include <linux/mfd/core.h>
24
+
#include <linux/regmap.h>
25
+
26
+
struct simple_mfd_data {
27
+
const struct regmap_config *regmap_config;
28
+
const struct mfd_cell *mfd_cell;
29
+
size_t mfd_cell_size;
30
+
};
31
+
32
+
#endif /* __MFD_SIMPLE_MFD_I2C_H */
+2
-2
drivers/mfd/stmpe.c
+2
-2
drivers/mfd/stmpe.c
···
1095
1095
1096
1096
if (variant->id_val == STMPE801_ID ||
1097
1097
variant->id_val == STMPE1600_ID) {
1098
-
int base = irq_create_mapping(stmpe->domain, 0);
1098
+
int base = irq_find_mapping(stmpe->domain, 0);
1099
1099
1100
1100
handle_nested_irq(base);
1101
1101
return IRQ_HANDLED;
···
1123
1123
while (status) {
1124
1124
int bit = __ffs(status);
1125
1125
int line = bank * 8 + bit;
1126
-
int nestedirq = irq_create_mapping(stmpe->domain, line);
1126
+
int nestedirq = irq_find_mapping(stmpe->domain, line);
1127
1127
1128
1128
handle_nested_irq(nestedirq);
1129
1129
status &= ~(1 << bit);
+1
-1
drivers/mfd/syscon.c
+1
-1
drivers/mfd/syscon.c
+1
-1
drivers/mfd/tc3589x.c
+1
-1
drivers/mfd/tc3589x.c
+2
-3
drivers/mfd/ti_am335x_tscadc.c
+2
-3
drivers/mfd/ti_am335x_tscadc.c
···
175
175
tscadc->dev = &pdev->dev;
176
176
177
177
err = platform_get_irq(pdev, 0);
178
-
if (err < 0) {
179
-
dev_err(&pdev->dev, "no irq ID is specified.\n");
178
+
if (err < 0)
180
179
goto ret;
181
-
} else
180
+
else
182
181
tscadc->irq = err;
183
182
184
183
res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+12
-10
drivers/mfd/tps65086.c
+12
-10
drivers/mfd/tps65086.c
···
24
24
static const struct mfd_cell tps65086_cells[] = {
25
25
{ .name = "tps65086-regulator", },
26
26
{ .name = "tps65086-gpio", },
27
+
{ .name = "tps65086-reset", },
27
28
};
28
29
29
30
static const struct regmap_range tps65086_yes_ranges[] = {
···
101
100
(char)((version & TPS65086_DEVICEID_OTP_MASK) >> 4) + 'A',
102
101
(version & TPS65086_DEVICEID_REV_MASK) >> 6);
103
102
104
-
ret = regmap_add_irq_chip(tps->regmap, tps->irq, IRQF_ONESHOT, 0,
105
-
&tps65086_irq_chip, &tps->irq_data);
106
-
if (ret) {
107
-
dev_err(tps->dev, "Failed to register IRQ chip\n");
108
-
return ret;
103
+
if (tps->irq > 0) {
104
+
ret = regmap_add_irq_chip(tps->regmap, tps->irq, IRQF_ONESHOT, 0,
105
+
&tps65086_irq_chip, &tps->irq_data);
106
+
if (ret) {
107
+
dev_err(tps->dev, "Failed to register IRQ chip\n");
108
+
return ret;
109
+
}
109
110
}
110
111
111
112
ret = mfd_add_devices(tps->dev, PLATFORM_DEVID_AUTO, tps65086_cells,
112
113
ARRAY_SIZE(tps65086_cells), NULL, 0,
113
114
regmap_irq_get_domain(tps->irq_data));
114
-
if (ret) {
115
+
if (ret && tps->irq > 0)
115
116
regmap_del_irq_chip(tps->irq, tps->irq_data);
116
-
return ret;
117
-
}
118
117
119
-
return 0;
118
+
return ret;
120
119
}
121
120
122
121
static int tps65086_remove(struct i2c_client *client)
123
122
{
124
123
struct tps65086 *tps = i2c_get_clientdata(client);
125
124
126
-
regmap_del_irq_chip(tps->irq, tps->irq_data);
125
+
if (tps->irq > 0)
126
+
regmap_del_irq_chip(tps->irq, tps->irq_data);
127
127
128
128
return 0;
129
129
}
+38
-10
drivers/mfd/tqmx86.c
+38
-10
drivers/mfd/tqmx86.c
···
35
35
#define TQMX86_REG_BOARD_ID_E39x 7
36
36
#define TQMX86_REG_BOARD_ID_70EB 8
37
37
#define TQMX86_REG_BOARD_ID_80UC 9
38
-
#define TQMX86_REG_BOARD_ID_90UC 10
38
+
#define TQMX86_REG_BOARD_ID_110EB 11
39
+
#define TQMX86_REG_BOARD_ID_E40M 12
40
+
#define TQMX86_REG_BOARD_ID_E40S 13
41
+
#define TQMX86_REG_BOARD_ID_E40C1 14
42
+
#define TQMX86_REG_BOARD_ID_E40C2 15
39
43
#define TQMX86_REG_BOARD_REV 0x21
40
44
#define TQMX86_REG_IO_EXT_INT 0x26
41
45
#define TQMX86_REG_IO_EXT_INT_NONE 0
···
81
77
},
82
78
};
83
79
84
-
static struct ocores_i2c_platform_data ocores_platfom_data = {
80
+
static struct ocores_i2c_platform_data ocores_platform_data = {
85
81
.num_devices = ARRAY_SIZE(tqmx86_i2c_devices),
86
82
.devices = tqmx86_i2c_devices,
87
83
};
···
89
85
static const struct mfd_cell tqmx86_i2c_soft_dev[] = {
90
86
{
91
87
.name = "ocores-i2c",
92
-
.platform_data = &ocores_platfom_data,
93
-
.pdata_size = sizeof(ocores_platfom_data),
88
+
.platform_data = &ocores_platform_data,
89
+
.pdata_size = sizeof(ocores_platform_data),
94
90
.resources = tqmx_i2c_soft_resources,
95
91
.num_resources = ARRAY_SIZE(tqmx_i2c_soft_resources),
96
92
},
···
132
128
return "TQMx70EB";
133
129
case TQMX86_REG_BOARD_ID_80UC:
134
130
return "TQMx80UC";
135
-
case TQMX86_REG_BOARD_ID_90UC:
136
-
return "TQMx90UC";
131
+
case TQMX86_REG_BOARD_ID_110EB:
132
+
return "TQMx110EB";
133
+
case TQMX86_REG_BOARD_ID_E40M:
134
+
return "TQMxE40M";
135
+
case TQMX86_REG_BOARD_ID_E40S:
136
+
return "TQMxE40S";
137
+
case TQMX86_REG_BOARD_ID_E40C1:
138
+
return "TQMxE40C1";
139
+
case TQMX86_REG_BOARD_ID_E40C2:
140
+
return "TQMxE40C2";
137
141
default:
138
142
return "Unknown";
139
143
}
140
144
}
141
145
142
-
static int tqmx86_board_id_to_clk_rate(u8 board_id)
146
+
static int tqmx86_board_id_to_clk_rate(struct device *dev, u8 board_id)
143
147
{
144
148
switch (board_id) {
145
149
case TQMX86_REG_BOARD_ID_50UC:
146
150
case TQMX86_REG_BOARD_ID_60EB:
147
151
case TQMX86_REG_BOARD_ID_70EB:
148
152
case TQMX86_REG_BOARD_ID_80UC:
149
-
case TQMX86_REG_BOARD_ID_90UC:
153
+
case TQMX86_REG_BOARD_ID_110EB:
154
+
case TQMX86_REG_BOARD_ID_E40M:
155
+
case TQMX86_REG_BOARD_ID_E40S:
156
+
case TQMX86_REG_BOARD_ID_E40C1:
157
+
case TQMX86_REG_BOARD_ID_E40C2:
150
158
return 24000;
151
159
case TQMX86_REG_BOARD_ID_E39M:
152
160
case TQMX86_REG_BOARD_ID_E39C:
···
168
152
case TQMX86_REG_BOARD_ID_E38C:
169
153
return 33000;
170
154
default:
171
-
return 0;
155
+
dev_warn(dev, "unknown board %d, assuming 24MHz LPC clock\n",
156
+
board_id);
157
+
return 24000;
172
158
}
173
159
}
174
160
···
227
209
228
210
/* Assumes the IRQ resource is first. */
229
211
tqmx_gpio_resources[0].start = gpio_irq;
212
+
} else {
213
+
tqmx_gpio_resources[0].flags = 0;
230
214
}
231
215
232
-
ocores_platfom_data.clock_khz = tqmx86_board_id_to_clk_rate(board_id);
216
+
ocores_platform_data.clock_khz = tqmx86_board_id_to_clk_rate(dev, board_id);
233
217
234
218
if (i2c_det == TQMX86_REG_I2C_DETECT_SOFT) {
235
219
err = devm_mfd_add_devices(dev, PLATFORM_DEVID_NONE,
···
269
249
.ident = "TQMX86",
270
250
.matches = {
271
251
DMI_MATCH(DMI_SYS_VENDOR, "TQ-Group"),
252
+
DMI_MATCH(DMI_PRODUCT_NAME, "TQMx"),
253
+
},
254
+
.callback = tqmx86_create_platform_device,
255
+
},
256
+
{
257
+
.ident = "TQMX86",
258
+
.matches = {
259
+
DMI_MATCH(DMI_SYS_VENDOR, "TQ-Systems"),
272
260
DMI_MATCH(DMI_PRODUCT_NAME, "TQMx"),
273
261
},
274
262
.callback = tqmx86_create_platform_device,
+1
-1
drivers/mfd/wm8994-irq.c
+1
-1
drivers/mfd/wm8994-irq.c
+2
-1
include/linux/mfd/dbx500-prcmu.h
+2
-1
include/linux/mfd/dbx500-prcmu.h
···
186
186
#define PRCMU_FW_PROJECT_U8500_C3 8
187
187
#define PRCMU_FW_PROJECT_U8500_C4 9
188
188
#define PRCMU_FW_PROJECT_U9500_MBL 10
189
-
#define PRCMU_FW_PROJECT_U8500_MBL 11 /* Customer specific */
189
+
#define PRCMU_FW_PROJECT_U8500_SSG1 11 /* Samsung specific */
190
190
#define PRCMU_FW_PROJECT_U8500_MBL2 12 /* Customer specific */
191
191
#define PRCMU_FW_PROJECT_U8520 13
192
192
#define PRCMU_FW_PROJECT_U8420 14
193
+
#define PRCMU_FW_PROJECT_U8500_SSG2 15 /* Samsung specific */
193
194
#define PRCMU_FW_PROJECT_U8420_SYSCLK 17
194
195
#define PRCMU_FW_PROJECT_A9420 20
195
196
/* [32..63] 9540 and derivatives */
+112
include/linux/mfd/idt82p33_reg.h
+112
include/linux/mfd/idt82p33_reg.h
···
1
+
/* SPDX-License-Identifier: GPL-2.0+ */
2
+
/*
3
+
* Register Map - Based on AN888_SMUforIEEE_SynchEther_82P33xxx_RevH.pdf
4
+
*
5
+
* Copyright (C) 2021 Integrated Device Technology, Inc., a Renesas Company.
6
+
*/
7
+
#ifndef HAVE_IDT82P33_REG
8
+
#define HAVE_IDT82P33_REG
9
+
10
+
/* Register address */
11
+
#define DPLL1_TOD_CNFG 0x134
12
+
#define DPLL2_TOD_CNFG 0x1B4
13
+
14
+
#define DPLL1_TOD_STS 0x10B
15
+
#define DPLL2_TOD_STS 0x18B
16
+
17
+
#define DPLL1_TOD_TRIGGER 0x115
18
+
#define DPLL2_TOD_TRIGGER 0x195
19
+
20
+
#define DPLL1_OPERATING_MODE_CNFG 0x120
21
+
#define DPLL2_OPERATING_MODE_CNFG 0x1A0
22
+
23
+
#define DPLL1_HOLDOVER_FREQ_CNFG 0x12C
24
+
#define DPLL2_HOLDOVER_FREQ_CNFG 0x1AC
25
+
26
+
#define DPLL1_PHASE_OFFSET_CNFG 0x143
27
+
#define DPLL2_PHASE_OFFSET_CNFG 0x1C3
28
+
29
+
#define DPLL1_SYNC_EDGE_CNFG 0x140
30
+
#define DPLL2_SYNC_EDGE_CNFG 0x1C0
31
+
32
+
#define DPLL1_INPUT_MODE_CNFG 0x116
33
+
#define DPLL2_INPUT_MODE_CNFG 0x196
34
+
35
+
#define DPLL1_OPERATING_STS 0x102
36
+
#define DPLL2_OPERATING_STS 0x182
37
+
38
+
#define DPLL1_CURRENT_FREQ_STS 0x103
39
+
#define DPLL2_CURRENT_FREQ_STS 0x183
40
+
41
+
#define REG_SOFT_RESET 0X381
42
+
43
+
#define OUT_MUX_CNFG(outn) REG_ADDR(0x6, (0xC * (outn)))
44
+
45
+
/* Register bit definitions */
46
+
#define SYNC_TOD BIT(1)
47
+
#define PH_OFFSET_EN BIT(7)
48
+
#define SQUELCH_ENABLE BIT(5)
49
+
50
+
/* Bit definitions for the DPLL_MODE register */
51
+
#define PLL_MODE_SHIFT (0)
52
+
#define PLL_MODE_MASK (0x1F)
53
+
#define COMBO_MODE_EN BIT(5)
54
+
#define COMBO_MODE_SHIFT (6)
55
+
#define COMBO_MODE_MASK (0x3)
56
+
57
+
/* Bit definitions for DPLL_OPERATING_STS register */
58
+
#define OPERATING_STS_MASK (0x7)
59
+
#define OPERATING_STS_SHIFT (0x0)
60
+
61
+
/* Bit definitions for DPLL_TOD_TRIGGER register */
62
+
#define READ_TRIGGER_MASK (0xF)
63
+
#define READ_TRIGGER_SHIFT (0x0)
64
+
#define WRITE_TRIGGER_MASK (0xF0)
65
+
#define WRITE_TRIGGER_SHIFT (0x4)
66
+
67
+
/* Bit definitions for REG_SOFT_RESET register */
68
+
#define SOFT_RESET_EN BIT(7)
69
+
70
+
enum pll_mode {
71
+
PLL_MODE_MIN = 0,
72
+
PLL_MODE_AUTOMATIC = PLL_MODE_MIN,
73
+
PLL_MODE_FORCE_FREERUN = 1,
74
+
PLL_MODE_FORCE_HOLDOVER = 2,
75
+
PLL_MODE_FORCE_LOCKED = 4,
76
+
PLL_MODE_FORCE_PRE_LOCKED2 = 5,
77
+
PLL_MODE_FORCE_PRE_LOCKED = 6,
78
+
PLL_MODE_FORCE_LOST_PHASE = 7,
79
+
PLL_MODE_DCO = 10,
80
+
PLL_MODE_WPH = 18,
81
+
PLL_MODE_MAX = PLL_MODE_WPH,
82
+
};
83
+
84
+
enum hw_tod_trig_sel {
85
+
HW_TOD_TRIG_SEL_MIN = 0,
86
+
HW_TOD_TRIG_SEL_NO_WRITE = HW_TOD_TRIG_SEL_MIN,
87
+
HW_TOD_TRIG_SEL_NO_READ = HW_TOD_TRIG_SEL_MIN,
88
+
HW_TOD_TRIG_SEL_SYNC_SEL = 1,
89
+
HW_TOD_TRIG_SEL_IN12 = 2,
90
+
HW_TOD_TRIG_SEL_IN13 = 3,
91
+
HW_TOD_TRIG_SEL_IN14 = 4,
92
+
HW_TOD_TRIG_SEL_TOD_PPS = 5,
93
+
HW_TOD_TRIG_SEL_TIMER_INTERVAL = 6,
94
+
HW_TOD_TRIG_SEL_MSB_PHASE_OFFSET_CNFG = 7,
95
+
HW_TOD_TRIG_SEL_MSB_HOLDOVER_FREQ_CNFG = 8,
96
+
HW_TOD_WR_TRIG_SEL_MSB_TOD_CNFG = 9,
97
+
HW_TOD_RD_TRIG_SEL_LSB_TOD_STS = HW_TOD_WR_TRIG_SEL_MSB_TOD_CNFG,
98
+
WR_TRIG_SEL_MAX = HW_TOD_WR_TRIG_SEL_MSB_TOD_CNFG,
99
+
};
100
+
101
+
/** @brief Enumerated type listing DPLL operational modes */
102
+
enum dpll_state {
103
+
DPLL_STATE_FREERUN = 1,
104
+
DPLL_STATE_HOLDOVER = 2,
105
+
DPLL_STATE_LOCKED = 4,
106
+
DPLL_STATE_PRELOCKED2 = 5,
107
+
DPLL_STATE_PRELOCKED = 6,
108
+
DPLL_STATE_LOSTPHASE = 7,
109
+
DPLL_STATE_MAX
110
+
};
111
+
112
+
#endif
+729
include/linux/mfd/idt8a340_reg.h
+729
include/linux/mfd/idt8a340_reg.h
···
1
+
/* SPDX-License-Identifier: GPL-2.0+ */
2
+
/*
3
+
* Based on 5.2.0, Family Programming Guide (Sept 30, 2020)
4
+
*
5
+
* Copyright (C) 2021 Integrated Device Technology, Inc., a Renesas Company.
6
+
*/
7
+
#ifndef HAVE_IDT8A340_REG
8
+
#define HAVE_IDT8A340_REG
9
+
10
+
#define PAGE_ADDR_BASE 0x0000
11
+
#define PAGE_ADDR 0x00fc
12
+
13
+
#define HW_REVISION 0x8180
14
+
#define REV_ID 0x007a
15
+
16
+
#define HW_DPLL_0 (0x8a00)
17
+
#define HW_DPLL_1 (0x8b00)
18
+
#define HW_DPLL_2 (0x8c00)
19
+
#define HW_DPLL_3 (0x8d00)
20
+
#define HW_DPLL_4 (0x8e00)
21
+
#define HW_DPLL_5 (0x8f00)
22
+
#define HW_DPLL_6 (0x9000)
23
+
#define HW_DPLL_7 (0x9100)
24
+
25
+
#define HW_DPLL_TOD_SW_TRIG_ADDR__0 (0x080)
26
+
#define HW_DPLL_TOD_CTRL_1 (0x089)
27
+
#define HW_DPLL_TOD_CTRL_2 (0x08A)
28
+
#define HW_DPLL_TOD_OVR__0 (0x098)
29
+
#define HW_DPLL_TOD_OUT_0__0 (0x0B0)
30
+
31
+
#define HW_Q0_Q1_CH_SYNC_CTRL_0 (0xa740)
32
+
#define HW_Q0_Q1_CH_SYNC_CTRL_1 (0xa741)
33
+
#define HW_Q2_Q3_CH_SYNC_CTRL_0 (0xa742)
34
+
#define HW_Q2_Q3_CH_SYNC_CTRL_1 (0xa743)
35
+
#define HW_Q4_Q5_CH_SYNC_CTRL_0 (0xa744)
36
+
#define HW_Q4_Q5_CH_SYNC_CTRL_1 (0xa745)
37
+
#define HW_Q6_Q7_CH_SYNC_CTRL_0 (0xa746)
38
+
#define HW_Q6_Q7_CH_SYNC_CTRL_1 (0xa747)
39
+
#define HW_Q8_CH_SYNC_CTRL_0 (0xa748)
40
+
#define HW_Q8_CH_SYNC_CTRL_1 (0xa749)
41
+
#define HW_Q9_CH_SYNC_CTRL_0 (0xa74a)
42
+
#define HW_Q9_CH_SYNC_CTRL_1 (0xa74b)
43
+
#define HW_Q10_CH_SYNC_CTRL_0 (0xa74c)
44
+
#define HW_Q10_CH_SYNC_CTRL_1 (0xa74d)
45
+
#define HW_Q11_CH_SYNC_CTRL_0 (0xa74e)
46
+
#define HW_Q11_CH_SYNC_CTRL_1 (0xa74f)
47
+
48
+
#define SYNC_SOURCE_DPLL0_TOD_PPS 0x14
49
+
#define SYNC_SOURCE_DPLL1_TOD_PPS 0x15
50
+
#define SYNC_SOURCE_DPLL2_TOD_PPS 0x16
51
+
#define SYNC_SOURCE_DPLL3_TOD_PPS 0x17
52
+
53
+
#define SYNCTRL1_MASTER_SYNC_RST BIT(7)
54
+
#define SYNCTRL1_MASTER_SYNC_TRIG BIT(5)
55
+
#define SYNCTRL1_TOD_SYNC_TRIG BIT(4)
56
+
#define SYNCTRL1_FBDIV_FRAME_SYNC_TRIG BIT(3)
57
+
#define SYNCTRL1_FBDIV_SYNC_TRIG BIT(2)
58
+
#define SYNCTRL1_Q1_DIV_SYNC_TRIG BIT(1)
59
+
#define SYNCTRL1_Q0_DIV_SYNC_TRIG BIT(0)
60
+
61
+
#define HW_Q8_CTRL_SPARE (0xa7d4)
62
+
#define HW_Q11_CTRL_SPARE (0xa7ec)
63
+
64
+
/**
65
+
* Select FOD5 as sync_trigger for Q8 divider.
66
+
* Transition from logic zero to one
67
+
* sets trigger to sync Q8 divider.
68
+
*
69
+
* Unused when FOD4 is driving Q8 divider (normal operation).
70
+
*/
71
+
#define Q9_TO_Q8_SYNC_TRIG BIT(1)
72
+
73
+
/**
74
+
* Enable FOD5 as driver for clock and sync for Q8 divider.
75
+
* Enable fanout buffer for FOD5.
76
+
*
77
+
* Unused when FOD4 is driving Q8 divider (normal operation).
78
+
*/
79
+
#define Q9_TO_Q8_FANOUT_AND_CLOCK_SYNC_ENABLE_MASK (BIT(0) | BIT(2))
80
+
81
+
/**
82
+
* Select FOD6 as sync_trigger for Q11 divider.
83
+
* Transition from logic zero to one
84
+
* sets trigger to sync Q11 divider.
85
+
*
86
+
* Unused when FOD7 is driving Q11 divider (normal operation).
87
+
*/
88
+
#define Q10_TO_Q11_SYNC_TRIG BIT(1)
89
+
90
+
/**
91
+
* Enable FOD6 as driver for clock and sync for Q11 divider.
92
+
* Enable fanout buffer for FOD6.
93
+
*
94
+
* Unused when FOD7 is driving Q11 divider (normal operation).
95
+
*/
96
+
#define Q10_TO_Q11_FANOUT_AND_CLOCK_SYNC_ENABLE_MASK (BIT(0) | BIT(2))
97
+
98
+
#define RESET_CTRL 0xc000
99
+
#define SM_RESET 0x0012
100
+
#define SM_RESET_V520 0x0013
101
+
#define SM_RESET_CMD 0x5A
102
+
103
+
#define GENERAL_STATUS 0xc014
104
+
#define BOOT_STATUS 0x0000
105
+
#define HW_REV_ID 0x000A
106
+
#define BOND_ID 0x000B
107
+
#define HW_CSR_ID 0x000C
108
+
#define HW_IRQ_ID 0x000E
109
+
#define MAJ_REL 0x0010
110
+
#define MIN_REL 0x0011
111
+
#define HOTFIX_REL 0x0012
112
+
#define PIPELINE_ID 0x0014
113
+
#define BUILD_ID 0x0018
114
+
#define JTAG_DEVICE_ID 0x001c
115
+
#define PRODUCT_ID 0x001e
116
+
#define OTP_SCSR_CONFIG_SELECT 0x0022
117
+
118
+
#define STATUS 0xc03c
119
+
#define DPLL0_STATUS 0x0018
120
+
#define DPLL1_STATUS 0x0019
121
+
#define DPLL2_STATUS 0x001a
122
+
#define DPLL3_STATUS 0x001b
123
+
#define DPLL4_STATUS 0x001c
124
+
#define DPLL5_STATUS 0x001d
125
+
#define DPLL6_STATUS 0x001e
126
+
#define DPLL7_STATUS 0x001f
127
+
#define DPLL_SYS_STATUS 0x0020
128
+
#define DPLL_SYS_APLL_STATUS 0x0021
129
+
#define DPLL0_FILTER_STATUS 0x0044
130
+
#define DPLL1_FILTER_STATUS 0x004c
131
+
#define DPLL2_FILTER_STATUS 0x0054
132
+
#define DPLL3_FILTER_STATUS 0x005c
133
+
#define DPLL4_FILTER_STATUS 0x0064
134
+
#define DPLL5_FILTER_STATUS 0x006c
135
+
#define DPLL6_FILTER_STATUS 0x0074
136
+
#define DPLL7_FILTER_STATUS 0x007c
137
+
#define DPLLSYS_FILTER_STATUS 0x0084
138
+
#define USER_GPIO0_TO_7_STATUS 0x008a
139
+
#define USER_GPIO8_TO_15_STATUS 0x008b
140
+
141
+
#define GPIO_USER_CONTROL 0xc160
142
+
#define GPIO0_TO_7_OUT 0x0000
143
+
#define GPIO8_TO_15_OUT 0x0001
144
+
#define GPIO0_TO_7_OUT_V520 0x0002
145
+
#define GPIO8_TO_15_OUT_V520 0x0003
146
+
147
+
#define STICKY_STATUS_CLEAR 0xc164
148
+
149
+
#define GPIO_TOD_NOTIFICATION_CLEAR 0xc16c
150
+
151
+
#define ALERT_CFG 0xc188
152
+
153
+
#define SYS_DPLL_XO 0xc194
154
+
155
+
#define SYS_APLL 0xc19c
156
+
157
+
#define INPUT_0 0xc1b0
158
+
#define INPUT_1 0xc1c0
159
+
#define INPUT_2 0xc1d0
160
+
#define INPUT_3 0xc200
161
+
#define INPUT_4 0xc210
162
+
#define INPUT_5 0xc220
163
+
#define INPUT_6 0xc230
164
+
#define INPUT_7 0xc240
165
+
#define INPUT_8 0xc250
166
+
#define INPUT_9 0xc260
167
+
#define INPUT_10 0xc280
168
+
#define INPUT_11 0xc290
169
+
#define INPUT_12 0xc2a0
170
+
#define INPUT_13 0xc2b0
171
+
#define INPUT_14 0xc2c0
172
+
#define INPUT_15 0xc2d0
173
+
174
+
#define REF_MON_0 0xc2e0
175
+
#define REF_MON_1 0xc2ec
176
+
#define REF_MON_2 0xc300
177
+
#define REF_MON_3 0xc30c
178
+
#define REF_MON_4 0xc318
179
+
#define REF_MON_5 0xc324
180
+
#define REF_MON_6 0xc330
181
+
#define REF_MON_7 0xc33c
182
+
#define REF_MON_8 0xc348
183
+
#define REF_MON_9 0xc354
184
+
#define REF_MON_10 0xc360
185
+
#define REF_MON_11 0xc36c
186
+
#define REF_MON_12 0xc380
187
+
#define REF_MON_13 0xc38c
188
+
#define REF_MON_14 0xc398
189
+
#define REF_MON_15 0xc3a4
190
+
191
+
#define DPLL_0 0xc3b0
192
+
#define DPLL_CTRL_REG_0 0x0002
193
+
#define DPLL_CTRL_REG_1 0x0003
194
+
#define DPLL_CTRL_REG_2 0x0004
195
+
#define DPLL_TOD_SYNC_CFG 0x0031
196
+
#define DPLL_COMBO_SLAVE_CFG_0 0x0032
197
+
#define DPLL_COMBO_SLAVE_CFG_1 0x0033
198
+
#define DPLL_SLAVE_REF_CFG 0x0034
199
+
#define DPLL_REF_MODE 0x0035
200
+
#define DPLL_PHASE_MEASUREMENT_CFG 0x0036
201
+
#define DPLL_MODE 0x0037
202
+
#define DPLL_MODE_V520 0x003B
203
+
#define DPLL_1 0xc400
204
+
#define DPLL_2 0xc438
205
+
#define DPLL_2_V520 0xc43c
206
+
#define DPLL_3 0xc480
207
+
#define DPLL_4 0xc4b8
208
+
#define DPLL_4_V520 0xc4bc
209
+
#define DPLL_5 0xc500
210
+
#define DPLL_6 0xc538
211
+
#define DPLL_6_V520 0xc53c
212
+
#define DPLL_7 0xc580
213
+
#define SYS_DPLL 0xc5b8
214
+
#define SYS_DPLL_V520 0xc5bc
215
+
216
+
#define DPLL_CTRL_0 0xc600
217
+
#define DPLL_CTRL_DPLL_MANU_REF_CFG 0x0001
218
+
#define DPLL_CTRL_DPLL_FOD_FREQ 0x001c
219
+
#define DPLL_CTRL_COMBO_MASTER_CFG 0x003a
220
+
#define DPLL_CTRL_1 0xc63c
221
+
#define DPLL_CTRL_2 0xc680
222
+
#define DPLL_CTRL_3 0xc6bc
223
+
#define DPLL_CTRL_4 0xc700
224
+
#define DPLL_CTRL_5 0xc73c
225
+
#define DPLL_CTRL_6 0xc780
226
+
#define DPLL_CTRL_7 0xc7bc
227
+
#define SYS_DPLL_CTRL 0xc800
228
+
229
+
#define DPLL_PHASE_0 0xc818
230
+
/* Signed 42-bit FFO in units of 2^(-53) */
231
+
#define DPLL_WR_PHASE 0x0000
232
+
#define DPLL_PHASE_1 0xc81c
233
+
#define DPLL_PHASE_2 0xc820
234
+
#define DPLL_PHASE_3 0xc824
235
+
#define DPLL_PHASE_4 0xc828
236
+
#define DPLL_PHASE_5 0xc82c
237
+
#define DPLL_PHASE_6 0xc830
238
+
#define DPLL_PHASE_7 0xc834
239
+
240
+
#define DPLL_FREQ_0 0xc838
241
+
/* Signed 42-bit FFO in units of 2^(-53) */
242
+
#define DPLL_WR_FREQ 0x0000
243
+
#define DPLL_FREQ_1 0xc840
244
+
#define DPLL_FREQ_2 0xc848
245
+
#define DPLL_FREQ_3 0xc850
246
+
#define DPLL_FREQ_4 0xc858
247
+
#define DPLL_FREQ_5 0xc860
248
+
#define DPLL_FREQ_6 0xc868
249
+
#define DPLL_FREQ_7 0xc870
250
+
251
+
#define DPLL_PHASE_PULL_IN_0 0xc880
252
+
#define PULL_IN_OFFSET 0x0000 /* Signed 32 bit */
253
+
#define PULL_IN_SLOPE_LIMIT 0x0004 /* Unsigned 24 bit */
254
+
#define PULL_IN_CTRL 0x0007
255
+
#define DPLL_PHASE_PULL_IN_1 0xc888
256
+
#define DPLL_PHASE_PULL_IN_2 0xc890
257
+
#define DPLL_PHASE_PULL_IN_3 0xc898
258
+
#define DPLL_PHASE_PULL_IN_4 0xc8a0
259
+
#define DPLL_PHASE_PULL_IN_5 0xc8a8
260
+
#define DPLL_PHASE_PULL_IN_6 0xc8b0
261
+
#define DPLL_PHASE_PULL_IN_7 0xc8b8
262
+
263
+
#define GPIO_CFG 0xc8c0
264
+
#define GPIO_CFG_GBL 0x0000
265
+
#define GPIO_0 0xc8c2
266
+
#define GPIO_DCO_INC_DEC 0x0000
267
+
#define GPIO_OUT_CTRL_0 0x0001
268
+
#define GPIO_OUT_CTRL_1 0x0002
269
+
#define GPIO_TOD_TRIG 0x0003
270
+
#define GPIO_DPLL_INDICATOR 0x0004
271
+
#define GPIO_LOS_INDICATOR 0x0005
272
+
#define GPIO_REF_INPUT_DSQ_0 0x0006
273
+
#define GPIO_REF_INPUT_DSQ_1 0x0007
274
+
#define GPIO_REF_INPUT_DSQ_2 0x0008
275
+
#define GPIO_REF_INPUT_DSQ_3 0x0009
276
+
#define GPIO_MAN_CLK_SEL_0 0x000a
277
+
#define GPIO_MAN_CLK_SEL_1 0x000b
278
+
#define GPIO_MAN_CLK_SEL_2 0x000c
279
+
#define GPIO_SLAVE 0x000d
280
+
#define GPIO_ALERT_OUT_CFG 0x000e
281
+
#define GPIO_TOD_NOTIFICATION_CFG 0x000f
282
+
#define GPIO_CTRL 0x0010
283
+
#define GPIO_CTRL_V520 0x0011
284
+
#define GPIO_1 0xc8d4
285
+
#define GPIO_2 0xc8e6
286
+
#define GPIO_3 0xc900
287
+
#define GPIO_4 0xc912
288
+
#define GPIO_5 0xc924
289
+
#define GPIO_6 0xc936
290
+
#define GPIO_7 0xc948
291
+
#define GPIO_8 0xc95a
292
+
#define GPIO_9 0xc980
293
+
#define GPIO_10 0xc992
294
+
#define GPIO_11 0xc9a4
295
+
#define GPIO_12 0xc9b6
296
+
#define GPIO_13 0xc9c8
297
+
#define GPIO_14 0xc9da
298
+
#define GPIO_15 0xca00
299
+
300
+
#define OUT_DIV_MUX 0xca12
301
+
#define OUTPUT_0 0xca14
302
+
#define OUTPUT_0_V520 0xca20
303
+
/* FOD frequency output divider value */
304
+
#define OUT_DIV 0x0000
305
+
#define OUT_DUTY_CYCLE_HIGH 0x0004
306
+
#define OUT_CTRL_0 0x0008
307
+
#define OUT_CTRL_1 0x0009
308
+
/* Phase adjustment in FOD cycles */
309
+
#define OUT_PHASE_ADJ 0x000c
310
+
#define OUTPUT_1 0xca24
311
+
#define OUTPUT_1_V520 0xca30
312
+
#define OUTPUT_2 0xca34
313
+
#define OUTPUT_2_V520 0xca40
314
+
#define OUTPUT_3 0xca44
315
+
#define OUTPUT_3_V520 0xca50
316
+
#define OUTPUT_4 0xca54
317
+
#define OUTPUT_4_V520 0xca60
318
+
#define OUTPUT_5 0xca64
319
+
#define OUTPUT_5_V520 0xca80
320
+
#define OUTPUT_6 0xca80
321
+
#define OUTPUT_6_V520 0xca90
322
+
#define OUTPUT_7 0xca90
323
+
#define OUTPUT_7_V520 0xcaa0
324
+
#define OUTPUT_8 0xcaa0
325
+
#define OUTPUT_8_V520 0xcab0
326
+
#define OUTPUT_9 0xcab0
327
+
#define OUTPUT_9_V520 0xcac0
328
+
#define OUTPUT_10 0xcac0
329
+
#define OUTPUT_10_V520 0xcad0
330
+
#define OUTPUT_11 0xcad0
331
+
#define OUTPUT_11_V520 0xcae0
332
+
333
+
#define SERIAL 0xcae0
334
+
#define SERIAL_V520 0xcaf0
335
+
336
+
#define PWM_ENCODER_0 0xcb00
337
+
#define PWM_ENCODER_1 0xcb08
338
+
#define PWM_ENCODER_2 0xcb10
339
+
#define PWM_ENCODER_3 0xcb18
340
+
#define PWM_ENCODER_4 0xcb20
341
+
#define PWM_ENCODER_5 0xcb28
342
+
#define PWM_ENCODER_6 0xcb30
343
+
#define PWM_ENCODER_7 0xcb38
344
+
#define PWM_DECODER_0 0xcb40
345
+
#define PWM_DECODER_1 0xcb48
346
+
#define PWM_DECODER_1_V520 0xcb4a
347
+
#define PWM_DECODER_2 0xcb50
348
+
#define PWM_DECODER_2_V520 0xcb54
349
+
#define PWM_DECODER_3 0xcb58
350
+
#define PWM_DECODER_3_V520 0xcb5e
351
+
#define PWM_DECODER_4 0xcb60
352
+
#define PWM_DECODER_4_V520 0xcb68
353
+
#define PWM_DECODER_5 0xcb68
354
+
#define PWM_DECODER_5_V520 0xcb80
355
+
#define PWM_DECODER_6 0xcb70
356
+
#define PWM_DECODER_6_V520 0xcb8a
357
+
#define PWM_DECODER_7 0xcb80
358
+
#define PWM_DECODER_7_V520 0xcb94
359
+
#define PWM_DECODER_8 0xcb88
360
+
#define PWM_DECODER_8_V520 0xcb9e
361
+
#define PWM_DECODER_9 0xcb90
362
+
#define PWM_DECODER_9_V520 0xcba8
363
+
#define PWM_DECODER_10 0xcb98
364
+
#define PWM_DECODER_10_V520 0xcbb2
365
+
#define PWM_DECODER_11 0xcba0
366
+
#define PWM_DECODER_11_V520 0xcbbc
367
+
#define PWM_DECODER_12 0xcba8
368
+
#define PWM_DECODER_12_V520 0xcbc6
369
+
#define PWM_DECODER_13 0xcbb0
370
+
#define PWM_DECODER_13_V520 0xcbd0
371
+
#define PWM_DECODER_14 0xcbb8
372
+
#define PWM_DECODER_14_V520 0xcbda
373
+
#define PWM_DECODER_15 0xcbc0
374
+
#define PWM_DECODER_15_V520 0xcbe4
375
+
#define PWM_USER_DATA 0xcbc8
376
+
#define PWM_USER_DATA_V520 0xcbf0
377
+
378
+
#define TOD_0 0xcbcc
379
+
#define TOD_0_V520 0xcc00
380
+
/* Enable TOD counter, output channel sync and even-PPS mode */
381
+
#define TOD_CFG 0x0000
382
+
#define TOD_CFG_V520 0x0001
383
+
#define TOD_1 0xcbce
384
+
#define TOD_1_V520 0xcc02
385
+
#define TOD_2 0xcbd0
386
+
#define TOD_2_V520 0xcc04
387
+
#define TOD_3 0xcbd2
388
+
#define TOD_3_V520 0xcc06
389
+
390
+
#define TOD_WRITE_0 0xcc00
391
+
#define TOD_WRITE_0_V520 0xcc10
392
+
/* 8-bit subns, 32-bit ns, 48-bit seconds */
393
+
#define TOD_WRITE 0x0000
394
+
/* Counter increments after TOD write is completed */
395
+
#define TOD_WRITE_COUNTER 0x000c
396
+
/* TOD write trigger configuration */
397
+
#define TOD_WRITE_SELECT_CFG_0 0x000d
398
+
/* TOD write trigger selection */
399
+
#define TOD_WRITE_CMD 0x000f
400
+
#define TOD_WRITE_1 0xcc10
401
+
#define TOD_WRITE_1_V520 0xcc20
402
+
#define TOD_WRITE_2 0xcc20
403
+
#define TOD_WRITE_2_V520 0xcc30
404
+
#define TOD_WRITE_3 0xcc30
405
+
#define TOD_WRITE_3_V520 0xcc40
406
+
407
+
#define TOD_READ_PRIMARY_0 0xcc40
408
+
#define TOD_READ_PRIMARY_0_V520 0xcc50
409
+
/* 8-bit subns, 32-bit ns, 48-bit seconds */
410
+
#define TOD_READ_PRIMARY 0x0000
411
+
/* Counter increments after TOD write is completed */
412
+
#define TOD_READ_PRIMARY_COUNTER 0x000b
413
+
/* Read trigger configuration */
414
+
#define TOD_READ_PRIMARY_SEL_CFG_0 0x000c
415
+
/* Read trigger selection */
416
+
#define TOD_READ_PRIMARY_CMD 0x000e
417
+
#define TOD_READ_PRIMARY_CMD_V520 0x000f
418
+
#define TOD_READ_PRIMARY_1 0xcc50
419
+
#define TOD_READ_PRIMARY_1_V520 0xcc60
420
+
#define TOD_READ_PRIMARY_2 0xcc60
421
+
#define TOD_READ_PRIMARY_2_V520 0xcc80
422
+
#define TOD_READ_PRIMARY_3 0xcc80
423
+
#define TOD_READ_PRIMARY_3_V520 0xcc90
424
+
425
+
#define TOD_READ_SECONDARY_0 0xcc90
426
+
#define TOD_READ_SECONDARY_0_V520 0xcca0
427
+
#define TOD_READ_SECONDARY_1 0xcca0
428
+
#define TOD_READ_SECONDARY_1_V520 0xccb0
429
+
#define TOD_READ_SECONDARY_2 0xccb0
430
+
#define TOD_READ_SECONDARY_2_V520 0xccc0
431
+
#define TOD_READ_SECONDARY_3 0xccc0
432
+
#define TOD_READ_SECONDARY_3_V520 0xccd0
433
+
434
+
#define OUTPUT_TDC_CFG 0xccd0
435
+
#define OUTPUT_TDC_CFG_V520 0xcce0
436
+
#define OUTPUT_TDC_0 0xcd00
437
+
#define OUTPUT_TDC_1 0xcd08
438
+
#define OUTPUT_TDC_2 0xcd10
439
+
#define OUTPUT_TDC_3 0xcd18
440
+
#define INPUT_TDC 0xcd20
441
+
442
+
#define SCRATCH 0xcf50
443
+
#define SCRATCH_V520 0xcf4c
444
+
445
+
#define EEPROM 0xcf68
446
+
#define EEPROM_V520 0xcf64
447
+
448
+
#define OTP 0xcf70
449
+
450
+
#define BYTE 0xcf80
451
+
452
+
/* Bit definitions for the MAJ_REL register */
453
+
#define MAJOR_SHIFT (1)
454
+
#define MAJOR_MASK (0x7f)
455
+
#define PR_BUILD BIT(0)
456
+
457
+
/* Bit definitions for the USER_GPIO0_TO_7_STATUS register */
458
+
#define GPIO0_LEVEL BIT(0)
459
+
#define GPIO1_LEVEL BIT(1)
460
+
#define GPIO2_LEVEL BIT(2)
461
+
#define GPIO3_LEVEL BIT(3)
462
+
#define GPIO4_LEVEL BIT(4)
463
+
#define GPIO5_LEVEL BIT(5)
464
+
#define GPIO6_LEVEL BIT(6)
465
+
#define GPIO7_LEVEL BIT(7)
466
+
467
+
/* Bit definitions for the USER_GPIO8_TO_15_STATUS register */
468
+
#define GPIO8_LEVEL BIT(0)
469
+
#define GPIO9_LEVEL BIT(1)
470
+
#define GPIO10_LEVEL BIT(2)
471
+
#define GPIO11_LEVEL BIT(3)
472
+
#define GPIO12_LEVEL BIT(4)
473
+
#define GPIO13_LEVEL BIT(5)
474
+
#define GPIO14_LEVEL BIT(6)
475
+
#define GPIO15_LEVEL BIT(7)
476
+
477
+
/* Bit definitions for the GPIO0_TO_7_OUT register */
478
+
#define GPIO0_DRIVE_LEVEL BIT(0)
479
+
#define GPIO1_DRIVE_LEVEL BIT(1)
480
+
#define GPIO2_DRIVE_LEVEL BIT(2)
481
+
#define GPIO3_DRIVE_LEVEL BIT(3)
482
+
#define GPIO4_DRIVE_LEVEL BIT(4)
483
+
#define GPIO5_DRIVE_LEVEL BIT(5)
484
+
#define GPIO6_DRIVE_LEVEL BIT(6)
485
+
#define GPIO7_DRIVE_LEVEL BIT(7)
486
+
487
+
/* Bit definitions for the GPIO8_TO_15_OUT register */
488
+
#define GPIO8_DRIVE_LEVEL BIT(0)
489
+
#define GPIO9_DRIVE_LEVEL BIT(1)
490
+
#define GPIO10_DRIVE_LEVEL BIT(2)
491
+
#define GPIO11_DRIVE_LEVEL BIT(3)
492
+
#define GPIO12_DRIVE_LEVEL BIT(4)
493
+
#define GPIO13_DRIVE_LEVEL BIT(5)
494
+
#define GPIO14_DRIVE_LEVEL BIT(6)
495
+
#define GPIO15_DRIVE_LEVEL BIT(7)
496
+
497
+
/* Bit definitions for the DPLL_TOD_SYNC_CFG register */
498
+
#define TOD_SYNC_SOURCE_SHIFT (1)
499
+
#define TOD_SYNC_SOURCE_MASK (0x3)
500
+
#define TOD_SYNC_EN BIT(0)
501
+
502
+
/* Bit definitions for the DPLL_MODE register */
503
+
#define WRITE_TIMER_MODE BIT(6)
504
+
#define PLL_MODE_SHIFT (3)
505
+
#define PLL_MODE_MASK (0x7)
506
+
#define STATE_MODE_SHIFT (0)
507
+
#define STATE_MODE_MASK (0x7)
508
+
509
+
/* Bit definitions for the GPIO_CFG_GBL register */
510
+
#define SUPPLY_MODE_SHIFT (0)
511
+
#define SUPPLY_MODE_MASK (0x3)
512
+
513
+
/* Bit definitions for the GPIO_DCO_INC_DEC register */
514
+
#define INCDEC_DPLL_INDEX_SHIFT (0)
515
+
#define INCDEC_DPLL_INDEX_MASK (0x7)
516
+
517
+
/* Bit definitions for the GPIO_OUT_CTRL_0 register */
518
+
#define CTRL_OUT_0 BIT(0)
519
+
#define CTRL_OUT_1 BIT(1)
520
+
#define CTRL_OUT_2 BIT(2)
521
+
#define CTRL_OUT_3 BIT(3)
522
+
#define CTRL_OUT_4 BIT(4)
523
+
#define CTRL_OUT_5 BIT(5)
524
+
#define CTRL_OUT_6 BIT(6)
525
+
#define CTRL_OUT_7 BIT(7)
526
+
527
+
/* Bit definitions for the GPIO_OUT_CTRL_1 register */
528
+
#define CTRL_OUT_8 BIT(0)
529
+
#define CTRL_OUT_9 BIT(1)
530
+
#define CTRL_OUT_10 BIT(2)
531
+
#define CTRL_OUT_11 BIT(3)
532
+
#define CTRL_OUT_12 BIT(4)
533
+
#define CTRL_OUT_13 BIT(5)
534
+
#define CTRL_OUT_14 BIT(6)
535
+
#define CTRL_OUT_15 BIT(7)
536
+
537
+
/* Bit definitions for the GPIO_TOD_TRIG register */
538
+
#define TOD_TRIG_0 BIT(0)
539
+
#define TOD_TRIG_1 BIT(1)
540
+
#define TOD_TRIG_2 BIT(2)
541
+
#define TOD_TRIG_3 BIT(3)
542
+
543
+
/* Bit definitions for the GPIO_DPLL_INDICATOR register */
544
+
#define IND_DPLL_INDEX_SHIFT (0)
545
+
#define IND_DPLL_INDEX_MASK (0x7)
546
+
547
+
/* Bit definitions for the GPIO_LOS_INDICATOR register */
548
+
#define REFMON_INDEX_SHIFT (0)
549
+
#define REFMON_INDEX_MASK (0xf)
550
+
/* Active level of LOS indicator, 0=low 1=high */
551
+
#define ACTIVE_LEVEL BIT(4)
552
+
553
+
/* Bit definitions for the GPIO_REF_INPUT_DSQ_0 register */
554
+
#define DSQ_INP_0 BIT(0)
555
+
#define DSQ_INP_1 BIT(1)
556
+
#define DSQ_INP_2 BIT(2)
557
+
#define DSQ_INP_3 BIT(3)
558
+
#define DSQ_INP_4 BIT(4)
559
+
#define DSQ_INP_5 BIT(5)
560
+
#define DSQ_INP_6 BIT(6)
561
+
#define DSQ_INP_7 BIT(7)
562
+
563
+
/* Bit definitions for the GPIO_REF_INPUT_DSQ_1 register */
564
+
#define DSQ_INP_8 BIT(0)
565
+
#define DSQ_INP_9 BIT(1)
566
+
#define DSQ_INP_10 BIT(2)
567
+
#define DSQ_INP_11 BIT(3)
568
+
#define DSQ_INP_12 BIT(4)
569
+
#define DSQ_INP_13 BIT(5)
570
+
#define DSQ_INP_14 BIT(6)
571
+
#define DSQ_INP_15 BIT(7)
572
+
573
+
/* Bit definitions for the GPIO_REF_INPUT_DSQ_2 register */
574
+
#define DSQ_DPLL_0 BIT(0)
575
+
#define DSQ_DPLL_1 BIT(1)
576
+
#define DSQ_DPLL_2 BIT(2)
577
+
#define DSQ_DPLL_3 BIT(3)
578
+
#define DSQ_DPLL_4 BIT(4)
579
+
#define DSQ_DPLL_5 BIT(5)
580
+
#define DSQ_DPLL_6 BIT(6)
581
+
#define DSQ_DPLL_7 BIT(7)
582
+
583
+
/* Bit definitions for the GPIO_REF_INPUT_DSQ_3 register */
584
+
#define DSQ_DPLL_SYS BIT(0)
585
+
#define GPIO_DSQ_LEVEL BIT(1)
586
+
587
+
/* Bit definitions for the GPIO_TOD_NOTIFICATION_CFG register */
588
+
#define DPLL_TOD_SHIFT (0)
589
+
#define DPLL_TOD_MASK (0x3)
590
+
#define TOD_READ_SECONDARY BIT(2)
591
+
#define GPIO_ASSERT_LEVEL BIT(3)
592
+
593
+
/* Bit definitions for the GPIO_CTRL register */
594
+
#define GPIO_FUNCTION_EN BIT(0)
595
+
#define GPIO_CMOS_OD_MODE BIT(1)
596
+
#define GPIO_CONTROL_DIR BIT(2)
597
+
#define GPIO_PU_PD_MODE BIT(3)
598
+
#define GPIO_FUNCTION_SHIFT (4)
599
+
#define GPIO_FUNCTION_MASK (0xf)
600
+
601
+
/* Bit definitions for the OUT_CTRL_1 register */
602
+
#define OUT_SYNC_DISABLE BIT(7)
603
+
#define SQUELCH_VALUE BIT(6)
604
+
#define SQUELCH_DISABLE BIT(5)
605
+
#define PAD_VDDO_SHIFT (2)
606
+
#define PAD_VDDO_MASK (0x7)
607
+
#define PAD_CMOSDRV_SHIFT (0)
608
+
#define PAD_CMOSDRV_MASK (0x3)
609
+
610
+
/* Bit definitions for the TOD_CFG register */
611
+
#define TOD_EVEN_PPS_MODE BIT(2)
612
+
#define TOD_OUT_SYNC_ENABLE BIT(1)
613
+
#define TOD_ENABLE BIT(0)
614
+
615
+
/* Bit definitions for the TOD_WRITE_SELECT_CFG_0 register */
616
+
#define WR_PWM_DECODER_INDEX_SHIFT (4)
617
+
#define WR_PWM_DECODER_INDEX_MASK (0xf)
618
+
#define WR_REF_INDEX_SHIFT (0)
619
+
#define WR_REF_INDEX_MASK (0xf)
620
+
621
+
/* Bit definitions for the TOD_WRITE_CMD register */
622
+
#define TOD_WRITE_SELECTION_SHIFT (0)
623
+
#define TOD_WRITE_SELECTION_MASK (0xf)
624
+
/* 4.8.7 */
625
+
#define TOD_WRITE_TYPE_SHIFT (4)
626
+
#define TOD_WRITE_TYPE_MASK (0x3)
627
+
628
+
/* Bit definitions for the TOD_READ_PRIMARY_SEL_CFG_0 register */
629
+
#define RD_PWM_DECODER_INDEX_SHIFT (4)
630
+
#define RD_PWM_DECODER_INDEX_MASK (0xf)
631
+
#define RD_REF_INDEX_SHIFT (0)
632
+
#define RD_REF_INDEX_MASK (0xf)
633
+
634
+
/* Bit definitions for the TOD_READ_PRIMARY_CMD register */
635
+
#define TOD_READ_TRIGGER_MODE BIT(4)
636
+
#define TOD_READ_TRIGGER_SHIFT (0)
637
+
#define TOD_READ_TRIGGER_MASK (0xf)
638
+
639
+
/* Bit definitions for the DPLL_CTRL_COMBO_MASTER_CFG register */
640
+
#define COMBO_MASTER_HOLD BIT(0)
641
+
642
+
/* Bit definitions for DPLL_SYS_STATUS register */
643
+
#define DPLL_SYS_STATE_MASK (0xf)
644
+
645
+
/* Bit definitions for SYS_APLL_STATUS register */
646
+
#define SYS_APLL_LOSS_LOCK_LIVE_MASK BIT(0)
647
+
#define SYS_APLL_LOSS_LOCK_LIVE_LOCKED 0
648
+
#define SYS_APLL_LOSS_LOCK_LIVE_UNLOCKED 1
649
+
650
+
/* Bit definitions for the DPLL0_STATUS register */
651
+
#define DPLL_STATE_MASK (0xf)
652
+
#define DPLL_STATE_SHIFT (0x0)
653
+
654
+
/* Values of DPLL_N.DPLL_MODE.PLL_MODE */
655
+
enum pll_mode {
656
+
PLL_MODE_MIN = 0,
657
+
PLL_MODE_NORMAL = PLL_MODE_MIN,
658
+
PLL_MODE_WRITE_PHASE = 1,
659
+
PLL_MODE_WRITE_FREQUENCY = 2,
660
+
PLL_MODE_GPIO_INC_DEC = 3,
661
+
PLL_MODE_SYNTHESIS = 4,
662
+
PLL_MODE_PHASE_MEASUREMENT = 5,
663
+
PLL_MODE_DISABLED = 6,
664
+
PLL_MODE_MAX = PLL_MODE_DISABLED,
665
+
};
666
+
667
+
enum hw_tod_write_trig_sel {
668
+
HW_TOD_WR_TRIG_SEL_MIN = 0,
669
+
HW_TOD_WR_TRIG_SEL_MSB = HW_TOD_WR_TRIG_SEL_MIN,
670
+
HW_TOD_WR_TRIG_SEL_RESERVED = 1,
671
+
HW_TOD_WR_TRIG_SEL_TOD_PPS = 2,
672
+
HW_TOD_WR_TRIG_SEL_IRIGB_PPS = 3,
673
+
HW_TOD_WR_TRIG_SEL_PWM_PPS = 4,
674
+
HW_TOD_WR_TRIG_SEL_GPIO = 5,
675
+
HW_TOD_WR_TRIG_SEL_FOD_SYNC = 6,
676
+
WR_TRIG_SEL_MAX = HW_TOD_WR_TRIG_SEL_FOD_SYNC,
677
+
};
678
+
679
+
enum scsr_read_trig_sel {
680
+
/* CANCEL CURRENT TOD READ; MODULE BECOMES IDLE - NO TRIGGER OCCURS */
681
+
SCSR_TOD_READ_TRIG_SEL_DISABLE = 0,
682
+
/* TRIGGER IMMEDIATELY */
683
+
SCSR_TOD_READ_TRIG_SEL_IMMEDIATE = 1,
684
+
/* TRIGGER ON RISING EDGE OF INTERNAL TOD PPS SIGNAL */
685
+
SCSR_TOD_READ_TRIG_SEL_TODPPS = 2,
686
+
/* TRGGER ON RISING EDGE OF SELECTED REFERENCE INPUT */
687
+
SCSR_TOD_READ_TRIG_SEL_REFCLK = 3,
688
+
/* TRIGGER ON RISING EDGE OF SELECTED PWM DECODER 1PPS OUTPUT */
689
+
SCSR_TOD_READ_TRIG_SEL_PWMPPS = 4,
690
+
SCSR_TOD_READ_TRIG_SEL_RESERVED = 5,
691
+
/* TRIGGER WHEN WRITE FREQUENCY EVENT OCCURS */
692
+
SCSR_TOD_READ_TRIG_SEL_WRITEFREQUENCYEVENT = 6,
693
+
/* TRIGGER ON SELECTED GPIO */
694
+
SCSR_TOD_READ_TRIG_SEL_GPIO = 7,
695
+
SCSR_TOD_READ_TRIG_SEL_MAX = SCSR_TOD_READ_TRIG_SEL_GPIO,
696
+
};
697
+
698
+
/* Values STATUS.DPLL_SYS_STATUS.DPLL_SYS_STATE */
699
+
enum dpll_state {
700
+
DPLL_STATE_MIN = 0,
701
+
DPLL_STATE_FREERUN = DPLL_STATE_MIN,
702
+
DPLL_STATE_LOCKACQ = 1,
703
+
DPLL_STATE_LOCKREC = 2,
704
+
DPLL_STATE_LOCKED = 3,
705
+
DPLL_STATE_HOLDOVER = 4,
706
+
DPLL_STATE_OPEN_LOOP = 5,
707
+
DPLL_STATE_MAX = DPLL_STATE_OPEN_LOOP,
708
+
};
709
+
710
+
/* 4.8.7 only */
711
+
enum scsr_tod_write_trig_sel {
712
+
SCSR_TOD_WR_TRIG_SEL_DISABLE = 0,
713
+
SCSR_TOD_WR_TRIG_SEL_IMMEDIATE = 1,
714
+
SCSR_TOD_WR_TRIG_SEL_REFCLK = 2,
715
+
SCSR_TOD_WR_TRIG_SEL_PWMPPS = 3,
716
+
SCSR_TOD_WR_TRIG_SEL_TODPPS = 4,
717
+
SCSR_TOD_WR_TRIG_SEL_SYNCFOD = 5,
718
+
SCSR_TOD_WR_TRIG_SEL_GPIO = 6,
719
+
SCSR_TOD_WR_TRIG_SEL_MAX = SCSR_TOD_WR_TRIG_SEL_GPIO,
720
+
};
721
+
722
+
/* 4.8.7 only */
723
+
enum scsr_tod_write_type_sel {
724
+
SCSR_TOD_WR_TYPE_SEL_ABSOLUTE = 0,
725
+
SCSR_TOD_WR_TYPE_SEL_DELTA_PLUS = 1,
726
+
SCSR_TOD_WR_TYPE_SEL_DELTA_MINUS = 2,
727
+
SCSR_TOD_WR_TYPE_SEL_MAX = SCSR_TOD_WR_TYPE_SEL_DELTA_MINUS,
728
+
};
729
+
#endif
+36
include/linux/mfd/rsmu.h
+36
include/linux/mfd/rsmu.h
···
1
+
/* SPDX-License-Identifier: GPL-2.0+ */
2
+
/*
3
+
* Core interface for Renesas Synchronization Management Unit (SMU) devices.
4
+
*
5
+
* Copyright (C) 2021 Integrated Device Technology, Inc., a Renesas Company.
6
+
*/
7
+
8
+
#ifndef __LINUX_MFD_RSMU_H
9
+
#define __LINUX_MFD_RSMU_H
10
+
11
+
/* The supported devices are ClockMatrix, Sabre and SnowLotus */
12
+
enum rsmu_type {
13
+
RSMU_CM = 0x34000,
14
+
RSMU_SABRE = 0x33810,
15
+
RSMU_SL = 0x19850,
16
+
};
17
+
18
+
/**
19
+
*
20
+
* struct rsmu_ddata - device data structure for sub devices.
21
+
*
22
+
* @dev: i2c/spi device.
23
+
* @regmap: i2c/spi bus access.
24
+
* @lock: mutex used by sub devices to make sure a series of
25
+
* bus access requests are not interrupted.
26
+
* @type: RSMU device type.
27
+
* @page: i2c/spi bus driver internal use only.
28
+
*/
29
+
struct rsmu_ddata {
30
+
struct device *dev;
31
+
struct regmap *regmap;
32
+
struct mutex lock;
33
+
enum rsmu_type type;
34
+
u16 page;
35
+
};
36
+
#endif /* __LINUX_MFD_RSMU_H */