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git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
clk: qcom: add the SM8650 GPU Clock Controller driver
Add Graphics Clock Controller (GPUCC) support for SM8650 platform.
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org>
Link: https://lore.kernel.org/r/20231106-topic-sm8650-upstream-clocks-v3-10-761a6fadb4c0@linaro.org
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
authored by
Neil Armstrong
and committed by
Bjorn Andersson
8676fd4f
9e939f00
+670
+8
drivers/clk/qcom/Kconfig
+8
drivers/clk/qcom/Kconfig
···
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1047
Say Y if you want to support graphics controller devices and
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1048
functionality such as 3D graphics.
1049
1049
1050
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config SM_GPUCC_8650
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tristate "SM8650 Graphics Clock Controller"
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select SM_GCC_8650
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help
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Support for the graphics clock controller on SM8650 devices.
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Say Y if you want to support graphics controller devices and
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functionality such as 3D graphics.
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+
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config SM_TCSRCC_8550
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tristate "SM8550 TCSR Clock Controller"
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depends on ARM64 || COMPILE_TEST
+1
drivers/clk/qcom/Makefile
+1
drivers/clk/qcom/Makefile
···
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obj-$(CONFIG_SM_GPUCC_8350) += gpucc-sm8350.o
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obj-$(CONFIG_SM_GPUCC_8450) += gpucc-sm8450.o
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obj-$(CONFIG_SM_GPUCC_8550) += gpucc-sm8550.o
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obj-$(CONFIG_SM_GPUCC_8650) += gpucc-sm8650.o
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obj-$(CONFIG_SM_TCSRCC_8550) += tcsrcc-sm8550.o
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obj-$(CONFIG_SM_TCSRCC_8650) += tcsrcc-sm8650.o
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obj-$(CONFIG_SM_VIDEOCC_8150) += videocc-sm8150.o
+661
drivers/clk/qcom/gpucc-sm8650.c
+661
drivers/clk/qcom/gpucc-sm8650.c
···
1
+
// SPDX-License-Identifier: GPL-2.0-only
2
+
/*
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* Copyright (c) 2022, Qualcomm Innovation Center, Inc. All rights reserved
4
+
* Copyright (c) 2023, Linaro Limited
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+
*/
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+
7
+
#include <linux/clk-provider.h>
8
+
#include <linux/mod_devicetable.h>
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+
#include <linux/module.h>
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#include <linux/platform_device.h>
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#include <linux/regmap.h>
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+
13
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#include <dt-bindings/clock/qcom,sm8650-gpucc.h>
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+
#include <dt-bindings/reset/qcom,sm8650-gpucc.h>
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+
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#include "clk-alpha-pll.h"
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+
#include "clk-branch.h"
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+
#include "clk-rcg.h"
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#include "clk-regmap.h"
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+
#include "clk-regmap-divider.h"
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+
#include "clk-regmap-mux.h"
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#include "clk-regmap-phy-mux.h"
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+
#include "gdsc.h"
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#include "reset.h"
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+
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enum {
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DT_BI_TCXO,
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DT_GPLL0_OUT_MAIN,
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DT_GPLL0_OUT_MAIN_DIV,
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};
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+
32
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enum {
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P_BI_TCXO,
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P_GPLL0_OUT_MAIN,
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P_GPLL0_OUT_MAIN_DIV,
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P_GPU_CC_PLL0_OUT_MAIN,
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P_GPU_CC_PLL1_OUT_MAIN,
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};
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+
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static struct pll_vco lucid_ole_vco[] = {
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{ 249600000, 2100000000, 0 },
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};
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+
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static const struct alpha_pll_config gpu_cc_pll0_config = {
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.l = 0x20,
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+
.alpha = 0x4aaa,
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+
.config_ctl_val = 0x20485699,
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+
.config_ctl_hi_val = 0x00182261,
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+
.config_ctl_hi1_val = 0x82aa299c,
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+
.test_ctl_val = 0x00000000,
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+
.test_ctl_hi_val = 0x00000003,
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.test_ctl_hi1_val = 0x00009000,
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.user_ctl_val = 0x00000000,
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.user_ctl_hi_val = 0x00000005,
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+
};
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+
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static struct clk_alpha_pll gpu_cc_pll0 = {
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.offset = 0x0,
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.vco_table = lucid_ole_vco,
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+
.num_vco = ARRAY_SIZE(lucid_ole_vco),
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.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE],
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+
.clkr = {
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+
.hw.init = &(struct clk_init_data){
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.name = "gpu_cc_pll0",
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+
.parent_data = &(const struct clk_parent_data){
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+
.index = DT_BI_TCXO,
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+
},
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+
.num_parents = 1,
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+
.ops = &clk_alpha_pll_lucid_evo_ops,
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+
},
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},
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};
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+
74
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static const struct alpha_pll_config gpu_cc_pll1_config = {
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.l = 0x1b,
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.alpha = 0x1555,
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.config_ctl_val = 0x20485699,
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+
.config_ctl_hi_val = 0x00182261,
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+
.config_ctl_hi1_val = 0x82aa299c,
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+
.test_ctl_val = 0x00000000,
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.test_ctl_hi_val = 0x00000003,
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.test_ctl_hi1_val = 0x00009000,
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.user_ctl_val = 0x00000000,
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.user_ctl_hi_val = 0x00000005,
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};
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+
87
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static struct clk_alpha_pll gpu_cc_pll1 = {
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.offset = 0x1000,
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.vco_table = lucid_ole_vco,
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.num_vco = ARRAY_SIZE(lucid_ole_vco),
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.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE],
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+
.clkr = {
93
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.hw.init = &(struct clk_init_data){
94
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.name = "gpu_cc_pll1",
95
+
.parent_data = &(const struct clk_parent_data){
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.index = DT_BI_TCXO,
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+
},
98
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.num_parents = 1,
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.ops = &clk_alpha_pll_lucid_evo_ops,
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},
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},
102
+
};
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+
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static const struct parent_map gpu_cc_parent_map_0[] = {
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{ P_BI_TCXO, 0 },
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{ P_GPLL0_OUT_MAIN, 5 },
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{ P_GPLL0_OUT_MAIN_DIV, 6 },
108
+
};
109
+
110
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static const struct clk_parent_data gpu_cc_parent_data_0[] = {
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{ .index = DT_BI_TCXO },
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{ .index = DT_GPLL0_OUT_MAIN },
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{ .index = DT_GPLL0_OUT_MAIN_DIV },
114
+
};
115
+
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static const struct parent_map gpu_cc_parent_map_1[] = {
117
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{ P_BI_TCXO, 0 },
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{ P_GPU_CC_PLL0_OUT_MAIN, 1 },
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{ P_GPU_CC_PLL1_OUT_MAIN, 3 },
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{ P_GPLL0_OUT_MAIN, 5 },
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{ P_GPLL0_OUT_MAIN_DIV, 6 },
122
+
};
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+
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static const struct clk_parent_data gpu_cc_parent_data_1[] = {
125
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{ .index = DT_BI_TCXO },
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{ .hw = &gpu_cc_pll0.clkr.hw },
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{ .hw = &gpu_cc_pll1.clkr.hw },
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{ .index = DT_GPLL0_OUT_MAIN },
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{ .index = DT_GPLL0_OUT_MAIN_DIV },
130
+
};
131
+
132
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static const struct parent_map gpu_cc_parent_map_2[] = {
133
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{ P_BI_TCXO, 0 },
134
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{ P_GPU_CC_PLL1_OUT_MAIN, 3 },
135
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{ P_GPLL0_OUT_MAIN, 5 },
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{ P_GPLL0_OUT_MAIN_DIV, 6 },
137
+
};
138
+
139
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static const struct clk_parent_data gpu_cc_parent_data_2[] = {
140
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{ .index = DT_BI_TCXO },
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{ .hw = &gpu_cc_pll1.clkr.hw },
142
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{ .index = DT_GPLL0_OUT_MAIN },
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{ .index = DT_GPLL0_OUT_MAIN_DIV },
144
+
};
145
+
146
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static const struct freq_tbl ftbl_gpu_cc_ff_clk_src[] = {
147
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F(200000000, P_GPLL0_OUT_MAIN, 3, 0, 0),
148
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{ }
149
+
};
150
+
151
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static struct clk_rcg2 gpu_cc_ff_clk_src = {
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.cmd_rcgr = 0x9474,
153
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.mnd_width = 0,
154
+
.hid_width = 5,
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.parent_map = gpu_cc_parent_map_0,
156
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.freq_tbl = ftbl_gpu_cc_ff_clk_src,
157
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.hw_clk_ctrl = true,
158
+
.clkr.hw.init = &(struct clk_init_data){
159
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.name = "gpu_cc_ff_clk_src",
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.parent_data = gpu_cc_parent_data_0,
161
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.num_parents = ARRAY_SIZE(gpu_cc_parent_data_0),
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.flags = CLK_SET_RATE_PARENT,
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.ops = &clk_rcg2_shared_ops,
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},
165
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};
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+
167
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static const struct freq_tbl ftbl_gpu_cc_gmu_clk_src[] = {
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F(19200000, P_BI_TCXO, 1, 0, 0),
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F(260000000, P_GPU_CC_PLL1_OUT_MAIN, 2, 0, 0),
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F(625000000, P_GPU_CC_PLL1_OUT_MAIN, 2, 0, 0),
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{ }
172
+
};
173
+
174
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static struct clk_rcg2 gpu_cc_gmu_clk_src = {
175
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.cmd_rcgr = 0x9318,
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.mnd_width = 0,
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.hid_width = 5,
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.parent_map = gpu_cc_parent_map_1,
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+
.freq_tbl = ftbl_gpu_cc_gmu_clk_src,
180
+
.hw_clk_ctrl = true,
181
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.clkr.hw.init = &(struct clk_init_data){
182
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.name = "gpu_cc_gmu_clk_src",
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.parent_data = gpu_cc_parent_data_1,
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.num_parents = ARRAY_SIZE(gpu_cc_parent_data_1),
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.flags = CLK_SET_RATE_PARENT,
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.ops = &clk_rcg2_shared_ops,
187
+
},
188
+
};
189
+
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static const struct freq_tbl ftbl_gpu_cc_hub_clk_src[] = {
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F(200000000, P_GPLL0_OUT_MAIN, 3, 0, 0),
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F(300000000, P_GPLL0_OUT_MAIN, 2, 0, 0),
193
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{ }
194
+
};
195
+
196
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static struct clk_rcg2 gpu_cc_hub_clk_src = {
197
+
.cmd_rcgr = 0x93ec,
198
+
.mnd_width = 0,
199
+
.hid_width = 5,
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+
.parent_map = gpu_cc_parent_map_2,
201
+
.freq_tbl = ftbl_gpu_cc_hub_clk_src,
202
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.hw_clk_ctrl = true,
203
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.clkr.hw.init = &(struct clk_init_data){
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.name = "gpu_cc_hub_clk_src",
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.parent_data = gpu_cc_parent_data_2,
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.num_parents = ARRAY_SIZE(gpu_cc_parent_data_2),
207
+
.flags = CLK_SET_RATE_PARENT,
208
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.ops = &clk_rcg2_shared_ops,
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+
},
210
+
};
211
+
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static struct clk_regmap_div gpu_cc_hub_div_clk_src = {
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.reg = 0x942c,
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+
.shift = 0,
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.width = 4,
216
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.clkr.hw.init = &(const struct clk_init_data) {
217
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.name = "gpu_cc_hub_div_clk_src",
218
+
.parent_hws = (const struct clk_hw*[]){
219
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&gpu_cc_hub_clk_src.clkr.hw,
220
+
},
221
+
.num_parents = 1,
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.flags = CLK_SET_RATE_PARENT,
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.ops = &clk_regmap_div_ro_ops,
224
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},
225
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};
226
+
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static struct clk_branch gpu_cc_ahb_clk = {
228
+
.halt_reg = 0x911c,
229
+
.halt_check = BRANCH_HALT_DELAY,
230
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.clkr = {
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+
.enable_reg = 0x911c,
232
+
.enable_mask = BIT(0),
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+
.hw.init = &(struct clk_init_data){
234
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.name = "gpu_cc_ahb_clk",
235
+
.parent_hws = (const struct clk_hw*[]){
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&gpu_cc_hub_div_clk_src.clkr.hw,
237
+
},
238
+
.num_parents = 1,
239
+
.flags = CLK_SET_RATE_PARENT,
240
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.ops = &clk_branch2_ops,
241
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},
242
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},
243
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};
244
+
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static struct clk_branch gpu_cc_crc_ahb_clk = {
246
+
.halt_reg = 0x9120,
247
+
.halt_check = BRANCH_HALT_VOTED,
248
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.clkr = {
249
+
.enable_reg = 0x9120,
250
+
.enable_mask = BIT(0),
251
+
.hw.init = &(struct clk_init_data){
252
+
.name = "gpu_cc_crc_ahb_clk",
253
+
.parent_hws = (const struct clk_hw*[]){
254
+
&gpu_cc_hub_clk_src.clkr.hw,
255
+
},
256
+
.num_parents = 1,
257
+
.flags = CLK_SET_RATE_PARENT,
258
+
.ops = &clk_branch2_ops,
259
+
},
260
+
},
261
+
};
262
+
263
+
static struct clk_branch gpu_cc_cx_accu_shift_clk = {
264
+
.halt_reg = 0x9160,
265
+
.halt_check = BRANCH_HALT_VOTED,
266
+
.clkr = {
267
+
.enable_reg = 0x9160,
268
+
.enable_mask = BIT(0),
269
+
.hw.init = &(const struct clk_init_data){
270
+
.name = "gpu_cc_cx_accu_shift_clk",
271
+
.ops = &clk_branch2_ops,
272
+
},
273
+
},
274
+
};
275
+
276
+
static struct clk_branch gpu_cc_cx_ff_clk = {
277
+
.halt_reg = 0x914c,
278
+
.halt_check = BRANCH_HALT,
279
+
.clkr = {
280
+
.enable_reg = 0x914c,
281
+
.enable_mask = BIT(0),
282
+
.hw.init = &(struct clk_init_data){
283
+
.name = "gpu_cc_cx_ff_clk",
284
+
.parent_hws = (const struct clk_hw*[]){
285
+
&gpu_cc_ff_clk_src.clkr.hw,
286
+
},
287
+
.num_parents = 1,
288
+
.flags = CLK_SET_RATE_PARENT,
289
+
.ops = &clk_branch2_ops,
290
+
},
291
+
},
292
+
};
293
+
294
+
static struct clk_branch gpu_cc_cx_gmu_clk = {
295
+
.halt_reg = 0x913c,
296
+
.halt_check = BRANCH_HALT_VOTED,
297
+
.clkr = {
298
+
.enable_reg = 0x913c,
299
+
.enable_mask = BIT(0),
300
+
.hw.init = &(struct clk_init_data){
301
+
.name = "gpu_cc_cx_gmu_clk",
302
+
.parent_hws = (const struct clk_hw*[]){
303
+
&gpu_cc_gmu_clk_src.clkr.hw,
304
+
},
305
+
.num_parents = 1,
306
+
.flags = CLK_SET_RATE_PARENT,
307
+
.ops = &clk_branch2_aon_ops,
308
+
},
309
+
},
310
+
};
311
+
312
+
static struct clk_branch gpu_cc_cxo_aon_clk = {
313
+
.halt_reg = 0x9004,
314
+
.halt_check = BRANCH_HALT_VOTED,
315
+
.clkr = {
316
+
.enable_reg = 0x9004,
317
+
.enable_mask = BIT(0),
318
+
.hw.init = &(struct clk_init_data){
319
+
.name = "gpu_cc_cxo_aon_clk",
320
+
.ops = &clk_branch2_ops,
321
+
},
322
+
},
323
+
};
324
+
325
+
static struct clk_branch gpu_cc_cxo_clk = {
326
+
.halt_reg = 0x9144,
327
+
.halt_check = BRANCH_HALT,
328
+
.clkr = {
329
+
.enable_reg = 0x9144,
330
+
.enable_mask = BIT(0),
331
+
.hw.init = &(struct clk_init_data){
332
+
.name = "gpu_cc_cxo_clk",
333
+
.ops = &clk_branch2_ops,
334
+
},
335
+
},
336
+
};
337
+
338
+
static struct clk_branch gpu_cc_demet_clk = {
339
+
.halt_reg = 0x900c,
340
+
.halt_check = BRANCH_HALT,
341
+
.clkr = {
342
+
.enable_reg = 0x900c,
343
+
.enable_mask = BIT(0),
344
+
.hw.init = &(struct clk_init_data){
345
+
.name = "gpu_cc_demet_clk",
346
+
.ops = &clk_branch2_aon_ops,
347
+
},
348
+
},
349
+
};
350
+
351
+
static struct clk_branch gpu_cc_freq_measure_clk = {
352
+
.halt_reg = 0x9008,
353
+
.halt_check = BRANCH_HALT,
354
+
.clkr = {
355
+
.enable_reg = 0x9008,
356
+
.enable_mask = BIT(0),
357
+
.hw.init = &(struct clk_init_data){
358
+
.name = "gpu_cc_freq_measure_clk",
359
+
.ops = &clk_branch2_ops,
360
+
},
361
+
},
362
+
};
363
+
364
+
static struct clk_branch gpu_cc_gx_gfx3d_clk = {
365
+
.halt_reg = 0x90a8,
366
+
.halt_check = BRANCH_HALT,
367
+
.clkr = {
368
+
.enable_reg = 0x90a8,
369
+
.enable_mask = BIT(0),
370
+
.hw.init = &(struct clk_init_data){
371
+
.name = "gpu_cc_gx_gfx3d_clk",
372
+
.ops = &clk_branch2_ops,
373
+
},
374
+
},
375
+
};
376
+
377
+
static struct clk_branch gpu_cc_gx_gfx3d_rdvm_clk = {
378
+
.halt_reg = 0x90c8,
379
+
.halt_check = BRANCH_HALT,
380
+
.clkr = {
381
+
.enable_reg = 0x90c8,
382
+
.enable_mask = BIT(0),
383
+
.hw.init = &(struct clk_init_data){
384
+
.name = "gpu_cc_gx_gfx3d_rdvm_clk",
385
+
.ops = &clk_branch2_ops,
386
+
},
387
+
},
388
+
};
389
+
390
+
static struct clk_branch gpu_cc_gx_gmu_clk = {
391
+
.halt_reg = 0x90bc,
392
+
.halt_check = BRANCH_HALT,
393
+
.clkr = {
394
+
.enable_reg = 0x90bc,
395
+
.enable_mask = BIT(0),
396
+
.hw.init = &(struct clk_init_data){
397
+
.name = "gpu_cc_gx_gmu_clk",
398
+
.parent_hws = (const struct clk_hw*[]){
399
+
&gpu_cc_gmu_clk_src.clkr.hw,
400
+
},
401
+
.num_parents = 1,
402
+
.flags = CLK_SET_RATE_PARENT,
403
+
.ops = &clk_branch2_ops,
404
+
},
405
+
},
406
+
};
407
+
408
+
static struct clk_branch gpu_cc_gx_vsense_clk = {
409
+
.halt_reg = 0x90b0,
410
+
.halt_check = BRANCH_HALT_VOTED,
411
+
.clkr = {
412
+
.enable_reg = 0x90b0,
413
+
.enable_mask = BIT(0),
414
+
.hw.init = &(struct clk_init_data){
415
+
.name = "gpu_cc_gx_vsense_clk",
416
+
.ops = &clk_branch2_ops,
417
+
},
418
+
},
419
+
};
420
+
421
+
static struct clk_branch gpu_cc_gx_accu_shift_clk = {
422
+
.halt_reg = 0x90d0,
423
+
.halt_check = BRANCH_HALT_VOTED,
424
+
.clkr = {
425
+
.enable_reg = 0x90d0,
426
+
.enable_mask = BIT(0),
427
+
.hw.init = &(const struct clk_init_data){
428
+
.name = "gpu_cc_gx_accu_shift_clk",
429
+
.ops = &clk_branch2_ops,
430
+
},
431
+
},
432
+
};
433
+
434
+
static struct clk_branch gpu_cc_gx_ff_clk = {
435
+
.halt_reg = 0x90c0,
436
+
.halt_check = BRANCH_HALT,
437
+
.clkr = {
438
+
.enable_reg = 0x90c0,
439
+
.enable_mask = BIT(0),
440
+
.hw.init = &(const struct clk_init_data){
441
+
.name = "gpu_cc_gx_ff_clk",
442
+
.parent_hws = (const struct clk_hw*[]){
443
+
&gpu_cc_ff_clk_src.clkr.hw,
444
+
},
445
+
.num_parents = 1,
446
+
.flags = CLK_SET_RATE_PARENT,
447
+
.ops = &clk_branch2_ops,
448
+
},
449
+
},
450
+
};
451
+
452
+
static struct clk_branch gpu_cc_hlos1_vote_gpu_smmu_clk = {
453
+
.halt_reg = 0x7000,
454
+
.halt_check = BRANCH_HALT_VOTED,
455
+
.clkr = {
456
+
.enable_reg = 0x7000,
457
+
.enable_mask = BIT(0),
458
+
.hw.init = &(struct clk_init_data){
459
+
.name = "gpu_cc_hlos1_vote_gpu_smmu_clk",
460
+
.ops = &clk_branch2_ops,
461
+
},
462
+
},
463
+
};
464
+
465
+
static struct clk_branch gpu_cc_hub_aon_clk = {
466
+
.halt_reg = 0x93e8,
467
+
.halt_check = BRANCH_HALT_VOTED,
468
+
.clkr = {
469
+
.enable_reg = 0x93e8,
470
+
.enable_mask = BIT(0),
471
+
.hw.init = &(struct clk_init_data){
472
+
.name = "gpu_cc_hub_aon_clk",
473
+
.parent_hws = (const struct clk_hw*[]){
474
+
&gpu_cc_hub_clk_src.clkr.hw,
475
+
},
476
+
.num_parents = 1,
477
+
.flags = CLK_SET_RATE_PARENT,
478
+
.ops = &clk_branch2_aon_ops,
479
+
},
480
+
},
481
+
};
482
+
483
+
static struct clk_branch gpu_cc_hub_cx_int_clk = {
484
+
.halt_reg = 0x9148,
485
+
.halt_check = BRANCH_HALT_VOTED,
486
+
.clkr = {
487
+
.enable_reg = 0x9148,
488
+
.enable_mask = BIT(0),
489
+
.hw.init = &(struct clk_init_data){
490
+
.name = "gpu_cc_hub_cx_int_clk",
491
+
.parent_hws = (const struct clk_hw*[]){
492
+
&gpu_cc_hub_clk_src.clkr.hw,
493
+
},
494
+
.num_parents = 1,
495
+
.flags = CLK_SET_RATE_PARENT,
496
+
.ops = &clk_branch2_aon_ops,
497
+
},
498
+
},
499
+
};
500
+
501
+
static struct clk_branch gpu_cc_memnoc_gfx_clk = {
502
+
.halt_reg = 0x9150,
503
+
.halt_check = BRANCH_HALT_VOTED,
504
+
.clkr = {
505
+
.enable_reg = 0x9150,
506
+
.enable_mask = BIT(0),
507
+
.hw.init = &(struct clk_init_data){
508
+
.name = "gpu_cc_memnoc_gfx_clk",
509
+
.ops = &clk_branch2_ops,
510
+
},
511
+
},
512
+
};
513
+
514
+
static struct clk_branch gpu_cc_sleep_clk = {
515
+
.halt_reg = 0x9134,
516
+
.halt_check = BRANCH_HALT_VOTED,
517
+
.clkr = {
518
+
.enable_reg = 0x9134,
519
+
.enable_mask = BIT(0),
520
+
.hw.init = &(struct clk_init_data){
521
+
.name = "gpu_cc_sleep_clk",
522
+
.ops = &clk_branch2_ops,
523
+
},
524
+
},
525
+
};
526
+
527
+
static struct clk_branch gpu_cc_dpm_clk = {
528
+
.halt_reg = 0x9164,
529
+
.halt_check = BRANCH_HALT,
530
+
.clkr = {
531
+
.enable_reg = 0x9164,
532
+
.enable_mask = BIT(0),
533
+
.hw.init = &(const struct clk_init_data){
534
+
.name = "gpu_cc_dpm_clk",
535
+
.ops = &clk_branch2_ops,
536
+
},
537
+
},
538
+
};
539
+
540
+
static struct gdsc gpu_cx_gdsc = {
541
+
.gdscr = 0x9108,
542
+
.gds_hw_ctrl = 0x9168,
543
+
.clk_dis_wait_val = 8,
544
+
.pd = {
545
+
.name = "gpu_cx_gdsc",
546
+
},
547
+
.pwrsts = PWRSTS_OFF_ON,
548
+
.flags = VOTABLE | RETAIN_FF_ENABLE,
549
+
};
550
+
551
+
static struct gdsc gpu_gx_gdsc = {
552
+
.gdscr = 0x905c,
553
+
.clamp_io_ctrl = 0x9504,
554
+
.resets = (unsigned int []){ GPUCC_GPU_CC_GX_BCR,
555
+
GPUCC_GPU_CC_ACD_BCR,
556
+
GPUCC_GPU_CC_GX_ACD_IROOT_BCR },
557
+
.reset_count = 3,
558
+
.pd = {
559
+
.name = "gpu_gx_gdsc",
560
+
.power_on = gdsc_gx_do_nothing_enable,
561
+
},
562
+
.pwrsts = PWRSTS_OFF_ON,
563
+
.flags = CLAMP_IO | AON_RESET | SW_RESET | POLL_CFG_GDSCR,
564
+
};
565
+
566
+
static struct clk_regmap *gpu_cc_sm8650_clocks[] = {
567
+
[GPU_CC_AHB_CLK] = &gpu_cc_ahb_clk.clkr,
568
+
[GPU_CC_CRC_AHB_CLK] = &gpu_cc_crc_ahb_clk.clkr,
569
+
[GPU_CC_CX_ACCU_SHIFT_CLK] = &gpu_cc_cx_accu_shift_clk.clkr,
570
+
[GPU_CC_CX_FF_CLK] = &gpu_cc_cx_ff_clk.clkr,
571
+
[GPU_CC_CX_GMU_CLK] = &gpu_cc_cx_gmu_clk.clkr,
572
+
[GPU_CC_CXO_AON_CLK] = &gpu_cc_cxo_aon_clk.clkr,
573
+
[GPU_CC_CXO_CLK] = &gpu_cc_cxo_clk.clkr,
574
+
[GPU_CC_DEMET_CLK] = &gpu_cc_demet_clk.clkr,
575
+
[GPU_CC_DPM_CLK] = &gpu_cc_dpm_clk.clkr,
576
+
[GPU_CC_FF_CLK_SRC] = &gpu_cc_ff_clk_src.clkr,
577
+
[GPU_CC_FREQ_MEASURE_CLK] = &gpu_cc_freq_measure_clk.clkr,
578
+
[GPU_CC_GMU_CLK_SRC] = &gpu_cc_gmu_clk_src.clkr,
579
+
[GPU_CC_GX_ACCU_SHIFT_CLK] = &gpu_cc_gx_accu_shift_clk.clkr,
580
+
[GPU_CC_GX_FF_CLK] = &gpu_cc_gx_ff_clk.clkr,
581
+
[GPU_CC_GX_GFX3D_CLK] = &gpu_cc_gx_gfx3d_clk.clkr,
582
+
[GPU_CC_GX_GFX3D_RDVM_CLK] = &gpu_cc_gx_gfx3d_rdvm_clk.clkr,
583
+
[GPU_CC_GX_GMU_CLK] = &gpu_cc_gx_gmu_clk.clkr,
584
+
[GPU_CC_GX_VSENSE_CLK] = &gpu_cc_gx_vsense_clk.clkr,
585
+
[GPU_CC_HLOS1_VOTE_GPU_SMMU_CLK] = &gpu_cc_hlos1_vote_gpu_smmu_clk.clkr,
586
+
[GPU_CC_HUB_AON_CLK] = &gpu_cc_hub_aon_clk.clkr,
587
+
[GPU_CC_HUB_CLK_SRC] = &gpu_cc_hub_clk_src.clkr,
588
+
[GPU_CC_HUB_CX_INT_CLK] = &gpu_cc_hub_cx_int_clk.clkr,
589
+
[GPU_CC_HUB_DIV_CLK_SRC] = &gpu_cc_hub_div_clk_src.clkr,
590
+
[GPU_CC_MEMNOC_GFX_CLK] = &gpu_cc_memnoc_gfx_clk.clkr,
591
+
[GPU_CC_PLL0] = &gpu_cc_pll0.clkr,
592
+
[GPU_CC_PLL1] = &gpu_cc_pll1.clkr,
593
+
[GPU_CC_SLEEP_CLK] = &gpu_cc_sleep_clk.clkr,
594
+
};
595
+
596
+
static const struct qcom_reset_map gpu_cc_sm8650_resets[] = {
597
+
[GPUCC_GPU_CC_XO_BCR] = { 0x9000 },
598
+
[GPUCC_GPU_CC_GX_BCR] = { 0x9058 },
599
+
[GPUCC_GPU_CC_CX_BCR] = { 0x9104 },
600
+
[GPUCC_GPU_CC_GFX3D_AON_BCR] = { 0x9198 },
601
+
[GPUCC_GPU_CC_ACD_BCR] = { 0x9358 },
602
+
[GPUCC_GPU_CC_FAST_HUB_BCR] = { 0x93e4 },
603
+
[GPUCC_GPU_CC_FF_BCR] = { 0x9470 },
604
+
[GPUCC_GPU_CC_GMU_BCR] = { 0x9314 },
605
+
[GPUCC_GPU_CC_GX_ACD_IROOT_BCR] = { 0x958c },
606
+
};
607
+
608
+
static struct gdsc *gpu_cc_sm8650_gdscs[] = {
609
+
[GPU_CX_GDSC] = &gpu_cx_gdsc,
610
+
[GPU_GX_GDSC] = &gpu_gx_gdsc,
611
+
};
612
+
613
+
static const struct regmap_config gpu_cc_sm8650_regmap_config = {
614
+
.reg_bits = 32,
615
+
.reg_stride = 4,
616
+
.val_bits = 32,
617
+
.max_register = 0xa000,
618
+
.fast_io = true,
619
+
};
620
+
621
+
static const struct qcom_cc_desc gpu_cc_sm8650_desc = {
622
+
.config = &gpu_cc_sm8650_regmap_config,
623
+
.clks = gpu_cc_sm8650_clocks,
624
+
.num_clks = ARRAY_SIZE(gpu_cc_sm8650_clocks),
625
+
.resets = gpu_cc_sm8650_resets,
626
+
.num_resets = ARRAY_SIZE(gpu_cc_sm8650_resets),
627
+
.gdscs = gpu_cc_sm8650_gdscs,
628
+
.num_gdscs = ARRAY_SIZE(gpu_cc_sm8650_gdscs),
629
+
};
630
+
631
+
static const struct of_device_id gpu_cc_sm8650_match_table[] = {
632
+
{ .compatible = "qcom,sm8650-gpucc" },
633
+
{ }
634
+
};
635
+
MODULE_DEVICE_TABLE(of, gpu_cc_sm8650_match_table);
636
+
637
+
static int gpu_cc_sm8650_probe(struct platform_device *pdev)
638
+
{
639
+
struct regmap *regmap;
640
+
641
+
regmap = qcom_cc_map(pdev, &gpu_cc_sm8650_desc);
642
+
if (IS_ERR(regmap))
643
+
return PTR_ERR(regmap);
644
+
645
+
clk_lucid_ole_pll_configure(&gpu_cc_pll0, regmap, &gpu_cc_pll0_config);
646
+
clk_lucid_ole_pll_configure(&gpu_cc_pll1, regmap, &gpu_cc_pll1_config);
647
+
648
+
return qcom_cc_really_probe(pdev, &gpu_cc_sm8650_desc, regmap);
649
+
}
650
+
651
+
static struct platform_driver gpu_cc_sm8650_driver = {
652
+
.probe = gpu_cc_sm8650_probe,
653
+
.driver = {
654
+
.name = "sm8650-gpucc",
655
+
.of_match_table = gpu_cc_sm8650_match_table,
656
+
},
657
+
};
658
+
module_platform_driver(gpu_cc_sm8650_driver);
659
+
660
+
MODULE_DESCRIPTION("QTI GPU_CC SM8650 Driver");
661
+
MODULE_LICENSE("GPL");