Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
Merge branch 'pci/controller/rcar-gen4'
- Fix a typo that prevented correct PHY initialization (Marek Vasut)
- Add a missing 1ms delay after PWR reset assertion as required by the V4H
manual (Marek Vasut)
- Assure reset has completed before DBI access to avoid SError (Marek
Vasut)
- Fix inverted PHY initialization check, which sometimes led to timeouts
and failure to start the controller (Marek Vasut)
* pci/controller/rcar-gen4:
PCI: rcar-gen4: Fix inverted break condition in PHY initialization
PCI: rcar-gen4: Assure reset occurs before DBI access
PCI: rcar-gen4: Add missing 1ms delay after PWR reset assertion
PCI: rcar-gen4: Fix PHY initialization
+25
-3
+25
-3
drivers/pci/controller/dwc/pcie-rcar-gen4.c
+25
-3
drivers/pci/controller/dwc/pcie-rcar-gen4.c
···
182
182
return ret;
183
183
}
184
184
185
-
if (!reset_control_status(dw->core_rsts[DW_PCIE_PWR_RST].rstc))
185
+
if (!reset_control_status(dw->core_rsts[DW_PCIE_PWR_RST].rstc)) {
186
186
reset_control_assert(dw->core_rsts[DW_PCIE_PWR_RST].rstc);
187
+
/*
188
+
* R-Car V4H Reference Manual R19UH0186EJ0130 Rev.1.30 Apr.
189
+
* 21, 2025 page 585 Figure 9.3.2 Software Reset flow (B)
190
+
* indicates that for peripherals in HSC domain, after
191
+
* reset has been asserted by writing a matching reset bit
192
+
* into register SRCR, it is mandatory to wait 1ms.
193
+
*/
194
+
fsleep(1000);
195
+
}
187
196
188
197
val = readl(rcar->base + PCIEMSR0);
189
198
if (rcar->drvdata->mode == DW_PCIE_RC_TYPE) {
···
212
203
ret = reset_control_deassert(dw->core_rsts[DW_PCIE_PWR_RST].rstc);
213
204
if (ret)
214
205
goto err_unprepare;
206
+
207
+
/*
208
+
* Assure the reset is latched and the core is ready for DBI access.
209
+
* On R-Car V4H, the PCIe reset is asynchronous and does not take
210
+
* effect immediately, but needs a short time to complete. In case
211
+
* DBI access happens in that short time, that access generates an
212
+
* SError. To make sure that condition can never happen, read back the
213
+
* state of the reset, which should turn the asynchronous reset into
214
+
* synchronous one, and wait a little over 1ms to add additional
215
+
* safety margin.
216
+
*/
217
+
reset_control_status(dw->core_rsts[DW_PCIE_PWR_RST].rstc);
218
+
fsleep(1000);
215
219
216
220
if (rcar->drvdata->additional_common_init)
217
221
rcar->drvdata->additional_common_init(rcar);
···
721
699
rcar_gen4_pcie_phy_reg_update_bits(rcar, 0x148, GENMASK(23, 22), BIT(22));
722
700
rcar_gen4_pcie_phy_reg_update_bits(rcar, 0x148, GENMASK(18, 16), GENMASK(17, 16));
723
701
rcar_gen4_pcie_phy_reg_update_bits(rcar, 0x148, GENMASK(7, 6), BIT(6));
724
-
rcar_gen4_pcie_phy_reg_update_bits(rcar, 0x148, GENMASK(2, 0), GENMASK(11, 0));
702
+
rcar_gen4_pcie_phy_reg_update_bits(rcar, 0x148, GENMASK(2, 0), GENMASK(1, 0));
725
703
rcar_gen4_pcie_phy_reg_update_bits(rcar, 0x1d4, GENMASK(16, 15), GENMASK(16, 15));
726
704
rcar_gen4_pcie_phy_reg_update_bits(rcar, 0x514, BIT(26), BIT(26));
727
705
rcar_gen4_pcie_phy_reg_update_bits(rcar, 0x0f8, BIT(16), 0);
···
731
709
val &= ~APP_HOLD_PHY_RST;
732
710
writel(val, rcar->base + PCIERSTCTRL1);
733
711
734
-
ret = readl_poll_timeout(rcar->phy_base + 0x0f8, val, !(val & BIT(18)), 100, 10000);
712
+
ret = readl_poll_timeout(rcar->phy_base + 0x0f8, val, val & BIT(18), 100, 10000);
735
713
if (ret < 0)
736
714
return ret;
737
715