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drm/msm/dpu: Rename `ctx` parameter to `intf` to match other functions

All other functions in dpu_hw_intf name the "self" parameter `intf`,
except dpu_hw_intf_setup_timing_engine() and the recently added
dpu_hw_intf_program_intf_cmd_cfg(). Clean that up for consistency.

Signed-off-by: Marijn Suijten <marijn.suijten@somainline.org>
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Patchwork: https://patchwork.freedesktop.org/patch/589903/
Link: https://lore.kernel.org/r/20240417-drm-msm-initial-dualpipe-dsc-fixes-v1-7-78ae3ee9a697@somainline.org
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>

authored by

Marijn Suijten and committed by
Dmitry Baryshkov 88148bfe ca97fa41

+7 -7
+7 -7
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c
··· 96 96 #define INTF_CFG2_DCE_DATA_COMPRESS BIT(12) 97 97 98 98 99 - static void dpu_hw_intf_setup_timing_engine(struct dpu_hw_intf *ctx, 99 + static void dpu_hw_intf_setup_timing_engine(struct dpu_hw_intf *intf, 100 100 const struct dpu_hw_intf_timing_params *p, 101 101 const struct dpu_format *fmt) 102 102 { 103 - struct dpu_hw_blk_reg_map *c = &ctx->hw; 103 + struct dpu_hw_blk_reg_map *c = &intf->hw; 104 104 u32 hsync_period, vsync_period; 105 105 u32 display_v_start, display_v_end; 106 106 u32 hsync_start_x, hsync_end_x; ··· 118 118 /* read interface_cfg */ 119 119 intf_cfg = DPU_REG_READ(c, INTF_CONFIG); 120 120 121 - if (ctx->cap->type == INTF_DP) 121 + if (intf->cap->type == INTF_DP) 122 122 dp_intf = true; 123 123 124 124 hsync_period = p->hsync_pulse_width + p->h_back_porch + p->width + ··· 223 223 DPU_REG_WRITE(c, INTF_FRAME_LINE_COUNT_EN, 0x3); 224 224 DPU_REG_WRITE(c, INTF_CONFIG, intf_cfg); 225 225 DPU_REG_WRITE(c, INTF_PANEL_FORMAT, panel_format); 226 - if (ctx->cap->features & BIT(DPU_DATA_HCTL_EN)) { 226 + if (intf->cap->features & BIT(DPU_DATA_HCTL_EN)) { 227 227 /* 228 228 * DATA_HCTL_EN controls data timing which can be different from 229 229 * video timing. It is recommended to enable it for all cases, except ··· 518 518 519 519 } 520 520 521 - static void dpu_hw_intf_program_intf_cmd_cfg(struct dpu_hw_intf *ctx, 521 + static void dpu_hw_intf_program_intf_cmd_cfg(struct dpu_hw_intf *intf, 522 522 struct dpu_hw_intf_cmd_mode_cfg *cmd_mode_cfg) 523 523 { 524 - u32 intf_cfg2 = DPU_REG_READ(&ctx->hw, INTF_CONFIG2); 524 + u32 intf_cfg2 = DPU_REG_READ(&intf->hw, INTF_CONFIG2); 525 525 526 526 if (cmd_mode_cfg->data_compress) 527 527 intf_cfg2 |= INTF_CFG2_DCE_DATA_COMPRESS; ··· 529 529 if (cmd_mode_cfg->wide_bus_en) 530 530 intf_cfg2 |= INTF_CFG2_DATABUS_WIDEN; 531 531 532 - DPU_REG_WRITE(&ctx->hw, INTF_CONFIG2, intf_cfg2); 532 + DPU_REG_WRITE(&intf->hw, INTF_CONFIG2, intf_cfg2); 533 533 } 534 534 535 535 struct dpu_hw_intf *dpu_hw_intf_init(struct drm_device *dev,