tjh.dev / kernel
Linux kernel mirror (for testing) git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
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drm/amd/pm: Add baseboard temperature metrics support

Add baseboard temperature metrics support via system metrics table for
smu_v15_0_8

v4: Add separate function to fill baseboard temperature, use 16, remove
casting

v5: Optimize to use single switch case (Lijo)

Signed-off-by: Asad Kamal <asad.kamal@amd.com>
Reviewed-by: Lijo Lazar <lijo.lazar@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

authored by

Asad Kamal and committed by
Alex Deucher 8847d599 e3b96f5b

+184 -13
+29
drivers/gpu/drm/amd/include/kgd_pp_interface.h
··· 619 619 AMDGPU_METRICS_ATTR_ID_VR_TEMP_VDDIO_065_UCIEAM_A, 620 620 AMDGPU_METRICS_ATTR_ID_VR_TEMP_VDDIO_065_UCIEAM_C, 621 621 AMDGPU_METRICS_ATTR_ID_VR_TEMP_VDDAN_075, 622 + AMDGPU_METRICS_ATTR_ID_SYSTEM_TEMP_UBB_FPGA, 623 + AMDGPU_METRICS_ATTR_ID_SYSTEM_TEMP_UBB_FRONT, 624 + AMDGPU_METRICS_ATTR_ID_SYSTEM_TEMP_UBB_BACK, 625 + AMDGPU_METRICS_ATTR_ID_SYSTEM_TEMP_UBB_OAM7, 626 + AMDGPU_METRICS_ATTR_ID_SYSTEM_TEMP_UBB_IBC, 627 + AMDGPU_METRICS_ATTR_ID_SYSTEM_TEMP_UBB_UFPGA, 628 + AMDGPU_METRICS_ATTR_ID_SYSTEM_TEMP_UBB_OAM1, 629 + AMDGPU_METRICS_ATTR_ID_SYSTEM_TEMP_OAM_0_1_HSC, 630 + AMDGPU_METRICS_ATTR_ID_SYSTEM_TEMP_OAM_2_3_HSC, 631 + AMDGPU_METRICS_ATTR_ID_SYSTEM_TEMP_OAM_4_5_HSC, 632 + AMDGPU_METRICS_ATTR_ID_SYSTEM_TEMP_OAM_6_7_HSC, 633 + AMDGPU_METRICS_ATTR_ID_SYSTEM_TEMP_UBB_FPGA_0V72_VR, 634 + AMDGPU_METRICS_ATTR_ID_SYSTEM_TEMP_UBB_FPGA_3V3_VR, 635 + AMDGPU_METRICS_ATTR_ID_SYSTEM_TEMP_RETIMER_0_1_2_3_1V2_VR, 636 + AMDGPU_METRICS_ATTR_ID_SYSTEM_TEMP_RETIMER_4_5_6_7_1V2_VR, 637 + AMDGPU_METRICS_ATTR_ID_SYSTEM_TEMP_RETIMER_0_1_0V9_VR, 638 + AMDGPU_METRICS_ATTR_ID_SYSTEM_TEMP_RETIMER_4_5_0V9_VR, 639 + AMDGPU_METRICS_ATTR_ID_SYSTEM_TEMP_RETIMER_2_3_0V9_VR, 640 + AMDGPU_METRICS_ATTR_ID_SYSTEM_TEMP_RETIMER_6_7_0V9_VR, 641 + AMDGPU_METRICS_ATTR_ID_SYSTEM_TEMP_OAM_0_1_2_3_3V3_VR, 642 + AMDGPU_METRICS_ATTR_ID_SYSTEM_TEMP_OAM_4_5_6_7_3V3_VR, 643 + AMDGPU_METRICS_ATTR_ID_SYSTEM_TEMP_IBC_HSC, 644 + AMDGPU_METRICS_ATTR_ID_SYSTEM_TEMP_IBC, 622 645 AMDGPU_METRICS_ATTR_ID_MAX, 623 646 }; 624 647 ··· 1895 1872 }; 1896 1873 1897 1874 struct amdgpu_gpuboard_temp_metrics_v1_1 { 1875 + struct metrics_table_header common_header; 1876 + int attr_count; 1877 + struct gpu_metrics_attr metrics_attrs[]; 1878 + }; 1879 + 1880 + struct amdgpu_baseboard_temp_metrics_v1_1 { 1898 1881 struct metrics_table_header common_header; 1899 1882 int attr_count; 1900 1883 struct gpu_metrics_attr metrics_attrs[];
+97 -13
drivers/gpu/drm/amd/pm/swsmu/smu15/smu_v15_0_8_ppt.c
··· 178 178 179 179 static int smu_v15_0_8_tables_init(struct smu_context *smu) 180 180 { 181 + struct smu_v15_0_8_baseboard_temp_metrics *baseboard_temp_metrics; 181 182 struct smu_v15_0_8_gpuboard_temp_metrics *gpuboard_temp_metrics; 182 183 struct smu_table_context *smu_table = &smu->smu_table; 183 184 int ret, gpu_metrcs_size = sizeof(MetricsTable_t); ··· 224 223 if (ret) 225 224 return ret; 226 225 226 + /* Initialize base board temperature metrics */ 227 + ret = smu_driver_table_init(smu, 228 + SMU_DRIVER_TABLE_BASEBOARD_TEMP_METRICS, 229 + sizeof(*baseboard_temp_metrics), 50); 230 + if (ret) 231 + return ret; 232 + baseboard_temp_metrics = (struct smu_v15_0_8_baseboard_temp_metrics *) 233 + smu_driver_table_ptr(smu, 234 + SMU_DRIVER_TABLE_BASEBOARD_TEMP_METRICS); 235 + smu_v15_0_8_baseboard_temp_metrics_init(baseboard_temp_metrics, 1, 1); 227 236 /* Initialize GPU board temperature metrics */ 228 237 ret = smu_driver_table_init(smu, SMU_DRIVER_TABLE_GPUBOARD_TEMP_METRICS, 229 238 sizeof(*gpuboard_temp_metrics), 50); 230 239 if (ret) { 231 240 smu_table_cache_fini(smu, SMU_TABLE_PMFW_SYSTEM_METRICS); 241 + smu_driver_table_fini(smu, 242 + SMU_DRIVER_TABLE_BASEBOARD_TEMP_METRICS); 232 243 return ret; 233 244 } 234 245 gpuboard_temp_metrics = (struct smu_v15_0_8_gpuboard_temp_metrics *) ··· 293 280 { 294 281 struct smu_table_context *smu_table = &smu->smu_table; 295 282 283 + smu_driver_table_fini(smu, SMU_DRIVER_TABLE_BASEBOARD_TEMP_METRICS); 296 284 smu_driver_table_fini(smu, SMU_DRIVER_TABLE_GPUBOARD_TEMP_METRICS); 297 285 smu_table_cache_fini(smu, SMU_TABLE_PMFW_SYSTEM_METRICS); 298 286 mutex_destroy(&smu_table->metrics_lock); ··· 1367 1353 enum smu_temp_metric_type type) 1368 1354 { 1369 1355 switch (type) { 1356 + case SMU_TEMP_METRIC_BASEBOARD: 1357 + if (smu->adev->gmc.xgmi.physical_node_id == 0) 1358 + return true; 1359 + return false; 1370 1360 case SMU_TEMP_METRIC_GPUBOARD: 1371 1361 return true; 1372 1362 default: 1373 1363 return false; 1374 1364 } 1365 + } 1366 + 1367 + static void smu_v15_0_8_fill_baseboard_temp_metrics( 1368 + struct smu_v15_0_8_baseboard_temp_metrics *baseboard_temp_metrics, 1369 + const SystemMetricsTable_t *metrics) 1370 + { 1371 + baseboard_temp_metrics->accumulation_counter = metrics->AccumulationCounter; 1372 + baseboard_temp_metrics->label_version = metrics->LabelVersion; 1373 + baseboard_temp_metrics->node_id = metrics->NodeIdentifier; 1374 + 1375 + baseboard_temp_metrics->system_temp_ubb_fpga = 1376 + metrics->SystemTemperatures[SYSTEM_TEMP_UBB_FPGA]; 1377 + baseboard_temp_metrics->system_temp_ubb_front = 1378 + metrics->SystemTemperatures[SYSTEM_TEMP_UBB_FRONT]; 1379 + baseboard_temp_metrics->system_temp_ubb_back = 1380 + metrics->SystemTemperatures[SYSTEM_TEMP_UBB_BACK]; 1381 + baseboard_temp_metrics->system_temp_ubb_oam7 = 1382 + metrics->SystemTemperatures[SYSTEM_TEMP_UBB_OAM7]; 1383 + baseboard_temp_metrics->system_temp_ubb_ibc = 1384 + metrics->SystemTemperatures[SYSTEM_TEMP_UBB_IBC]; 1385 + baseboard_temp_metrics->system_temp_ubb_ufpga = 1386 + metrics->SystemTemperatures[SYSTEM_TEMP_UBB_UFPGA]; 1387 + baseboard_temp_metrics->system_temp_ubb_oam1 = 1388 + metrics->SystemTemperatures[SYSTEM_TEMP_UBB_OAM1]; 1389 + baseboard_temp_metrics->system_temp_oam_0_1_hsc = 1390 + metrics->SystemTemperatures[SYSTEM_TEMP_OAM_0_1_HSC]; 1391 + baseboard_temp_metrics->system_temp_oam_2_3_hsc = 1392 + metrics->SystemTemperatures[SYSTEM_TEMP_OAM_2_3_HSC]; 1393 + baseboard_temp_metrics->system_temp_oam_4_5_hsc = 1394 + metrics->SystemTemperatures[SYSTEM_TEMP_OAM_4_5_HSC]; 1395 + baseboard_temp_metrics->system_temp_oam_6_7_hsc = 1396 + metrics->SystemTemperatures[SYSTEM_TEMP_OAM_6_7_HSC]; 1397 + baseboard_temp_metrics->system_temp_ubb_fpga_0v72_vr = 1398 + metrics->SystemTemperatures[SYSTEM_TEMP_UBB_FPGA_0V72_VR]; 1399 + baseboard_temp_metrics->system_temp_ubb_fpga_3v3_vr = 1400 + metrics->SystemTemperatures[SYSTEM_TEMP_UBB_FPGA_3V3_VR]; 1401 + baseboard_temp_metrics->system_temp_retimer_0_1_2_3_1v2_vr = 1402 + metrics->SystemTemperatures[SYSTEM_TEMP_RETIMER_0_1_2_3_1V2_VR]; 1403 + baseboard_temp_metrics->system_temp_retimer_4_5_6_7_1v2_vr = 1404 + metrics->SystemTemperatures[SYSTEM_TEMP_RETIMER_4_5_6_7_1V2_VR]; 1405 + baseboard_temp_metrics->system_temp_retimer_0_1_0v9_vr = 1406 + metrics->SystemTemperatures[SYSTEM_TEMP_RETIMER_0_1_0V9_VR]; 1407 + baseboard_temp_metrics->system_temp_retimer_4_5_0v9_vr = 1408 + metrics->SystemTemperatures[SYSTEM_TEMP_RETIMER_4_5_0V9_VR]; 1409 + baseboard_temp_metrics->system_temp_retimer_2_3_0v9_vr = 1410 + metrics->SystemTemperatures[SYSTEM_TEMP_RETIMER_2_3_0V9_VR]; 1411 + baseboard_temp_metrics->system_temp_retimer_6_7_0v9_vr = 1412 + metrics->SystemTemperatures[SYSTEM_TEMP_RETIMER_6_7_0V9_VR]; 1413 + baseboard_temp_metrics->system_temp_oam_0_1_2_3_3v3_vr = 1414 + metrics->SystemTemperatures[SYSTEM_TEMP_OAM_0_1_2_3_3V3_VR]; 1415 + baseboard_temp_metrics->system_temp_oam_4_5_6_7_3v3_vr = 1416 + metrics->SystemTemperatures[SYSTEM_TEMP_OAM_4_5_6_7_3V3_VR]; 1417 + baseboard_temp_metrics->system_temp_ibc_hsc = 1418 + metrics->SystemTemperatures[SYSTEM_TEMP_IBC_HSC]; 1419 + baseboard_temp_metrics->system_temp_ibc = 1420 + metrics->SystemTemperatures[SYSTEM_TEMP_IBC]; 1375 1421 } 1376 1422 1377 1423 static void smu_v15_0_8_fill_gpuboard_temp_metrics( ··· 1503 1429 enum smu_temp_metric_type type, 1504 1430 void *table) 1505 1431 { 1432 + struct smu_v15_0_8_baseboard_temp_metrics *baseboard_temp_metrics; 1506 1433 struct smu_v15_0_8_gpuboard_temp_metrics *gpuboard_temp_metrics; 1507 1434 struct smu_table_context *smu_table = &smu->smu_table; 1508 1435 struct smu_table *tables = smu_table->tables; 1509 - enum smu_driver_table_id table_id; 1510 1436 SystemMetricsTable_t *metrics; 1511 1437 struct smu_table *sys_table; 1512 - ssize_t size; 1513 1438 int ret; 1514 - 1515 - table_id = SMU_DRIVER_TABLE_GPUBOARD_TEMP_METRICS; 1516 - gpuboard_temp_metrics = 1517 - (struct smu_v15_0_8_gpuboard_temp_metrics *) 1518 - smu_driver_table_ptr(smu, table_id); 1519 - size = sizeof(*gpuboard_temp_metrics); 1520 1439 1521 1440 ret = smu_v15_0_8_get_system_metrics_table(smu); 1522 1441 if (ret) ··· 1517 1450 1518 1451 sys_table = &tables[SMU_TABLE_PMFW_SYSTEM_METRICS]; 1519 1452 metrics = (SystemMetricsTable_t *)sys_table->cache.buffer; 1520 - smu_driver_table_update_cache_time(smu, table_id); 1521 1453 1522 - smu_v15_0_8_fill_gpuboard_temp_metrics(gpuboard_temp_metrics, 1523 - metrics); 1524 - memcpy(table, gpuboard_temp_metrics, size); 1525 - return size; 1454 + switch (type) { 1455 + case SMU_TEMP_METRIC_GPUBOARD: 1456 + gpuboard_temp_metrics = 1457 + (struct smu_v15_0_8_gpuboard_temp_metrics *) 1458 + smu_driver_table_ptr(smu, SMU_DRIVER_TABLE_GPUBOARD_TEMP_METRICS); 1459 + smu_driver_table_update_cache_time(smu, SMU_DRIVER_TABLE_GPUBOARD_TEMP_METRICS); 1460 + smu_v15_0_8_fill_gpuboard_temp_metrics(gpuboard_temp_metrics, 1461 + metrics); 1462 + memcpy(table, gpuboard_temp_metrics, sizeof(*gpuboard_temp_metrics)); 1463 + return sizeof(*gpuboard_temp_metrics); 1464 + case SMU_TEMP_METRIC_BASEBOARD: 1465 + baseboard_temp_metrics = 1466 + (struct smu_v15_0_8_baseboard_temp_metrics *) 1467 + smu_driver_table_ptr(smu, SMU_DRIVER_TABLE_BASEBOARD_TEMP_METRICS); 1468 + smu_driver_table_update_cache_time(smu, SMU_DRIVER_TABLE_BASEBOARD_TEMP_METRICS); 1469 + smu_v15_0_8_fill_baseboard_temp_metrics(baseboard_temp_metrics, 1470 + metrics); 1471 + memcpy(table, baseboard_temp_metrics, sizeof(*baseboard_temp_metrics)); 1472 + return sizeof(*baseboard_temp_metrics); 1473 + default: 1474 + return -EINVAL; 1475 + } 1526 1476 } 1527 1477 1528 1478 static ssize_t smu_v15_0_8_get_gpu_metrics(struct smu_context *smu, void **table)
+58
drivers/gpu/drm/amd/pm/swsmu/smu15/smu_v15_0_8_ppt.h
··· 182 182 DECLARE_SMU_METRICS_CLASS(smu_v15_0_8_gpu_metrics, SMU_15_0_8_METRICS_FIELDS); 183 183 184 184 /* Maximum temperature sensor counts for system metrics */ 185 + #define SMU_15_0_8_MAX_SYSTEM_TEMP_ENTRIES 32 185 186 #define SMU_15_0_8_MAX_NODE_TEMP_ENTRIES 12 186 187 #define SMU_15_0_8_MAX_VR_TEMP_ENTRIES 22 187 188 ··· 252 251 DECLARE_SMU_METRICS_CLASS(smu_v15_0_8_gpuboard_temp_metrics, 253 252 SMU_15_0_8_GPUBOARD_TEMP_METRICS_FIELDS); 254 253 254 + /* SMUv 15.0.8 Baseboard temperature metrics - ID-based approach */ 255 + #define SMU_15_0_8_BASEBOARD_TEMP_METRICS_FIELDS(SMU_SCALAR, SMU_ARRAY) \ 256 + SMU_SCALAR(SMU_MATTR(ACCUMULATION_COUNTER), SMU_MUNIT(NONE), \ 257 + SMU_MTYPE(U64), accumulation_counter); \ 258 + SMU_SCALAR(SMU_MATTR(LABEL_VERSION), SMU_MUNIT(NONE), \ 259 + SMU_MTYPE(U16), label_version); \ 260 + SMU_SCALAR(SMU_MATTR(NODE_ID), SMU_MUNIT(NONE), \ 261 + SMU_MTYPE(U16), node_id); \ 262 + SMU_SCALAR(SMU_MATTR(SYSTEM_TEMP_UBB_FPGA), SMU_MUNIT(TEMP_1), \ 263 + SMU_MTYPE(S16), system_temp_ubb_fpga); \ 264 + SMU_SCALAR(SMU_MATTR(SYSTEM_TEMP_UBB_FRONT), SMU_MUNIT(TEMP_1), \ 265 + SMU_MTYPE(S16), system_temp_ubb_front); \ 266 + SMU_SCALAR(SMU_MATTR(SYSTEM_TEMP_UBB_BACK), SMU_MUNIT(TEMP_1), \ 267 + SMU_MTYPE(S16), system_temp_ubb_back); \ 268 + SMU_SCALAR(SMU_MATTR(SYSTEM_TEMP_UBB_OAM7), SMU_MUNIT(TEMP_1), \ 269 + SMU_MTYPE(S16), system_temp_ubb_oam7); \ 270 + SMU_SCALAR(SMU_MATTR(SYSTEM_TEMP_UBB_IBC), SMU_MUNIT(TEMP_1), \ 271 + SMU_MTYPE(S16), system_temp_ubb_ibc); \ 272 + SMU_SCALAR(SMU_MATTR(SYSTEM_TEMP_UBB_UFPGA), SMU_MUNIT(TEMP_1), \ 273 + SMU_MTYPE(S16), system_temp_ubb_ufpga); \ 274 + SMU_SCALAR(SMU_MATTR(SYSTEM_TEMP_UBB_OAM1), SMU_MUNIT(TEMP_1), \ 275 + SMU_MTYPE(S16), system_temp_ubb_oam1); \ 276 + SMU_SCALAR(SMU_MATTR(SYSTEM_TEMP_OAM_0_1_HSC), SMU_MUNIT(TEMP_1), \ 277 + SMU_MTYPE(S16), system_temp_oam_0_1_hsc); \ 278 + SMU_SCALAR(SMU_MATTR(SYSTEM_TEMP_OAM_2_3_HSC), SMU_MUNIT(TEMP_1), \ 279 + SMU_MTYPE(S16), system_temp_oam_2_3_hsc); \ 280 + SMU_SCALAR(SMU_MATTR(SYSTEM_TEMP_OAM_4_5_HSC), SMU_MUNIT(TEMP_1), \ 281 + SMU_MTYPE(S16), system_temp_oam_4_5_hsc); \ 282 + SMU_SCALAR(SMU_MATTR(SYSTEM_TEMP_OAM_6_7_HSC), SMU_MUNIT(TEMP_1), \ 283 + SMU_MTYPE(S16), system_temp_oam_6_7_hsc); \ 284 + SMU_SCALAR(SMU_MATTR(SYSTEM_TEMP_UBB_FPGA_0V72_VR), SMU_MUNIT(TEMP_1), \ 285 + SMU_MTYPE(S16), system_temp_ubb_fpga_0v72_vr); \ 286 + SMU_SCALAR(SMU_MATTR(SYSTEM_TEMP_UBB_FPGA_3V3_VR), SMU_MUNIT(TEMP_1), \ 287 + SMU_MTYPE(S16), system_temp_ubb_fpga_3v3_vr); \ 288 + SMU_SCALAR(SMU_MATTR(SYSTEM_TEMP_RETIMER_0_1_2_3_1V2_VR), SMU_MUNIT(TEMP_1), \ 289 + SMU_MTYPE(S16), system_temp_retimer_0_1_2_3_1v2_vr); \ 290 + SMU_SCALAR(SMU_MATTR(SYSTEM_TEMP_RETIMER_4_5_6_7_1V2_VR), SMU_MUNIT(TEMP_1), \ 291 + SMU_MTYPE(S16), system_temp_retimer_4_5_6_7_1v2_vr); \ 292 + SMU_SCALAR(SMU_MATTR(SYSTEM_TEMP_RETIMER_0_1_0V9_VR), SMU_MUNIT(TEMP_1), \ 293 + SMU_MTYPE(S16), system_temp_retimer_0_1_0v9_vr); \ 294 + SMU_SCALAR(SMU_MATTR(SYSTEM_TEMP_RETIMER_4_5_0V9_VR), SMU_MUNIT(TEMP_1), \ 295 + SMU_MTYPE(S16), system_temp_retimer_4_5_0v9_vr); \ 296 + SMU_SCALAR(SMU_MATTR(SYSTEM_TEMP_RETIMER_2_3_0V9_VR), SMU_MUNIT(TEMP_1), \ 297 + SMU_MTYPE(S16), system_temp_retimer_2_3_0v9_vr); \ 298 + SMU_SCALAR(SMU_MATTR(SYSTEM_TEMP_RETIMER_6_7_0V9_VR), SMU_MUNIT(TEMP_1), \ 299 + SMU_MTYPE(S16), system_temp_retimer_6_7_0v9_vr); \ 300 + SMU_SCALAR(SMU_MATTR(SYSTEM_TEMP_OAM_0_1_2_3_3V3_VR), SMU_MUNIT(TEMP_1), \ 301 + SMU_MTYPE(S16), system_temp_oam_0_1_2_3_3v3_vr); \ 302 + SMU_SCALAR(SMU_MATTR(SYSTEM_TEMP_OAM_4_5_6_7_3V3_VR), SMU_MUNIT(TEMP_1), \ 303 + SMU_MTYPE(S16), system_temp_oam_4_5_6_7_3v3_vr); \ 304 + SMU_SCALAR(SMU_MATTR(SYSTEM_TEMP_IBC_HSC), SMU_MUNIT(TEMP_1), \ 305 + SMU_MTYPE(S16), system_temp_ibc_hsc); \ 306 + SMU_SCALAR(SMU_MATTR(SYSTEM_TEMP_IBC), SMU_MUNIT(TEMP_1), \ 307 + SMU_MTYPE(S16), system_temp_ibc); 308 + 309 + DECLARE_SMU_METRICS_CLASS(smu_v15_0_8_baseboard_temp_metrics, 310 + SMU_15_0_8_BASEBOARD_TEMP_METRICS_FIELDS); 255 311 #endif 256 312 #endif