tjh.dev / kernel
Linux kernel mirror (for testing) git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
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Merge tag 'fixes-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc

Pull ARM SoC fixes from Arnd Bergmann:
"The arm-soc bug fixes this time around are mostly for the omap
platform, coming from a pull request from Tony Lindgren and are almost
entirely fixing dts files.

The other two changes enable support for the shmobile platform in
generic armv7 kernels and change some properties in the ARM64
reference board dts files"

* tag 'fixes-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc:
ARM: multi_v7_defconfig: Enable shmobile platforms
arm64: Add L2 cache topology to ARM Ltd boards/models
ARM: dts: am335x-bone*: usb0 is hardwired for peripheral
ARM: dts: dra7x-evm: beagle-x15: Fix USB Host
ARM: omap2plus_defconfig: Fix SATA boot
ARM: omap2plus_defconfig: Enable OMAP NAND BCH driver
ARM: dts: dra7: Correct the dma controller's property names
ARM: dts: omap5: Correct the dma controller's property names
ARM: dts: omap4: Correct the dma controller's property names
ARM: dts: omap3: Correct the dma controller's property names
ARM: dts: omap2: Correct the dma controller's property names
ARM: dts: am437x-idk: fix sleep pinctrl state
ARM: omap2plus_defconfig: enable TPS62362 regulator
ARM: dts: am437x-idk: fix TPS62362 i2c bus
ARM: dts: n900: Fix offset for smc91x ethernet
ARM: dts: n900: fix i2c bus numbering
ARM: dts: Fix USB dts configuration for dm816x
ARM: dts: OMAP5: Fix SATA PHY node
ARM: dts: DRA7: Fix SATA PHY node

Linus Torvalds 895c8b7b 8d20a3dd

+190 -72
+1
arch/arm/boot/dts/am335x-bone-common.dtsi
··· 195 195 196 196 &usb0 { 197 197 status = "okay"; 198 + dr_mode = "peripheral"; 198 199 }; 199 200 200 201 &usb1 {
+2 -23
arch/arm/boot/dts/am437x-idk-evm.dts
··· 133 133 >; 134 134 }; 135 135 136 - i2c1_pins_default: i2c1_pins_default { 137 - pinctrl-single,pins = < 138 - 0x15c (PIN_INPUT | SLEWCTRL_FAST | MUX_MODE2) /* spi0_cs0.i2c1_scl */ 139 - 0x158 (PIN_INPUT | SLEWCTRL_FAST | MUX_MODE2) /* spi0_d1.i2c1_sda */ 140 - >; 141 - }; 142 - 143 - i2c1_pins_sleep: i2c1_pins_sleep { 144 - pinctrl-single,pins = < 145 - 0x15c (PIN_INPUT_PULLDOWN | MUX_MODE7) /* spi0_cs0.i2c1_scl */ 146 - 0x158 (PIN_INPUT_PULLDOWN | MUX_MODE7) /* spi0_d1.i2c1_sda */ 147 - >; 148 - }; 149 - 150 136 mmc1_pins_default: pinmux_mmc1_pins_default { 151 137 pinctrl-single,pins = < 152 138 0x100 (PIN_INPUT | MUX_MODE0) /* mmc0_clk.mmc0_clk */ ··· 240 254 status = "okay"; 241 255 pinctrl-names = "default", "sleep"; 242 256 pinctrl-0 = <&i2c0_pins_default>; 243 - pinctrl-1 = <&i2c0_pins_default>; 257 + pinctrl-1 = <&i2c0_pins_sleep>; 244 258 clock-frequency = <400000>; 245 259 246 260 at24@50 { ··· 248 262 pagesize = <64>; 249 263 reg = <0x50>; 250 264 }; 251 - }; 252 - 253 - &i2c1 { 254 - status = "okay"; 255 - pinctrl-names = "default", "sleep"; 256 - pinctrl-0 = <&i2c1_pins_default>; 257 - pinctrl-1 = <&i2c1_pins_default>; 258 - clock-frequency = <400000>; 259 265 260 266 tps: tps62362@60 { 261 267 compatible = "ti,tps62362"; 268 + reg = <0x60>; 262 269 regulator-name = "VDD_MPU"; 263 270 regulator-min-microvolt = <950000>; 264 271 regulator-max-microvolt = <1330000>;
-8
arch/arm/boot/dts/am57xx-beagle-x15.dts
··· 549 549 pinctrl-0 = <&usb1_pins>; 550 550 }; 551 551 552 - &omap_dwc3_1 { 553 - extcon = <&extcon_usb1>; 554 - }; 555 - 556 - &omap_dwc3_2 { 557 - extcon = <&extcon_usb2>; 558 - }; 559 - 560 552 &usb2 { 561 553 dr_mode = "peripheral"; 562 554 };
+25
arch/arm/boot/dts/dm8168-evm.dts
··· 35 35 DM816X_IOPAD(0x0aac, PIN_INPUT | MUX_MODE0) /* SPI_D1 */ 36 36 >; 37 37 }; 38 + 39 + usb0_pins: pinmux_usb0_pins { 40 + pinctrl-single,pins = < 41 + DM816X_IOPAD(0x0d00, MUX_MODE0) /* USB0_DRVVBUS */ 42 + >; 43 + }; 44 + 45 + usb1_pins: pinmux_usb0_pins { 46 + pinctrl-single,pins = < 47 + DM816X_IOPAD(0x0d04, MUX_MODE0) /* USB1_DRVVBUS */ 48 + >; 49 + }; 38 50 }; 39 51 40 52 &i2c1 { ··· 138 126 139 127 &mmc1 { 140 128 vmmc-supply = <&vmmcsd_fixed>; 129 + }; 130 + 131 + /* At least dm8168-evm rev c won't support multipoint, later may */ 132 + &usb0 { 133 + pinctrl-names = "default"; 134 + pinctrl-0 = <&usb0_pins>; 135 + mentor,multipoint = <0>; 136 + }; 137 + 138 + &usb1 { 139 + pinctrl-names = "default"; 140 + pinctrl-0 = <&usb1_pins>; 141 + mentor,multipoint = <0>; 141 142 };
+30 -4
arch/arm/boot/dts/dm816x.dtsi
··· 97 97 98 98 /* Device Configuration Registers */ 99 99 scm_conf: syscon@600 { 100 - compatible = "syscon"; 100 + compatible = "syscon", "simple-bus"; 101 101 reg = <0x600 0x110>; 102 102 #address-cells = <1>; 103 103 #size-cells = <1>; 104 + ranges = <0 0x600 0x110>; 105 + 106 + usb_phy0: usb-phy@20 { 107 + compatible = "ti,dm8168-usb-phy"; 108 + reg = <0x20 0x8>; 109 + reg-names = "phy"; 110 + clocks = <&main_fapll 6>; 111 + clock-names = "refclk"; 112 + #phy-cells = <0>; 113 + syscon = <&scm_conf>; 114 + }; 115 + 116 + usb_phy1: usb-phy@28 { 117 + compatible = "ti,dm8168-usb-phy"; 118 + reg = <0x28 0x8>; 119 + reg-names = "phy"; 120 + clocks = <&main_fapll 6>; 121 + clock-names = "refclk"; 122 + #phy-cells = <0>; 123 + syscon = <&scm_conf>; 124 + }; 104 125 }; 105 126 106 127 scrm_clocks: clocks { ··· 378 357 reg-names = "mc", "control"; 379 358 interrupts = <18>; 380 359 interrupt-names = "mc"; 381 - dr_mode = "otg"; 360 + dr_mode = "host"; 361 + interface-type = <0>; 362 + phys = <&usb_phy0>; 363 + phy-names = "usb2-phy"; 382 364 mentor,multipoint = <1>; 383 365 mentor,num-eps = <16>; 384 366 mentor,ram-bits = <12>; ··· 390 366 391 367 usb1: usb@47401800 { 392 368 compatible = "ti,musb-am33xx"; 393 - status = "disabled"; 394 369 reg = <0x47401c00 0x400 395 370 0x47401800 0x200>; 396 371 reg-names = "mc", "control"; 397 372 interrupts = <19>; 398 373 interrupt-names = "mc"; 399 - dr_mode = "otg"; 374 + dr_mode = "host"; 375 + interface-type = <0>; 376 + phys = <&usb_phy1>; 377 + phy-names = "usb2-phy"; 400 378 mentor,multipoint = <1>; 401 379 mentor,num-eps = <16>; 402 380 mentor,ram-bits = <12>;
-8
arch/arm/boot/dts/dra7-evm.dts
··· 543 543 }; 544 544 }; 545 545 546 - &omap_dwc3_1 { 547 - extcon = <&extcon_usb1>; 548 - }; 549 - 550 - &omap_dwc3_2 { 551 - extcon = <&extcon_usb2>; 552 - }; 553 - 554 546 &usb1 { 555 547 dr_mode = "peripheral"; 556 548 pinctrl-names = "default";
+4 -4
arch/arm/boot/dts/dra7.dtsi
··· 249 249 <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>, 250 250 <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; 251 251 #dma-cells = <1>; 252 - #dma-channels = <32>; 253 - #dma-requests = <127>; 252 + dma-channels = <32>; 253 + dma-requests = <127>; 254 254 }; 255 255 256 256 gpio1: gpio@4ae10000 { ··· 1090 1090 <0x4A096800 0x40>; /* pll_ctrl */ 1091 1091 reg-names = "phy_rx", "phy_tx", "pll_ctrl"; 1092 1092 ctrl-module = <&omap_control_sata>; 1093 - clocks = <&sys_clkin1>; 1094 - clock-names = "sysclk"; 1093 + clocks = <&sys_clkin1>, <&sata_ref_clk>; 1094 + clock-names = "sysclk", "refclk"; 1095 1095 #phy-cells = <0>; 1096 1096 }; 1097 1097
-8
arch/arm/boot/dts/dra72-evm.dts
··· 380 380 phy-supply = <&ldo4_reg>; 381 381 }; 382 382 383 - &omap_dwc3_1 { 384 - extcon = <&extcon_usb1>; 385 - }; 386 - 387 - &omap_dwc3_2 { 388 - extcon = <&extcon_usb2>; 389 - }; 390 - 391 383 &usb1 { 392 384 dr_mode = "peripheral"; 393 385 pinctrl-names = "default";
+2 -2
arch/arm/boot/dts/omap2.dtsi
··· 87 87 <14>, 88 88 <15>; 89 89 #dma-cells = <1>; 90 - #dma-channels = <32>; 91 - #dma-requests = <64>; 90 + dma-channels = <32>; 91 + dma-requests = <64>; 92 92 }; 93 93 94 94 i2c1: i2c@48070000 {
+8 -1
arch/arm/boot/dts/omap3-n900.dts
··· 16 16 model = "Nokia N900"; 17 17 compatible = "nokia,omap3-n900", "ti,omap3430", "ti,omap3"; 18 18 19 + aliases { 20 + i2c0; 21 + i2c1 = &i2c1; 22 + i2c2 = &i2c2; 23 + i2c3 = &i2c3; 24 + }; 25 + 19 26 cpus { 20 27 cpu@0 { 21 28 cpu0-supply = <&vcc>; ··· 711 704 compatible = "smsc,lan91c94"; 712 705 interrupt-parent = <&gpio2>; 713 706 interrupts = <22 IRQ_TYPE_LEVEL_HIGH>; /* gpio54 */ 714 - reg = <1 0x300 0xf>; /* 16 byte IO range at offset 0x300 */ 707 + reg = <1 0 0xf>; /* 16 byte IO range */ 715 708 bank-width = <2>; 716 709 pinctrl-names = "default"; 717 710 pinctrl-0 = <&ethernet_pins>;
+2 -2
arch/arm/boot/dts/omap3.dtsi
··· 155 155 <14>, 156 156 <15>; 157 157 #dma-cells = <1>; 158 - #dma-channels = <32>; 159 - #dma-requests = <96>; 158 + dma-channels = <32>; 159 + dma-requests = <96>; 160 160 }; 161 161 162 162 omap3_pmx_core: pinmux@48002030 {
+2 -2
arch/arm/boot/dts/omap4.dtsi
··· 223 223 <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>, 224 224 <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>; 225 225 #dma-cells = <1>; 226 - #dma-channels = <32>; 227 - #dma-requests = <127>; 226 + dma-channels = <32>; 227 + dma-requests = <127>; 228 228 }; 229 229 230 230 gpio1: gpio@4a310000 {
+4 -4
arch/arm/boot/dts/omap5.dtsi
··· 238 238 <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>, 239 239 <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>; 240 240 #dma-cells = <1>; 241 - #dma-channels = <32>; 242 - #dma-requests = <127>; 241 + dma-channels = <32>; 242 + dma-requests = <127>; 243 243 }; 244 244 245 245 gpio1: gpio@4ae10000 { ··· 929 929 <0x4A096800 0x40>; /* pll_ctrl */ 930 930 reg-names = "phy_rx", "phy_tx", "pll_ctrl"; 931 931 ctrl-module = <&omap_control_sata>; 932 - clocks = <&sys_clkin>; 933 - clock-names = "sysclk"; 932 + clocks = <&sys_clkin>, <&sata_ref_clk>; 933 + clock-names = "sysclk", "refclk"; 934 934 #phy-cells = <0>; 935 935 }; 936 936 };
+77 -5
arch/arm/configs/multi_v7_defconfig
··· 62 62 CONFIG_ARCH_STI=y 63 63 CONFIG_ARCH_EXYNOS=y 64 64 CONFIG_EXYNOS5420_MCPM=y 65 + CONFIG_ARCH_SHMOBILE_MULTI=y 66 + CONFIG_ARCH_EMEV2=y 67 + CONFIG_ARCH_R7S72100=y 68 + CONFIG_ARCH_R8A73A4=y 69 + CONFIG_ARCH_R8A7740=y 70 + CONFIG_ARCH_R8A7779=y 71 + CONFIG_ARCH_R8A7790=y 72 + CONFIG_ARCH_R8A7791=y 73 + CONFIG_ARCH_R8A7794=y 74 + CONFIG_ARCH_SH73A0=y 75 + CONFIG_MACH_MARZEN=y 65 76 CONFIG_ARCH_SUNXI=y 66 77 CONFIG_ARCH_SIRF=y 67 78 CONFIG_ARCH_TEGRA=y ··· 95 84 CONFIG_PCI_MSI=y 96 85 CONFIG_PCI_MVEBU=y 97 86 CONFIG_PCI_TEGRA=y 87 + CONFIG_PCI_RCAR_GEN2=y 88 + CONFIG_PCI_RCAR_GEN2_PCIE=y 98 89 CONFIG_PCIEPORTBUS=y 99 90 CONFIG_SMP=y 100 91 CONFIG_NR_CPUS=8 ··· 143 130 CONFIG_DMA_CMA=y 144 131 CONFIG_CMA_SIZE_MBYTES=64 145 132 CONFIG_OMAP_OCP2SCP=y 133 + CONFIG_SIMPLE_PM_BUS=y 146 134 CONFIG_MTD=y 147 135 CONFIG_MTD_CMDLINE_PARTS=y 148 136 CONFIG_MTD_BLOCK=y ··· 171 157 CONFIG_AHCI_TEGRA=y 172 158 CONFIG_SATA_HIGHBANK=y 173 159 CONFIG_SATA_MV=y 160 + CONFIG_SATA_RCAR=y 174 161 CONFIG_NETDEVICES=y 175 162 CONFIG_HIX5HD2_GMAC=y 176 163 CONFIG_SUN4I_EMAC=y ··· 182 167 CONFIG_MVNETA=y 183 168 CONFIG_KS8851=y 184 169 CONFIG_R8169=y 170 + CONFIG_SH_ETH=y 185 171 CONFIG_SMSC911X=y 186 172 CONFIG_STMMAC_ETH=y 187 173 CONFIG_TI_CPSW=y 188 174 CONFIG_XILINX_EMACLITE=y 189 175 CONFIG_AT803X_PHY=y 190 176 CONFIG_MARVELL_PHY=y 177 + CONFIG_SMSC_PHY=y 191 178 CONFIG_BROADCOM_PHY=y 192 179 CONFIG_ICPLUS_PHY=y 180 + CONFIG_MICREL_PHY=y 193 181 CONFIG_USB_PEGASUS=y 194 182 CONFIG_USB_USBNET=y 195 183 CONFIG_USB_NET_SMSC75XX=y ··· 210 192 CONFIG_MOUSE_PS2_ELANTECH=y 211 193 CONFIG_INPUT_TOUCHSCREEN=y 212 194 CONFIG_TOUCHSCREEN_ATMEL_MXT=y 195 + CONFIG_TOUCHSCREEN_ST1232=m 213 196 CONFIG_TOUCHSCREEN_STMPE=y 214 197 CONFIG_TOUCHSCREEN_SUN4I=y 215 198 CONFIG_INPUT_MISC=y 216 199 CONFIG_INPUT_MPU3050=y 217 200 CONFIG_INPUT_AXP20X_PEK=y 201 + CONFIG_INPUT_ADXL34X=m 218 202 CONFIG_SERIO_AMBAKMI=y 219 203 CONFIG_SERIAL_8250=y 220 204 CONFIG_SERIAL_8250_CONSOLE=y 221 205 CONFIG_SERIAL_8250_DW=y 206 + CONFIG_SERIAL_8250_EM=y 222 207 CONFIG_SERIAL_8250_MT6577=y 223 208 CONFIG_SERIAL_AMBA_PL011=y 224 209 CONFIG_SERIAL_AMBA_PL011_CONSOLE=y ··· 234 213 CONFIG_SERIAL_TEGRA=y 235 214 CONFIG_SERIAL_IMX=y 236 215 CONFIG_SERIAL_IMX_CONSOLE=y 216 + CONFIG_SERIAL_SH_SCI=y 217 + CONFIG_SERIAL_SH_SCI_NR_UARTS=20 218 + CONFIG_SERIAL_SH_SCI_CONSOLE=y 237 219 CONFIG_SERIAL_MSM=y 238 220 CONFIG_SERIAL_MSM_CONSOLE=y 239 221 CONFIG_SERIAL_VT8500=y ··· 257 233 CONFIG_I2C_MUX_PINCTRL=y 258 234 CONFIG_I2C_CADENCE=y 259 235 CONFIG_I2C_DESIGNWARE_PLATFORM=y 236 + CONFIG_I2C_GPIO=m 260 237 CONFIG_I2C_EXYNOS5=y 261 238 CONFIG_I2C_MV64XXX=y 239 + CONFIG_I2C_RIIC=y 262 240 CONFIG_I2C_S3C2410=y 241 + CONFIG_I2C_SH_MOBILE=y 263 242 CONFIG_I2C_SIRF=y 264 - CONFIG_I2C_TEGRA=y 265 243 CONFIG_I2C_ST=y 266 - CONFIG_SPI=y 244 + CONFIG_I2C_TEGRA=y 267 245 CONFIG_I2C_XILINX=y 268 - CONFIG_SPI_DAVINCI=y 246 + CONFIG_I2C_RCAR=y 247 + CONFIG_SPI=y 269 248 CONFIG_SPI_CADENCE=y 249 + CONFIG_SPI_DAVINCI=y 270 250 CONFIG_SPI_OMAP24XX=y 271 251 CONFIG_SPI_ORION=y 272 252 CONFIG_SPI_PL022=y 253 + CONFIG_SPI_RSPI=y 254 + CONFIG_SPI_SH_MSIOF=m 255 + CONFIG_SPI_SH_HSPI=y 273 256 CONFIG_SPI_SIRF=y 274 257 CONFIG_SPI_SUN4I=y 275 258 CONFIG_SPI_SUN6I=y ··· 290 259 CONFIG_PINCTRL_APQ8084=y 291 260 CONFIG_GPIO_SYSFS=y 292 261 CONFIG_GPIO_GENERIC_PLATFORM=y 293 - CONFIG_GPIO_DWAPB=y 294 262 CONFIG_GPIO_DAVINCI=y 263 + CONFIG_GPIO_DWAPB=y 264 + CONFIG_GPIO_EM=y 265 + CONFIG_GPIO_RCAR=y 295 266 CONFIG_GPIO_XILINX=y 296 267 CONFIG_GPIO_ZYNQ=y 297 268 CONFIG_GPIO_PCA953X=y 298 269 CONFIG_GPIO_PCA953X_IRQ=y 270 + CONFIG_GPIO_PCF857X=y 299 271 CONFIG_GPIO_TWL4030=y 300 272 CONFIG_GPIO_PALMAS=y 301 273 CONFIG_GPIO_SYSCON=y ··· 310 276 CONFIG_POWER_RESET_GPIO=y 311 277 CONFIG_POWER_RESET_KEYSTONE=y 312 278 CONFIG_POWER_RESET_SUN6I=y 279 + CONFIG_POWER_RESET_RMOBILE=y 313 280 CONFIG_SENSORS_LM90=y 314 281 CONFIG_SENSORS_LM95245=y 315 282 CONFIG_THERMAL=y 316 283 CONFIG_CPU_THERMAL=y 284 + CONFIG_RCAR_THERMAL=y 317 285 CONFIG_ARMADA_THERMAL=y 318 286 CONFIG_DAVINCI_WATCHDOG 319 287 CONFIG_ST_THERMAL_SYSCFG=y ··· 326 290 CONFIG_ORION_WATCHDOG=y 327 291 CONFIG_SUNXI_WATCHDOG=y 328 292 CONFIG_MESON_WATCHDOG=y 293 + CONFIG_MFD_AS3711=y 329 294 CONFIG_MFD_AS3722=y 330 295 CONFIG_MFD_BCM590XX=y 331 296 CONFIG_MFD_AXP20X=y ··· 341 304 CONFIG_MFD_TPS6586X=y 342 305 CONFIG_MFD_TPS65910=y 343 306 CONFIG_REGULATOR_AB8500=y 307 + CONFIG_REGULATOR_AS3711=y 344 308 CONFIG_REGULATOR_AS3722=y 345 309 CONFIG_REGULATOR_AXP20X=y 346 310 CONFIG_REGULATOR_BCM590XX=y 311 + CONFIG_REGULATOR_DA9210=y 347 312 CONFIG_REGULATOR_GPIO=y 348 313 CONFIG_MFD_SYSCON=y 349 314 CONFIG_POWER_RESET_SYSCON=y 350 315 CONFIG_REGULATOR_MAX8907=y 316 + CONFIG_REGULATOR_MAX8973=y 351 317 CONFIG_REGULATOR_MAX77686=y 352 318 CONFIG_REGULATOR_PALMAS=y 353 319 CONFIG_REGULATOR_S2MPS11=y ··· 364 324 CONFIG_REGULATOR_VEXPRESS=y 365 325 CONFIG_MEDIA_SUPPORT=y 366 326 CONFIG_MEDIA_CAMERA_SUPPORT=y 327 + CONFIG_MEDIA_CONTROLLER=y 328 + CONFIG_VIDEO_V4L2_SUBDEV_API=y 367 329 CONFIG_MEDIA_USB_SUPPORT=y 368 330 CONFIG_USB_VIDEO_CLASS=y 369 331 CONFIG_USB_GSPCA=y 332 + CONFIG_V4L_PLATFORM_DRIVERS=y 333 + CONFIG_SOC_CAMERA=m 334 + CONFIG_SOC_CAMERA_PLATFORM=m 335 + CONFIG_VIDEO_RCAR_VIN=m 336 + CONFIG_V4L_MEM2MEM_DRIVERS=y 337 + CONFIG_VIDEO_RENESAS_VSP1=m 338 + # CONFIG_MEDIA_SUBDRV_AUTOSELECT is not set 339 + CONFIG_VIDEO_ADV7180=m 370 340 CONFIG_DRM=y 341 + CONFIG_DRM_RCAR_DU=m 371 342 CONFIG_DRM_TEGRA=y 372 343 CONFIG_DRM_PANEL_SIMPLE=y 373 344 CONFIG_FB_ARMCLCD=y 374 345 CONFIG_FB_WM8505=y 346 + CONFIG_FB_SH_MOBILE_LCDC=y 375 347 CONFIG_FB_SIMPLE=y 348 + CONFIG_FB_SH_MOBILE_MERAM=y 376 349 CONFIG_BACKLIGHT_LCD_SUPPORT=y 377 350 CONFIG_BACKLIGHT_CLASS_DEVICE=y 378 351 CONFIG_BACKLIGHT_PWM=y 352 + CONFIG_BACKLIGHT_AS3711=y 379 353 CONFIG_FRAMEBUFFER_CONSOLE=y 380 354 CONFIG_FRAMEBUFFER_CONSOLE_ROTATION=y 381 355 CONFIG_SOUND=y ··· 397 343 CONFIG_SND_DYNAMIC_MINORS=y 398 344 CONFIG_SND_USB_AUDIO=y 399 345 CONFIG_SND_SOC=y 346 + CONFIG_SND_SOC_SH4_FSI=m 347 + CONFIG_SND_SOC_RCAR=m 400 348 CONFIG_SND_SOC_TEGRA=y 401 349 CONFIG_SND_SOC_TEGRA_RT5640=y 402 350 CONFIG_SND_SOC_TEGRA_WM8753=y ··· 406 350 CONFIG_SND_SOC_TEGRA_TRIMSLICE=y 407 351 CONFIG_SND_SOC_TEGRA_ALC5632=y 408 352 CONFIG_SND_SOC_TEGRA_MAX98090=y 353 + CONFIG_SND_SOC_AK4642=m 354 + CONFIG_SND_SOC_WM8978=m 409 355 CONFIG_USB=y 410 356 CONFIG_USB_XHCI_HCD=y 411 357 CONFIG_USB_XHCI_MVEBU=y ··· 420 362 CONFIG_USB_OHCI_HCD=y 421 363 CONFIG_USB_OHCI_HCD_STI=y 422 364 CONFIG_USB_OHCI_HCD_PLATFORM=y 365 + CONFIG_USB_R8A66597_HCD=m 366 + CONFIG_USB_RENESAS_USBHS=m 423 367 CONFIG_USB_STORAGE=y 424 368 CONFIG_USB_DWC3=y 425 369 CONFIG_USB_CHIPIDEA=y ··· 434 374 CONFIG_USB_GPIO_VBUS=y 435 375 CONFIG_USB_ISP1301=y 436 376 CONFIG_USB_MXS_PHY=y 377 + CONFIG_USB_RCAR_PHY=m 378 + CONFIG_USB_RCAR_GEN2_PHY=m 379 + CONFIG_USB_GADGET=y 380 + CONFIG_USB_RENESAS_USBHS_UDC=m 437 381 CONFIG_MMC=y 438 382 CONFIG_MMC_BLOCK_MINORS=16 439 383 CONFIG_MMC_ARMMMCI=y ··· 456 392 CONFIG_MMC_OMAP=y 457 393 CONFIG_MMC_OMAP_HS=y 458 394 CONFIG_MMC_MVSDIO=y 459 - CONFIG_MMC_SUNXI=y 395 + CONFIG_MMC_SDHI=y 460 396 CONFIG_MMC_DW=y 461 397 CONFIG_MMC_DW_IDMAC=y 462 398 CONFIG_MMC_DW_PLTFM=y 463 399 CONFIG_MMC_DW_EXYNOS=y 464 400 CONFIG_MMC_DW_ROCKCHIP=y 401 + CONFIG_MMC_SH_MMCIF=y 402 + CONFIG_MMC_SUNXI=y 465 403 CONFIG_NEW_LEDS=y 466 404 CONFIG_LEDS_CLASS=y 467 405 CONFIG_LEDS_GPIO=y ··· 487 421 CONFIG_RTC_DRV_DS1307=y 488 422 CONFIG_RTC_DRV_MAX8907=y 489 423 CONFIG_RTC_DRV_MAX77686=y 424 + CONFIG_RTC_DRV_RS5C372=m 490 425 CONFIG_RTC_DRV_PALMAS=y 491 426 CONFIG_RTC_DRV_TWL4030=y 492 427 CONFIG_RTC_DRV_TPS6586X=y 493 428 CONFIG_RTC_DRV_TPS65910=y 429 + CONFIG_RTC_DRV_S35390A=m 494 430 CONFIG_RTC_DRV_EM3027=y 495 431 CONFIG_RTC_DRV_PL031=y 496 432 CONFIG_RTC_DRV_VT8500=y ··· 504 436 CONFIG_DW_DMAC=y 505 437 CONFIG_MV_XOR=y 506 438 CONFIG_TEGRA20_APB_DMA=y 439 + CONFIG_SH_DMAE=y 440 + CONFIG_RCAR_AUDMAC_PP=m 441 + CONFIG_RCAR_DMAC=y 507 442 CONFIG_STE_DMA40=y 508 443 CONFIG_SIRF_DMA=y 509 444 CONFIG_TI_EDMA=y ··· 539 468 CONFIG_XILINX_XADC=y 540 469 CONFIG_AK8975=y 541 470 CONFIG_PWM=y 471 + CONFIG_PWM_RENESAS_TPU=y 542 472 CONFIG_PWM_TEGRA=y 543 473 CONFIG_PWM_VT8500=y 544 474 CONFIG_PHY_HIX5HD2_SATA=y
+3 -1
arch/arm/configs/omap2plus_defconfig
··· 114 114 CONFIG_MTD_NAND=y 115 115 CONFIG_MTD_NAND_ECC_BCH=y 116 116 CONFIG_MTD_NAND_OMAP2=y 117 + CONFIG_MTD_NAND_OMAP_BCH=y 117 118 CONFIG_MTD_ONENAND=y 118 119 CONFIG_MTD_ONENAND_VERIFY_WRITE=y 119 120 CONFIG_MTD_ONENAND_OMAP2=y ··· 249 248 CONFIG_REGULATOR_PALMAS=y 250 249 CONFIG_REGULATOR_PBIAS=y 251 250 CONFIG_REGULATOR_TI_ABB=y 251 + CONFIG_REGULATOR_TPS62360=m 252 252 CONFIG_REGULATOR_TPS65023=y 253 253 CONFIG_REGULATOR_TPS6507X=y 254 254 CONFIG_REGULATOR_TPS65217=y ··· 376 374 CONFIG_PWM_TWL=m 377 375 CONFIG_PWM_TWL_LED=m 378 376 CONFIG_OMAP_USB2=m 379 - CONFIG_TI_PIPE3=m 377 + CONFIG_TI_PIPE3=y 380 378 CONFIG_EXT2_FS=y 381 379 CONFIG_EXT3_FS=y 382 380 # CONFIG_EXT3_FS_XATTR is not set
+8
arch/arm64/boot/dts/arm/foundation-v8.dts
··· 34 34 reg = <0x0 0x0>; 35 35 enable-method = "spin-table"; 36 36 cpu-release-addr = <0x0 0x8000fff8>; 37 + next-level-cache = <&L2_0>; 37 38 }; 38 39 cpu@1 { 39 40 device_type = "cpu"; ··· 42 41 reg = <0x0 0x1>; 43 42 enable-method = "spin-table"; 44 43 cpu-release-addr = <0x0 0x8000fff8>; 44 + next-level-cache = <&L2_0>; 45 45 }; 46 46 cpu@2 { 47 47 device_type = "cpu"; ··· 50 48 reg = <0x0 0x2>; 51 49 enable-method = "spin-table"; 52 50 cpu-release-addr = <0x0 0x8000fff8>; 51 + next-level-cache = <&L2_0>; 53 52 }; 54 53 cpu@3 { 55 54 device_type = "cpu"; ··· 58 55 reg = <0x0 0x3>; 59 56 enable-method = "spin-table"; 60 57 cpu-release-addr = <0x0 0x8000fff8>; 58 + next-level-cache = <&L2_0>; 59 + }; 60 + 61 + L2_0: l2-cache0 { 62 + compatible = "cache"; 61 63 }; 62 64 }; 63 65
+14
arch/arm64/boot/dts/arm/juno.dts
··· 39 39 reg = <0x0 0x0>; 40 40 device_type = "cpu"; 41 41 enable-method = "psci"; 42 + next-level-cache = <&A57_L2>; 42 43 }; 43 44 44 45 A57_1: cpu@1 { ··· 47 46 reg = <0x0 0x1>; 48 47 device_type = "cpu"; 49 48 enable-method = "psci"; 49 + next-level-cache = <&A57_L2>; 50 50 }; 51 51 52 52 A53_0: cpu@100 { ··· 55 53 reg = <0x0 0x100>; 56 54 device_type = "cpu"; 57 55 enable-method = "psci"; 56 + next-level-cache = <&A53_L2>; 58 57 }; 59 58 60 59 A53_1: cpu@101 { ··· 63 60 reg = <0x0 0x101>; 64 61 device_type = "cpu"; 65 62 enable-method = "psci"; 63 + next-level-cache = <&A53_L2>; 66 64 }; 67 65 68 66 A53_2: cpu@102 { ··· 71 67 reg = <0x0 0x102>; 72 68 device_type = "cpu"; 73 69 enable-method = "psci"; 70 + next-level-cache = <&A53_L2>; 74 71 }; 75 72 76 73 A53_3: cpu@103 { ··· 79 74 reg = <0x0 0x103>; 80 75 device_type = "cpu"; 81 76 enable-method = "psci"; 77 + next-level-cache = <&A53_L2>; 78 + }; 79 + 80 + A57_L2: l2-cache0 { 81 + compatible = "cache"; 82 + }; 83 + 84 + A53_L2: l2-cache1 { 85 + compatible = "cache"; 82 86 }; 83 87 }; 84 88
+8
arch/arm64/boot/dts/arm/rtsm_ve-aemv8a.dts
··· 37 37 reg = <0x0 0x0>; 38 38 enable-method = "spin-table"; 39 39 cpu-release-addr = <0x0 0x8000fff8>; 40 + next-level-cache = <&L2_0>; 40 41 }; 41 42 cpu@1 { 42 43 device_type = "cpu"; ··· 45 44 reg = <0x0 0x1>; 46 45 enable-method = "spin-table"; 47 46 cpu-release-addr = <0x0 0x8000fff8>; 47 + next-level-cache = <&L2_0>; 48 48 }; 49 49 cpu@2 { 50 50 device_type = "cpu"; ··· 53 51 reg = <0x0 0x2>; 54 52 enable-method = "spin-table"; 55 53 cpu-release-addr = <0x0 0x8000fff8>; 54 + next-level-cache = <&L2_0>; 56 55 }; 57 56 cpu@3 { 58 57 device_type = "cpu"; ··· 61 58 reg = <0x0 0x3>; 62 59 enable-method = "spin-table"; 63 60 cpu-release-addr = <0x0 0x8000fff8>; 61 + next-level-cache = <&L2_0>; 62 + }; 63 + 64 + L2_0: l2-cache0 { 65 + compatible = "cache"; 64 66 }; 65 67 }; 66 68