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git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
clk: qcom: gcc-sdm845: Add general purpose clock ops
SDM845 has "General Purpose" clocks that can be muxed to
SoC pins to clock various external devices.
Those clocks may be used as e.g. PWM sources for external peripherals.
GPCLK can in theory have arbitrary value depending on the use case, so
the concept of frequency tables, used in rcg2 clock driver, is not
efficient, because it allows only defined frequencies.
Introduce clk_rcg2_gp_ops, which automatically calculate clock
mnd values for arbitrary clock rate. The calculation done as follows:
- upon determine rate request, we calculate m/n/pre_div as follows:
- find parent(from our client's assigned-clock-parent) rate
- find scaled rates by dividing rates on its greatest common divisor
- assign requested scaled rate to m
- factorize scaled parent rate, put multipliers to n till max value
(determined by mnd_width)
- validate calculated values with *_width:
- if doesn't fit, delete divisor and multiplier by 2 until fit
- return determined rate
Limitations:
- The driver doesn't select a parent clock (it may be selected by client
in device tree with assigned-clocks, assigned-clock-parents properties)
Signed-off-by: Dzmitry Sankouski <dsankouski@gmail.com>
Link: https://lore.kernel.org/r/20241118-starqltechn_integration_upstream-v8-3-ac8e36a3aa65@gmail.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
authored by
Dzmitry Sankouski
and committed by
Bjorn Andersson
898b72fa
faddad52
+150
-8
+1
drivers/clk/qcom/clk-rcg.h
+1
drivers/clk/qcom/clk-rcg.h
···
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container_of(to_clk_rcg2(_hw), struct clk_rcg2_gfx3d, rcg)
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extern const struct clk_ops clk_rcg2_ops;
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extern const struct clk_ops clk_rcg2_gp_ops;
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extern const struct clk_ops clk_rcg2_floor_ops;
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extern const struct clk_ops clk_rcg2_fm_ops;
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extern const struct clk_ops clk_rcg2_mux_closest_ops;
+146
drivers/clk/qcom/clk-rcg2.c
+146
drivers/clk/qcom/clk-rcg2.c
···
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#include <linux/err.h>
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#include <linux/bug.h>
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#include <linux/export.h>
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#include <linux/clk.h>
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#include <linux/clk-provider.h>
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#include <linux/delay.h>
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#include <linux/rational.h>
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#include <linux/regmap.h>
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#include <linux/math64.h>
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#include <linux/gcd.h>
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#include <linux/minmax.h>
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#include <linux/slab.h>
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···
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#define CFG_REG 0x4
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#define CFG_SRC_DIV_SHIFT 0
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#define CFG_SRC_DIV_LENGTH 8
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#define CFG_SRC_SEL_SHIFT 8
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#define CFG_SRC_SEL_MASK (0x7 << CFG_SRC_SEL_SHIFT)
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#define CFG_MODE_SHIFT 12
···
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return ret;
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return update_config(rcg);
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}
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/**
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* convert_to_reg_val() - Convert divisor values to hardware values.
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*
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* @f: Frequency table with pure m/n/pre_div parameters.
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*/
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static void convert_to_reg_val(struct freq_tbl *f)
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{
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f->pre_div *= 2;
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f->pre_div -= 1;
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}
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/**
···
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return _freq_tbl_fm_determine_rate(hw, rcg->freq_multi_tbl, req);
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}
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/**
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* clk_rcg2_split_div() - Split multiplier that doesn't fit in n neither in pre_div.
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*
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* @multiplier: Multiplier to split between n and pre_div.
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* @pre_div: Pointer to pre divisor value.
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* @n: Pointer to n divisor value.
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* @pre_div_max: Pre divisor maximum value.
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*/
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static inline void clk_rcg2_split_div(int multiplier, unsigned int *pre_div,
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u16 *n, unsigned int pre_div_max)
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{
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*n = mult_frac(multiplier * *n, *pre_div, pre_div_max);
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*pre_div = pre_div_max;
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}
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static void clk_rcg2_calc_mnd(u64 parent_rate, u64 rate, struct freq_tbl *f,
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unsigned int mnd_max, unsigned int pre_div_max)
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{
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int i = 2;
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unsigned int pre_div = 1;
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unsigned long rates_gcd, scaled_parent_rate;
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u16 m, n = 1, n_candidate = 1, n_max;
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rates_gcd = gcd(parent_rate, rate);
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m = div64_u64(rate, rates_gcd);
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scaled_parent_rate = div64_u64(parent_rate, rates_gcd);
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while (scaled_parent_rate > (mnd_max + m) * pre_div_max) {
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// we're exceeding divisor's range, trying lower scale.
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if (m > 1) {
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m--;
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scaled_parent_rate = mult_frac(scaled_parent_rate, m, (m + 1));
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} else {
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// cannot lower scale, just set max divisor values.
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f->n = mnd_max + m;
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f->pre_div = pre_div_max;
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f->m = m;
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return;
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}
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}
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n_max = m + mnd_max;
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while (scaled_parent_rate > 1) {
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while (scaled_parent_rate % i == 0) {
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n_candidate *= i;
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if (n_candidate < n_max)
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n = n_candidate;
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else if (pre_div * i < pre_div_max)
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pre_div *= i;
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else
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clk_rcg2_split_div(i, &pre_div, &n, pre_div_max);
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scaled_parent_rate /= i;
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}
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i++;
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}
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f->m = m;
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f->n = n;
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f->pre_div = pre_div > 1 ? pre_div : 0;
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}
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static int clk_rcg2_determine_gp_rate(struct clk_hw *hw,
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struct clk_rate_request *req)
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{
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struct clk_rcg2 *rcg = to_clk_rcg2(hw);
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struct freq_tbl f_tbl = {}, *f = &f_tbl;
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int mnd_max = BIT(rcg->mnd_width) - 1;
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int hid_max = BIT(rcg->hid_width) - 1;
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struct clk_hw *parent;
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u64 parent_rate;
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parent = clk_hw_get_parent(hw);
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parent_rate = clk_get_rate(parent->clk);
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if (!parent_rate)
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return -EINVAL;
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clk_rcg2_calc_mnd(parent_rate, req->rate, f, mnd_max, hid_max / 2);
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convert_to_reg_val(f);
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req->rate = calc_rate(parent_rate, f->m, f->n, f->n, f->pre_div);
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return 0;
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}
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static int __clk_rcg2_configure_parent(struct clk_rcg2 *rcg, u8 src, u32 *_cfg)
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{
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struct clk_hw *hw = &rcg->clkr.hw;
···
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return update_config(rcg);
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}
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static int clk_rcg2_configure_gp(struct clk_rcg2 *rcg, const struct freq_tbl *f)
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{
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u32 cfg;
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int ret;
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ret = regmap_read(rcg->clkr.regmap, RCG_CFG_OFFSET(rcg), &cfg);
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if (ret)
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return ret;
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ret = __clk_rcg2_configure_mnd(rcg, f, &cfg);
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if (ret)
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return ret;
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ret = regmap_write(rcg->clkr.regmap, RCG_CFG_OFFSET(rcg), cfg);
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if (ret)
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return ret;
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return update_config(rcg);
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}
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static int __clk_rcg2_set_rate(struct clk_hw *hw, unsigned long rate,
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enum freq_policy policy)
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{
···
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unsigned long parent_rate)
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{
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return __clk_rcg2_set_rate(hw, rate, CEIL);
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}
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static int clk_rcg2_set_gp_rate(struct clk_hw *hw, unsigned long rate,
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unsigned long parent_rate)
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{
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struct clk_rcg2 *rcg = to_clk_rcg2(hw);
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int mnd_max = BIT(rcg->mnd_width) - 1;
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int hid_max = BIT(rcg->hid_width) - 1;
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struct freq_tbl f_tbl = {}, *f = &f_tbl;
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int ret;
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clk_rcg2_calc_mnd(parent_rate, rate, f, mnd_max, hid_max / 2);
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convert_to_reg_val(f);
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ret = clk_rcg2_configure_gp(rcg, f);
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return ret;
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}
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static int clk_rcg2_set_floor_rate(struct clk_hw *hw, unsigned long rate,
···
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.set_duty_cycle = clk_rcg2_set_duty_cycle,
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};
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EXPORT_SYMBOL_GPL(clk_rcg2_ops);
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const struct clk_ops clk_rcg2_gp_ops = {
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.is_enabled = clk_rcg2_is_enabled,
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.get_parent = clk_rcg2_get_parent,
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.set_parent = clk_rcg2_set_parent,
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.recalc_rate = clk_rcg2_recalc_rate,
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.determine_rate = clk_rcg2_determine_gp_rate,
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.set_rate = clk_rcg2_set_gp_rate,
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.get_duty_cycle = clk_rcg2_get_duty_cycle,
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.set_duty_cycle = clk_rcg2_set_duty_cycle,
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};
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EXPORT_SYMBOL_GPL(clk_rcg2_gp_ops);
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const struct clk_ops clk_rcg2_floor_ops = {
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.is_enabled = clk_rcg2_is_enabled,
+3
-8
drivers/clk/qcom/gcc-sdm845.c
+3
-8
drivers/clk/qcom/gcc-sdm845.c
···
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};
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static const struct freq_tbl ftbl_gcc_gp1_clk_src[] = {
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F(19200000, P_BI_TCXO, 1, 0, 0),
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F(25000000, P_GPLL0_OUT_EVEN, 12, 0, 0),
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F(50000000, P_GPLL0_OUT_EVEN, 6, 0, 0),
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F(100000000, P_GPLL0_OUT_MAIN, 6, 0, 0),
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F(200000000, P_GPLL0_OUT_MAIN, 3, 0, 0),
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{ }
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};
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···
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.name = "gcc_gp1_clk_src",
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.parent_data = gcc_parent_data_1,
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.num_parents = ARRAY_SIZE(gcc_parent_data_1),
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.ops = &clk_rcg2_ops,
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.ops = &clk_rcg2_gp_ops,
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},
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};
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···
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.name = "gcc_gp2_clk_src",
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.parent_data = gcc_parent_data_1,
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.num_parents = ARRAY_SIZE(gcc_parent_data_1),
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.ops = &clk_rcg2_ops,
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.ops = &clk_rcg2_gp_ops,
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},
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};
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···
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.name = "gcc_gp3_clk_src",
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.parent_data = gcc_parent_data_1,
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.num_parents = ARRAY_SIZE(gcc_parent_data_1),
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.ops = &clk_rcg2_ops,
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.ops = &clk_rcg2_gp_ops,
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},
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};
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