Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
drm/amd/ras: add initialization func for pmfw eeprom
add initialization func for pmfw eeprom
Signed-off-by: Gangliang Xie <ganglxie@amd.com>
Reviewed-by: Tao Zhou <tao.zhou1@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
authored by
Gangliang Xie
and committed by
Alex Deucher
89b814a3
72289903
+98
-3
+12
-3
drivers/gpu/drm/amd/ras/rascore/ras_core.c
+12
-3
drivers/gpu/drm/amd/ras/rascore/ras_core.c
···
389
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ras_fw_init_feature_flags(ras_core);
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-
ret = ras_eeprom_hw_init(ras_core);
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+
if (ras_fw_eeprom_supported(ras_core))
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+
ret = ras_fw_eeprom_hw_init(ras_core);
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+
else
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ret = ras_eeprom_hw_init(ras_core);
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if (ret)
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goto init_err6;
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···
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return 0;
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init_err7:
419
-
ras_eeprom_hw_fini(ras_core);
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+
if (ras_fw_eeprom_supported(ras_core))
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+
ras_fw_eeprom_hw_fini(ras_core);
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+
else
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+
ras_eeprom_hw_fini(ras_core);
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init_err6:
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ras_gfx_hw_fini(ras_core);
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422
init_err5:
···
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ras_core->is_initialized = false;
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ras_process_fini(ras_core);
443
-
ras_eeprom_hw_fini(ras_core);
437
+
if (ras_fw_eeprom_supported(ras_core))
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+
ras_fw_eeprom_hw_fini(ras_core);
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+
else
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ras_eeprom_hw_fini(ras_core);
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ras_gfx_hw_fini(ras_core);
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ras_nbio_hw_fini(ras_core);
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ras_umc_hw_fini(ras_core);
+84
drivers/gpu/drm/amd/ras/rascore/ras_eeprom_fw.c
+84
drivers/gpu/drm/amd/ras/rascore/ras_eeprom_fw.c
···
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return ret;
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}
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+
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+
static int __check_ras_fw_table_status(struct ras_core_context *ras_core)
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+
{
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struct ras_fw_eeprom_control *control = &ras_core->ras_fw_eeprom;
376
+
uint64_t local_time;
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+
int res;
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+
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+
mutex_init(&control->ras_tbl_mutex);
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+
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+
res = ras_fw_get_table_version(ras_core, &(control->version));
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+
if (res)
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+
return res;
384
+
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+
res = ras_fw_get_badpage_count(ras_core, &(control->ras_num_recs), 100);
386
+
if (res)
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+
return res;
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+
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+
local_time = (uint64_t)ktime_get_real_seconds();
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+
res = ras_fw_set_timestamp(ras_core, local_time);
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+
if (res)
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+
return res;
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+
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+
control->ras_max_record_count = 4000;
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+
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+
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+
if (control->ras_num_recs > control->ras_max_record_count) {
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RAS_DEV_ERR(ras_core->dev,
399
+
"RAS header invalid, records in header: %u max allowed :%u",
400
+
control->ras_num_recs, control->ras_max_record_count);
401
+
return -EINVAL;
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+
}
403
+
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+
return 0;
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+
}
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+
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+
int ras_fw_eeprom_hw_init(struct ras_core_context *ras_core)
408
+
{
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struct ras_fw_eeprom_control *control;
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+
struct ras_eeprom_config *eeprom_cfg;
411
+
struct ras_mp1 *mp1;
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+
const struct ras_mp1_sys_func *sys_func;
413
+
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+
if (!ras_core)
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+
return -EINVAL;
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+
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+
mp1 = &ras_core->ras_mp1;
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+
sys_func = mp1->sys_func;
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+
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+
if (!sys_func || !sys_func->mp1_send_eeprom_msg)
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+
return -EINVAL;
422
+
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+
ras_core->is_rma = false;
424
+
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+
control = &ras_core->ras_fw_eeprom;
426
+
427
+
memset(control, 0, sizeof(*control));
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+
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+
eeprom_cfg = &ras_core->config->eeprom_cfg;
430
+
control->record_threshold_config =
431
+
eeprom_cfg->eeprom_record_threshold_config;
432
+
433
+
control->record_threshold_count = 4000;
434
+
if (eeprom_cfg->eeprom_record_threshold_count <
435
+
control->record_threshold_count)
436
+
control->record_threshold_count =
437
+
eeprom_cfg->eeprom_record_threshold_count;
438
+
439
+
control->update_channel_flag = false;
440
+
441
+
return __check_ras_fw_table_status(ras_core);
442
+
}
443
+
444
+
int ras_fw_eeprom_hw_fini(struct ras_core_context *ras_core)
445
+
{
446
+
struct ras_fw_eeprom_control *control;
447
+
448
+
if (!ras_core)
449
+
return -EINVAL;
450
+
451
+
control = &ras_core->ras_fw_eeprom;
452
+
mutex_destroy(&control->ras_tbl_mutex);
453
+
454
+
return 0;
455
+
}
+2
drivers/gpu/drm/amd/ras/rascore/ras_eeprom_fw.h
+2
drivers/gpu/drm/amd/ras/rascore/ras_eeprom_fw.h
···
77
77
uint32_t ras_fw_eeprom_get_record_count(struct ras_core_context *ras_core);
78
78
int ras_fw_eeprom_update_record(struct ras_core_context *ras_core,
79
79
struct ras_bank_ecc *ras_ecc);
80
+
int ras_fw_eeprom_hw_init(struct ras_core_context *ras_core);
81
+
int ras_fw_eeprom_hw_fini(struct ras_core_context *ras_core);
80
82
81
83
#endif