Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
iio: adc: rzg2l_adc: Simplify the runtime PM code
All Renesas SoCs using the rzg2l_adc driver manage ADC clocks through PM
domains. Calling pm_runtime_{resume_and_get, put_sync}() implicitly sets
the state of the clocks. As a result, the code in the rzg2l_adc driver that
explicitly manages ADC clocks can be removed, leading to simpler and
cleaner implementation.
Additionally, replace the use of rzg2l_adc_set_power() with direct PM
runtime API calls to further simplify and clean up the code.
Signed-off-by: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com>
Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Link: https://patch.msgid.link/20241206111337.726244-5-claudiu.beznea.uj@bp.renesas.com
Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
authored by
Claudiu Beznea
and committed by
Jonathan Cameron
89ee8174
b010b104
+20
-78
+20
-78
drivers/iio/adc/rzg2l_adc.c
+20
-78
drivers/iio/adc/rzg2l_adc.c
···
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*/
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#include <linux/bitfield.h>
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-
#include <linux/clk.h>
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#include <linux/completion.h>
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#include <linux/delay.h>
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#include <linux/iio/iio.h>
···
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struct rzg2l_adc {
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void __iomem *base;
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struct clk *pclk;
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struct clk *adclk;
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struct reset_control *presetn;
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struct reset_control *adrstn;
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struct completion completion;
···
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return 0;
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}
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static int rzg2l_adc_set_power(struct iio_dev *indio_dev, bool on)
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{
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struct device *dev = indio_dev->dev.parent;
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-
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if (on)
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return pm_runtime_resume_and_get(dev);
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-
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return pm_runtime_put_sync(dev);
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}
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static int rzg2l_adc_conversion(struct iio_dev *indio_dev, struct rzg2l_adc *adc, u8 ch)
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{
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struct device *dev = indio_dev->dev.parent;
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int ret;
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ret = rzg2l_adc_set_power(indio_dev, true);
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ret = pm_runtime_resume_and_get(dev);
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if (ret)
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return ret;
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ret = rzg2l_adc_conversion_setup(adc, ch);
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if (ret) {
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rzg2l_adc_set_power(indio_dev, false);
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return ret;
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}
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if (ret)
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goto rpm_put;
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reinit_completion(&adc->completion);
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···
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if (!wait_for_completion_timeout(&adc->completion, RZG2L_ADC_TIMEOUT)) {
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rzg2l_adc_writel(adc, RZG2L_ADINT,
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rzg2l_adc_readl(adc, RZG2L_ADINT) & ~RZG2L_ADINT_INTEN_MASK);
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rzg2l_adc_start_stop(adc, false);
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rzg2l_adc_set_power(indio_dev, false);
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return -ETIMEDOUT;
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ret = -ETIMEDOUT;
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}
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return rzg2l_adc_set_power(indio_dev, false);
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rzg2l_adc_start_stop(adc, false);
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rpm_put:
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pm_runtime_put_sync(dev);
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return ret;
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}
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static int rzg2l_adc_read_raw(struct iio_dev *indio_dev,
···
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return 0;
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}
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static int rzg2l_adc_hw_init(struct rzg2l_adc *adc)
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static int rzg2l_adc_hw_init(struct device *dev, struct rzg2l_adc *adc)
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{
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int timeout = 5;
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u32 reg;
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int ret;
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ret = clk_prepare_enable(adc->pclk);
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ret = pm_runtime_resume_and_get(dev);
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if (ret)
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return ret;
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···
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rzg2l_adc_writel(adc, RZG2L_ADM(3), reg);
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exit_hw_init:
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clk_disable_unprepare(adc->pclk);
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pm_runtime_put_sync(dev);
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return ret;
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}
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static void rzg2l_adc_pm_runtime_disable(void *data)
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{
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struct device *dev = data;
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pm_runtime_disable(dev->parent);
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}
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static void rzg2l_adc_pm_runtime_set_suspended(void *data)
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{
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struct device *dev = data;
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pm_runtime_set_suspended(dev->parent);
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}
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static int rzg2l_adc_probe(struct platform_device *pdev)
···
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if (IS_ERR(adc->base))
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return PTR_ERR(adc->base);
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adc->pclk = devm_clk_get(dev, "pclk");
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if (IS_ERR(adc->pclk))
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return dev_err_probe(dev, PTR_ERR(adc->pclk),
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"Failed to get pclk");
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adc->adclk = devm_clk_get(dev, "adclk");
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if (IS_ERR(adc->adclk))
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return dev_err_probe(dev, PTR_ERR(adc->adclk),
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"Failed to get adclk");
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adc->adrstn = devm_reset_control_get_exclusive_deasserted(dev, "adrst-n");
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if (IS_ERR(adc->adrstn))
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return dev_err_probe(dev, PTR_ERR(adc->adrstn),
···
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return dev_err_probe(dev, PTR_ERR(adc->presetn),
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"failed to get/deassert presetn\n");
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ret = rzg2l_adc_hw_init(adc);
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ret = devm_pm_runtime_enable(dev);
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if (ret)
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return ret;
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platform_set_drvdata(pdev, indio_dev);
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ret = rzg2l_adc_hw_init(dev, adc);
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if (ret)
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return dev_err_probe(&pdev->dev, ret,
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"failed to initialize ADC HW\n");
···
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init_completion(&adc->completion);
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platform_set_drvdata(pdev, indio_dev);
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indio_dev->name = DRIVER_NAME;
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indio_dev->info = &rzg2l_adc_iio_info;
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indio_dev->modes = INDIO_DIRECT_MODE;
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indio_dev->channels = adc->data->channels;
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indio_dev->num_channels = adc->data->num_channels;
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pm_runtime_set_suspended(dev);
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ret = devm_add_action_or_reset(&pdev->dev,
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rzg2l_adc_pm_runtime_set_suspended, &indio_dev->dev);
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if (ret)
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return ret;
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pm_runtime_enable(dev);
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ret = devm_add_action_or_reset(&pdev->dev,
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rzg2l_adc_pm_runtime_disable, &indio_dev->dev);
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if (ret)
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return ret;
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return devm_iio_device_register(dev, indio_dev);
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}
···
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struct rzg2l_adc *adc = iio_priv(indio_dev);
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rzg2l_adc_pwr(adc, false);
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clk_disable_unprepare(adc->adclk);
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clk_disable_unprepare(adc->pclk);
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return 0;
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}
···
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{
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struct iio_dev *indio_dev = dev_get_drvdata(dev);
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struct rzg2l_adc *adc = iio_priv(indio_dev);
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int ret;
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ret = clk_prepare_enable(adc->pclk);
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if (ret)
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return ret;
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ret = clk_prepare_enable(adc->adclk);
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if (ret) {
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clk_disable_unprepare(adc->pclk);
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return ret;
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}
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rzg2l_adc_pwr(adc, true);
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