Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
Merge tag 'soundwire-6.9-fixes' of git://git.kernel.org/pub/scm/linux/kernel/git/vkoul/soundwire
Pull soundwire fix from Vinod Koul:
- Single AMD driver fix for wake interrupt handling in clockstop mode
* tag 'soundwire-6.9-fixes' of git://git.kernel.org/pub/scm/linux/kernel/git/vkoul/soundwire:
soundwire: amd: fix for wake interrupt handling for clockstop mode
+17
-1
+15
drivers/soundwire/amd_manager.c
+15
drivers/soundwire/amd_manager.c
···
130
130
writel(frame_size, amd_manager->mmio + ACP_SW_FRAMESIZE);
131
131
}
132
132
133
+
static void amd_sdw_wake_enable(struct amd_sdw_manager *amd_manager, bool enable)
134
+
{
135
+
u32 wake_ctrl;
136
+
137
+
wake_ctrl = readl(amd_manager->mmio + ACP_SW_STATE_CHANGE_STATUS_MASK_8TO11);
138
+
if (enable)
139
+
wake_ctrl |= AMD_SDW_WAKE_INTR_MASK;
140
+
else
141
+
wake_ctrl &= ~AMD_SDW_WAKE_INTR_MASK;
142
+
143
+
writel(wake_ctrl, amd_manager->mmio + ACP_SW_STATE_CHANGE_STATUS_MASK_8TO11);
144
+
}
145
+
133
146
static void amd_sdw_ctl_word_prep(u32 *lower_word, u32 *upper_word, struct sdw_msg *msg,
134
147
int cmd_offset)
135
148
{
···
1108
1095
}
1109
1096
1110
1097
if (amd_manager->power_mode_mask & AMD_SDW_CLK_STOP_MODE) {
1098
+
amd_sdw_wake_enable(amd_manager, false);
1111
1099
return amd_sdw_clock_stop(amd_manager);
1112
1100
} else if (amd_manager->power_mode_mask & AMD_SDW_POWER_OFF_MODE) {
1113
1101
/*
···
1135
1121
return 0;
1136
1122
}
1137
1123
if (amd_manager->power_mode_mask & AMD_SDW_CLK_STOP_MODE) {
1124
+
amd_sdw_wake_enable(amd_manager, true);
1138
1125
return amd_sdw_clock_stop(amd_manager);
1139
1126
} else if (amd_manager->power_mode_mask & AMD_SDW_POWER_OFF_MODE) {
1140
1127
ret = amd_sdw_clock_stop(amd_manager);
+2
-1
drivers/soundwire/amd_manager.h
+2
-1
drivers/soundwire/amd_manager.h
···
152
152
#define AMD_SDW0_EXT_INTR_MASK 0x200000
153
153
#define AMD_SDW1_EXT_INTR_MASK 4
154
154
#define AMD_SDW_IRQ_MASK_0TO7 0x77777777
155
-
#define AMD_SDW_IRQ_MASK_8TO11 0x000d7777
155
+
#define AMD_SDW_IRQ_MASK_8TO11 0x000c7777
156
156
#define AMD_SDW_IRQ_ERROR_MASK 0xff
157
157
#define AMD_SDW_MAX_FREQ_NUM 1
158
158
#define AMD_SDW0_MAX_TX_PORTS 3
···
190
190
#define AMD_SDW_CLK_RESUME_REQ 2
191
191
#define AMD_SDW_CLK_RESUME_DONE 3
192
192
#define AMD_SDW_WAKE_STAT_MASK BIT(16)
193
+
#define AMD_SDW_WAKE_INTR_MASK BIT(16)
193
194
194
195
static u32 amd_sdw_freq_tbl[AMD_SDW_MAX_FREQ_NUM] = {
195
196
AMD_SDW_DEFAULT_CLK_FREQ,