Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
clk: qcom: gcc-x1e80100: Add missing USB4 clocks/resets
Currently, some of the USB4 clocks/resets are described, but not all
of the back-end muxes are present. Configuring them properly is
necessary for proper operation of the hardware.
Add all the resets & muxes and wire up any unaccounted USB4 clock paths.
Fixes: 161b7c401f4b ("clk: qcom: Add Global Clock controller (GCC) driver for X1E80100")
Reviewed-by: Bryan O'Donoghue <bod@kernel.org>
Signed-off-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Reviewed-by: Taniya Das <taniya.das@oss.qualcomm.com>
Reviewed-by: Abel Vesa <abel.vesa@linaro.org>
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
Link: https://lore.kernel.org/r/20251003-topic-hamoa_gcc_usb4-v2-2-61d27a14ee65@oss.qualcomm.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
authored by
Konrad Dybcio
and committed by
Bjorn Andersson
8abe970e
49551c7d
+681
-17
+681
-17
drivers/clk/qcom/gcc-x1e80100.c
+681
-17
drivers/clk/qcom/gcc-x1e80100.c
···
32
32
DT_USB3_PHY_0_WRAPPER_GCC_USB30_PIPE,
33
33
DT_USB3_PHY_1_WRAPPER_GCC_USB30_PIPE,
34
34
DT_USB3_PHY_2_WRAPPER_GCC_USB30_PIPE,
35
+
DT_GCC_USB4_0_PHY_DP0_GMUX_CLK_SRC,
36
+
DT_GCC_USB4_0_PHY_DP1_GMUX_CLK_SRC,
37
+
DT_GCC_USB4_0_PHY_PCIE_PIPEGMUX_CLK_SRC,
38
+
DT_GCC_USB4_0_PHY_PIPEGMUX_CLK_SRC,
39
+
DT_GCC_USB4_0_PHY_SYS_PIPEGMUX_CLK_SRC,
40
+
DT_GCC_USB4_1_PHY_DP0_GMUX_CLK_SRC,
41
+
DT_GCC_USB4_1_PHY_DP1_GMUX_CLK_SRC,
42
+
DT_GCC_USB4_1_PHY_PCIE_PIPEGMUX_CLK_SRC,
43
+
DT_GCC_USB4_1_PHY_PIPEGMUX_CLK_SRC,
44
+
DT_GCC_USB4_1_PHY_SYS_PIPEGMUX_CLK_SRC,
45
+
DT_GCC_USB4_2_PHY_DP0_GMUX_CLK_SRC,
46
+
DT_GCC_USB4_2_PHY_DP1_GMUX_CLK_SRC,
47
+
DT_GCC_USB4_2_PHY_PCIE_PIPEGMUX_CLK_SRC,
48
+
DT_GCC_USB4_2_PHY_PIPEGMUX_CLK_SRC,
49
+
DT_GCC_USB4_2_PHY_SYS_PIPEGMUX_CLK_SRC,
50
+
DT_QUSB4PHY_0_GCC_USB4_RX0_CLK,
51
+
DT_QUSB4PHY_0_GCC_USB4_RX1_CLK,
52
+
DT_QUSB4PHY_1_GCC_USB4_RX0_CLK,
53
+
DT_QUSB4PHY_1_GCC_USB4_RX1_CLK,
54
+
DT_QUSB4PHY_2_GCC_USB4_RX0_CLK,
55
+
DT_QUSB4PHY_2_GCC_USB4_RX1_CLK,
56
+
DT_USB4_0_PHY_GCC_USB4_PCIE_PIPE_CLK,
57
+
DT_USB4_0_PHY_GCC_USB4RTR_MAX_PIPE_CLK,
58
+
DT_USB4_1_PHY_GCC_USB4_PCIE_PIPE_CLK,
59
+
DT_USB4_1_PHY_GCC_USB4RTR_MAX_PIPE_CLK,
60
+
DT_USB4_2_PHY_GCC_USB4_PCIE_PIPE_CLK,
61
+
DT_USB4_2_PHY_GCC_USB4RTR_MAX_PIPE_CLK,
35
62
};
36
63
37
64
enum {
···
69
42
P_GCC_GPLL7_OUT_MAIN,
70
43
P_GCC_GPLL8_OUT_MAIN,
71
44
P_GCC_GPLL9_OUT_MAIN,
45
+
P_GCC_USB3_PRIM_PHY_PIPE_CLK_SRC,
46
+
P_GCC_USB3_SEC_PHY_PIPE_CLK_SRC,
47
+
P_GCC_USB3_TERT_PHY_PIPE_CLK_SRC,
48
+
P_GCC_USB4_0_PHY_DP0_GMUX_CLK_SRC,
49
+
P_GCC_USB4_0_PHY_DP1_GMUX_CLK_SRC,
50
+
P_GCC_USB4_0_PHY_PCIE_PIPEGMUX_CLK_SRC,
51
+
P_GCC_USB4_0_PHY_PIPEGMUX_CLK_SRC,
52
+
P_GCC_USB4_0_PHY_SYS_PIPEGMUX_CLK_SRC,
53
+
P_GCC_USB4_1_PHY_DP0_GMUX_CLK_SRC,
54
+
P_GCC_USB4_1_PHY_DP1_GMUX_CLK_SRC,
55
+
P_GCC_USB4_1_PHY_PCIE_PIPEGMUX_CLK_SRC,
56
+
P_GCC_USB4_1_PHY_PIPEGMUX_CLK_SRC,
57
+
P_GCC_USB4_1_PHY_SYS_PIPEGMUX_CLK_SRC,
58
+
P_GCC_USB4_2_PHY_DP0_GMUX_CLK_SRC,
59
+
P_GCC_USB4_2_PHY_DP1_GMUX_CLK_SRC,
60
+
P_GCC_USB4_2_PHY_PCIE_PIPEGMUX_CLK_SRC,
61
+
P_GCC_USB4_2_PHY_PIPEGMUX_CLK_SRC,
62
+
P_GCC_USB4_2_PHY_SYS_PIPEGMUX_CLK_SRC,
63
+
P_QUSB4PHY_0_GCC_USB4_RX0_CLK,
64
+
P_QUSB4PHY_0_GCC_USB4_RX1_CLK,
65
+
P_QUSB4PHY_1_GCC_USB4_RX0_CLK,
66
+
P_QUSB4PHY_1_GCC_USB4_RX1_CLK,
67
+
P_QUSB4PHY_2_GCC_USB4_RX0_CLK,
68
+
P_QUSB4PHY_2_GCC_USB4_RX1_CLK,
72
69
P_SLEEP_CLK,
73
70
P_USB3_PHY_0_WRAPPER_GCC_USB30_PIPE_CLK,
74
71
P_USB3_PHY_1_WRAPPER_GCC_USB30_PIPE_CLK,
75
72
P_USB3_PHY_2_WRAPPER_GCC_USB30_PIPE_CLK,
73
+
P_USB4_0_PHY_GCC_USB4_PCIE_PIPE_CLK,
74
+
P_USB4_0_PHY_GCC_USB4RTR_MAX_PIPE_CLK,
75
+
P_USB4_1_PHY_GCC_USB4_PCIE_PIPE_CLK,
76
+
P_USB4_1_PHY_GCC_USB4RTR_MAX_PIPE_CLK,
77
+
P_USB4_2_PHY_GCC_USB4_PCIE_PIPE_CLK,
78
+
P_USB4_2_PHY_GCC_USB4RTR_MAX_PIPE_CLK,
76
79
};
77
80
78
81
static struct clk_alpha_pll gcc_gpll0 = {
···
375
318
F(100000000, P_GCC_GPLL0_OUT_MAIN, 6, 0, 0),
376
319
F(200000000, P_GCC_GPLL0_OUT_MAIN, 3, 0, 0),
377
320
{ }
321
+
};
322
+
323
+
static const struct clk_parent_data gcc_parent_data_13[] = {
324
+
{ .index = DT_GCC_USB4_0_PHY_DP0_GMUX_CLK_SRC },
325
+
{ .index = DT_USB4_0_PHY_GCC_USB4RTR_MAX_PIPE_CLK },
326
+
};
327
+
328
+
static const struct clk_parent_data gcc_parent_data_14[] = {
329
+
{ .index = DT_GCC_USB4_0_PHY_DP1_GMUX_CLK_SRC },
330
+
{ .index = DT_USB4_0_PHY_GCC_USB4RTR_MAX_PIPE_CLK },
331
+
};
332
+
333
+
static const struct clk_parent_data gcc_parent_data_15[] = {
334
+
{ .index = DT_USB4_0_PHY_GCC_USB4_PCIE_PIPE_CLK },
335
+
{ .index = DT_BI_TCXO },
336
+
};
337
+
338
+
static const struct clk_parent_data gcc_parent_data_16[] = {
339
+
{ .index = DT_GCC_USB4_0_PHY_PCIE_PIPEGMUX_CLK_SRC },
340
+
{ .index = DT_USB4_0_PHY_GCC_USB4_PCIE_PIPE_CLK },
341
+
};
342
+
343
+
static const struct clk_parent_data gcc_parent_data_17[] = {
344
+
{ .index = DT_QUSB4PHY_0_GCC_USB4_RX0_CLK },
345
+
{ .index = DT_BI_TCXO },
346
+
};
347
+
348
+
static const struct clk_parent_data gcc_parent_data_18[] = {
349
+
{ .index = DT_QUSB4PHY_0_GCC_USB4_RX1_CLK },
350
+
{ .index = DT_BI_TCXO },
351
+
};
352
+
353
+
static const struct clk_parent_data gcc_parent_data_19[] = {
354
+
{ .index = DT_GCC_USB4_0_PHY_SYS_PIPEGMUX_CLK_SRC },
355
+
{ .index = DT_USB4_0_PHY_GCC_USB4_PCIE_PIPE_CLK },
356
+
};
357
+
358
+
static const struct clk_parent_data gcc_parent_data_20[] = {
359
+
{ .index = DT_GCC_USB4_1_PHY_DP0_GMUX_CLK_SRC },
360
+
{ .index = DT_USB4_1_PHY_GCC_USB4RTR_MAX_PIPE_CLK },
361
+
};
362
+
363
+
static const struct clk_parent_data gcc_parent_data_21[] = {
364
+
{ .index = DT_GCC_USB4_1_PHY_DP1_GMUX_CLK_SRC },
365
+
{ .index = DT_USB4_1_PHY_GCC_USB4RTR_MAX_PIPE_CLK },
366
+
};
367
+
368
+
static const struct clk_parent_data gcc_parent_data_22[] = {
369
+
{ .index = DT_USB4_1_PHY_GCC_USB4_PCIE_PIPE_CLK },
370
+
{ .index = DT_BI_TCXO },
371
+
};
372
+
373
+
static const struct clk_parent_data gcc_parent_data_23[] = {
374
+
{ .index = DT_GCC_USB4_1_PHY_PCIE_PIPEGMUX_CLK_SRC },
375
+
{ .index = DT_USB4_1_PHY_GCC_USB4_PCIE_PIPE_CLK },
376
+
};
377
+
378
+
static const struct clk_parent_data gcc_parent_data_24[] = {
379
+
{ .index = DT_QUSB4PHY_1_GCC_USB4_RX0_CLK },
380
+
{ .index = DT_BI_TCXO },
381
+
};
382
+
383
+
static const struct clk_parent_data gcc_parent_data_25[] = {
384
+
{ .index = DT_QUSB4PHY_1_GCC_USB4_RX1_CLK },
385
+
{ .index = DT_BI_TCXO },
386
+
};
387
+
388
+
static const struct clk_parent_data gcc_parent_data_26[] = {
389
+
{ .index = DT_GCC_USB4_1_PHY_SYS_PIPEGMUX_CLK_SRC },
390
+
{ .index = DT_USB4_1_PHY_GCC_USB4_PCIE_PIPE_CLK },
391
+
};
392
+
393
+
static const struct clk_parent_data gcc_parent_data_27[] = {
394
+
{ .index = DT_GCC_USB4_2_PHY_DP0_GMUX_CLK_SRC },
395
+
{ .index = DT_USB4_2_PHY_GCC_USB4RTR_MAX_PIPE_CLK },
396
+
};
397
+
398
+
static const struct clk_parent_data gcc_parent_data_28[] = {
399
+
{ .index = DT_GCC_USB4_2_PHY_DP1_GMUX_CLK_SRC },
400
+
{ .index = DT_USB4_2_PHY_GCC_USB4RTR_MAX_PIPE_CLK },
401
+
};
402
+
403
+
static const struct clk_parent_data gcc_parent_data_29[] = {
404
+
{ .index = DT_USB4_2_PHY_GCC_USB4_PCIE_PIPE_CLK },
405
+
{ .index = DT_BI_TCXO },
406
+
};
407
+
408
+
static const struct clk_parent_data gcc_parent_data_30[] = {
409
+
{ .index = DT_GCC_USB4_2_PHY_PCIE_PIPEGMUX_CLK_SRC },
410
+
{ .index = DT_USB4_2_PHY_GCC_USB4_PCIE_PIPE_CLK },
411
+
};
412
+
413
+
static const struct clk_parent_data gcc_parent_data_31[] = {
414
+
{ .index = DT_QUSB4PHY_2_GCC_USB4_RX0_CLK },
415
+
{ .index = DT_BI_TCXO },
416
+
};
417
+
418
+
static const struct clk_parent_data gcc_parent_data_32[] = {
419
+
{ .index = DT_QUSB4PHY_2_GCC_USB4_RX1_CLK },
420
+
{ .index = DT_BI_TCXO },
421
+
};
422
+
423
+
static const struct clk_parent_data gcc_parent_data_33[] = {
424
+
{ .index = DT_GCC_USB4_2_PHY_SYS_PIPEGMUX_CLK_SRC },
425
+
{ .index = DT_USB4_2_PHY_GCC_USB4_PCIE_PIPE_CLK },
426
+
};
427
+
428
+
static struct clk_regmap_phy_mux gcc_usb4_0_phy_dp0_clk_src = {
429
+
.reg = 0x9f06c,
430
+
.clkr = {
431
+
.hw.init = &(const struct clk_init_data) {
432
+
.name = "gcc_usb4_0_phy_dp0_clk_src",
433
+
.parent_data = gcc_parent_data_13,
434
+
.ops = &clk_regmap_phy_mux_ops,
435
+
},
436
+
},
437
+
};
438
+
439
+
static struct clk_regmap_phy_mux gcc_usb4_0_phy_dp1_clk_src = {
440
+
.reg = 0x9f114,
441
+
.clkr = {
442
+
.hw.init = &(const struct clk_init_data) {
443
+
.name = "gcc_usb4_0_phy_dp1_clk_src",
444
+
.parent_data = gcc_parent_data_14,
445
+
.ops = &clk_regmap_phy_mux_ops,
446
+
},
447
+
},
448
+
};
449
+
450
+
static struct clk_regmap_phy_mux gcc_usb4_0_phy_p2rr2p_pipe_clk_src = {
451
+
.reg = 0x9f0d4,
452
+
.clkr = {
453
+
.hw.init = &(const struct clk_init_data) {
454
+
.name = "gcc_usb4_0_phy_p2rr2p_pipe_clk_src",
455
+
.parent_data = gcc_parent_data_15,
456
+
.ops = &clk_regmap_phy_mux_ops,
457
+
},
458
+
},
459
+
};
460
+
461
+
static struct clk_regmap_phy_mux gcc_usb4_0_phy_pcie_pipe_mux_clk_src = {
462
+
.reg = 0x9f104,
463
+
.clkr = {
464
+
.hw.init = &(const struct clk_init_data) {
465
+
.name = "gcc_usb4_0_phy_pcie_pipe_mux_clk_src",
466
+
.parent_data = gcc_parent_data_16,
467
+
.ops = &clk_regmap_phy_mux_ops,
468
+
},
469
+
},
470
+
};
471
+
472
+
static struct clk_regmap_phy_mux gcc_usb4_0_phy_rx0_clk_src = {
473
+
.reg = 0x9f0ac,
474
+
.clkr = {
475
+
.hw.init = &(const struct clk_init_data) {
476
+
.name = "gcc_usb4_0_phy_rx0_clk_src",
477
+
.parent_data = gcc_parent_data_17,
478
+
.ops = &clk_regmap_phy_mux_ops,
479
+
},
480
+
},
481
+
};
482
+
483
+
static struct clk_regmap_phy_mux gcc_usb4_0_phy_rx1_clk_src = {
484
+
.reg = 0x9f0bc,
485
+
.clkr = {
486
+
.hw.init = &(const struct clk_init_data) {
487
+
.name = "gcc_usb4_0_phy_rx1_clk_src",
488
+
.parent_data = gcc_parent_data_18,
489
+
.ops = &clk_regmap_phy_mux_ops,
490
+
},
491
+
},
492
+
};
493
+
494
+
static struct clk_regmap_phy_mux gcc_usb4_0_phy_sys_clk_src = {
495
+
.reg = 0x9f0e4,
496
+
.clkr = {
497
+
.hw.init = &(const struct clk_init_data) {
498
+
.name = "gcc_usb4_0_phy_sys_clk_src",
499
+
.parent_data = gcc_parent_data_19,
500
+
.ops = &clk_regmap_phy_mux_ops,
501
+
},
502
+
},
503
+
};
504
+
505
+
static struct clk_regmap_phy_mux gcc_usb4_1_phy_dp0_clk_src = {
506
+
.reg = 0x2b06c,
507
+
.clkr = {
508
+
.hw.init = &(const struct clk_init_data) {
509
+
.name = "gcc_usb4_1_phy_dp0_clk_src",
510
+
.parent_data = gcc_parent_data_20,
511
+
.ops = &clk_regmap_phy_mux_ops,
512
+
},
513
+
},
514
+
};
515
+
516
+
static struct clk_regmap_phy_mux gcc_usb4_1_phy_dp1_clk_src = {
517
+
.reg = 0x2b114,
518
+
.clkr = {
519
+
.hw.init = &(const struct clk_init_data) {
520
+
.name = "gcc_usb4_1_phy_dp1_clk_src",
521
+
.parent_data = gcc_parent_data_21,
522
+
.ops = &clk_regmap_phy_mux_ops,
523
+
},
524
+
},
525
+
};
526
+
527
+
static struct clk_regmap_phy_mux gcc_usb4_1_phy_p2rr2p_pipe_clk_src = {
528
+
.reg = 0x2b0d4,
529
+
.clkr = {
530
+
.hw.init = &(const struct clk_init_data) {
531
+
.name = "gcc_usb4_1_phy_p2rr2p_pipe_clk_src",
532
+
.parent_data = gcc_parent_data_22,
533
+
.ops = &clk_regmap_phy_mux_ops,
534
+
},
535
+
},
536
+
};
537
+
538
+
static struct clk_regmap_phy_mux gcc_usb4_1_phy_pcie_pipe_mux_clk_src = {
539
+
.reg = 0x2b104,
540
+
.clkr = {
541
+
.hw.init = &(const struct clk_init_data) {
542
+
.name = "gcc_usb4_1_phy_pcie_pipe_mux_clk_src",
543
+
.parent_data = gcc_parent_data_23,
544
+
.ops = &clk_regmap_phy_mux_ops,
545
+
},
546
+
},
547
+
};
548
+
549
+
static struct clk_regmap_phy_mux gcc_usb4_1_phy_rx0_clk_src = {
550
+
.reg = 0x2b0ac,
551
+
.clkr = {
552
+
.hw.init = &(const struct clk_init_data) {
553
+
.name = "gcc_usb4_1_phy_rx0_clk_src",
554
+
.parent_data = gcc_parent_data_24,
555
+
.ops = &clk_regmap_phy_mux_ops,
556
+
},
557
+
},
558
+
};
559
+
560
+
static struct clk_regmap_phy_mux gcc_usb4_1_phy_rx1_clk_src = {
561
+
.reg = 0x2b0bc,
562
+
.clkr = {
563
+
.hw.init = &(const struct clk_init_data) {
564
+
.name = "gcc_usb4_1_phy_rx1_clk_src",
565
+
.parent_data = gcc_parent_data_25,
566
+
.ops = &clk_regmap_phy_mux_ops,
567
+
},
568
+
},
569
+
};
570
+
571
+
static struct clk_regmap_phy_mux gcc_usb4_1_phy_sys_clk_src = {
572
+
.reg = 0x2b0e4,
573
+
.clkr = {
574
+
.hw.init = &(const struct clk_init_data) {
575
+
.name = "gcc_usb4_1_phy_sys_clk_src",
576
+
.parent_data = gcc_parent_data_26,
577
+
.ops = &clk_regmap_phy_mux_ops,
578
+
},
579
+
},
580
+
};
581
+
582
+
static struct clk_regmap_phy_mux gcc_usb4_2_phy_dp0_clk_src = {
583
+
.reg = 0x1106c,
584
+
.clkr = {
585
+
.hw.init = &(const struct clk_init_data) {
586
+
.name = "gcc_usb4_2_phy_dp0_clk_src",
587
+
.parent_data = gcc_parent_data_27,
588
+
.ops = &clk_regmap_phy_mux_ops,
589
+
},
590
+
},
591
+
};
592
+
593
+
static struct clk_regmap_phy_mux gcc_usb4_2_phy_dp1_clk_src = {
594
+
.reg = 0x11114,
595
+
.clkr = {
596
+
.hw.init = &(const struct clk_init_data) {
597
+
.name = "gcc_usb4_2_phy_dp1_clk_src",
598
+
.parent_data = gcc_parent_data_28,
599
+
.ops = &clk_regmap_phy_mux_ops,
600
+
},
601
+
},
602
+
};
603
+
604
+
static struct clk_regmap_phy_mux gcc_usb4_2_phy_p2rr2p_pipe_clk_src = {
605
+
.reg = 0x110d4,
606
+
.clkr = {
607
+
.hw.init = &(const struct clk_init_data) {
608
+
.name = "gcc_usb4_2_phy_p2rr2p_pipe_clk_src",
609
+
.parent_data = gcc_parent_data_29,
610
+
.ops = &clk_regmap_phy_mux_ops,
611
+
},
612
+
},
613
+
};
614
+
615
+
static struct clk_regmap_phy_mux gcc_usb4_2_phy_pcie_pipe_mux_clk_src = {
616
+
.reg = 0x11104,
617
+
.clkr = {
618
+
.hw.init = &(const struct clk_init_data) {
619
+
.name = "gcc_usb4_2_phy_pcie_pipe_mux_clk_src",
620
+
.parent_data = gcc_parent_data_30,
621
+
.ops = &clk_regmap_phy_mux_ops,
622
+
},
623
+
},
624
+
};
625
+
626
+
static struct clk_regmap_phy_mux gcc_usb4_2_phy_rx0_clk_src = {
627
+
.reg = 0x110ac,
628
+
.clkr = {
629
+
.hw.init = &(const struct clk_init_data) {
630
+
.name = "gcc_usb4_2_phy_rx0_clk_src",
631
+
.parent_data = gcc_parent_data_31,
632
+
.ops = &clk_regmap_phy_mux_ops,
633
+
},
634
+
},
635
+
};
636
+
637
+
static struct clk_regmap_phy_mux gcc_usb4_2_phy_rx1_clk_src = {
638
+
.reg = 0x110bc,
639
+
.clkr = {
640
+
.hw.init = &(const struct clk_init_data) {
641
+
.name = "gcc_usb4_2_phy_rx1_clk_src",
642
+
.parent_data = gcc_parent_data_32,
643
+
.ops = &clk_regmap_phy_mux_ops,
644
+
},
645
+
},
646
+
};
647
+
648
+
static struct clk_regmap_phy_mux gcc_usb4_2_phy_sys_clk_src = {
649
+
.reg = 0x110e4,
650
+
.clkr = {
651
+
.hw.init = &(const struct clk_init_data) {
652
+
.name = "gcc_usb4_2_phy_sys_clk_src",
653
+
.parent_data = gcc_parent_data_33,
654
+
.ops = &clk_regmap_phy_mux_ops,
655
+
},
656
+
},
378
657
};
379
658
380
659
static struct clk_rcg2 gcc_gp1_clk_src = {
···
3183
2790
.enable_mask = BIT(25),
3184
2791
.hw.init = &(const struct clk_init_data) {
3185
2792
.name = "gcc_pcie_0_pipe_clk",
2793
+
.parent_hws = (const struct clk_hw*[]) {
2794
+
&gcc_usb4_0_phy_pcie_pipe_mux_clk_src.clkr.hw,
2795
+
},
2796
+
.num_parents = 1,
2797
+
.flags = CLK_SET_RATE_PARENT,
3186
2798
.ops = &clk_branch2_ops,
3187
2799
},
3188
2800
},
···
3277
2879
.enable_mask = BIT(30),
3278
2880
.hw.init = &(const struct clk_init_data) {
3279
2881
.name = "gcc_pcie_1_pipe_clk",
2882
+
.parent_hws = (const struct clk_hw*[]) {
2883
+
&gcc_usb4_1_phy_pcie_pipe_mux_clk_src.clkr.hw,
2884
+
},
2885
+
.num_parents = 1,
2886
+
.flags = CLK_SET_RATE_PARENT,
3280
2887
.ops = &clk_branch2_ops,
3281
2888
},
3282
2889
},
···
3371
2968
.enable_mask = BIT(23),
3372
2969
.hw.init = &(const struct clk_init_data) {
3373
2970
.name = "gcc_pcie_2_pipe_clk",
2971
+
.parent_hws = (const struct clk_hw*[]) {
2972
+
&gcc_usb4_2_phy_pcie_pipe_mux_clk_src.clkr.hw,
2973
+
},
2974
+
.num_parents = 1,
2975
+
.flags = CLK_SET_RATE_PARENT,
3374
2976
.ops = &clk_branch2_ops,
3375
2977
},
3376
2978
},
···
5564
5156
},
5565
5157
};
5566
5158
5159
+
static const struct parent_map gcc_parent_map_34[] = {
5160
+
{ P_GCC_USB3_PRIM_PHY_PIPE_CLK_SRC, 0 },
5161
+
{ P_USB4_0_PHY_GCC_USB4RTR_MAX_PIPE_CLK, 1 },
5162
+
{ P_GCC_USB4_0_PHY_PIPEGMUX_CLK_SRC, 3 },
5163
+
};
5164
+
5165
+
static const struct clk_parent_data gcc_parent_data_34[] = {
5166
+
{ .hw = &gcc_usb3_prim_phy_pipe_clk_src.clkr.hw },
5167
+
{ .index = DT_USB4_0_PHY_GCC_USB4RTR_MAX_PIPE_CLK },
5168
+
{ .index = DT_GCC_USB4_0_PHY_PIPEGMUX_CLK_SRC },
5169
+
};
5170
+
5171
+
static struct clk_regmap_mux gcc_usb34_prim_phy_pipe_clk_src = {
5172
+
.reg = 0x39070,
5173
+
.shift = 0,
5174
+
.width = 2,
5175
+
.parent_map = gcc_parent_map_34,
5176
+
.clkr = {
5177
+
.hw.init = &(const struct clk_init_data) {
5178
+
.name = "gcc_usb34_prim_phy_pipe_clk_src",
5179
+
.parent_data = gcc_parent_data_34,
5180
+
.num_parents = ARRAY_SIZE(gcc_parent_data_34),
5181
+
.ops = &clk_regmap_mux_closest_ops,
5182
+
},
5183
+
},
5184
+
};
5185
+
5567
5186
static struct clk_branch gcc_usb3_prim_phy_pipe_clk = {
5568
5187
.halt_reg = 0x39068,
5569
5188
.halt_check = BRANCH_HALT_SKIP,
···
5602
5167
.hw.init = &(const struct clk_init_data) {
5603
5168
.name = "gcc_usb3_prim_phy_pipe_clk",
5604
5169
.parent_hws = (const struct clk_hw*[]) {
5605
-
&gcc_usb3_prim_phy_pipe_clk_src.clkr.hw,
5170
+
&gcc_usb34_prim_phy_pipe_clk_src.clkr.hw,
5606
5171
},
5607
5172
.num_parents = 1,
5608
5173
.flags = CLK_SET_RATE_PARENT,
···
5662
5227
},
5663
5228
};
5664
5229
5230
+
static const struct parent_map gcc_parent_map_35[] = {
5231
+
{ P_GCC_USB3_SEC_PHY_PIPE_CLK_SRC, 0 },
5232
+
{ P_USB4_1_PHY_GCC_USB4RTR_MAX_PIPE_CLK, 1 },
5233
+
{ P_GCC_USB4_1_PHY_PIPEGMUX_CLK_SRC, 3 },
5234
+
};
5235
+
5236
+
static const struct clk_parent_data gcc_parent_data_35[] = {
5237
+
{ .hw = &gcc_usb3_sec_phy_pipe_clk_src.clkr.hw },
5238
+
{ .index = DT_USB4_1_PHY_GCC_USB4RTR_MAX_PIPE_CLK },
5239
+
{ .index = DT_GCC_USB4_1_PHY_PIPEGMUX_CLK_SRC },
5240
+
};
5241
+
5242
+
static struct clk_regmap_mux gcc_usb34_sec_phy_pipe_clk_src = {
5243
+
.reg = 0xa1070,
5244
+
.shift = 0,
5245
+
.width = 2,
5246
+
.parent_map = gcc_parent_map_35,
5247
+
.clkr = {
5248
+
.hw.init = &(const struct clk_init_data) {
5249
+
.name = "gcc_usb34_sec_phy_pipe_clk_src",
5250
+
.parent_data = gcc_parent_data_35,
5251
+
.num_parents = ARRAY_SIZE(gcc_parent_data_35),
5252
+
.ops = &clk_regmap_mux_closest_ops,
5253
+
},
5254
+
},
5255
+
};
5256
+
5665
5257
static struct clk_branch gcc_usb3_sec_phy_pipe_clk = {
5666
5258
.halt_reg = 0xa1068,
5667
5259
.halt_check = BRANCH_HALT_SKIP,
···
5700
5238
.hw.init = &(const struct clk_init_data) {
5701
5239
.name = "gcc_usb3_sec_phy_pipe_clk",
5702
5240
.parent_hws = (const struct clk_hw*[]) {
5703
-
&gcc_usb3_sec_phy_pipe_clk_src.clkr.hw,
5241
+
&gcc_usb34_sec_phy_pipe_clk_src.clkr.hw,
5704
5242
},
5705
5243
.num_parents = 1,
5706
5244
.flags = CLK_SET_RATE_PARENT,
···
5760
5298
},
5761
5299
};
5762
5300
5301
+
static const struct parent_map gcc_parent_map_36[] = {
5302
+
{ P_GCC_USB3_TERT_PHY_PIPE_CLK_SRC, 0 },
5303
+
{ P_USB4_2_PHY_GCC_USB4RTR_MAX_PIPE_CLK, 1 },
5304
+
{ P_GCC_USB4_2_PHY_PIPEGMUX_CLK_SRC, 3 },
5305
+
};
5306
+
5307
+
static const struct clk_parent_data gcc_parent_data_36[] = {
5308
+
{ .hw = &gcc_usb3_tert_phy_pipe_clk_src.clkr.hw },
5309
+
{ .index = DT_USB4_2_PHY_GCC_USB4RTR_MAX_PIPE_CLK },
5310
+
{ .index = DT_GCC_USB4_2_PHY_PIPEGMUX_CLK_SRC },
5311
+
};
5312
+
5313
+
static struct clk_regmap_mux gcc_usb34_tert_phy_pipe_clk_src = {
5314
+
.reg = 0xa2070,
5315
+
.shift = 0,
5316
+
.width = 2,
5317
+
.parent_map = gcc_parent_map_36,
5318
+
.clkr = {
5319
+
.hw.init = &(const struct clk_init_data) {
5320
+
.name = "gcc_usb34_tert_phy_pipe_clk_src",
5321
+
.parent_data = gcc_parent_data_36,
5322
+
.num_parents = ARRAY_SIZE(gcc_parent_data_36),
5323
+
.ops = &clk_regmap_mux_closest_ops,
5324
+
},
5325
+
},
5326
+
};
5327
+
5763
5328
static struct clk_branch gcc_usb3_tert_phy_pipe_clk = {
5764
5329
.halt_reg = 0xa2068,
5765
5330
.halt_check = BRANCH_HALT_SKIP,
···
5798
5309
.hw.init = &(const struct clk_init_data) {
5799
5310
.name = "gcc_usb3_tert_phy_pipe_clk",
5800
5311
.parent_hws = (const struct clk_hw*[]) {
5801
-
&gcc_usb3_tert_phy_pipe_clk_src.clkr.hw,
5312
+
&gcc_usb34_tert_phy_pipe_clk_src.clkr.hw,
5802
5313
},
5803
5314
.num_parents = 1,
5804
5315
.flags = CLK_SET_RATE_PARENT,
···
5824
5335
5825
5336
static struct clk_branch gcc_usb4_0_dp0_clk = {
5826
5337
.halt_reg = 0x9f060,
5827
-
.halt_check = BRANCH_HALT,
5338
+
.halt_check = BRANCH_HALT_SKIP,
5828
5339
.clkr = {
5829
5340
.enable_reg = 0x9f060,
5830
5341
.enable_mask = BIT(0),
5831
5342
.hw.init = &(const struct clk_init_data) {
5832
5343
.name = "gcc_usb4_0_dp0_clk",
5344
+
.parent_hws = (const struct clk_hw*[]) {
5345
+
&gcc_usb4_0_phy_dp0_clk_src.clkr.hw,
5346
+
},
5347
+
.num_parents = 1,
5348
+
.flags = CLK_SET_RATE_PARENT,
5833
5349
.ops = &clk_branch2_ops,
5834
5350
},
5835
5351
},
···
5842
5348
5843
5349
static struct clk_branch gcc_usb4_0_dp1_clk = {
5844
5350
.halt_reg = 0x9f108,
5845
-
.halt_check = BRANCH_HALT,
5351
+
.halt_check = BRANCH_HALT_SKIP,
5846
5352
.clkr = {
5847
5353
.enable_reg = 0x9f108,
5848
5354
.enable_mask = BIT(0),
5849
5355
.hw.init = &(const struct clk_init_data) {
5850
5356
.name = "gcc_usb4_0_dp1_clk",
5357
+
.parent_hws = (const struct clk_hw*[]) {
5358
+
&gcc_usb4_0_phy_dp1_clk_src.clkr.hw,
5359
+
},
5360
+
.num_parents = 1,
5361
+
.flags = CLK_SET_RATE_PARENT,
5851
5362
.ops = &clk_branch2_ops,
5852
5363
},
5853
5364
},
···
5884
5385
.enable_mask = BIT(0),
5885
5386
.hw.init = &(const struct clk_init_data) {
5886
5387
.name = "gcc_usb4_0_phy_p2rr2p_pipe_clk",
5388
+
.parent_hws = (const struct clk_hw*[]) {
5389
+
&gcc_usb4_0_phy_p2rr2p_pipe_clk_src.clkr.hw,
5390
+
},
5391
+
.num_parents = 1,
5392
+
.flags = CLK_SET_RATE_PARENT,
5887
5393
.ops = &clk_branch2_ops,
5888
5394
},
5889
5395
},
···
5902
5398
.enable_mask = BIT(19),
5903
5399
.hw.init = &(const struct clk_init_data) {
5904
5400
.name = "gcc_usb4_0_phy_pcie_pipe_clk",
5401
+
.parent_hws = (const struct clk_hw*[]) {
5402
+
&gcc_usb4_0_phy_pcie_pipe_mux_clk_src.clkr.hw,
5403
+
},
5404
+
.num_parents = 1,
5405
+
.flags = CLK_SET_RATE_PARENT,
5905
5406
.ops = &clk_branch2_ops,
5906
5407
},
5907
5408
},
···
5914
5405
5915
5406
static struct clk_branch gcc_usb4_0_phy_rx0_clk = {
5916
5407
.halt_reg = 0x9f0b0,
5917
-
.halt_check = BRANCH_HALT,
5408
+
.halt_check = BRANCH_HALT_SKIP,
5918
5409
.clkr = {
5919
5410
.enable_reg = 0x9f0b0,
5920
5411
.enable_mask = BIT(0),
5921
5412
.hw.init = &(const struct clk_init_data) {
5922
5413
.name = "gcc_usb4_0_phy_rx0_clk",
5414
+
.parent_hws = (const struct clk_hw*[]) {
5415
+
&gcc_usb4_0_phy_rx0_clk_src.clkr.hw,
5416
+
},
5417
+
.num_parents = 1,
5418
+
.flags = CLK_SET_RATE_PARENT,
5923
5419
.ops = &clk_branch2_ops,
5924
5420
},
5925
5421
},
···
5932
5418
5933
5419
static struct clk_branch gcc_usb4_0_phy_rx1_clk = {
5934
5420
.halt_reg = 0x9f0c0,
5935
-
.halt_check = BRANCH_HALT,
5421
+
.halt_check = BRANCH_HALT_SKIP,
5936
5422
.clkr = {
5937
5423
.enable_reg = 0x9f0c0,
5938
5424
.enable_mask = BIT(0),
5939
5425
.hw.init = &(const struct clk_init_data) {
5940
5426
.name = "gcc_usb4_0_phy_rx1_clk",
5427
+
.parent_hws = (const struct clk_hw*[]) {
5428
+
&gcc_usb4_0_phy_rx1_clk_src.clkr.hw,
5429
+
},
5430
+
.num_parents = 1,
5431
+
.flags = CLK_SET_RATE_PARENT,
5941
5432
.ops = &clk_branch2_ops,
5942
5433
},
5943
5434
},
···
5958
5439
.enable_mask = BIT(0),
5959
5440
.hw.init = &(const struct clk_init_data) {
5960
5441
.name = "gcc_usb4_0_phy_usb_pipe_clk",
5442
+
.parent_hws = (const struct clk_hw*[]) {
5443
+
&gcc_usb34_prim_phy_pipe_clk_src.clkr.hw,
5444
+
},
5445
+
.num_parents = 1,
5446
+
.flags = CLK_SET_RATE_PARENT,
5961
5447
.ops = &clk_branch2_ops,
5962
5448
},
5963
5449
},
···
5994
5470
.enable_mask = BIT(0),
5995
5471
.hw.init = &(const struct clk_init_data) {
5996
5472
.name = "gcc_usb4_0_sys_clk",
5473
+
.parent_hws = (const struct clk_hw*[]) {
5474
+
&gcc_usb4_0_phy_sys_clk_src.clkr.hw,
5475
+
},
5476
+
.num_parents = 1,
5477
+
.flags = CLK_SET_RATE_PARENT,
5997
5478
.ops = &clk_branch2_ops,
5998
5479
},
5999
5480
},
···
6041
5512
6042
5513
static struct clk_branch gcc_usb4_1_dp0_clk = {
6043
5514
.halt_reg = 0x2b060,
6044
-
.halt_check = BRANCH_HALT,
5515
+
.halt_check = BRANCH_HALT_SKIP,
6045
5516
.clkr = {
6046
5517
.enable_reg = 0x2b060,
6047
5518
.enable_mask = BIT(0),
6048
5519
.hw.init = &(const struct clk_init_data) {
6049
5520
.name = "gcc_usb4_1_dp0_clk",
5521
+
.parent_hws = (const struct clk_hw*[]) {
5522
+
&gcc_usb4_1_phy_dp0_clk_src.clkr.hw,
5523
+
},
5524
+
.num_parents = 1,
5525
+
.flags = CLK_SET_RATE_PARENT,
6050
5526
.ops = &clk_branch2_ops,
6051
5527
},
6052
5528
},
···
6059
5525
6060
5526
static struct clk_branch gcc_usb4_1_dp1_clk = {
6061
5527
.halt_reg = 0x2b108,
6062
-
.halt_check = BRANCH_HALT,
5528
+
.halt_check = BRANCH_HALT_SKIP,
6063
5529
.clkr = {
6064
5530
.enable_reg = 0x2b108,
6065
5531
.enable_mask = BIT(0),
6066
5532
.hw.init = &(const struct clk_init_data) {
6067
5533
.name = "gcc_usb4_1_dp1_clk",
5534
+
.parent_hws = (const struct clk_hw*[]) {
5535
+
&gcc_usb4_1_phy_dp1_clk_src.clkr.hw,
5536
+
},
5537
+
.num_parents = 1,
5538
+
.flags = CLK_SET_RATE_PARENT,
6068
5539
.ops = &clk_branch2_ops,
6069
5540
},
6070
5541
},
···
6101
5562
.enable_mask = BIT(0),
6102
5563
.hw.init = &(const struct clk_init_data) {
6103
5564
.name = "gcc_usb4_1_phy_p2rr2p_pipe_clk",
5565
+
.parent_hws = (const struct clk_hw*[]) {
5566
+
&gcc_usb4_1_phy_p2rr2p_pipe_clk_src.clkr.hw,
5567
+
},
5568
+
.num_parents = 1,
5569
+
.flags = CLK_SET_RATE_PARENT,
6104
5570
.ops = &clk_branch2_ops,
6105
5571
},
6106
5572
},
···
6119
5575
.enable_mask = BIT(0),
6120
5576
.hw.init = &(const struct clk_init_data) {
6121
5577
.name = "gcc_usb4_1_phy_pcie_pipe_clk",
5578
+
.parent_hws = (const struct clk_hw*[]) {
5579
+
&gcc_usb4_1_phy_pcie_pipe_mux_clk_src.clkr.hw,
5580
+
},
5581
+
.num_parents = 1,
5582
+
.flags = CLK_SET_RATE_PARENT,
6122
5583
.ops = &clk_branch2_ops,
6123
5584
},
6124
5585
},
···
6131
5582
6132
5583
static struct clk_branch gcc_usb4_1_phy_rx0_clk = {
6133
5584
.halt_reg = 0x2b0b0,
6134
-
.halt_check = BRANCH_HALT,
5585
+
.halt_check = BRANCH_HALT_SKIP,
6135
5586
.clkr = {
6136
5587
.enable_reg = 0x2b0b0,
6137
5588
.enable_mask = BIT(0),
6138
5589
.hw.init = &(const struct clk_init_data) {
6139
5590
.name = "gcc_usb4_1_phy_rx0_clk",
5591
+
.parent_hws = (const struct clk_hw*[]) {
5592
+
&gcc_usb4_1_phy_rx0_clk_src.clkr.hw,
5593
+
},
5594
+
.num_parents = 1,
5595
+
.flags = CLK_SET_RATE_PARENT,
6140
5596
.ops = &clk_branch2_ops,
6141
5597
},
6142
5598
},
···
6149
5595
6150
5596
static struct clk_branch gcc_usb4_1_phy_rx1_clk = {
6151
5597
.halt_reg = 0x2b0c0,
6152
-
.halt_check = BRANCH_HALT,
5598
+
.halt_check = BRANCH_HALT_SKIP,
6153
5599
.clkr = {
6154
5600
.enable_reg = 0x2b0c0,
6155
5601
.enable_mask = BIT(0),
6156
5602
.hw.init = &(const struct clk_init_data) {
6157
5603
.name = "gcc_usb4_1_phy_rx1_clk",
5604
+
.parent_hws = (const struct clk_hw*[]) {
5605
+
&gcc_usb4_1_phy_rx1_clk_src.clkr.hw,
5606
+
},
5607
+
.num_parents = 1,
5608
+
.flags = CLK_SET_RATE_PARENT,
6158
5609
.ops = &clk_branch2_ops,
6159
5610
},
6160
5611
},
···
6175
5616
.enable_mask = BIT(0),
6176
5617
.hw.init = &(const struct clk_init_data) {
6177
5618
.name = "gcc_usb4_1_phy_usb_pipe_clk",
5619
+
.parent_hws = (const struct clk_hw*[]) {
5620
+
&gcc_usb34_sec_phy_pipe_clk_src.clkr.hw,
5621
+
},
5622
+
.num_parents = 1,
5623
+
.flags = CLK_SET_RATE_PARENT,
6178
5624
.ops = &clk_branch2_ops,
6179
5625
},
6180
5626
},
···
6211
5647
.enable_mask = BIT(0),
6212
5648
.hw.init = &(const struct clk_init_data) {
6213
5649
.name = "gcc_usb4_1_sys_clk",
5650
+
.parent_hws = (const struct clk_hw*[]) {
5651
+
&gcc_usb4_1_phy_sys_clk_src.clkr.hw,
5652
+
},
5653
+
.num_parents = 1,
5654
+
.flags = CLK_SET_RATE_PARENT,
6214
5655
.ops = &clk_branch2_ops,
6215
5656
},
6216
5657
},
···
6258
5689
6259
5690
static struct clk_branch gcc_usb4_2_dp0_clk = {
6260
5691
.halt_reg = 0x11060,
6261
-
.halt_check = BRANCH_HALT,
5692
+
.halt_check = BRANCH_HALT_SKIP,
6262
5693
.clkr = {
6263
5694
.enable_reg = 0x11060,
6264
5695
.enable_mask = BIT(0),
6265
5696
.hw.init = &(const struct clk_init_data) {
6266
5697
.name = "gcc_usb4_2_dp0_clk",
5698
+
.parent_hws = (const struct clk_hw*[]) {
5699
+
&gcc_usb4_2_phy_dp0_clk_src.clkr.hw,
5700
+
},
5701
+
.num_parents = 1,
5702
+
.flags = CLK_SET_RATE_PARENT,
6267
5703
.ops = &clk_branch2_ops,
6268
5704
},
6269
5705
},
···
6276
5702
6277
5703
static struct clk_branch gcc_usb4_2_dp1_clk = {
6278
5704
.halt_reg = 0x11108,
6279
-
.halt_check = BRANCH_HALT,
5705
+
.halt_check = BRANCH_HALT_SKIP,
6280
5706
.clkr = {
6281
5707
.enable_reg = 0x11108,
6282
5708
.enable_mask = BIT(0),
6283
5709
.hw.init = &(const struct clk_init_data) {
6284
5710
.name = "gcc_usb4_2_dp1_clk",
5711
+
.parent_hws = (const struct clk_hw*[]) {
5712
+
&gcc_usb4_2_phy_dp1_clk_src.clkr.hw,
5713
+
},
5714
+
.num_parents = 1,
5715
+
.flags = CLK_SET_RATE_PARENT,
6285
5716
.ops = &clk_branch2_ops,
6286
5717
},
6287
5718
},
···
6318
5739
.enable_mask = BIT(0),
6319
5740
.hw.init = &(const struct clk_init_data) {
6320
5741
.name = "gcc_usb4_2_phy_p2rr2p_pipe_clk",
5742
+
.parent_hws = (const struct clk_hw*[]) {
5743
+
&gcc_usb4_2_phy_p2rr2p_pipe_clk_src.clkr.hw,
5744
+
},
5745
+
.num_parents = 1,
5746
+
.flags = CLK_SET_RATE_PARENT,
6321
5747
.ops = &clk_branch2_ops,
6322
5748
},
6323
5749
},
···
6336
5752
.enable_mask = BIT(1),
6337
5753
.hw.init = &(const struct clk_init_data) {
6338
5754
.name = "gcc_usb4_2_phy_pcie_pipe_clk",
5755
+
.parent_hws = (const struct clk_hw*[]) {
5756
+
&gcc_usb4_2_phy_pcie_pipe_mux_clk_src.clkr.hw,
5757
+
},
5758
+
.num_parents = 1,
5759
+
.flags = CLK_SET_RATE_PARENT,
6339
5760
.ops = &clk_branch2_ops,
6340
5761
},
6341
5762
},
···
6348
5759
6349
5760
static struct clk_branch gcc_usb4_2_phy_rx0_clk = {
6350
5761
.halt_reg = 0x110b0,
6351
-
.halt_check = BRANCH_HALT,
5762
+
.halt_check = BRANCH_HALT_SKIP,
6352
5763
.clkr = {
6353
5764
.enable_reg = 0x110b0,
6354
5765
.enable_mask = BIT(0),
6355
5766
.hw.init = &(const struct clk_init_data) {
6356
5767
.name = "gcc_usb4_2_phy_rx0_clk",
5768
+
.parent_hws = (const struct clk_hw*[]) {
5769
+
&gcc_usb4_2_phy_rx0_clk_src.clkr.hw,
5770
+
},
5771
+
.num_parents = 1,
5772
+
.flags = CLK_SET_RATE_PARENT,
6357
5773
.ops = &clk_branch2_ops,
6358
5774
},
6359
5775
},
···
6366
5772
6367
5773
static struct clk_branch gcc_usb4_2_phy_rx1_clk = {
6368
5774
.halt_reg = 0x110c0,
6369
-
.halt_check = BRANCH_HALT,
5775
+
.halt_check = BRANCH_HALT_SKIP,
6370
5776
.clkr = {
6371
5777
.enable_reg = 0x110c0,
6372
5778
.enable_mask = BIT(0),
6373
5779
.hw.init = &(const struct clk_init_data) {
6374
5780
.name = "gcc_usb4_2_phy_rx1_clk",
5781
+
.parent_hws = (const struct clk_hw*[]) {
5782
+
&gcc_usb4_2_phy_rx1_clk_src.clkr.hw,
5783
+
},
5784
+
.num_parents = 1,
5785
+
.flags = CLK_SET_RATE_PARENT,
6375
5786
.ops = &clk_branch2_ops,
6376
5787
},
6377
5788
},
···
6392
5793
.enable_mask = BIT(0),
6393
5794
.hw.init = &(const struct clk_init_data) {
6394
5795
.name = "gcc_usb4_2_phy_usb_pipe_clk",
5796
+
.parent_hws = (const struct clk_hw*[]) {
5797
+
&gcc_usb34_tert_phy_pipe_clk_src.clkr.hw,
5798
+
},
5799
+
.num_parents = 1,
5800
+
.flags = CLK_SET_RATE_PARENT,
6395
5801
.ops = &clk_branch2_ops,
6396
5802
},
6397
5803
},
···
7087
6483
[GCC_USB30_TERT_MOCK_UTMI_CLK_SRC] = &gcc_usb30_tert_mock_utmi_clk_src.clkr,
7088
6484
[GCC_USB30_TERT_MOCK_UTMI_POSTDIV_CLK_SRC] = &gcc_usb30_tert_mock_utmi_postdiv_clk_src.clkr,
7089
6485
[GCC_USB30_TERT_SLEEP_CLK] = &gcc_usb30_tert_sleep_clk.clkr,
6486
+
[GCC_USB34_PRIM_PHY_PIPE_CLK_SRC] = &gcc_usb34_prim_phy_pipe_clk_src.clkr,
6487
+
[GCC_USB34_SEC_PHY_PIPE_CLK_SRC] = &gcc_usb34_sec_phy_pipe_clk_src.clkr,
6488
+
[GCC_USB34_TERT_PHY_PIPE_CLK_SRC] = &gcc_usb34_tert_phy_pipe_clk_src.clkr,
7090
6489
[GCC_USB3_MP_PHY_AUX_CLK] = &gcc_usb3_mp_phy_aux_clk.clkr,
7091
6490
[GCC_USB3_MP_PHY_AUX_CLK_SRC] = &gcc_usb3_mp_phy_aux_clk_src.clkr,
7092
6491
[GCC_USB3_MP_PHY_COM_AUX_CLK] = &gcc_usb3_mp_phy_com_aux_clk.clkr,
···
7115
6508
[GCC_USB4_0_DP1_CLK] = &gcc_usb4_0_dp1_clk.clkr,
7116
6509
[GCC_USB4_0_MASTER_CLK] = &gcc_usb4_0_master_clk.clkr,
7117
6510
[GCC_USB4_0_MASTER_CLK_SRC] = &gcc_usb4_0_master_clk_src.clkr,
6511
+
[GCC_USB4_0_PHY_DP0_CLK_SRC] = &gcc_usb4_0_phy_dp0_clk_src.clkr,
6512
+
[GCC_USB4_0_PHY_DP1_CLK_SRC] = &gcc_usb4_0_phy_dp1_clk_src.clkr,
7118
6513
[GCC_USB4_0_PHY_P2RR2P_PIPE_CLK] = &gcc_usb4_0_phy_p2rr2p_pipe_clk.clkr,
6514
+
[GCC_USB4_0_PHY_P2RR2P_PIPE_CLK_SRC] = &gcc_usb4_0_phy_p2rr2p_pipe_clk_src.clkr,
7119
6515
[GCC_USB4_0_PHY_PCIE_PIPE_CLK] = &gcc_usb4_0_phy_pcie_pipe_clk.clkr,
7120
6516
[GCC_USB4_0_PHY_PCIE_PIPE_CLK_SRC] = &gcc_usb4_0_phy_pcie_pipe_clk_src.clkr,
6517
+
[GCC_USB4_0_PHY_PCIE_PIPE_MUX_CLK_SRC] = &gcc_usb4_0_phy_pcie_pipe_mux_clk_src.clkr,
7121
6518
[GCC_USB4_0_PHY_RX0_CLK] = &gcc_usb4_0_phy_rx0_clk.clkr,
6519
+
[GCC_USB4_0_PHY_RX0_CLK_SRC] = &gcc_usb4_0_phy_rx0_clk_src.clkr,
7122
6520
[GCC_USB4_0_PHY_RX1_CLK] = &gcc_usb4_0_phy_rx1_clk.clkr,
6521
+
[GCC_USB4_0_PHY_RX1_CLK_SRC] = &gcc_usb4_0_phy_rx1_clk_src.clkr,
6522
+
[GCC_USB4_0_PHY_SYS_CLK_SRC] = &gcc_usb4_0_phy_sys_clk_src.clkr,
7123
6523
[GCC_USB4_0_PHY_USB_PIPE_CLK] = &gcc_usb4_0_phy_usb_pipe_clk.clkr,
7124
6524
[GCC_USB4_0_SB_IF_CLK] = &gcc_usb4_0_sb_if_clk.clkr,
7125
6525
[GCC_USB4_0_SB_IF_CLK_SRC] = &gcc_usb4_0_sb_if_clk_src.clkr,
···
7138
6524
[GCC_USB4_1_DP1_CLK] = &gcc_usb4_1_dp1_clk.clkr,
7139
6525
[GCC_USB4_1_MASTER_CLK] = &gcc_usb4_1_master_clk.clkr,
7140
6526
[GCC_USB4_1_MASTER_CLK_SRC] = &gcc_usb4_1_master_clk_src.clkr,
6527
+
[GCC_USB4_1_PHY_DP0_CLK_SRC] = &gcc_usb4_1_phy_dp0_clk_src.clkr,
6528
+
[GCC_USB4_1_PHY_DP1_CLK_SRC] = &gcc_usb4_1_phy_dp1_clk_src.clkr,
7141
6529
[GCC_USB4_1_PHY_P2RR2P_PIPE_CLK] = &gcc_usb4_1_phy_p2rr2p_pipe_clk.clkr,
6530
+
[GCC_USB4_1_PHY_P2RR2P_PIPE_CLK_SRC] = &gcc_usb4_1_phy_p2rr2p_pipe_clk_src.clkr,
7142
6531
[GCC_USB4_1_PHY_PCIE_PIPE_CLK] = &gcc_usb4_1_phy_pcie_pipe_clk.clkr,
7143
6532
[GCC_USB4_1_PHY_PCIE_PIPE_CLK_SRC] = &gcc_usb4_1_phy_pcie_pipe_clk_src.clkr,
6533
+
[GCC_USB4_1_PHY_PCIE_PIPE_MUX_CLK_SRC] = &gcc_usb4_1_phy_pcie_pipe_mux_clk_src.clkr,
7144
6534
[GCC_USB4_1_PHY_RX0_CLK] = &gcc_usb4_1_phy_rx0_clk.clkr,
6535
+
[GCC_USB4_1_PHY_RX0_CLK_SRC] = &gcc_usb4_1_phy_rx0_clk_src.clkr,
7145
6536
[GCC_USB4_1_PHY_RX1_CLK] = &gcc_usb4_1_phy_rx1_clk.clkr,
6537
+
[GCC_USB4_1_PHY_RX1_CLK_SRC] = &gcc_usb4_1_phy_rx1_clk_src.clkr,
6538
+
[GCC_USB4_1_PHY_SYS_CLK_SRC] = &gcc_usb4_1_phy_sys_clk_src.clkr,
7146
6539
[GCC_USB4_1_PHY_USB_PIPE_CLK] = &gcc_usb4_1_phy_usb_pipe_clk.clkr,
7147
6540
[GCC_USB4_1_SB_IF_CLK] = &gcc_usb4_1_sb_if_clk.clkr,
7148
6541
[GCC_USB4_1_SB_IF_CLK_SRC] = &gcc_usb4_1_sb_if_clk_src.clkr,
···
7161
6540
[GCC_USB4_2_DP1_CLK] = &gcc_usb4_2_dp1_clk.clkr,
7162
6541
[GCC_USB4_2_MASTER_CLK] = &gcc_usb4_2_master_clk.clkr,
7163
6542
[GCC_USB4_2_MASTER_CLK_SRC] = &gcc_usb4_2_master_clk_src.clkr,
6543
+
[GCC_USB4_2_PHY_DP0_CLK_SRC] = &gcc_usb4_2_phy_dp0_clk_src.clkr,
6544
+
[GCC_USB4_2_PHY_DP1_CLK_SRC] = &gcc_usb4_2_phy_dp1_clk_src.clkr,
7164
6545
[GCC_USB4_2_PHY_P2RR2P_PIPE_CLK] = &gcc_usb4_2_phy_p2rr2p_pipe_clk.clkr,
6546
+
[GCC_USB4_2_PHY_P2RR2P_PIPE_CLK_SRC] = &gcc_usb4_2_phy_p2rr2p_pipe_clk_src.clkr,
7165
6547
[GCC_USB4_2_PHY_PCIE_PIPE_CLK] = &gcc_usb4_2_phy_pcie_pipe_clk.clkr,
7166
6548
[GCC_USB4_2_PHY_PCIE_PIPE_CLK_SRC] = &gcc_usb4_2_phy_pcie_pipe_clk_src.clkr,
6549
+
[GCC_USB4_2_PHY_PCIE_PIPE_MUX_CLK_SRC] = &gcc_usb4_2_phy_pcie_pipe_mux_clk_src.clkr,
7167
6550
[GCC_USB4_2_PHY_RX0_CLK] = &gcc_usb4_2_phy_rx0_clk.clkr,
6551
+
[GCC_USB4_2_PHY_RX0_CLK_SRC] = &gcc_usb4_2_phy_rx0_clk_src.clkr,
7168
6552
[GCC_USB4_2_PHY_RX1_CLK] = &gcc_usb4_2_phy_rx1_clk.clkr,
6553
+
[GCC_USB4_2_PHY_RX1_CLK_SRC] = &gcc_usb4_2_phy_rx1_clk_src.clkr,
6554
+
[GCC_USB4_2_PHY_SYS_CLK_SRC] = &gcc_usb4_2_phy_sys_clk_src.clkr,
7169
6555
[GCC_USB4_2_PHY_USB_PIPE_CLK] = &gcc_usb4_2_phy_usb_pipe_clk.clkr,
7170
6556
[GCC_USB4_2_SB_IF_CLK] = &gcc_usb4_2_sb_if_clk.clkr,
7171
6557
[GCC_USB4_2_SB_IF_CLK_SRC] = &gcc_usb4_2_sb_if_clk_src.clkr,
···
7288
6660
[GCC_USB3_UNIPHY_MP0_BCR] = { 0x19000 },
7289
6661
[GCC_USB3_UNIPHY_MP1_BCR] = { 0x54000 },
7290
6662
[GCC_USB3PHY_PHY_PRIM_BCR] = { 0x50004 },
6663
+
[GCC_USB4PHY_PHY_PRIM_BCR] = { 0x5000c },
7291
6664
[GCC_USB3PHY_PHY_SEC_BCR] = { 0x2a004 },
6665
+
[GCC_USB4PHY_PHY_SEC_BCR] = { 0x2a00c },
7292
6666
[GCC_USB3PHY_PHY_TERT_BCR] = { 0xa3004 },
6667
+
[GCC_USB4PHY_PHY_TERT_BCR] = { 0xa300c },
7293
6668
[GCC_USB3UNIPHY_PHY_MP0_BCR] = { 0x19004 },
7294
6669
[GCC_USB3UNIPHY_PHY_MP1_BCR] = { 0x54004 },
7295
6670
[GCC_USB4_0_BCR] = { 0x9f000 },
7296
6671
[GCC_USB4_0_DP0_PHY_PRIM_BCR] = { 0x50010 },
7297
-
[GCC_USB4_1_DP0_PHY_SEC_BCR] = { 0x2a010 },
7298
-
[GCC_USB4_2_DP0_PHY_TERT_BCR] = { 0xa3010 },
6672
+
[GCC_USB4_0_MISC_USB4_SYS_BCR] = { .reg = 0xad0f8, .bit = 0 },
6673
+
[GCC_USB4_0_MISC_RX_CLK_0_BCR] = { .reg = 0xad0f8, .bit = 1 },
6674
+
[GCC_USB4_0_MISC_RX_CLK_1_BCR] = { .reg = 0xad0f8, .bit = 2 },
6675
+
[GCC_USB4_0_MISC_USB_PIPE_BCR] = { .reg = 0xad0f8, .bit = 3 },
6676
+
[GCC_USB4_0_MISC_PCIE_PIPE_BCR] = { .reg = 0xad0f8, .bit = 4 },
6677
+
[GCC_USB4_0_MISC_TMU_BCR] = { .reg = 0xad0f8, .bit = 5 },
6678
+
[GCC_USB4_0_MISC_SB_IF_BCR] = { .reg = 0xad0f8, .bit = 6 },
6679
+
[GCC_USB4_0_MISC_HIA_MSTR_BCR] = { .reg = 0xad0f8, .bit = 7 },
6680
+
[GCC_USB4_0_MISC_AHB_BCR] = { .reg = 0xad0f8, .bit = 8 },
6681
+
[GCC_USB4_0_MISC_DP0_MAX_PCLK_BCR] = { .reg = 0xad0f8, .bit = 9 },
6682
+
[GCC_USB4_0_MISC_DP1_MAX_PCLK_BCR] = { .reg = 0xad0f8, .bit = 10 },
7299
6683
[GCC_USB4_1_BCR] = { 0x2b000 },
6684
+
[GCC_USB4_1_DP0_PHY_SEC_BCR] = { 0x2a010 },
6685
+
[GCC_USB4_1_MISC_USB4_SYS_BCR] = { .reg = 0xae0f8, .bit = 0 },
6686
+
[GCC_USB4_1_MISC_RX_CLK_0_BCR] = { .reg = 0xae0f8, .bit = 1 },
6687
+
[GCC_USB4_1_MISC_RX_CLK_1_BCR] = { .reg = 0xae0f8, .bit = 2 },
6688
+
[GCC_USB4_1_MISC_USB_PIPE_BCR] = { .reg = 0xae0f8, .bit = 3 },
6689
+
[GCC_USB4_1_MISC_PCIE_PIPE_BCR] = { .reg = 0xae0f8, .bit = 4 },
6690
+
[GCC_USB4_1_MISC_TMU_BCR] = { .reg = 0xae0f8, .bit = 5 },
6691
+
[GCC_USB4_1_MISC_SB_IF_BCR] = { .reg = 0xae0f8, .bit = 6 },
6692
+
[GCC_USB4_1_MISC_HIA_MSTR_BCR] = { .reg = 0xae0f8, .bit = 7 },
6693
+
[GCC_USB4_1_MISC_AHB_BCR] = { .reg = 0xae0f8, .bit = 8 },
6694
+
[GCC_USB4_1_MISC_DP0_MAX_PCLK_BCR] = { .reg = 0xae0f8, .bit = 9 },
6695
+
[GCC_USB4_1_MISC_DP1_MAX_PCLK_BCR] = { .reg = 0xae0f8, .bit = 10 },
7300
6696
[GCC_USB4_2_BCR] = { 0x11000 },
6697
+
[GCC_USB4_2_DP0_PHY_TERT_BCR] = { 0xa3010 },
6698
+
[GCC_USB4_2_MISC_USB4_SYS_BCR] = { .reg = 0xaf0f8, .bit = 0 },
6699
+
[GCC_USB4_2_MISC_RX_CLK_0_BCR] = { .reg = 0xaf0f8, .bit = 1 },
6700
+
[GCC_USB4_2_MISC_RX_CLK_1_BCR] = { .reg = 0xaf0f8, .bit = 2 },
6701
+
[GCC_USB4_2_MISC_USB_PIPE_BCR] = { .reg = 0xaf0f8, .bit = 3 },
6702
+
[GCC_USB4_2_MISC_PCIE_PIPE_BCR] = { .reg = 0xaf0f8, .bit = 4 },
6703
+
[GCC_USB4_2_MISC_TMU_BCR] = { .reg = 0xaf0f8, .bit = 5 },
6704
+
[GCC_USB4_2_MISC_SB_IF_BCR] = { .reg = 0xaf0f8, .bit = 6 },
6705
+
[GCC_USB4_2_MISC_HIA_MSTR_BCR] = { .reg = 0xaf0f8, .bit = 7 },
6706
+
[GCC_USB4_2_MISC_AHB_BCR] = { .reg = 0xaf0f8, .bit = 8 },
6707
+
[GCC_USB4_2_MISC_DP0_MAX_PCLK_BCR] = { .reg = 0xaf0f8, .bit = 9 },
6708
+
[GCC_USB4_2_MISC_DP1_MAX_PCLK_BCR] = { .reg = 0xaf0f8, .bit = 10 },
7301
6709
[GCC_USB_0_PHY_BCR] = { 0x50020 },
7302
6710
[GCC_USB_1_PHY_BCR] = { 0x2a020 },
7303
6711
[GCC_USB_2_PHY_BCR] = { 0xa3020 },