tjh.dev / kernel
Linux kernel mirror (for testing) git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
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Merge tag 'x86-sev-2025-03-22' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip

Pull x86 SEV updates from Ingo Molnar:

- Improve sme_enable() PIC build robustness (Kevin Loughlin)

- Simplify vc_handle_msr() a bit (Peng Hao)

[ Just reminding myself and everybody else about the endless stream of
x86 TLAs: "SEV" is AMD's Secure Encrypted Virtualization - Linus ]

* tag 'x86-sev-2025-03-22' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip:
x86/sev: Simplify the code by removing unnecessary 'else' statement
x86/sev: Add missing RIP_REL_REF() invocations during sme_enable()

Linus Torvalds 8ac6067b a49a879f

+3 -4
+1 -2
arch/x86/coco/sev/core.c
··· 1480 1480 case MSR_AMD64_GUEST_TSC_FREQ: 1481 1481 if (sev_status & MSR_AMD64_SNP_SECURE_TSC) 1482 1482 return __vc_handle_secure_tsc_msrs(regs, write); 1483 - else 1484 - break; 1483 + break; 1485 1484 default: 1486 1485 break; 1487 1486 }
+2 -2
arch/x86/mm/mem_encrypt_identity.c
··· 563 563 } 564 564 565 565 RIP_REL_REF(sme_me_mask) = me_mask; 566 - physical_mask &= ~me_mask; 567 - cc_vendor = CC_VENDOR_AMD; 566 + RIP_REL_REF(physical_mask) &= ~me_mask; 567 + RIP_REL_REF(cc_vendor) = CC_VENDOR_AMD; 568 568 cc_set_mask(me_mask); 569 569 }