drm/i915/psr: Check if final vblank is sufficient for PSR features

Currently, wake line latency checks rely on the vblank length,
which does not account for either the extra vblank delay for icl/tgl or for
the optimized guardband which will come into picture later at some point.

Validate whether the final vblank (with extra vblank delay) or guardband
is sufficient to support wake line latencies required by Panel Replay and
PSR2 selective update. Disable the PSR features if their wake requirements
cannot be accomodated.

v2: Add comments clarifying wake line checks and rationale for not
resetting SCL. (Jouni)
v3: Reset other psr flags based on features that are dropped. (Jouni)
v4: Update commit message.
v5: Remove early return and simplify the checking for wakelines. (Jouni)

Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
Cc: Animesh Manna <animesh.manna@intel.com>
Cc: Jouni Högander <jouni.hogander@intel.com>
Reviewed-by: Jouni Högander <jouni.hogander@intel.com>
Link: https://lore.kernel.org/r/20251016055415.2101347-9-ankit.k.nautiyal@intel.com

Ankit Nautiyal 8 months ago 8c0cf4fe 0d7f4e99

+63 -8

1 changed file

expand all

drivers

gpu

drm

i915

display

intel_psr.c

+63 -8

drivers/gpu/drm/i915/display/intel_psr.c

··· 1405 1405 return 1; 1406 1406 } 1407 1407 1408 + static bool _wake_lines_fit_into_vblank(const struct intel_crtc_state *crtc_state, 1409 + int vblank, 1410 + int wake_lines) 1411 + { 1412 + if (crtc_state->req_psr2_sdp_prior_scanline) 1413 + vblank -= 1; 1414 + 1415 + /* Vblank >= PSR2_CTL Block Count Number maximum line count */ 1416 + if (vblank < wake_lines) 1417 + return false; 1418 + 1419 + return true; 1420 + } 1421 + 1408 1422 static bool wake_lines_fit_into_vblank(struct intel_dp *intel_dp, 1409 1423 const struct intel_crtc_state *crtc_state, 1410 1424 bool aux_less, ··· 1442 1428 crtc_state->alpm_state.fast_wake_lines) : 1443 1429 crtc_state->alpm_state.io_wake_lines; 1444 1430 1445 - if (crtc_state->req_psr2_sdp_prior_scanline) 1446 - vblank -= 1; 1447 - 1448 - /* Vblank >= PSR2_CTL Block Count Number maximum line count */ 1449 - if (vblank < wake_lines) 1450 - return false; 1451 - 1452 - return true; 1431 + /* 1432 + * Guardband has not been computed yet, so we conservatively check if the 1433 + * full vblank duration is sufficient to accommodate wake line requirements 1434 + * for PSR features like Panel Replay and Selective Update. 1435 + * 1436 + * Once the actual guardband is available, a more accurate validation is 1437 + * performed in intel_psr_compute_config_late(), and PSR features are 1438 + * disabled if wake lines exceed the available guardband. 1439 + */ 1440 + return _wake_lines_fit_into_vblank(crtc_state, vblank, wake_lines); 1453 1441 } 1454 1442 1455 1443 static bool alpm_config_valid(struct intel_dp *intel_dp, ··· 4367 4351 struct intel_crtc_state *crtc_state) 4368 4352 { 4369 4353 struct intel_display *display = to_intel_display(intel_dp); 4354 + int vblank = intel_crtc_vblank_length(crtc_state); 4355 + int wake_lines; 4356 + 4357 + if (intel_psr_needs_alpm_aux_less(intel_dp, crtc_state)) 4358 + wake_lines = crtc_state->alpm_state.aux_less_wake_lines; 4359 + else if (intel_psr_needs_alpm(intel_dp, crtc_state)) 4360 + wake_lines = DISPLAY_VER(display) < 20 ? 4361 + psr2_block_count_lines(crtc_state->alpm_state.io_wake_lines, 4362 + crtc_state->alpm_state.fast_wake_lines) : 4363 + crtc_state->alpm_state.io_wake_lines; 4364 + else 4365 + wake_lines = 0; 4366 + 4367 + /* 4368 + * Disable the PSR features if wake lines exceed the available vblank. 4369 + * Though SCL is computed based on these PSR features, it is not reset 4370 + * even if the PSR features are disabled to avoid changing vblank start 4371 + * at this stage. 4372 + */ 4373 + if (wake_lines && !_wake_lines_fit_into_vblank(crtc_state, vblank, wake_lines)) { 4374 + drm_dbg_kms(display->drm, 4375 + "Adjusting PSR/PR mode: vblank too short for wake lines = %d\n", 4376 + wake_lines); 4377 + 4378 + if (crtc_state->has_panel_replay) { 4379 + crtc_state->has_panel_replay = false; 4380 + /* 4381 + * #TODO : Add fall back to PSR/PSR2 4382 + * Since panel replay cannot be supported, we can fall back to PSR/PSR2. 4383 + * This will require calling compute_config for psr and psr2 with check for 4384 + * actual guardband instead of vblank_length. 4385 + */ 4386 + crtc_state->has_psr = false; 4387 + } 4388 + 4389 + crtc_state->has_sel_update = false; 4390 + crtc_state->enable_psr2_su_region_et = false; 4391 + crtc_state->enable_psr2_sel_fetch = false; 4392 + } 4370 4393 4371 4394 /* Wa_18037818876 */ 4372 4395 if (intel_psr_needs_wa_18037818876(intel_dp, crtc_state)) {

Configure Feed

Configure Feed