tjh.dev / kernel
Linux kernel mirror (for testing) git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel os linux
1
fork

Configure Feed

Select the types of activity you want to include in your feed.

drm/i915/dram: Sort SKL+ DIMM register bits

Use the customary big endian order when defining the
SKL/ICL DIMM registers.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Link: https://patch.msgid.link/20251029204215.12292-3-ville.syrjala@linux.intel.com
Reviewed-by: Lucas De Marchi <lucas.demarchi@intel.com>

Ville Syrjälä 8c171a9b 5b23aa42

+9 -9
+9 -9
drivers/gpu/drm/i915/intel_mchbar_regs.h
··· 161 161 #define SKL_MAD_DIMM_CH0_0_0_0_MCHBAR_MCMAIN _MMIO(MCHBAR_MIRROR_BASE_SNB + 0x500C) 162 162 #define SKL_MAD_DIMM_CH1_0_0_0_MCHBAR_MCMAIN _MMIO(MCHBAR_MIRROR_BASE_SNB + 0x5010) 163 163 #define SKL_DRAM_S_SHIFT 16 164 - #define SKL_DRAM_SIZE_MASK REG_GENMASK(5, 0) 164 + #define SKL_DRAM_RANK_MASK REG_GENMASK(10, 10) 165 + #define SKL_DRAM_RANK_1 REG_FIELD_PREP(SKL_DRAM_RANK_MASK, 0) 166 + #define SKL_DRAM_RANK_2 REG_FIELD_PREP(SKL_DRAM_RANK_MASK, 1) 165 167 #define SKL_DRAM_WIDTH_MASK REG_GENMASK(9, 8) 166 168 #define SKL_DRAM_WIDTH_X8 REG_FIELD_PREP(SKL_DRAM_WIDTH_MASK, 0) 167 169 #define SKL_DRAM_WIDTH_X16 REG_FIELD_PREP(SKL_DRAM_WIDTH_MASK, 1) 168 170 #define SKL_DRAM_WIDTH_X32 REG_FIELD_PREP(SKL_DRAM_WIDTH_MASK, 2) 169 - #define SKL_DRAM_RANK_MASK REG_GENMASK(10, 10) 170 - #define SKL_DRAM_RANK_1 REG_FIELD_PREP(SKL_DRAM_RANK_MASK, 0) 171 - #define SKL_DRAM_RANK_2 REG_FIELD_PREP(SKL_DRAM_RANK_MASK, 1) 172 - #define ICL_DRAM_SIZE_MASK REG_GENMASK(6, 0) 173 - #define ICL_DRAM_WIDTH_MASK REG_GENMASK(8, 7) 174 - #define ICL_DRAM_WIDTH_X8 REG_FIELD_PREP(ICL_DRAM_WIDTH_MASK, 0) 175 - #define ICL_DRAM_WIDTH_X16 REG_FIELD_PREP(ICL_DRAM_WIDTH_MASK, 1) 176 - #define ICL_DRAM_WIDTH_X32 REG_FIELD_PREP(ICL_DRAM_WIDTH_MASK, 2) 171 + #define SKL_DRAM_SIZE_MASK REG_GENMASK(5, 0) 177 172 #define ICL_DRAM_RANK_MASK REG_GENMASK(10, 9) 178 173 #define ICL_DRAM_RANK_1 REG_FIELD_PREP(ICL_DRAM_RANK_MASK, 0) 179 174 #define ICL_DRAM_RANK_2 REG_FIELD_PREP(ICL_DRAM_RANK_MASK, 1) 180 175 #define ICL_DRAM_RANK_3 REG_FIELD_PREP(ICL_DRAM_RANK_MASK, 2) 181 176 #define ICL_DRAM_RANK_4 REG_FIELD_PREP(ICL_DRAM_RANK_MASK, 3) 177 + #define ICL_DRAM_WIDTH_MASK REG_GENMASK(8, 7) 178 + #define ICL_DRAM_WIDTH_X8 REG_FIELD_PREP(ICL_DRAM_WIDTH_MASK, 0) 179 + #define ICL_DRAM_WIDTH_X16 REG_FIELD_PREP(ICL_DRAM_WIDTH_MASK, 1) 180 + #define ICL_DRAM_WIDTH_X32 REG_FIELD_PREP(ICL_DRAM_WIDTH_MASK, 2) 181 + #define ICL_DRAM_SIZE_MASK REG_GENMASK(6, 0) 182 182 183 183 #define SA_PERF_STATUS_0_0_0_MCHBAR_PC _MMIO(MCHBAR_MIRROR_BASE_SNB + 0x5918) 184 184 #define DG1_QCLK_RATIO_MASK REG_GENMASK(9, 2)