Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
Merge branch 'fixes' of git://git.linaro.org/people/rmk/linux-arm
Pull ARM fixes from Russell King:
"A set of fixes from various people - Will Deacon gets a prize for
removing code this time around. The biggest fix in this lot is
sorting out the ARM740T mess. The rest are relatively small fixes."
* 'fixes' of git://git.linaro.org/people/rmk/linux-arm:
ARM: 7699/1: sched_clock: Add more notrace to prevent recursion
ARM: 7698/1: perf: fix group validation when using enable_on_exec
ARM: 7697/1: hw_breakpoint: do not use __cpuinitdata for dbg_cpu_pm_nb
ARM: 7696/1: Fix kexec by setting outer_cache.inv_all for Feroceon
ARM: 7694/1: ARM, TCM: initialize TCM in paging_init(), instead of setup_arch()
ARM: 7692/1: iop3xx: move IOP3XX_PERIPHERAL_VIRT_BASE
ARM: modules: don't export cpu_set_pte_ext when !MMU
ARM: mm: remove broken condition check for v4 flushing
ARM: mm: fix numerous hideous errors in proc-arm740.S
ARM: cache: remove ARMv3 support code
ARM: tlbflush: remove ARMv3 support
+34
-182
-8
arch/arm/include/asm/glue-cache.h
-8
arch/arm/include/asm/glue-cache.h
+1
-1
arch/arm/include/asm/hardware/iop3xx.h
+1
-1
arch/arm/include/asm/hardware/iop3xx.h
···
37
37
* IOP3XX processor registers
38
38
*/
39
39
#define IOP3XX_PERIPHERAL_PHYS_BASE 0xffffe000
40
-
#define IOP3XX_PERIPHERAL_VIRT_BASE 0xfeffe000
40
+
#define IOP3XX_PERIPHERAL_VIRT_BASE 0xfedfe000
41
41
#define IOP3XX_PERIPHERAL_SIZE 0x00002000
42
42
#define IOP3XX_PERIPHERAL_UPPER_PA (IOP3XX_PERIPHERAL_PHYS_BASE +\
43
43
IOP3XX_PERIPHERAL_SIZE - 1)
+2
-9
arch/arm/include/asm/tlbflush.h
+2
-9
arch/arm/include/asm/tlbflush.h
···
14
14
15
15
#include <asm/glue.h>
16
16
17
-
#define TLB_V3_PAGE (1 << 0)
18
17
#define TLB_V4_U_PAGE (1 << 1)
19
18
#define TLB_V4_D_PAGE (1 << 2)
20
19
#define TLB_V4_I_PAGE (1 << 3)
···
21
22
#define TLB_V6_D_PAGE (1 << 5)
22
23
#define TLB_V6_I_PAGE (1 << 6)
23
24
24
-
#define TLB_V3_FULL (1 << 8)
25
25
#define TLB_V4_U_FULL (1 << 9)
26
26
#define TLB_V4_D_FULL (1 << 10)
27
27
#define TLB_V4_I_FULL (1 << 11)
···
50
52
* =============
51
53
*
52
54
* We have the following to choose from:
53
-
* v3 - ARMv3
54
55
* v4 - ARMv4 without write buffer
55
56
* v4wb - ARMv4 with write buffer without I TLB flush entry instruction
56
57
* v4wbi - ARMv4 with write buffer with I TLB flush entry instruction
···
327
330
if (tlb_flag(TLB_WB))
328
331
dsb();
329
332
330
-
tlb_op(TLB_V3_FULL, "c6, c0, 0", zero);
331
333
tlb_op(TLB_V4_U_FULL | TLB_V6_U_FULL, "c8, c7, 0", zero);
332
334
tlb_op(TLB_V4_D_FULL | TLB_V6_D_FULL, "c8, c6, 0", zero);
333
335
tlb_op(TLB_V4_I_FULL | TLB_V6_I_FULL, "c8, c5, 0", zero);
···
347
351
if (tlb_flag(TLB_WB))
348
352
dsb();
349
353
350
-
if (possible_tlb_flags & (TLB_V3_FULL|TLB_V4_U_FULL|TLB_V4_D_FULL|TLB_V4_I_FULL)) {
354
+
if (possible_tlb_flags & (TLB_V4_U_FULL|TLB_V4_D_FULL|TLB_V4_I_FULL)) {
351
355
if (cpumask_test_cpu(get_cpu(), mm_cpumask(mm))) {
352
-
tlb_op(TLB_V3_FULL, "c6, c0, 0", zero);
353
356
tlb_op(TLB_V4_U_FULL, "c8, c7, 0", zero);
354
357
tlb_op(TLB_V4_D_FULL, "c8, c6, 0", zero);
355
358
tlb_op(TLB_V4_I_FULL, "c8, c5, 0", zero);
···
380
385
if (tlb_flag(TLB_WB))
381
386
dsb();
382
387
383
-
if (possible_tlb_flags & (TLB_V3_PAGE|TLB_V4_U_PAGE|TLB_V4_D_PAGE|TLB_V4_I_PAGE|TLB_V4_I_FULL) &&
388
+
if (possible_tlb_flags & (TLB_V4_U_PAGE|TLB_V4_D_PAGE|TLB_V4_I_PAGE|TLB_V4_I_FULL) &&
384
389
cpumask_test_cpu(smp_processor_id(), mm_cpumask(vma->vm_mm))) {
385
-
tlb_op(TLB_V3_PAGE, "c6, c0, 0", uaddr);
386
390
tlb_op(TLB_V4_U_PAGE, "c8, c7, 1", uaddr);
387
391
tlb_op(TLB_V4_D_PAGE, "c8, c6, 1", uaddr);
388
392
tlb_op(TLB_V4_I_PAGE, "c8, c5, 1", uaddr);
···
412
418
if (tlb_flag(TLB_WB))
413
419
dsb();
414
420
415
-
tlb_op(TLB_V3_PAGE, "c6, c0, 0", kaddr);
416
421
tlb_op(TLB_V4_U_PAGE, "c8, c7, 1", kaddr);
417
422
tlb_op(TLB_V4_D_PAGE, "c8, c6, 1", kaddr);
418
423
tlb_op(TLB_V4_I_PAGE, "c8, c5, 1", kaddr);
+1
-1
arch/arm/kernel/hw_breakpoint.c
+1
-1
arch/arm/kernel/hw_breakpoint.c
+4
-1
arch/arm/kernel/perf_event.c
+4
-1
arch/arm/kernel/perf_event.c
···
253
253
struct arm_pmu *armpmu = to_arm_pmu(event->pmu);
254
254
struct pmu *leader_pmu = event->group_leader->pmu;
255
255
256
-
if (event->pmu != leader_pmu || event->state <= PERF_EVENT_STATE_OFF)
256
+
if (event->pmu != leader_pmu || event->state < PERF_EVENT_STATE_OFF)
257
+
return 1;
258
+
259
+
if (event->state == PERF_EVENT_STATE_OFF && !event->attr.enable_on_exec)
257
260
return 1;
258
261
259
262
return armpmu->get_event_idx(hw_events, event) >= 0;
+2
-2
arch/arm/kernel/sched_clock.c
+2
-2
arch/arm/kernel/sched_clock.c
···
45
45
46
46
static u32 __read_mostly (*read_sched_clock)(void) = jiffy_sched_clock_read;
47
47
48
-
static inline u64 cyc_to_ns(u64 cyc, u32 mult, u32 shift)
48
+
static inline u64 notrace cyc_to_ns(u64 cyc, u32 mult, u32 shift)
49
49
{
50
50
return (cyc * mult) >> shift;
51
51
}
52
52
53
-
static unsigned long long cyc_to_sched_clock(u32 cyc, u32 mask)
53
+
static unsigned long long notrace cyc_to_sched_clock(u32 cyc, u32 mask)
54
54
{
55
55
u64 epoch_ns;
56
56
u32 epoch_cyc;
-3
arch/arm/kernel/setup.c
-3
arch/arm/kernel/setup.c
···
56
56
#include <asm/virt.h>
57
57
58
58
#include "atags.h"
59
-
#include "tcm.h"
60
59
61
60
62
61
#if defined(CONFIG_FPE_NWFPE) || defined(CONFIG_FPE_FASTFPE)
···
796
797
hyp_mode_check();
797
798
798
799
reserve_crashkernel();
799
-
800
-
tcm_init();
801
800
802
801
#ifdef CONFIG_MULTI_IRQ_HANDLER
803
802
handle_arch_irq = mdesc->handle_irq;
-1
arch/arm/kernel/tcm.c
-1
arch/arm/kernel/tcm.c
arch/arm/kernel/tcm.h
arch/arm/mm/tcm.h
arch/arm/kernel/tcm.h
arch/arm/mm/tcm.h
+1
-4
arch/arm/mm/Kconfig
+1
-4
arch/arm/mm/Kconfig
···
43
43
depends on !MMU
44
44
select CPU_32v4T
45
45
select CPU_ABRT_LV4T
46
-
select CPU_CACHE_V3 # although the core is v4t
46
+
select CPU_CACHE_V4
47
47
select CPU_CP15_MPU
48
48
select CPU_PABRT_LEGACY
49
49
help
···
469
469
bool
470
470
471
471
# The cache model
472
-
config CPU_CACHE_V3
473
-
bool
474
-
475
472
config CPU_CACHE_V4
476
473
bool
477
474
-1
arch/arm/mm/Makefile
-1
arch/arm/mm/Makefile
···
33
33
obj-$(CONFIG_CPU_PABRT_V6) += pabort-v6.o
34
34
obj-$(CONFIG_CPU_PABRT_V7) += pabort-v7.o
35
35
36
-
obj-$(CONFIG_CPU_CACHE_V3) += cache-v3.o
37
36
obj-$(CONFIG_CPU_CACHE_V4) += cache-v4.o
38
37
obj-$(CONFIG_CPU_CACHE_V4WT) += cache-v4wt.o
39
38
obj-$(CONFIG_CPU_CACHE_V4WB) += cache-v4wb.o
+1
arch/arm/mm/cache-feroceon-l2.c
+1
arch/arm/mm/cache-feroceon-l2.c
-137
arch/arm/mm/cache-v3.S
-137
arch/arm/mm/cache-v3.S
···
1
-
/*
2
-
* linux/arch/arm/mm/cache-v3.S
3
-
*
4
-
* Copyright (C) 1997-2002 Russell king
5
-
*
6
-
* This program is free software; you can redistribute it and/or modify
7
-
* it under the terms of the GNU General Public License version 2 as
8
-
* published by the Free Software Foundation.
9
-
*/
10
-
#include <linux/linkage.h>
11
-
#include <linux/init.h>
12
-
#include <asm/page.h>
13
-
#include "proc-macros.S"
14
-
15
-
/*
16
-
* flush_icache_all()
17
-
*
18
-
* Unconditionally clean and invalidate the entire icache.
19
-
*/
20
-
ENTRY(v3_flush_icache_all)
21
-
mov pc, lr
22
-
ENDPROC(v3_flush_icache_all)
23
-
24
-
/*
25
-
* flush_user_cache_all()
26
-
*
27
-
* Invalidate all cache entries in a particular address
28
-
* space.
29
-
*
30
-
* - mm - mm_struct describing address space
31
-
*/
32
-
ENTRY(v3_flush_user_cache_all)
33
-
/* FALLTHROUGH */
34
-
/*
35
-
* flush_kern_cache_all()
36
-
*
37
-
* Clean and invalidate the entire cache.
38
-
*/
39
-
ENTRY(v3_flush_kern_cache_all)
40
-
/* FALLTHROUGH */
41
-
42
-
/*
43
-
* flush_user_cache_range(start, end, flags)
44
-
*
45
-
* Invalidate a range of cache entries in the specified
46
-
* address space.
47
-
*
48
-
* - start - start address (may not be aligned)
49
-
* - end - end address (exclusive, may not be aligned)
50
-
* - flags - vma_area_struct flags describing address space
51
-
*/
52
-
ENTRY(v3_flush_user_cache_range)
53
-
mov ip, #0
54
-
mcreq p15, 0, ip, c7, c0, 0 @ flush ID cache
55
-
mov pc, lr
56
-
57
-
/*
58
-
* coherent_kern_range(start, end)
59
-
*
60
-
* Ensure coherency between the Icache and the Dcache in the
61
-
* region described by start. If you have non-snooping
62
-
* Harvard caches, you need to implement this function.
63
-
*
64
-
* - start - virtual start address
65
-
* - end - virtual end address
66
-
*/
67
-
ENTRY(v3_coherent_kern_range)
68
-
/* FALLTHROUGH */
69
-
70
-
/*
71
-
* coherent_user_range(start, end)
72
-
*
73
-
* Ensure coherency between the Icache and the Dcache in the
74
-
* region described by start. If you have non-snooping
75
-
* Harvard caches, you need to implement this function.
76
-
*
77
-
* - start - virtual start address
78
-
* - end - virtual end address
79
-
*/
80
-
ENTRY(v3_coherent_user_range)
81
-
mov r0, #0
82
-
mov pc, lr
83
-
84
-
/*
85
-
* flush_kern_dcache_area(void *page, size_t size)
86
-
*
87
-
* Ensure no D cache aliasing occurs, either with itself or
88
-
* the I cache
89
-
*
90
-
* - addr - kernel address
91
-
* - size - region size
92
-
*/
93
-
ENTRY(v3_flush_kern_dcache_area)
94
-
/* FALLTHROUGH */
95
-
96
-
/*
97
-
* dma_flush_range(start, end)
98
-
*
99
-
* Clean and invalidate the specified virtual address range.
100
-
*
101
-
* - start - virtual start address
102
-
* - end - virtual end address
103
-
*/
104
-
ENTRY(v3_dma_flush_range)
105
-
mov r0, #0
106
-
mcr p15, 0, r0, c7, c0, 0 @ flush ID cache
107
-
mov pc, lr
108
-
109
-
/*
110
-
* dma_unmap_area(start, size, dir)
111
-
* - start - kernel virtual start address
112
-
* - size - size of region
113
-
* - dir - DMA direction
114
-
*/
115
-
ENTRY(v3_dma_unmap_area)
116
-
teq r2, #DMA_TO_DEVICE
117
-
bne v3_dma_flush_range
118
-
/* FALLTHROUGH */
119
-
120
-
/*
121
-
* dma_map_area(start, size, dir)
122
-
* - start - kernel virtual start address
123
-
* - size - size of region
124
-
* - dir - DMA direction
125
-
*/
126
-
ENTRY(v3_dma_map_area)
127
-
mov pc, lr
128
-
ENDPROC(v3_dma_unmap_area)
129
-
ENDPROC(v3_dma_map_area)
130
-
131
-
.globl v3_flush_kern_cache_louis
132
-
.equ v3_flush_kern_cache_louis, v3_flush_kern_cache_all
133
-
134
-
__INITDATA
135
-
136
-
@ define struct cpu_cache_fns (see <asm/cacheflush.h> and proc-macros.S)
137
-
define_cache_functions v3
+1
-1
arch/arm/mm/cache-v4.S
+1
-1
arch/arm/mm/cache-v4.S
+2
arch/arm/mm/mmu.c
+2
arch/arm/mm/mmu.c
···
34
34
#include <asm/mach/pci.h>
35
35
36
36
#include "mm.h"
37
+
#include "tcm.h"
37
38
38
39
/*
39
40
* empty_zero_page is a special page that is used for
···
1278
1277
dma_contiguous_remap();
1279
1278
devicemaps_init(mdesc);
1280
1279
kmap_init();
1280
+
tcm_init();
1281
1281
1282
1282
top_pmd = pmd_off_k(0xffff0000);
1283
1283
+17
-13
arch/arm/mm/proc-arm740.S
+17
-13
arch/arm/mm/proc-arm740.S
···
77
77
mcr p15, 0, r0, c6, c0 @ set area 0, default
78
78
79
79
ldr r0, =(CONFIG_DRAM_BASE & 0xFFFFF000) @ base[31:12] of RAM
80
-
ldr r1, =(CONFIG_DRAM_SIZE >> 12) @ size of RAM (must be >= 4KB)
81
-
mov r2, #10 @ 11 is the minimum (4KB)
82
-
1: add r2, r2, #1 @ area size *= 2
83
-
mov r1, r1, lsr #1
80
+
ldr r3, =(CONFIG_DRAM_SIZE >> 12) @ size of RAM (must be >= 4KB)
81
+
mov r4, #10 @ 11 is the minimum (4KB)
82
+
1: add r4, r4, #1 @ area size *= 2
83
+
movs r3, r3, lsr #1
84
84
bne 1b @ count not zero r-shift
85
-
orr r0, r0, r2, lsl #1 @ the area register value
85
+
orr r0, r0, r4, lsl #1 @ the area register value
86
86
orr r0, r0, #1 @ set enable bit
87
87
mcr p15, 0, r0, c6, c1 @ set area 1, RAM
88
88
89
89
ldr r0, =(CONFIG_FLASH_MEM_BASE & 0xFFFFF000) @ base[31:12] of FLASH
90
-
ldr r1, =(CONFIG_FLASH_SIZE >> 12) @ size of FLASH (must be >= 4KB)
91
-
mov r2, #10 @ 11 is the minimum (4KB)
92
-
1: add r2, r2, #1 @ area size *= 2
93
-
mov r1, r1, lsr #1
90
+
ldr r3, =(CONFIG_FLASH_SIZE >> 12) @ size of FLASH (must be >= 4KB)
91
+
cmp r3, #0
92
+
moveq r0, #0
93
+
beq 2f
94
+
mov r4, #10 @ 11 is the minimum (4KB)
95
+
1: add r4, r4, #1 @ area size *= 2
96
+
movs r3, r3, lsr #1
94
97
bne 1b @ count not zero r-shift
95
-
orr r0, r0, r2, lsl #1 @ the area register value
98
+
orr r0, r0, r4, lsl #1 @ the area register value
96
99
orr r0, r0, #1 @ set enable bit
97
-
mcr p15, 0, r0, c6, c2 @ set area 2, ROM/FLASH
100
+
2: mcr p15, 0, r0, c6, c2 @ set area 2, ROM/FLASH
98
101
99
102
mov r0, #0x06
100
103
mcr p15, 0, r0, c2, c0 @ Region 1&2 cacheable
···
140
137
.long 0x41807400
141
138
.long 0xfffffff0
142
139
.long 0
140
+
.long 0
143
141
b __arm740_setup
144
142
.long cpu_arch_name
145
143
.long cpu_elf_name
146
-
.long HWCAP_SWP | HWCAP_HALF | HWCAP_26BIT
144
+
.long HWCAP_SWP | HWCAP_HALF | HWCAP_THUMB | HWCAP_26BIT
147
145
.long cpu_arm740_name
148
146
.long arm740_processor_functions
149
147
.long 0
150
148
.long 0
151
-
.long v3_cache_fns @ cache model
149
+
.long v4_cache_fns @ cache model
152
150
.size __arm740_proc_info, . - __arm740_proc_info