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git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
clk: qcom: Add QCM2290 GPU clock controller driver
Add a driver for the GPU clock controller block found on the QCM2290 SoC.
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Link: https://lore.kernel.org/r/20240606-topic-rb1_gpu-v4-3-4bc0c19da4af@linaro.org
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
authored by
Konrad Dybcio
and committed by
Bjorn Andersson
8cab0336
d4d74e4b
+433
+9
drivers/clk/qcom/Kconfig
+9
drivers/clk/qcom/Kconfig
···
65
65
Support for the TCSR clock controller on X1E80100 devices.
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Say Y if you want to use peripheral devices such as SD/UFS.
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config CLK_QCM2290_GPUCC
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tristate "QCM2290 Graphics Clock Controller"
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depends on ARM64 || COMPILE_TEST
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select CLK_QCM2290_GCC
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help
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Support for the graphics clock controller on QCM2290 devices.
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Say Y if you want to support graphics controller devices and
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functionality such as 3D graphics.
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+
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config QCOM_A53PLL
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tristate "MSM8916 A53 PLL"
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help
+1
drivers/clk/qcom/Makefile
+1
drivers/clk/qcom/Makefile
···
26
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obj-$(CONFIG_CLK_X1E80100_GCC) += gcc-x1e80100.o
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obj-$(CONFIG_CLK_X1E80100_GPUCC) += gpucc-x1e80100.o
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obj-$(CONFIG_CLK_X1E80100_TCSRCC) += tcsrcc-x1e80100.o
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obj-$(CONFIG_CLK_QCM2290_GPUCC) += gpucc-qcm2290.o
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obj-$(CONFIG_IPQ_APSS_PLL) += apss-ipq-pll.o
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obj-$(CONFIG_IPQ_APSS_6018) += apss-ipq6018.o
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obj-$(CONFIG_IPQ_GCC_4019) += gcc-ipq4019.o
+423
drivers/clk/qcom/gpucc-qcm2290.c
+423
drivers/clk/qcom/gpucc-qcm2290.c
···
1
+
// SPDX-License-Identifier: GPL-2.0-only
2
+
/*
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* Copyright (c) 2020, The Linux Foundation. All rights reserved.
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* Copyright (c) 2024, Linaro Limited
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+
*/
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+
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#include <linux/clk-provider.h>
8
+
#include <linux/mod_devicetable.h>
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#include <linux/module.h>
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#include <linux/platform_device.h>
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#include <linux/pm_clock.h>
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#include <linux/pm_runtime.h>
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#include <linux/regmap.h>
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+
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#include <dt-bindings/clock/qcom,qcm2290-gpucc.h>
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+
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#include "clk-alpha-pll.h"
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#include "clk-branch.h"
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#include "clk-rcg.h"
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#include "clk-regmap.h"
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#include "clk-regmap-divider.h"
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#include "clk-regmap-mux.h"
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#include "clk-regmap-phy-mux.h"
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#include "gdsc.h"
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#include "reset.h"
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+
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enum {
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DT_GCC_AHB_CLK,
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DT_BI_TCXO,
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DT_GCC_GPU_GPLL0_CLK_SRC,
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DT_GCC_GPU_GPLL0_DIV_CLK_SRC,
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};
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+
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enum {
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P_BI_TCXO,
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P_GPLL0_OUT_MAIN,
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P_GPLL0_OUT_MAIN_DIV,
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P_GPU_CC_PLL0_2X_DIV_CLK_SRC,
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P_GPU_CC_PLL0_OUT_AUX,
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P_GPU_CC_PLL0_OUT_AUX2,
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P_GPU_CC_PLL0_OUT_MAIN,
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};
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+
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static const struct pll_vco huayra_vco[] = {
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{ 600000000, 3300000000, 0 },
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{ 600000000, 2200000000, 1 },
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};
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+
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static const struct alpha_pll_config gpu_cc_pll0_config = {
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.l = 0x25,
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.config_ctl_val = 0x200d4828,
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.config_ctl_hi_val = 0x6,
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.test_ctl_val = GENMASK(28, 26),
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.test_ctl_hi_val = BIT(14),
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.user_ctl_val = 0xf,
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};
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+
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static struct clk_alpha_pll gpu_cc_pll0 = {
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.offset = 0x0,
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.vco_table = huayra_vco,
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.num_vco = ARRAY_SIZE(huayra_vco),
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.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_HUAYRA_2290],
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.clkr = {
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.hw.init = &(struct clk_init_data){
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.name = "gpu_cc_pll0",
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.parent_data = &(const struct clk_parent_data) {
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.index = DT_BI_TCXO,
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},
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.num_parents = 1,
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.ops = &clk_alpha_pll_huayra_ops,
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},
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},
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};
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+
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static const struct parent_map gpu_cc_parent_map_0[] = {
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{ P_BI_TCXO, 0 },
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{ P_GPU_CC_PLL0_OUT_MAIN, 1 },
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{ P_GPLL0_OUT_MAIN, 5 },
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{ P_GPLL0_OUT_MAIN_DIV, 6 },
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};
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+
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static const struct clk_parent_data gpu_cc_parent_data_0[] = {
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{ .index = DT_BI_TCXO, },
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{ .hw = &gpu_cc_pll0.clkr.hw, },
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{ .index = DT_GCC_GPU_GPLL0_CLK_SRC, },
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{ .index = DT_GCC_GPU_GPLL0_DIV_CLK_SRC, },
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};
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+
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static const struct parent_map gpu_cc_parent_map_1[] = {
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{ P_BI_TCXO, 0 },
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{ P_GPU_CC_PLL0_2X_DIV_CLK_SRC, 1 },
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{ P_GPU_CC_PLL0_OUT_AUX2, 2 },
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{ P_GPU_CC_PLL0_OUT_AUX, 3 },
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{ P_GPLL0_OUT_MAIN, 5 },
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};
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+
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static const struct clk_parent_data gpu_cc_parent_data_1[] = {
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{ .index = DT_BI_TCXO, },
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{ .hw = &gpu_cc_pll0.clkr.hw, },
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{ .hw = &gpu_cc_pll0.clkr.hw, },
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{ .hw = &gpu_cc_pll0.clkr.hw, },
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{ .index = DT_GCC_GPU_GPLL0_CLK_SRC, },
103
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};
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+
105
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static const struct freq_tbl ftbl_gpu_cc_gmu_clk_src[] = {
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F(200000000, P_GPLL0_OUT_MAIN, 3, 0, 0),
107
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{ }
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+
};
109
+
110
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static struct clk_rcg2 gpu_cc_gmu_clk_src = {
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.cmd_rcgr = 0x1120,
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.mnd_width = 0,
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.hid_width = 5,
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.parent_map = gpu_cc_parent_map_0,
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.freq_tbl = ftbl_gpu_cc_gmu_clk_src,
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.clkr.hw.init = &(struct clk_init_data){
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.name = "gpu_cc_gmu_clk_src",
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.parent_data = gpu_cc_parent_data_0,
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.num_parents = ARRAY_SIZE(gpu_cc_parent_data_0),
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.flags = CLK_SET_RATE_PARENT,
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.ops = &clk_rcg2_shared_ops,
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},
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};
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+
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static const struct freq_tbl ftbl_gpu_cc_gx_gfx3d_clk_src[] = {
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F(355200000, P_GPU_CC_PLL0_OUT_AUX, 2, 0, 0),
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F(537600000, P_GPU_CC_PLL0_OUT_AUX2, 2, 0, 0),
128
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F(672000000, P_GPU_CC_PLL0_OUT_AUX2, 2, 0, 0),
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F(844800000, P_GPU_CC_PLL0_OUT_AUX2, 2, 0, 0),
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F(921600000, P_GPU_CC_PLL0_OUT_AUX2, 2, 0, 0),
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F(1017600000, P_GPU_CC_PLL0_OUT_AUX2, 2, 0, 0),
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F(1123200000, P_GPU_CC_PLL0_OUT_AUX2, 2, 0, 0),
133
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{ }
134
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};
135
+
136
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static struct clk_rcg2 gpu_cc_gx_gfx3d_clk_src = {
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.cmd_rcgr = 0x101c,
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.mnd_width = 0,
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.hid_width = 5,
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.parent_map = gpu_cc_parent_map_1,
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.freq_tbl = ftbl_gpu_cc_gx_gfx3d_clk_src,
142
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.clkr.hw.init = &(struct clk_init_data){
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.name = "gpu_cc_gx_gfx3d_clk_src",
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.parent_data = gpu_cc_parent_data_1,
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.num_parents = ARRAY_SIZE(gpu_cc_parent_data_1),
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.flags = CLK_SET_RATE_PARENT,
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.ops = &clk_rcg2_ops,
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},
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};
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+
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static struct clk_branch gpu_cc_ahb_clk = {
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.halt_reg = 0x1078,
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.halt_check = BRANCH_HALT_DELAY,
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.clkr = {
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.enable_reg = 0x1078,
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.enable_mask = BIT(0),
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.hw.init = &(struct clk_init_data){
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.name = "gpu_cc_ahb_clk",
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.flags = CLK_IS_CRITICAL,
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.ops = &clk_branch2_ops,
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},
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},
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};
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+
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static struct clk_branch gpu_cc_crc_ahb_clk = {
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.halt_reg = 0x107c,
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.halt_check = BRANCH_HALT_DELAY,
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.clkr = {
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.enable_reg = 0x107c,
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.enable_mask = BIT(0),
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.hw.init = &(struct clk_init_data){
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.name = "gpu_cc_crc_ahb_clk",
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.ops = &clk_branch2_ops,
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},
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},
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};
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+
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static struct clk_branch gpu_cc_cx_gfx3d_clk = {
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.halt_reg = 0x10a4,
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.halt_check = BRANCH_HALT_DELAY,
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.clkr = {
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.enable_reg = 0x10a4,
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.enable_mask = BIT(0),
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.hw.init = &(struct clk_init_data){
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.name = "gpu_cc_cx_gfx3d_clk",
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.parent_data = &(const struct clk_parent_data){
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.hw = &gpu_cc_gx_gfx3d_clk_src.clkr.hw,
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},
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.num_parents = 1,
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.flags = CLK_SET_RATE_PARENT,
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.ops = &clk_branch2_ops,
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},
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},
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};
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+
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static struct clk_branch gpu_cc_cx_gmu_clk = {
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.halt_reg = 0x1098,
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.halt_check = BRANCH_HALT,
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.clkr = {
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.enable_reg = 0x1098,
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.enable_mask = BIT(0),
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.hw.init = &(struct clk_init_data){
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.name = "gpu_cc_cx_gmu_clk",
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.parent_data = &(const struct clk_parent_data){
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.hw = &gpu_cc_gmu_clk_src.clkr.hw,
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},
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.num_parents = 1,
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.flags = CLK_SET_RATE_PARENT,
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.ops = &clk_branch2_ops,
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},
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},
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};
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+
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static struct clk_branch gpu_cc_cx_snoc_dvm_clk = {
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.halt_reg = 0x108c,
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.halt_check = BRANCH_HALT_DELAY,
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.clkr = {
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.enable_reg = 0x108c,
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.enable_mask = BIT(0),
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.hw.init = &(struct clk_init_data){
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.name = "gpu_cc_cx_snoc_dvm_clk",
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.ops = &clk_branch2_ops,
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},
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},
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};
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+
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static struct clk_branch gpu_cc_cxo_aon_clk = {
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.halt_reg = 0x1004,
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.halt_check = BRANCH_HALT_DELAY,
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.clkr = {
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.enable_reg = 0x1004,
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.enable_mask = BIT(0),
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.hw.init = &(struct clk_init_data){
234
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.name = "gpu_cc_cxo_aon_clk",
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.ops = &clk_branch2_ops,
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},
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},
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};
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+
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static struct clk_branch gpu_cc_cxo_clk = {
241
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.halt_reg = 0x109c,
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.halt_check = BRANCH_HALT,
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.clkr = {
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.enable_reg = 0x109c,
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.enable_mask = BIT(0),
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.hw.init = &(struct clk_init_data){
247
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.name = "gpu_cc_cxo_clk",
248
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.ops = &clk_branch2_ops,
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},
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},
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};
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+
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static struct clk_branch gpu_cc_gx_gfx3d_clk = {
254
+
.halt_reg = 0x1054,
255
+
.halt_check = BRANCH_HALT_DELAY,
256
+
.clkr = {
257
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.enable_reg = 0x1054,
258
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.enable_mask = BIT(0),
259
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.hw.init = &(struct clk_init_data){
260
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.name = "gpu_cc_gx_gfx3d_clk",
261
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.parent_data = &(const struct clk_parent_data){
262
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.hw = &gpu_cc_gx_gfx3d_clk_src.clkr.hw,
263
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},
264
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.num_parents = 1,
265
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.flags = CLK_SET_RATE_PARENT,
266
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.ops = &clk_branch2_ops,
267
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},
268
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},
269
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};
270
+
271
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static struct clk_branch gpu_cc_sleep_clk = {
272
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.halt_reg = 0x1090,
273
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.halt_check = BRANCH_VOTED,
274
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.clkr = {
275
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.enable_reg = 0x1090,
276
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.enable_mask = BIT(0),
277
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.hw.init = &(struct clk_init_data){
278
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.name = "gpu_cc_sleep_clk",
279
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.ops = &clk_branch2_ops,
280
+
},
281
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},
282
+
};
283
+
284
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static struct clk_branch gpu_cc_hlos1_vote_gpu_smmu_clk = {
285
+
.halt_reg = 0x5000,
286
+
.halt_check = BRANCH_VOTED,
287
+
.clkr = {
288
+
.enable_reg = 0x5000,
289
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.enable_mask = BIT(0),
290
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.hw.init = &(struct clk_init_data){
291
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.name = "gpu_cc_hlos1_vote_gpu_smmu_clk",
292
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.ops = &clk_branch2_ops,
293
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},
294
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},
295
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};
296
+
297
+
static struct gdsc gpu_cx_gdsc = {
298
+
.gdscr = 0x106c,
299
+
.gds_hw_ctrl = 0x1540,
300
+
.pd = {
301
+
.name = "gpu_cx_gdsc",
302
+
},
303
+
.pwrsts = PWRSTS_OFF_ON,
304
+
.flags = VOTABLE,
305
+
};
306
+
307
+
static struct gdsc gpu_gx_gdsc = {
308
+
.gdscr = 0x100c,
309
+
.clamp_io_ctrl = 0x1508,
310
+
.resets = (unsigned int []){ GPU_GX_BCR },
311
+
.reset_count = 1,
312
+
.pd = {
313
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.name = "gpu_gx_gdsc",
314
+
},
315
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.parent = &gpu_cx_gdsc.pd,
316
+
.pwrsts = PWRSTS_OFF_ON,
317
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.flags = CLAMP_IO | AON_RESET | SW_RESET,
318
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};
319
+
320
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static struct clk_regmap *gpu_cc_qcm2290_clocks[] = {
321
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[GPU_CC_AHB_CLK] = &gpu_cc_ahb_clk.clkr,
322
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[GPU_CC_CRC_AHB_CLK] = &gpu_cc_crc_ahb_clk.clkr,
323
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[GPU_CC_CX_GFX3D_CLK] = &gpu_cc_cx_gfx3d_clk.clkr,
324
+
[GPU_CC_CX_GMU_CLK] = &gpu_cc_cx_gmu_clk.clkr,
325
+
[GPU_CC_CX_SNOC_DVM_CLK] = &gpu_cc_cx_snoc_dvm_clk.clkr,
326
+
[GPU_CC_CXO_AON_CLK] = &gpu_cc_cxo_aon_clk.clkr,
327
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[GPU_CC_CXO_CLK] = &gpu_cc_cxo_clk.clkr,
328
+
[GPU_CC_GMU_CLK_SRC] = &gpu_cc_gmu_clk_src.clkr,
329
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[GPU_CC_GX_GFX3D_CLK] = &gpu_cc_gx_gfx3d_clk.clkr,
330
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[GPU_CC_GX_GFX3D_CLK_SRC] = &gpu_cc_gx_gfx3d_clk_src.clkr,
331
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[GPU_CC_PLL0] = &gpu_cc_pll0.clkr,
332
+
[GPU_CC_SLEEP_CLK] = &gpu_cc_sleep_clk.clkr,
333
+
[GPU_CC_HLOS1_VOTE_GPU_SMMU_CLK] = &gpu_cc_hlos1_vote_gpu_smmu_clk.clkr,
334
+
};
335
+
336
+
static const struct qcom_reset_map gpu_cc_qcm2290_resets[] = {
337
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[GPU_GX_BCR] = { 0x1008 },
338
+
};
339
+
340
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static struct gdsc *gpu_cc_qcm2290_gdscs[] = {
341
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[GPU_CX_GDSC] = &gpu_cx_gdsc,
342
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[GPU_GX_GDSC] = &gpu_gx_gdsc,
343
+
};
344
+
345
+
static const struct regmap_config gpu_cc_qcm2290_regmap_config = {
346
+
.reg_bits = 32,
347
+
.reg_stride = 4,
348
+
.val_bits = 32,
349
+
.max_register = 0x9000,
350
+
.fast_io = true,
351
+
};
352
+
353
+
354
+
static const struct qcom_cc_desc gpu_cc_qcm2290_desc = {
355
+
.config = &gpu_cc_qcm2290_regmap_config,
356
+
.clks = gpu_cc_qcm2290_clocks,
357
+
.num_clks = ARRAY_SIZE(gpu_cc_qcm2290_clocks),
358
+
.resets = gpu_cc_qcm2290_resets,
359
+
.num_resets = ARRAY_SIZE(gpu_cc_qcm2290_resets),
360
+
.gdscs = gpu_cc_qcm2290_gdscs,
361
+
.num_gdscs = ARRAY_SIZE(gpu_cc_qcm2290_gdscs),
362
+
};
363
+
364
+
static const struct of_device_id gpu_cc_qcm2290_match_table[] = {
365
+
{ .compatible = "qcom,qcm2290-gpucc" },
366
+
{ }
367
+
};
368
+
MODULE_DEVICE_TABLE(of, gpu_cc_qcm2290_match_table);
369
+
370
+
static int gpu_cc_qcm2290_probe(struct platform_device *pdev)
371
+
{
372
+
struct regmap *regmap;
373
+
int ret;
374
+
375
+
regmap = qcom_cc_map(pdev, &gpu_cc_qcm2290_desc);
376
+
if (IS_ERR(regmap))
377
+
return PTR_ERR(regmap);
378
+
379
+
ret = devm_pm_runtime_enable(&pdev->dev);
380
+
if (ret)
381
+
return ret;
382
+
383
+
ret = devm_pm_clk_create(&pdev->dev);
384
+
if (ret)
385
+
return ret;
386
+
387
+
ret = pm_clk_add(&pdev->dev, NULL);
388
+
if (ret < 0) {
389
+
dev_err(&pdev->dev, "failed to acquire ahb clock\n");
390
+
return ret;
391
+
}
392
+
393
+
ret = pm_runtime_resume_and_get(&pdev->dev);
394
+
if (ret)
395
+
return ret;
396
+
397
+
clk_huayra_2290_pll_configure(&gpu_cc_pll0, regmap, &gpu_cc_pll0_config);
398
+
399
+
regmap_update_bits(regmap, 0x1060, BIT(0), BIT(0)); /* GPU_CC_GX_CXO_CLK */
400
+
401
+
ret = qcom_cc_really_probe(&pdev->dev, &gpu_cc_qcm2290_desc, regmap);
402
+
if (ret) {
403
+
dev_err(&pdev->dev, "Failed to register display clock controller\n");
404
+
goto out_pm_runtime_put;
405
+
}
406
+
407
+
out_pm_runtime_put:
408
+
pm_runtime_put_sync(&pdev->dev);
409
+
410
+
return 0;
411
+
}
412
+
413
+
static struct platform_driver gpu_cc_qcm2290_driver = {
414
+
.probe = gpu_cc_qcm2290_probe,
415
+
.driver = {
416
+
.name = "gpucc-qcm2290",
417
+
.of_match_table = gpu_cc_qcm2290_match_table,
418
+
},
419
+
};
420
+
module_platform_driver(gpu_cc_qcm2290_driver);
421
+
422
+
MODULE_DESCRIPTION("QTI QCM2290 GPU clock controller driver");
423
+
MODULE_LICENSE("GPL");