tjh.dev / kernel
Linux kernel mirror (for testing) git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
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Merge tag 'v6.1-next-dts64' of https://git.kernel.org/pub/scm/linux/kernel/git/matthias.bgg/linux into soc/dt

Fix check warnings all over the place.

mt7986:
- Add crypto, I2C and SPI nodes

mt6795:
- Add clock nodes
- Add DMA support for UARTs
- Add MMC nodes
- Add basic support for Sonyx Xperia M5

mt8195:
- Add video enconder node
- Add PCIe support
- Fine tune capacity-dmips-mhz
- Add support for internal and external display port

* tag 'v6.1-next-dts64' of https://git.kernel.org/pub/scm/linux/kernel/git/matthias.bgg/linux: (35 commits)
arm64: dts: mt7986: add spi related device nodes
arm64: dts: mt7986: move wed_pcie node
arm64: dts: mediatek: Add support for MT6795 Sony Xperia M5 smartphone
dt-bindings: arm: mediatek: Add compatible for MT6795 Sony Xperia M5
arm64: dts: mediatek: mt6795: Add support for eMMC/SD/SDIO controllers
arm64: dts: mediatek: mt6795: Add support for APDMA and wire up UART DMAs
arm64: dts: mediatek: mt6795: Replace UART dummy clocks with pericfg
arm64: dts: mediatek: mt6795: Add topckgen, infra, peri clocks/resets
arm64: dts: mediatek: cherry: Add edptx and dptx support
arm64: dts: mediatek: cherry: Add dp-intf ports
arm64: dts: mt8195: Add edptx and dptx nodes
arm64: dts: mt8195: Add dp-intf nodes
arm64: dts: mediatek: mt6797: Fix 26M oscillator unit name
arm64: dts: mediatek: pumpkin-common: Fix devicetree warnings
arm64: dts: mt2712-evb: Fix usb vbus regulators unit names
arm64: dts: mt2712-evb: Fix vproc fixed regulators unit names
arm64: dts: mt2712e: Fix unit address for pinctrl node
arm64: dts: mt2712e: Fix unit_address_vs_reg warning for oscillators
arm64: dts: mt6779: Fix devicetree build warnings
arm64: dts: mt7896a: Fix unit_address_vs_reg warning for oscillator
...

Link: https://lore.kernel.org/r/8933d687-71f0-e9ad-a7c6-2e5a8993463d@gmail.com
Signed-off-by: Arnd Bergmann <arnd@arndb.de>

Arnd Bergmann 8ccf49d7 02946788

+750 -110
+2
Documentation/devicetree/bindings/arm/mediatek.yaml
··· 58 58 - items: 59 59 - enum: 60 60 - mediatek,mt6795-evb 61 + - sony,xperia-m5 61 62 - const: mediatek,mt6795 62 63 - items: 63 64 - enum: ··· 84 83 - const: mediatek,mt7629 85 84 - items: 86 85 - enum: 86 + - bananapi,bpi-r3 87 87 - mediatek,mt7986a-rfb 88 88 - const: mediatek,mt7986a 89 89 - items:
+1
arch/arm64/boot/dts/mediatek/Makefile
··· 3 3 dtb-$(CONFIG_ARCH_MEDIATEK) += mt6755-evb.dtb 4 4 dtb-$(CONFIG_ARCH_MEDIATEK) += mt6779-evb.dtb 5 5 dtb-$(CONFIG_ARCH_MEDIATEK) += mt6795-evb.dtb 6 + dtb-$(CONFIG_ARCH_MEDIATEK) += mt6795-sony-xperia-m5.dtb 6 7 dtb-$(CONFIG_ARCH_MEDIATEK) += mt6797-evb.dtb 7 8 dtb-$(CONFIG_ARCH_MEDIATEK) += mt6797-x20-dev.dtb 8 9 dtb-$(CONFIG_ARCH_MEDIATEK) += mt7622-rfb1.dtb
+6 -6
arch/arm64/boot/dts/mediatek/mt2712-evb.dts
··· 26 26 stdout-path = "serial0:921600n8"; 27 27 }; 28 28 29 - cpus_fixed_vproc0: fixedregulator@0 { 29 + cpus_fixed_vproc0: regulator-vproc-buck0 { 30 30 compatible = "regulator-fixed"; 31 31 regulator-name = "vproc_buck0"; 32 32 regulator-min-microvolt = <1000000>; 33 33 regulator-max-microvolt = <1000000>; 34 34 }; 35 35 36 - cpus_fixed_vproc1: fixedregulator@1 { 36 + cpus_fixed_vproc1: regulator-vproc-buck1 { 37 37 compatible = "regulator-fixed"; 38 38 regulator-name = "vproc_buck1"; 39 39 regulator-min-microvolt = <1000000>; ··· 50 50 id-gpio = <&pio 14 GPIO_ACTIVE_HIGH>; 51 51 }; 52 52 53 - usb_p0_vbus: regulator@2 { 53 + usb_p0_vbus: regulator-usb-p0-vbus { 54 54 compatible = "regulator-fixed"; 55 55 regulator-name = "p0_vbus"; 56 56 regulator-min-microvolt = <5000000>; ··· 59 59 enable-active-high; 60 60 }; 61 61 62 - usb_p1_vbus: regulator@3 { 62 + usb_p1_vbus: regulator-usb-p1-vbus { 63 63 compatible = "regulator-fixed"; 64 64 regulator-name = "p1_vbus"; 65 65 regulator-min-microvolt = <5000000>; ··· 68 68 enable-active-high; 69 69 }; 70 70 71 - usb_p2_vbus: regulator@4 { 71 + usb_p2_vbus: regulator-usb-p2-vbus { 72 72 compatible = "regulator-fixed"; 73 73 regulator-name = "p2_vbus"; 74 74 regulator-min-microvolt = <5000000>; ··· 77 77 enable-active-high; 78 78 }; 79 79 80 - usb_p3_vbus: regulator@5 { 80 + usb_p3_vbus: regulator-usb-p3-vbus { 81 81 compatible = "regulator-fixed"; 82 82 regulator-name = "p3_vbus"; 83 83 regulator-min-microvolt = <5000000>;
+14 -14
arch/arm64/boot/dts/mediatek/mt2712e.dtsi
··· 160 160 #clock-cells = <0>; 161 161 }; 162 162 163 - clk26m: oscillator@0 { 163 + clk26m: oscillator-26m { 164 164 compatible = "fixed-clock"; 165 165 #clock-cells = <0>; 166 166 clock-frequency = <26000000>; 167 167 clock-output-names = "clk26m"; 168 168 }; 169 169 170 - clk32k: oscillator@1 { 170 + clk32k: oscillator-32k { 171 171 compatible = "fixed-clock"; 172 172 #clock-cells = <0>; 173 173 clock-frequency = <32768>; 174 174 clock-output-names = "clk32k"; 175 175 }; 176 176 177 - clkfpc: oscillator@2 { 177 + clkfpc: oscillator-50m { 178 178 compatible = "fixed-clock"; 179 179 #clock-cells = <0>; 180 180 clock-frequency = <50000000>; 181 181 clock-output-names = "clkfpc"; 182 182 }; 183 183 184 - clkaud_ext_i_0: oscillator@3 { 184 + clkaud_ext_i_0: oscillator-aud0 { 185 185 compatible = "fixed-clock"; 186 186 #clock-cells = <0>; 187 187 clock-frequency = <6500000>; 188 188 clock-output-names = "clkaud_ext_i_0"; 189 189 }; 190 190 191 - clkaud_ext_i_1: oscillator@4 { 191 + clkaud_ext_i_1: oscillator-aud1 { 192 192 compatible = "fixed-clock"; 193 193 #clock-cells = <0>; 194 194 clock-frequency = <196608000>; 195 195 clock-output-names = "clkaud_ext_i_1"; 196 196 }; 197 197 198 - clkaud_ext_i_2: oscillator@5 { 198 + clkaud_ext_i_2: oscillator-aud2 { 199 199 compatible = "fixed-clock"; 200 200 #clock-cells = <0>; 201 201 clock-frequency = <180633600>; 202 202 clock-output-names = "clkaud_ext_i_2"; 203 203 }; 204 204 205 - clki2si0_mck_i: oscillator@6 { 205 + clki2si0_mck_i: oscillator-i2s0 { 206 206 compatible = "fixed-clock"; 207 207 #clock-cells = <0>; 208 208 clock-frequency = <30000000>; 209 209 clock-output-names = "clki2si0_mck_i"; 210 210 }; 211 211 212 - clki2si1_mck_i: oscillator@7 { 212 + clki2si1_mck_i: oscillator-i2s1 { 213 213 compatible = "fixed-clock"; 214 214 #clock-cells = <0>; 215 215 clock-frequency = <30000000>; 216 216 clock-output-names = "clki2si1_mck_i"; 217 217 }; 218 218 219 - clki2si2_mck_i: oscillator@8 { 219 + clki2si2_mck_i: oscillator-i2s2 { 220 220 compatible = "fixed-clock"; 221 221 #clock-cells = <0>; 222 222 clock-frequency = <30000000>; 223 223 clock-output-names = "clki2si2_mck_i"; 224 224 }; 225 225 226 - clktdmin_mclk_i: oscillator@9 { 226 + clktdmin_mclk_i: oscillator-mclk { 227 227 compatible = "fixed-clock"; 228 228 #clock-cells = <0>; 229 229 clock-frequency = <30000000>; ··· 266 266 reg = <0 0x10005000 0 0x1000>; 267 267 }; 268 268 269 - pio: pinctrl@10005000 { 269 + pio: pinctrl@1000b000 { 270 270 compatible = "mediatek,mt2712-pinctrl"; 271 271 reg = <0 0x1000b000 0 0x1000>; 272 272 mediatek,pctl-regmap = <&syscfg_pctl_a>; ··· 766 766 interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_LOW>; 767 767 clocks = <&pericfg CLK_PERI_MSDC30_0>, 768 768 <&pericfg CLK_PERI_MSDC50_0_HCLK_EN>, 769 - <&pericfg CLK_PERI_MSDC30_0_QTR_EN>, 770 - <&pericfg CLK_PERI_MSDC50_0_EN>; 771 - clock-names = "source", "hclk", "bus_clk", "source_cg"; 769 + <&pericfg CLK_PERI_MSDC50_0_EN>, 770 + <&pericfg CLK_PERI_MSDC30_0_QTR_EN>; 771 + clock-names = "source", "hclk", "source_cg", "bus_clk"; 772 772 status = "disabled"; 773 773 }; 774 774
+5 -5
arch/arm64/boot/dts/mediatek/mt6779.dtsi
··· 88 88 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW 0>; 89 89 }; 90 90 91 - clk26m: oscillator@0 { 91 + clk26m: oscillator-26m { 92 92 compatible = "fixed-clock"; 93 93 #clock-cells = <0>; 94 94 clock-frequency = <26000000>; 95 95 clock-output-names = "clk26m"; 96 96 }; 97 97 98 - clk32k: oscillator@1 { 98 + clk32k: oscillator-32k { 99 99 compatible = "fixed-clock"; 100 100 #clock-cells = <0>; 101 101 clock-frequency = <32768>; ··· 117 117 compatible = "simple-bus"; 118 118 ranges; 119 119 120 - gic: interrupt-controller@0c000000 { 120 + gic: interrupt-controller@c000000 { 121 121 compatible = "arm,gic-v3"; 122 122 #interrupt-cells = <4>; 123 123 interrupt-parent = <&gic>; ··· 138 138 139 139 }; 140 140 141 - sysirq: intpol-controller@0c53a650 { 141 + sysirq: intpol-controller@c53a650 { 142 142 compatible = "mediatek,mt6779-sysirq", 143 143 "mediatek,mt6577-sysirq"; 144 144 interrupt-controller; ··· 160 160 }; 161 161 162 162 pio: pinctrl@10005000 { 163 - compatible = "mediatek,mt6779-pinctrl", "syscon"; 163 + compatible = "mediatek,mt6779-pinctrl"; 164 164 reg = <0 0x10005000 0 0x1000>, 165 165 <0 0x11c20000 0 0x1000>, 166 166 <0 0x11d10000 0 0x1000>,
+88
arch/arm64/boot/dts/mediatek/mt6795-sony-xperia-m5.dts
··· 1 + // SPDX-License-Identifier: GPL-2.0-only 2 + /* 3 + * Copyright (c) 2022, Collabora Ltd 4 + * Author: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> 5 + */ 6 + 7 + /dts-v1/; 8 + #include "mt6795.dtsi" 9 + 10 + / { 11 + model = "Sony Xperia M5"; 12 + compatible = "sony,xperia-m5", "mediatek,mt6795"; 13 + chassis-type = "handset"; 14 + 15 + aliases { 16 + mmc0 = &mmc0; 17 + mmc1 = &mmc1; 18 + serial0 = &uart0; 19 + serial1 = &uart1; 20 + }; 21 + 22 + memory@40000000 { 23 + device_type = "memory"; 24 + reg = <0 0x40000000 0 0x1e800000>; 25 + }; 26 + 27 + reserved_memory: reserved-memory { 28 + #address-cells = <2>; 29 + #size-cells = <2>; 30 + ranges; 31 + 32 + /* 128 KiB reserved for ARM Trusted Firmware (BL31) */ 33 + bl31_secmon_reserved: secmon@43000000 { 34 + reg = <0 0x43000000 0 0x30000>; 35 + no-map; 36 + }; 37 + 38 + /* preloader and bootloader regions cannot be touched */ 39 + preloader-region@44800000 { 40 + reg = <0 0x44800000 0 0x100000>; 41 + no-map; 42 + }; 43 + 44 + bootloader-region@46000000 { 45 + reg = <0 0x46000000 0 0x400000>; 46 + no-map; 47 + }; 48 + }; 49 + }; 50 + 51 + &pio { 52 + uart0_pins: uart0-pins { 53 + pins-rx { 54 + pinmux = <PINMUX_GPIO113__FUNC_URXD0>; 55 + bias-pull-up; 56 + input-enable; 57 + }; 58 + pins-tx { 59 + pinmux = <PINMUX_GPIO114__FUNC_UTXD0>; 60 + output-high; 61 + }; 62 + }; 63 + 64 + uart2_pins: uart2-pins { 65 + pins-rx { 66 + pinmux = <PINMUX_GPIO31__FUNC_URXD2>; 67 + bias-pull-up; 68 + input-enable; 69 + }; 70 + pins-tx { 71 + pinmux = <PINMUX_GPIO32__FUNC_UTXD2>; 72 + }; 73 + }; 74 + }; 75 + 76 + &uart0 { 77 + status = "okay"; 78 + 79 + pinctrl-names = "default"; 80 + pinctrl-0 = <&uart0_pins>; 81 + }; 82 + 83 + &uart2 { 84 + status = "okay"; 85 + 86 + pinctrl-names = "default"; 87 + pinctrl-0 = <&uart2_pins>; 88 + };
+105 -4
arch/arm64/boot/dts/mediatek/mt6795.dtsi
··· 6 6 7 7 #include <dt-bindings/interrupt-controller/irq.h> 8 8 #include <dt-bindings/interrupt-controller/arm-gic.h> 9 + #include <dt-bindings/clock/mediatek,mt6795-clk.h> 9 10 #include <dt-bindings/pinctrl/mt6795-pinfunc.h> 11 + #include <dt-bindings/reset/mediatek,mt6795-resets.h> 10 12 11 13 / { 12 14 compatible = "mediatek,mt6795"; ··· 194 192 compatible = "simple-bus"; 195 193 ranges; 196 194 195 + topckgen: syscon@10000000 { 196 + compatible = "mediatek,mt6795-topckgen", "syscon"; 197 + reg = <0 0x10000000 0 0x1000>; 198 + #clock-cells = <1>; 199 + }; 200 + 201 + infracfg: syscon@10001000 { 202 + compatible = "mediatek,mt6795-infracfg", "syscon"; 203 + reg = <0 0x10001000 0 0x1000>; 204 + #clock-cells = <1>; 205 + #reset-cells = <1>; 206 + }; 207 + 208 + pericfg: syscon@10003000 { 209 + compatible = "mediatek,mt6795-pericfg", "syscon"; 210 + reg = <0 0x10003000 0 0x1000>; 211 + #clock-cells = <1>; 212 + #reset-cells = <1>; 213 + }; 214 + 197 215 pio: pinctrl@10005000 { 198 216 compatible = "mediatek,mt6795-pinctrl"; 199 217 reg = <0 0x10005000 0 0x1000>, <0 0x1000b000 0 0x1000>; ··· 314 292 "mediatek,mt6577-uart"; 315 293 reg = <0 0x11002000 0 0x400>; 316 294 interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_LOW>; 317 - clocks = <&clk26m>; 295 + clocks = <&pericfg CLK_PERI_UART0_SEL>, <&pericfg CLK_PERI_UART0>; 296 + clock-names = "baud", "bus"; 297 + dmas = <&apdma 0>, <&apdma 1>; 298 + dma-names = "tx", "rx"; 318 299 status = "disabled"; 319 300 }; 320 301 ··· 326 301 "mediatek,mt6577-uart"; 327 302 reg = <0 0x11003000 0 0x400>; 328 303 interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_LOW>; 329 - clocks = <&clk26m>; 304 + clocks = <&pericfg CLK_PERI_UART1_SEL>, <&pericfg CLK_PERI_UART1>; 305 + clock-names = "baud", "bus"; 306 + dmas = <&apdma 2>, <&apdma 3>; 307 + dma-names = "tx", "rx"; 330 308 status = "disabled"; 309 + }; 310 + 311 + apdma: dma-controller@11000380 { 312 + compatible = "mediatek,mt6795-uart-dma", 313 + "mediatek,mt6577-uart-dma"; 314 + reg = <0 0x11000380 0 0x60>, 315 + <0 0x11000400 0 0x60>, 316 + <0 0x11000480 0 0x60>, 317 + <0 0x11000500 0 0x60>, 318 + <0 0x11000580 0 0x60>, 319 + <0 0x11000600 0 0x60>, 320 + <0 0x11000680 0 0x60>, 321 + <0 0x11000700 0 0x60>; 322 + interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_LOW>, 323 + <GIC_SPI 104 IRQ_TYPE_LEVEL_LOW>, 324 + <GIC_SPI 105 IRQ_TYPE_LEVEL_LOW>, 325 + <GIC_SPI 106 IRQ_TYPE_LEVEL_LOW>, 326 + <GIC_SPI 107 IRQ_TYPE_LEVEL_LOW>, 327 + <GIC_SPI 108 IRQ_TYPE_LEVEL_LOW>, 328 + <GIC_SPI 109 IRQ_TYPE_LEVEL_LOW>, 329 + <GIC_SPI 110 IRQ_TYPE_LEVEL_LOW>; 330 + dma-requests = <8>; 331 + clocks = <&pericfg CLK_PERI_AP_DMA>; 332 + clock-names = "apdma"; 333 + mediatek,dma-33bits; 334 + #dma-cells = <1>; 331 335 }; 332 336 333 337 uart2: serial@11004000 { ··· 364 310 "mediatek,mt6577-uart"; 365 311 reg = <0 0x11004000 0 0x400>; 366 312 interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_LOW>; 367 - clocks = <&clk26m>; 313 + clocks = <&pericfg CLK_PERI_UART2_SEL>, <&pericfg CLK_PERI_UART2>; 314 + clock-names = "baud", "bus"; 315 + dmas = <&apdma 4>, <&apdma 5>; 316 + dma-names = "tx", "rx"; 368 317 status = "disabled"; 369 318 }; 370 319 ··· 376 319 "mediatek,mt6577-uart"; 377 320 reg = <0 0x11005000 0 0x400>; 378 321 interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_LOW>; 379 - clocks = <&clk26m>; 322 + clocks = <&pericfg CLK_PERI_UART3_SEL>, <&pericfg CLK_PERI_UART3>; 323 + clock-names = "baud", "bus"; 324 + dmas = <&apdma 6>, <&apdma 7>; 325 + dma-names = "tx", "rx"; 326 + status = "disabled"; 327 + }; 328 + 329 + mmc0: mmc@11230000 { 330 + compatible = "mediatek,mt6795-mmc"; 331 + reg = <0 0x11230000 0 0x1000>; 332 + interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_LOW>; 333 + clocks = <&pericfg CLK_PERI_MSDC30_0>, 334 + <&topckgen CLK_TOP_MSDC50_0_H_SEL>, 335 + <&topckgen CLK_TOP_MSDC50_0_SEL>; 336 + clock-names = "source", "hclk", "source_cg"; 337 + status = "disabled"; 338 + }; 339 + 340 + mmc1: mmc@11240000 { 341 + compatible = "mediatek,mt6795-mmc"; 342 + reg = <0 0x11240000 0 0x1000>; 343 + interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_LOW>; 344 + clocks = <&pericfg CLK_PERI_MSDC30_1>, 345 + <&topckgen CLK_TOP_AXI_SEL>; 346 + clock-names = "source", "hclk"; 347 + status = "disabled"; 348 + }; 349 + 350 + mmc2: mmc@11250000 { 351 + compatible = "mediatek,mt6795-mmc"; 352 + reg = <0 0x11250000 0 0x1000>; 353 + interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_LOW>; 354 + clocks = <&pericfg CLK_PERI_MSDC30_2>, 355 + <&topckgen CLK_TOP_AXI_SEL>; 356 + clock-names = "source", "hclk"; 357 + status = "disabled"; 358 + }; 359 + 360 + mmc3: mmc@11260000 { 361 + compatible = "mediatek,mt6795-mmc"; 362 + reg = <0 0x11260000 0 0x1000>; 363 + interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_LOW>; 364 + clocks = <&pericfg CLK_PERI_MSDC30_3>, 365 + <&topckgen CLK_TOP_AXI_SEL>; 366 + clock-names = "source", "hclk"; 380 367 status = "disabled"; 381 368 }; 382 369 };
+1 -1
arch/arm64/boot/dts/mediatek/mt6797.dtsi
··· 95 95 }; 96 96 }; 97 97 98 - clk26m: oscillator@0 { 98 + clk26m: oscillator-26m { 99 99 compatible = "fixed-clock"; 100 100 #clock-cells = <0>; 101 101 clock-frequency = <26000000>;
-1
arch/arm64/boot/dts/mediatek/mt7622-bananapi-bpi-r64.dts
··· 235 235 bus-width = <4>; 236 236 max-frequency = <50000000>; 237 237 cap-sd-highspeed; 238 - r_smpl = <1>; 239 238 cd-gpios = <&pio 81 GPIO_ACTIVE_LOW>; 240 239 vmmc-supply = <&reg_3p3v>; 241 240 vqmmc-supply = <&reg_3p3v>;
-1
arch/arm64/boot/dts/mediatek/mt7622-rfb1.dts
··· 208 208 bus-width = <4>; 209 209 max-frequency = <50000000>; 210 210 cap-sd-highspeed; 211 - r_smpl = <1>; 212 211 cd-gpios = <&pio 81 GPIO_ACTIVE_LOW>; 213 212 vmmc-supply = <&reg_3p3v>; 214 213 vqmmc-supply = <&reg_3p3v>;
+87 -48
arch/arm64/boot/dts/mediatek/mt7986a-rfb.dts
··· 9 9 10 10 / { 11 11 model = "MediaTek MT7986a RFB"; 12 - compatible = "mediatek,mt7986a-rfb"; 12 + compatible = "mediatek,mt7986a-rfb", "mediatek,mt7986a"; 13 13 14 14 aliases { 15 15 serial0 = &uart0; ··· 23 23 device_type = "memory"; 24 24 reg = <0 0x40000000 0 0x40000000>; 25 25 }; 26 + }; 27 + 28 + &crypto { 29 + status = "okay"; 26 30 }; 27 31 28 32 &eth { ··· 56 52 reg = <31>; 57 53 reset-gpios = <&pio 5 0>; 58 54 }; 55 + }; 56 + 57 + &pio { 58 + spi_flash_pins: spi-flash-pins { 59 + mux { 60 + function = "spi"; 61 + groups = "spi0", "spi0_wp_hold"; 62 + }; 63 + }; 64 + 65 + spic_pins: spic-pins { 66 + mux { 67 + function = "spi"; 68 + groups = "spi1_2"; 69 + }; 70 + }; 71 + 72 + uart1_pins: uart1-pins { 73 + mux { 74 + function = "uart"; 75 + groups = "uart1"; 76 + }; 77 + }; 78 + 79 + uart2_pins: uart2-pins { 80 + mux { 81 + function = "uart"; 82 + groups = "uart2"; 83 + }; 84 + }; 85 + 86 + wf_2g_5g_pins: wf-2g-5g-pins { 87 + mux { 88 + function = "wifi"; 89 + groups = "wf_2g", "wf_5g"; 90 + }; 91 + conf { 92 + pins = "WF0_HB1", "WF0_HB2", "WF0_HB3", "WF0_HB4", 93 + "WF0_HB0", "WF0_HB0_B", "WF0_HB5", "WF0_HB6", 94 + "WF0_HB7", "WF0_HB8", "WF0_HB9", "WF0_HB10", 95 + "WF0_TOP_CLK", "WF0_TOP_DATA", "WF1_HB1", 96 + "WF1_HB2", "WF1_HB3", "WF1_HB4", "WF1_HB0", 97 + "WF1_HB5", "WF1_HB6", "WF1_HB7", "WF1_HB8", 98 + "WF1_TOP_CLK", "WF1_TOP_DATA"; 99 + drive-strength = <4>; 100 + }; 101 + }; 102 + 103 + wf_dbdc_pins: wf-dbdc-pins { 104 + mux { 105 + function = "wifi"; 106 + groups = "wf_dbdc"; 107 + }; 108 + conf { 109 + pins = "WF0_HB1", "WF0_HB2", "WF0_HB3", "WF0_HB4", 110 + "WF0_HB0", "WF0_HB0_B", "WF0_HB5", "WF0_HB6", 111 + "WF0_HB7", "WF0_HB8", "WF0_HB9", "WF0_HB10", 112 + "WF0_TOP_CLK", "WF0_TOP_DATA"; 113 + drive-strength = <4>; 114 + }; 115 + }; 116 + }; 117 + 118 + &spi0 { 119 + pinctrl-names = "default"; 120 + pinctrl-0 = <&spi_flash_pins>; 121 + cs-gpios = <0>, <0>; 122 + status = "okay"; 123 + spi_nand: spi_nand@0 { 124 + compatible = "spi-nand"; 125 + reg = <0>; 126 + spi-max-frequency = <10000000>; 127 + spi-tx-buswidth = <4>; 128 + spi-rx-buswidth = <4>; 129 + }; 130 + }; 131 + 132 + &spi1 { 133 + pinctrl-names = "default"; 134 + pinctrl-0 = <&spic_pins>; 135 + cs-gpios = <0>, <0>; 136 + status = "okay"; 59 137 }; 60 138 61 139 &switch { ··· 206 120 pinctrl-names = "default", "dbdc"; 207 121 pinctrl-0 = <&wf_2g_5g_pins>; 208 122 pinctrl-1 = <&wf_dbdc_pins>; 209 - }; 210 - 211 - &pio { 212 - uart1_pins: uart1-pins { 213 - mux { 214 - function = "uart"; 215 - groups = "uart1"; 216 - }; 217 - }; 218 - 219 - uart2_pins: uart2-pins { 220 - mux { 221 - function = "uart"; 222 - groups = "uart2"; 223 - }; 224 - }; 225 - 226 - wf_2g_5g_pins: wf-2g-5g-pins { 227 - mux { 228 - function = "wifi"; 229 - groups = "wf_2g", "wf_5g"; 230 - }; 231 - conf { 232 - pins = "WF0_HB1", "WF0_HB2", "WF0_HB3", "WF0_HB4", 233 - "WF0_HB0", "WF0_HB0_B", "WF0_HB5", "WF0_HB6", 234 - "WF0_HB7", "WF0_HB8", "WF0_HB9", "WF0_HB10", 235 - "WF0_TOP_CLK", "WF0_TOP_DATA", "WF1_HB1", 236 - "WF1_HB2", "WF1_HB3", "WF1_HB4", "WF1_HB0", 237 - "WF1_HB5", "WF1_HB6", "WF1_HB7", "WF1_HB8", 238 - "WF1_TOP_CLK", "WF1_TOP_DATA"; 239 - drive-strength = <4>; 240 - }; 241 - }; 242 - 243 - wf_dbdc_pins: wf-dbdc-pins { 244 - mux { 245 - function = "wifi"; 246 - groups = "wf_dbdc"; 247 - }; 248 - conf { 249 - pins = "WF0_HB1", "WF0_HB2", "WF0_HB3", "WF0_HB4", 250 - "WF0_HB0", "WF0_HB0_B", "WF0_HB5", "WF0_HB6", 251 - "WF0_HB7", "WF0_HB8", "WF0_HB9", "WF0_HB10", 252 - "WF0_TOP_CLK", "WF0_TOP_DATA"; 253 - drive-strength = <4>; 254 - }; 255 - }; 256 123 };
+66 -8
arch/arm64/boot/dts/mediatek/mt7986a.dtsi
··· 10 10 #include <dt-bindings/reset/mt7986-resets.h> 11 11 12 12 / { 13 + compatible = "mediatek,mt7986a"; 13 14 interrupt-parent = <&gic>; 14 15 #address-cells = <2>; 15 16 #size-cells = <2>; 16 17 17 - clk40m: oscillator@0 { 18 + clk40m: oscillator-40m { 18 19 compatible = "fixed-clock"; 19 20 clock-frequency = <40000000>; 20 21 #clock-cells = <0>; ··· 113 112 #clock-cells = <1>; 114 113 }; 115 114 115 + wed_pcie: wed-pcie@10003000 { 116 + compatible = "mediatek,mt7986-wed-pcie", 117 + "syscon"; 118 + reg = <0 0x10003000 0 0x10>; 119 + }; 120 + 116 121 topckgen: topckgen@1001b000 { 117 122 compatible = "mediatek,mt7986-topckgen", "syscon"; 118 123 reg = <0 0x1001B000 0 0x1000>; ··· 175 168 #clock-cells = <1>; 176 169 }; 177 170 178 - trng: trng@1020f000 { 171 + trng: rng@1020f000 { 179 172 compatible = "mediatek,mt7986-rng", 180 173 "mediatek,mt7623-rng"; 181 174 reg = <0 0x1020f000 0 0x100>; 182 175 clocks = <&infracfg CLK_INFRA_TRNG_CK>; 183 176 clock-names = "rng"; 177 + status = "disabled"; 178 + }; 179 + 180 + crypto: crypto@10320000 { 181 + compatible = "inside-secure,safexcel-eip97"; 182 + reg = <0 0x10320000 0 0x40000>; 183 + interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>, 184 + <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>, 185 + <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>, 186 + <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>; 187 + interrupt-names = "ring0", "ring1", "ring2", "ring3"; 188 + clocks = <&infracfg CLK_INFRA_EIP97_CK>; 189 + clock-names = "infra_eip97_ck"; 190 + assigned-clocks = <&topckgen CLK_TOP_EIP_B_SEL>; 191 + assigned-clock-parents = <&apmixedsys CLK_APMIXED_NET2PLL>; 184 192 status = "disabled"; 185 193 }; 186 194 ··· 240 218 status = "disabled"; 241 219 }; 242 220 221 + i2c0: i2c@11008000 { 222 + compatible = "mediatek,mt7986-i2c"; 223 + reg = <0 0x11008000 0 0x90>, 224 + <0 0x10217080 0 0x80>; 225 + interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>; 226 + clock-div = <5>; 227 + clocks = <&infracfg CLK_INFRA_I2C0_CK>, 228 + <&infracfg CLK_INFRA_AP_DMA_CK>; 229 + clock-names = "main", "dma"; 230 + #address-cells = <1>; 231 + #size-cells = <0>; 232 + status = "disabled"; 233 + }; 234 + 235 + spi0: spi@1100a000 { 236 + compatible = "mediatek,mt7986-spi-ipm", "mediatek,spi-ipm"; 237 + #address-cells = <1>; 238 + #size-cells = <0>; 239 + reg = <0 0x1100a000 0 0x100>; 240 + interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>; 241 + clocks = <&topckgen CLK_TOP_MPLL_D2>, 242 + <&topckgen CLK_TOP_SPI_SEL>, 243 + <&infracfg CLK_INFRA_SPI0_CK>, 244 + <&infracfg CLK_INFRA_SPI0_HCK_CK>; 245 + clock-names = "parent-clk", "sel-clk", "spi-clk", "hclk"; 246 + status = "disabled"; 247 + }; 248 + 249 + spi1: spi@1100b000 { 250 + compatible = "mediatek,mt7986-spi-ipm", "mediatek,spi-ipm"; 251 + #address-cells = <1>; 252 + #size-cells = <0>; 253 + reg = <0 0x1100b000 0 0x100>; 254 + interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>; 255 + clocks = <&topckgen CLK_TOP_MPLL_D2>, 256 + <&topckgen CLK_TOP_SPIM_MST_SEL>, 257 + <&infracfg CLK_INFRA_SPI1_CK>, 258 + <&infracfg CLK_INFRA_SPI1_HCK_CK>; 259 + clock-names = "parent-clk", "sel-clk", "spi-clk", "hclk"; 260 + status = "disabled"; 261 + }; 262 + 243 263 ethsys: syscon@15000000 { 244 264 #address-cells = <1>; 245 265 #size-cells = <1>; ··· 290 226 reg = <0 0x15000000 0 0x1000>; 291 227 #clock-cells = <1>; 292 228 #reset-cells = <1>; 293 - }; 294 - 295 - wed_pcie: wed-pcie@10003000 { 296 - compatible = "mediatek,mt7986-wed-pcie", 297 - "syscon"; 298 - reg = <0 0x10003000 0 0x10>; 299 229 }; 300 230 301 231 wed0: wed@15010000 {
+48 -9
arch/arm64/boot/dts/mediatek/mt7986b-rfb.dts
··· 9 9 10 10 / { 11 11 model = "MediaTek MT7986b RFB"; 12 - compatible = "mediatek,mt7986b-rfb"; 12 + compatible = "mediatek,mt7986b-rfb", "mediatek,mt7986b"; 13 13 14 14 aliases { 15 15 serial0 = &uart0; ··· 25 25 }; 26 26 }; 27 27 28 - &uart0 { 28 + &crypto { 29 29 status = "okay"; 30 30 }; 31 31 ··· 99 99 }; 100 100 }; 101 101 102 - &wifi { 103 - status = "okay"; 104 - pinctrl-names = "default", "dbdc"; 105 - pinctrl-0 = <&wf_2g_5g_pins>; 106 - pinctrl-1 = <&wf_dbdc_pins>; 107 - }; 108 - 109 102 &pio { 103 + spi_flash_pins: spi-flash-pins { 104 + mux { 105 + function = "spi"; 106 + groups = "spi0", "spi0_wp_hold"; 107 + }; 108 + }; 109 + 110 + spic_pins: spic-pins { 111 + mux { 112 + function = "spi"; 113 + groups = "spi1_2"; 114 + }; 115 + }; 116 + 110 117 wf_2g_5g_pins: wf-2g-5g-pins { 111 118 mux { 112 119 function = "wifi"; ··· 144 137 drive-strength = <4>; 145 138 }; 146 139 }; 140 + }; 141 + 142 + &spi0 { 143 + pinctrl-names = "default"; 144 + pinctrl-0 = <&spi_flash_pins>; 145 + cs-gpios = <0>, <0>; 146 + status = "okay"; 147 + spi_nand: spi_nand@0 { 148 + compatible = "spi-nand"; 149 + reg = <0>; 150 + spi-max-frequency = <10000000>; 151 + spi-tx-buswidth = <4>; 152 + spi-rx-buswidth = <4>; 153 + }; 154 + }; 155 + 156 + &spi1 { 157 + pinctrl-names = "default"; 158 + pinctrl-0 = <&spic_pins>; 159 + cs-gpios = <0>, <0>; 160 + status = "okay"; 161 + }; 162 + 163 + &uart0 { 164 + status = "okay"; 165 + }; 166 + 167 + &wifi { 168 + status = "okay"; 169 + pinctrl-names = "default", "dbdc"; 170 + pinctrl-0 = <&wf_2g_5g_pins>; 171 + pinctrl-1 = <&wf_dbdc_pins>; 147 172 };
+3
arch/arm64/boot/dts/mediatek/mt7986b.dtsi
··· 5 5 */ 6 6 7 7 #include "mt7986a.dtsi" 8 + / { 9 + compatible = "mediatek,mt7986b"; 10 + }; 8 11 9 12 &pio { 10 13 compatible = "mediatek,mt7986b-pinctrl";
-6
arch/arm64/boot/dts/mediatek/mt8183-kukui.dtsi
··· 221 221 }; 222 222 }; 223 223 224 - &afe { 225 - i2s3-share = "I2S2"; 226 - i2s0-share = "I2S5"; 227 - }; 228 - 229 224 &auxadc { 230 225 status = "okay"; 231 226 }; ··· 373 378 mmc-pwrseq = <&wifi_pwrseq>; 374 379 bus-width = <4>; 375 380 max-frequency = <200000000>; 376 - drv-type = <2>; 377 381 cap-sd-highspeed; 378 382 sd-uhs-sdr50; 379 383 sd-uhs-sdr104;
+3
arch/arm64/boot/dts/mediatek/mt8186.dtsi
··· 198 198 199 199 l2_0: l2-cache0 { 200 200 compatible = "cache"; 201 + cache-level = <2>; 201 202 next-level-cache = <&l3_0>; 202 203 }; 203 204 204 205 l2_1: l2-cache1 { 205 206 compatible = "cache"; 207 + cache-level = <2>; 206 208 next-level-cache = <&l3_0>; 207 209 }; 208 210 209 211 l3_0: l3-cache { 210 212 compatible = "cache"; 213 + cache-level = <3>; 211 214 }; 212 215 }; 213 216
+3
arch/arm64/boot/dts/mediatek/mt8192.dtsi
··· 169 169 170 170 l2_0: l2-cache0 { 171 171 compatible = "cache"; 172 + cache-level = <2>; 172 173 next-level-cache = <&l3_0>; 173 174 }; 174 175 175 176 l2_1: l2-cache1 { 176 177 compatible = "cache"; 178 + cache-level = <2>; 177 179 next-level-cache = <&l3_0>; 178 180 }; 179 181 180 182 l3_0: l3-cache { 181 183 compatible = "cache"; 184 + cache-level = <3>; 182 185 }; 183 186 184 187 idle-states {
+86
arch/arm64/boot/dts/mediatek/mt8195-cherry.dtsi
··· 120 120 }; 121 121 }; 122 122 123 + &dp_intf0 { 124 + status = "okay"; 125 + 126 + port { 127 + dp_intf0_out: endpoint { 128 + remote-endpoint = <&edp_in>; 129 + }; 130 + }; 131 + }; 132 + 133 + &dp_intf1 { 134 + status = "okay"; 135 + 136 + port { 137 + dp_intf1_out: endpoint { 138 + remote-endpoint = <&dptx_in>; 139 + }; 140 + }; 141 + }; 142 + 143 + &edp_tx { 144 + status = "okay"; 145 + 146 + pinctrl-names = "default"; 147 + pinctrl-0 = <&edptx_pins_default>; 148 + 149 + ports { 150 + #address-cells = <1>; 151 + #size-cells = <0>; 152 + 153 + port@0 { 154 + reg = <0>; 155 + edp_in: endpoint { 156 + remote-endpoint = <&dp_intf0_out>; 157 + }; 158 + }; 159 + 160 + port@1 { 161 + reg = <1>; 162 + edp_out: endpoint { 163 + data-lanes = <0 1 2 3>; 164 + }; 165 + }; 166 + }; 167 + }; 168 + 169 + &dp_tx { 170 + status = "okay"; 171 + 172 + pinctrl-names = "default"; 173 + pinctrl-0 = <&dptx_pin>; 174 + 175 + ports { 176 + #address-cells = <1>; 177 + #size-cells = <0>; 178 + 179 + port@0 { 180 + reg = <0>; 181 + dptx_in: endpoint { 182 + remote-endpoint = <&dp_intf1_out>; 183 + }; 184 + }; 185 + 186 + port@1 { 187 + reg = <1>; 188 + dptx_out: endpoint { 189 + data-lanes = <0 1 2 3>; 190 + }; 191 + }; 192 + }; 193 + }; 194 + 123 195 &i2c0 { 124 196 status = "okay"; 125 197 ··· 548 476 pinmux = <PINMUX_GPIO4__FUNC_GPIO4>; 549 477 bias-pull-up = <MTK_PUPD_SET_R1R0_01>; 550 478 input-enable; 479 + }; 480 + }; 481 + 482 + edptx_pins_default: edptx-default-pins { 483 + pins-cmd-dat { 484 + pinmux = <PINMUX_GPIO7__FUNC_EDP_TX_HPD>; 485 + bias-pull-up; 486 + }; 487 + }; 488 + 489 + dptx_pin: dptx-default-pins { 490 + pins-cmd-dat { 491 + pinmux = <PINMUX_GPIO18__FUNC_DP_TX_HPD>; 492 + bias-pull-up; 551 493 }; 552 494 }; 553 495
+229 -4
arch/arm64/boot/dts/mediatek/mt8195.dtsi
··· 13 13 #include <dt-bindings/phy/phy.h> 14 14 #include <dt-bindings/pinctrl/mt8195-pinfunc.h> 15 15 #include <dt-bindings/power/mt8195-power.h> 16 + #include <dt-bindings/reset/mt8195-resets.h> 16 17 17 18 / { 18 19 compatible = "mediatek,mt8195"; ··· 37 36 enable-method = "psci"; 38 37 performance-domains = <&performance 0>; 39 38 clock-frequency = <1701000000>; 40 - capacity-dmips-mhz = <578>; 39 + capacity-dmips-mhz = <308>; 41 40 cpu-idle-states = <&cpu_off_l &cluster_off_l>; 42 41 next-level-cache = <&l2_0>; 43 42 #cooling-cells = <2>; ··· 50 49 enable-method = "psci"; 51 50 performance-domains = <&performance 0>; 52 51 clock-frequency = <1701000000>; 53 - capacity-dmips-mhz = <578>; 52 + capacity-dmips-mhz = <308>; 54 53 cpu-idle-states = <&cpu_off_l &cluster_off_l>; 55 54 next-level-cache = <&l2_0>; 56 55 #cooling-cells = <2>; ··· 63 62 enable-method = "psci"; 64 63 performance-domains = <&performance 0>; 65 64 clock-frequency = <1701000000>; 66 - capacity-dmips-mhz = <578>; 65 + capacity-dmips-mhz = <308>; 67 66 cpu-idle-states = <&cpu_off_l &cluster_off_l>; 68 67 next-level-cache = <&l2_0>; 69 68 #cooling-cells = <2>; ··· 76 75 enable-method = "psci"; 77 76 performance-domains = <&performance 0>; 78 77 clock-frequency = <1701000000>; 79 - capacity-dmips-mhz = <578>; 78 + capacity-dmips-mhz = <308>; 80 79 cpu-idle-states = <&cpu_off_l &cluster_off_l>; 81 80 next-level-cache = <&l2_0>; 82 81 #cooling-cells = <2>; ··· 214 213 215 214 l2_0: l2-cache0 { 216 215 compatible = "cache"; 216 + cache-level = <2>; 217 217 next-level-cache = <&l3_0>; 218 218 }; 219 219 220 220 l2_1: l2-cache1 { 221 221 compatible = "cache"; 222 + cache-level = <2>; 222 223 next-level-cache = <&l3_0>; 223 224 }; 224 225 225 226 l3_0: l3-cache { 226 227 compatible = "cache"; 228 + cache-level = <3>; 227 229 }; 228 230 }; 229 231 ··· 1186 1182 status = "disabled"; 1187 1183 }; 1188 1184 1185 + pcie0: pcie@112f0000 { 1186 + compatible = "mediatek,mt8195-pcie", 1187 + "mediatek,mt8192-pcie"; 1188 + device_type = "pci"; 1189 + #address-cells = <3>; 1190 + #size-cells = <2>; 1191 + reg = <0 0x112f0000 0 0x4000>; 1192 + reg-names = "pcie-mac"; 1193 + interrupts = <GIC_SPI 791 IRQ_TYPE_LEVEL_HIGH 0>; 1194 + bus-range = <0x00 0xff>; 1195 + ranges = <0x81000000 0 0x20000000 1196 + 0x0 0x20000000 0 0x200000>, 1197 + <0x82000000 0 0x20200000 1198 + 0x0 0x20200000 0 0x3e00000>; 1199 + 1200 + iommu-map = <0 &iommu_infra IOMMU_PORT_INFRA_PCIE0 0x2>; 1201 + iommu-map-mask = <0x0>; 1202 + 1203 + clocks = <&infracfg_ao CLK_INFRA_AO_PCIE_PL_P_250M_P0>, 1204 + <&infracfg_ao CLK_INFRA_AO_PCIE_TL_26M>, 1205 + <&infracfg_ao CLK_INFRA_AO_PCIE_TL_96M>, 1206 + <&infracfg_ao CLK_INFRA_AO_PCIE_TL_32K>, 1207 + <&infracfg_ao CLK_INFRA_AO_PCIE_PERI_26M>, 1208 + <&pericfg_ao CLK_PERI_AO_PCIE_P0_MEM>; 1209 + clock-names = "pl_250m", "tl_26m", "tl_96m", 1210 + "tl_32k", "peri_26m", "peri_mem"; 1211 + assigned-clocks = <&topckgen CLK_TOP_TL>; 1212 + assigned-clock-parents = <&topckgen CLK_TOP_MAINPLL_D4_D4>; 1213 + 1214 + phys = <&pciephy>; 1215 + phy-names = "pcie-phy"; 1216 + 1217 + power-domains = <&spm MT8195_POWER_DOMAIN_PCIE_MAC_P0>; 1218 + 1219 + resets = <&infracfg_ao MT8195_INFRA_RST2_PCIE_P0_SWRST>; 1220 + reset-names = "mac"; 1221 + 1222 + #interrupt-cells = <1>; 1223 + interrupt-map-mask = <0 0 0 7>; 1224 + interrupt-map = <0 0 0 1 &pcie_intc0 0>, 1225 + <0 0 0 2 &pcie_intc0 1>, 1226 + <0 0 0 3 &pcie_intc0 2>, 1227 + <0 0 0 4 &pcie_intc0 3>; 1228 + status = "disabled"; 1229 + 1230 + pcie_intc0: interrupt-controller { 1231 + interrupt-controller; 1232 + #address-cells = <0>; 1233 + #interrupt-cells = <1>; 1234 + }; 1235 + }; 1236 + 1237 + pcie1: pcie@112f8000 { 1238 + compatible = "mediatek,mt8195-pcie", 1239 + "mediatek,mt8192-pcie"; 1240 + device_type = "pci"; 1241 + #address-cells = <3>; 1242 + #size-cells = <2>; 1243 + reg = <0 0x112f8000 0 0x4000>; 1244 + reg-names = "pcie-mac"; 1245 + interrupts = <GIC_SPI 792 IRQ_TYPE_LEVEL_HIGH 0>; 1246 + bus-range = <0x00 0xff>; 1247 + ranges = <0x81000000 0 0x24000000 1248 + 0x0 0x24000000 0 0x200000>, 1249 + <0x82000000 0 0x24200000 1250 + 0x0 0x24200000 0 0x3e00000>; 1251 + 1252 + iommu-map = <0 &iommu_infra IOMMU_PORT_INFRA_PCIE1 0x2>; 1253 + iommu-map-mask = <0x0>; 1254 + 1255 + clocks = <&infracfg_ao CLK_INFRA_AO_PCIE_PL_P_250M_P1>, 1256 + <&clk26m>, 1257 + <&infracfg_ao CLK_INFRA_AO_PCIE_TL_96M>, 1258 + <&clk26m>, 1259 + <&infracfg_ao CLK_INFRA_AO_PCIE_PERI_26M>, 1260 + /* Designer has connect pcie1 with peri_mem_p0 clock */ 1261 + <&pericfg_ao CLK_PERI_AO_PCIE_P0_MEM>; 1262 + clock-names = "pl_250m", "tl_26m", "tl_96m", 1263 + "tl_32k", "peri_26m", "peri_mem"; 1264 + assigned-clocks = <&topckgen CLK_TOP_TL_P1>; 1265 + assigned-clock-parents = <&topckgen CLK_TOP_MAINPLL_D4_D4>; 1266 + 1267 + phys = <&u3port1 PHY_TYPE_PCIE>; 1268 + phy-names = "pcie-phy"; 1269 + power-domains = <&spm MT8195_POWER_DOMAIN_PCIE_MAC_P1>; 1270 + 1271 + resets = <&infracfg_ao MT8195_INFRA_RST2_PCIE_P1_SWRST>; 1272 + reset-names = "mac"; 1273 + 1274 + #interrupt-cells = <1>; 1275 + interrupt-map-mask = <0 0 0 7>; 1276 + interrupt-map = <0 0 0 1 &pcie_intc1 0>, 1277 + <0 0 0 2 &pcie_intc1 1>, 1278 + <0 0 0 3 &pcie_intc1 2>, 1279 + <0 0 0 4 &pcie_intc1 3>; 1280 + status = "disabled"; 1281 + 1282 + pcie_intc1: interrupt-controller { 1283 + interrupt-controller; 1284 + #address-cells = <0>; 1285 + #interrupt-cells = <1>; 1286 + }; 1287 + }; 1288 + 1189 1289 nor_flash: spi@1132c000 { 1190 1290 compatible = "mediatek,mt8195-nor", 1191 1291 "mediatek,mt8173-nor"; ··· 1348 1240 u2_intr_p3: usb2-intr-p3@189,2 { 1349 1241 reg = <0x189 0x2>; 1350 1242 bits = <7 5>; 1243 + }; 1244 + pciephy_rx_ln1: pciephy-rx-ln1@190,1 { 1245 + reg = <0x190 0x1>; 1246 + bits = <0 4>; 1247 + }; 1248 + pciephy_tx_ln1_nmos: pciephy-tx-ln1-nmos@190,2 { 1249 + reg = <0x190 0x1>; 1250 + bits = <4 4>; 1251 + }; 1252 + pciephy_tx_ln1_pmos: pciephy-tx-ln1-pmos@191,1 { 1253 + reg = <0x191 0x1>; 1254 + bits = <0 4>; 1255 + }; 1256 + pciephy_rx_ln0: pciephy-rx-ln0@191,2 { 1257 + reg = <0x191 0x1>; 1258 + bits = <4 4>; 1259 + }; 1260 + pciephy_tx_ln0_nmos: pciephy-tx-ln0-nmos@192,1 { 1261 + reg = <0x192 0x1>; 1262 + bits = <0 4>; 1263 + }; 1264 + pciephy_tx_ln0_pmos: pciephy-tx-ln0-pmos@192,2 { 1265 + reg = <0x192 0x1>; 1266 + bits = <4 4>; 1267 + }; 1268 + pciephy_glb_intr: pciephy-glb-intr@193 { 1269 + reg = <0x193 0x1>; 1270 + bits = <0 4>; 1271 + }; 1272 + dp_calibration: dp-data@1ac { 1273 + reg = <0x1ac 0x10>; 1351 1274 }; 1352 1275 }; 1353 1276 ··· 1598 1459 nvmem-cell-names = "intr", "rx_imp", "tx_imp"; 1599 1460 #phy-cells = <1>; 1600 1461 }; 1462 + }; 1463 + 1464 + pciephy: phy@11e80000 { 1465 + compatible = "mediatek,mt8195-pcie-phy"; 1466 + reg = <0 0x11e80000 0 0x10000>; 1467 + reg-names = "sif"; 1468 + nvmem-cells = <&pciephy_glb_intr>, <&pciephy_tx_ln0_pmos>, 1469 + <&pciephy_tx_ln0_nmos>, <&pciephy_rx_ln0>, 1470 + <&pciephy_tx_ln1_pmos>, <&pciephy_tx_ln1_nmos>, 1471 + <&pciephy_rx_ln1>; 1472 + nvmem-cell-names = "glb_intr", "tx_ln0_pmos", 1473 + "tx_ln0_nmos", "rx_ln0", 1474 + "tx_ln1_pmos", "tx_ln1_nmos", 1475 + "rx_ln1"; 1476 + power-domains = <&spm MT8195_POWER_DOMAIN_PCIE_PHY>; 1477 + #phy-cells = <0>; 1478 + status = "disabled"; 1601 1479 }; 1602 1480 1603 1481 ufsphy: ufs-phy@11fa0000 { ··· 2115 1959 power-domains = <&spm MT8195_POWER_DOMAIN_VENC>; 2116 1960 }; 2117 1961 1962 + venc: video-codec@1a020000 { 1963 + compatible = "mediatek,mt8195-vcodec-enc"; 1964 + reg = <0 0x1a020000 0 0x10000>; 1965 + iommus = <&iommu_vdo M4U_PORT_L19_VENC_RCPU>, 1966 + <&iommu_vdo M4U_PORT_L19_VENC_REC>, 1967 + <&iommu_vdo M4U_PORT_L19_VENC_BSDMA>, 1968 + <&iommu_vdo M4U_PORT_L19_VENC_SV_COMV>, 1969 + <&iommu_vdo M4U_PORT_L19_VENC_RD_COMV>, 1970 + <&iommu_vdo M4U_PORT_L19_VENC_CUR_LUMA>, 1971 + <&iommu_vdo M4U_PORT_L19_VENC_CUR_CHROMA>, 1972 + <&iommu_vdo M4U_PORT_L19_VENC_REF_LUMA>, 1973 + <&iommu_vdo M4U_PORT_L19_VENC_REF_CHROMA>; 1974 + interrupts = <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH 0>; 1975 + mediatek,scp = <&scp>; 1976 + clocks = <&vencsys CLK_VENC_VENC>; 1977 + clock-names = "venc_sel"; 1978 + assigned-clocks = <&topckgen CLK_TOP_VENC>; 1979 + assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL_D4>; 1980 + power-domains = <&spm MT8195_POWER_DOMAIN_VENC>; 1981 + #address-cells = <2>; 1982 + #size-cells = <2>; 1983 + dma-ranges = <0x1 0x0 0x0 0x40000000 0x0 0xfff00000>; 1984 + }; 1985 + 2118 1986 vencsys_core1: clock-controller@1b000000 { 2119 1987 compatible = "mediatek,mt8195-vencsys_core1"; 2120 1988 reg = <0 0x1b000000 0 0x1000>; ··· 2247 2067 mediatek,gce-client-reg = <&gce0 SUBSYS_1c01XXXX 0x4000 0x1000>; 2248 2068 }; 2249 2069 2070 + dp_intf0: dp-intf@1c015000 { 2071 + compatible = "mediatek,mt8195-dp-intf"; 2072 + reg = <0 0x1c015000 0 0x1000>; 2073 + interrupts = <GIC_SPI 657 IRQ_TYPE_LEVEL_HIGH 0>; 2074 + clocks = <&vdosys0 CLK_VDO0_DP_INTF0>, 2075 + <&vdosys0 CLK_VDO0_DP_INTF0_DP_INTF>, 2076 + <&apmixedsys CLK_APMIXED_TVDPLL1>; 2077 + clock-names = "engine", "pixel", "pll"; 2078 + status = "disabled"; 2079 + }; 2080 + 2250 2081 mutex: mutex@1c016000 { 2251 2082 compatible = "mediatek,mt8195-disp-mutex"; 2252 2083 reg = <0 0x1c016000 0 0x1000>; ··· 2345 2154 <&vppsys0 CLK_VPP0_GALS_VDO0_VDO1_VENCSYS_CORE1>; 2346 2155 clock-names = "apb", "smi", "gals"; 2347 2156 power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>; 2157 + }; 2158 + 2159 + dp_intf1: dp-intf@1c113000 { 2160 + compatible = "mediatek,mt8195-dp-intf"; 2161 + reg = <0 0x1c113000 0 0x1000>; 2162 + interrupts = <GIC_SPI 513 IRQ_TYPE_LEVEL_HIGH 0>; 2163 + power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>; 2164 + clocks = <&vdosys1 CLK_VDO1_DP_INTF0_MM>, 2165 + <&vdosys1 CLK_VDO1_DPINTF>, 2166 + <&apmixedsys CLK_APMIXED_TVDPLL2>; 2167 + clock-names = "engine", "pixel", "pll"; 2168 + status = "disabled"; 2169 + }; 2170 + 2171 + edp_tx: edp-tx@1c500000 { 2172 + compatible = "mediatek,mt8195-edp-tx"; 2173 + reg = <0 0x1c500000 0 0x8000>; 2174 + nvmem-cells = <&dp_calibration>; 2175 + nvmem-cell-names = "dp_calibration_data"; 2176 + power-domains = <&spm MT8195_POWER_DOMAIN_EPD_TX>; 2177 + interrupts = <GIC_SPI 676 IRQ_TYPE_LEVEL_HIGH 0>; 2178 + max-linkrate-mhz = <8100>; 2179 + status = "disabled"; 2180 + }; 2181 + 2182 + dp_tx: dp-tx@1c600000 { 2183 + compatible = "mediatek,mt8195-dp-tx"; 2184 + reg = <0 0x1c600000 0 0x8000>; 2185 + nvmem-cells = <&dp_calibration>; 2186 + nvmem-cell-names = "dp_calibration_data"; 2187 + power-domains = <&spm MT8195_POWER_DOMAIN_DP_TX>; 2188 + interrupts = <GIC_SPI 458 IRQ_TYPE_LEVEL_HIGH 0>; 2189 + max-linkrate-mhz = <8100>; 2190 + status = "disabled"; 2348 2191 }; 2349 2192 }; 2350 2193 };
+3 -3
arch/arm64/boot/dts/mediatek/pumpkin-common.dtsi
··· 17 17 }; 18 18 19 19 firmware { 20 - optee: optee@4fd00000 { 20 + optee: optee { 21 21 compatible = "linaro,optee-tz"; 22 22 method = "smc"; 23 23 }; ··· 209 209 }; 210 210 }; 211 211 212 - i2c0_pins_a: i2c0@0 { 212 + i2c0_pins_a: i2c0 { 213 213 pins1 { 214 214 pinmux = <MT8516_PIN_58_SDA0__FUNC_SDA0_0>, 215 215 <MT8516_PIN_59_SCL0__FUNC_SCL0_0>; ··· 217 217 }; 218 218 }; 219 219 220 - i2c2_pins_a: i2c2@0 { 220 + i2c2_pins_a: i2c2 { 221 221 pins1 { 222 222 pinmux = <MT8516_PIN_60_SDA2__FUNC_SDA2_0>, 223 223 <MT8516_PIN_61_SCL2__FUNC_SCL2_0>;