Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
Merge tag 'renesas-dts-for-v6.13-tag2' of https://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-devel into soc/dt
Renesas DTS updates for v6.13 (take two)
- Add a CPU Operating Performance Points table for the RZ/V2H SoC,
- Add Battery Backup Function (VBATTB) and RTC support for the RZ/G3S
SoC and the RZ/G3S SMARC SoM,
- Add DMAC support for MMC on the RZ/A1H SoC and the Genmai
development board,
- Miscellaneous fixes and improvements.
* tag 'renesas-dts-for-v6.13-tag2' of https://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-devel:
arm64: dts: renesas: rzg3s-smarc-som: Enable RTC
arm64: dts: renesas: rzg3s-smarc-som: Enable VBATTB
arm64: dts: renesas: r9a08g045: Add RTC node
arm64: dts: renesas: r9a08g045: Add VBATTB node
arm64: dts: renesas: white-hawk-cpu-common: Add pin control for DSI-eDP IRQ
ARM: dts: renesas: r7s72100: Add DMA support to MMCIF
ARM: dts: renesas: r7s72100: Add DMAC node
arm64: dts: renesas: hihope: Drop #sound-dai-cells
dt-bindings: clock: renesas,r9a08g045-vbattb: Document VBATTB
dt-bindings: clock: r9a08g045-cpg: Add power domain ID for RTC
arm64: dts: renesas: r9a09g057: Add OPP table
Link: https://lore.kernel.org/r/cover.1730726155.git.geert+renesas@glider.be
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
+230
-6
+84
Documentation/devicetree/bindings/clock/renesas,r9a08g045-vbattb.yaml
+84
Documentation/devicetree/bindings/clock/renesas,r9a08g045-vbattb.yaml
···
1
+
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2
+
%YAML 1.2
3
+
---
4
+
$id: http://devicetree.org/schemas/clock/renesas,r9a08g045-vbattb.yaml#
5
+
$schema: http://devicetree.org/meta-schemas/core.yaml#
6
+
7
+
title: Renesas Battery Backup Function (VBATTB)
8
+
9
+
description:
10
+
Renesas VBATTB is an always on powered module (backed by battery) which
11
+
controls the RTC clock (VBATTCLK), tamper detection logic and a small
12
+
general usage memory (128B).
13
+
14
+
maintainers:
15
+
- Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com>
16
+
17
+
properties:
18
+
compatible:
19
+
const: renesas,r9a08g045-vbattb
20
+
21
+
reg:
22
+
maxItems: 1
23
+
24
+
interrupts:
25
+
items:
26
+
- description: tamper detector interrupt
27
+
28
+
clocks:
29
+
items:
30
+
- description: VBATTB module clock
31
+
- description: RTC input clock (crystal or external clock device)
32
+
33
+
clock-names:
34
+
items:
35
+
- const: bclk
36
+
- const: rtx
37
+
38
+
'#clock-cells':
39
+
const: 1
40
+
41
+
power-domains:
42
+
maxItems: 1
43
+
44
+
resets:
45
+
items:
46
+
- description: VBATTB module reset
47
+
48
+
quartz-load-femtofarads:
49
+
description: load capacitance of the on board crystal
50
+
enum: [ 4000, 7000, 9000, 12500 ]
51
+
default: 4000
52
+
53
+
required:
54
+
- compatible
55
+
- reg
56
+
- interrupts
57
+
- clocks
58
+
- clock-names
59
+
- '#clock-cells'
60
+
- power-domains
61
+
- resets
62
+
63
+
additionalProperties: false
64
+
65
+
examples:
66
+
- |
67
+
#include <dt-bindings/clock/r9a08g045-cpg.h>
68
+
#include <dt-bindings/clock/renesas,r9a08g045-vbattb.h>
69
+
#include <dt-bindings/interrupt-controller/arm-gic.h>
70
+
#include <dt-bindings/interrupt-controller/irq.h>
71
+
72
+
clock-controller@1005c000 {
73
+
compatible = "renesas,r9a08g045-vbattb";
74
+
reg = <0x1005c000 0x1000>;
75
+
interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
76
+
clocks = <&cpg CPG_MOD R9A08G045_VBAT_BCLK>, <&vbattb_xtal>;
77
+
clock-names = "bclk", "rtx";
78
+
assigned-clocks = <&vbattb VBATTB_MUX>;
79
+
assigned-clock-parents = <&vbattb VBATTB_XC>;
80
+
#clock-cells = <1>;
81
+
power-domains = <&cpg>;
82
+
resets = <&cpg R9A08G045_VBAT_BRESETN>;
83
+
quartz-load-femtofarads = <12500>;
84
+
};
+33
arch/arm/boot/dts/renesas/r7s72100.dtsi
+33
arch/arm/boot/dts/renesas/r7s72100.dtsi
···
332
332
<GIC_SPI 269 IRQ_TYPE_LEVEL_HIGH>,
333
333
<GIC_SPI 267 IRQ_TYPE_LEVEL_HIGH>;
334
334
clocks = <&mstp8_clks R7S72100_CLK_MMCIF>;
335
+
dmas = <&dmac 0x2cc9>, <&dmac 0x2cca>;
336
+
dma-names = "tx", "rx";
335
337
power-domains = <&cpg_clocks>;
336
338
status = "disabled";
337
339
};
···
368
366
cap-sd-highspeed;
369
367
cap-sdio-irq;
370
368
status = "disabled";
369
+
};
370
+
371
+
dmac: dma-controller@e8200000 {
372
+
compatible = "renesas,r7s72100-dmac",
373
+
"renesas,rz-dmac";
374
+
reg = <0xe8200000 0x1000>,
375
+
<0xfcfe1000 0x20>;
376
+
interrupts = <GIC_SPI 25 IRQ_TYPE_EDGE_RISING>,
377
+
<GIC_SPI 9 IRQ_TYPE_EDGE_RISING>,
378
+
<GIC_SPI 10 IRQ_TYPE_EDGE_RISING>,
379
+
<GIC_SPI 11 IRQ_TYPE_EDGE_RISING>,
380
+
<GIC_SPI 12 IRQ_TYPE_EDGE_RISING>,
381
+
<GIC_SPI 13 IRQ_TYPE_EDGE_RISING>,
382
+
<GIC_SPI 14 IRQ_TYPE_EDGE_RISING>,
383
+
<GIC_SPI 15 IRQ_TYPE_EDGE_RISING>,
384
+
<GIC_SPI 16 IRQ_TYPE_EDGE_RISING>,
385
+
<GIC_SPI 17 IRQ_TYPE_EDGE_RISING>,
386
+
<GIC_SPI 18 IRQ_TYPE_EDGE_RISING>,
387
+
<GIC_SPI 19 IRQ_TYPE_EDGE_RISING>,
388
+
<GIC_SPI 20 IRQ_TYPE_EDGE_RISING>,
389
+
<GIC_SPI 21 IRQ_TYPE_EDGE_RISING>,
390
+
<GIC_SPI 22 IRQ_TYPE_EDGE_RISING>,
391
+
<GIC_SPI 23 IRQ_TYPE_EDGE_RISING>,
392
+
<GIC_SPI 24 IRQ_TYPE_EDGE_RISING>;
393
+
interrupt-names = "error",
394
+
"ch0", "ch1", "ch2", "ch3",
395
+
"ch4", "ch5", "ch6", "ch7",
396
+
"ch8", "ch9", "ch10", "ch11",
397
+
"ch12", "ch13", "ch14", "ch15";
398
+
#dma-cells = <1>;
399
+
dma-channels = <16>;
371
400
};
372
401
373
402
gic: interrupt-controller@e8201000 {
-3
arch/arm64/boot/dts/renesas/hihope-rev2.dtsi
-3
arch/arm64/boot/dts/renesas/hihope-rev2.dtsi
-3
arch/arm64/boot/dts/renesas/hihope-rev4.dtsi
-3
arch/arm64/boot/dts/renesas/hihope-rev4.dtsi
+34
arch/arm64/boot/dts/renesas/r9a08g045.dtsi
+34
arch/arm64/boot/dts/renesas/r9a08g045.dtsi
···
7
7
8
8
#include <dt-bindings/interrupt-controller/arm-gic.h>
9
9
#include <dt-bindings/clock/r9a08g045-cpg.h>
10
+
#include <dt-bindings/clock/renesas,r9a08g045-vbattb.h>
10
11
11
12
/ {
12
13
compatible = "renesas,r9a08g045";
···
70
69
clock-names = "fck";
71
70
power-domains = <&cpg>;
72
71
resets = <&cpg R9A08G045_SCIF0_RST_SYSTEM_N>;
72
+
status = "disabled";
73
+
};
74
+
75
+
rtc: rtc@1004ec00 {
76
+
compatible = "renesas,r9a08g045-rtca3", "renesas,rz-rtca3";
77
+
reg = <0 0x1004ec00 0 0x400>;
78
+
interrupts = <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>,
79
+
<GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>,
80
+
<GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>;
81
+
interrupt-names = "alarm", "period", "carry";
82
+
clocks = <&cpg CPG_MOD R9A08G045_VBAT_BCLK>, <&vbattb VBATTB_VBATTCLK>;
83
+
clock-names = "bus", "counter";
84
+
power-domains = <&cpg>;
85
+
resets = <&cpg R9A08G045_VBAT_BRESETN>;
86
+
status = "disabled";
87
+
};
88
+
89
+
vbattb: clock-controller@1005c000 {
90
+
compatible = "renesas,r9a08g045-vbattb";
91
+
reg = <0 0x1005c000 0 0x1000>;
92
+
interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
93
+
clocks = <&cpg CPG_MOD R9A08G045_VBAT_BCLK>, <&vbattb_xtal>;
94
+
clock-names = "bclk", "rtx";
95
+
#clock-cells = <1>;
96
+
power-domains = <&cpg>;
97
+
resets = <&cpg R9A08G045_VBAT_BRESETN>;
73
98
status = "disabled";
74
99
};
75
100
···
451
424
<&gic GIC_PPI 12 IRQ_TYPE_LEVEL_LOW>;
452
425
interrupt-names = "sec-phys", "phys", "virt", "hyp-phys",
453
426
"hyp-virt";
427
+
};
428
+
429
+
vbattb_xtal: vbattb-xtal {
430
+
compatible = "fixed-clock";
431
+
#clock-cells = <0>;
432
+
/* This value must be overridden by the board. */
433
+
clock-frequency = <0>;
454
434
};
455
435
};
+41
arch/arm64/boot/dts/renesas/r9a09g057.dtsi
+41
arch/arm64/boot/dts/renesas/r9a09g057.dtsi
···
20
20
clock-frequency = <0>;
21
21
};
22
22
23
+
/*
24
+
* The default cluster table is based on the assumption that the PLLCA55 clock
25
+
* frequency is set to 1.7GHz. The PLLCA55 clock frequency can be set to
26
+
* 1.7/1.6/1.5/1.1 GHz based on the BOOTPLLCA_0/1 pins (and additionally can be
27
+
* clocked to 1.8GHz as well). The table below should be overridden in the board
28
+
* DTS based on the PLLCA55 clock frequency.
29
+
*/
30
+
cluster0_opp: opp-table-0 {
31
+
compatible = "operating-points-v2";
32
+
33
+
opp-1700000000 {
34
+
opp-hz = /bits/ 64 <1700000000>;
35
+
opp-microvolt = <900000>;
36
+
clock-latency-ns = <300000>;
37
+
};
38
+
opp-850000000 {
39
+
opp-hz = /bits/ 64 <850000000>;
40
+
opp-microvolt = <800000>;
41
+
clock-latency-ns = <300000>;
42
+
};
43
+
opp-425000000 {
44
+
opp-hz = /bits/ 64 <425000000>;
45
+
opp-microvolt = <800000>;
46
+
clock-latency-ns = <300000>;
47
+
};
48
+
opp-212500000 {
49
+
opp-hz = /bits/ 64 <212500000>;
50
+
opp-microvolt = <800000>;
51
+
clock-latency-ns = <300000>;
52
+
opp-suspend;
53
+
};
54
+
};
55
+
23
56
cpus {
24
57
#address-cells = <1>;
25
58
#size-cells = <0>;
···
63
30
device_type = "cpu";
64
31
next-level-cache = <&L3_CA55>;
65
32
enable-method = "psci";
33
+
clocks = <&cpg CPG_CORE R9A09G057_CA55_0_CORE_CLK0>;
34
+
operating-points-v2 = <&cluster0_opp>;
66
35
};
67
36
68
37
cpu1: cpu@100 {
···
73
38
device_type = "cpu";
74
39
next-level-cache = <&L3_CA55>;
75
40
enable-method = "psci";
41
+
clocks = <&cpg CPG_CORE R9A09G057_CA55_0_CORE_CLK1>;
42
+
operating-points-v2 = <&cluster0_opp>;
76
43
};
77
44
78
45
cpu2: cpu@200 {
···
83
46
device_type = "cpu";
84
47
next-level-cache = <&L3_CA55>;
85
48
enable-method = "psci";
49
+
clocks = <&cpg CPG_CORE R9A09G057_CA55_0_CORE_CLK2>;
50
+
operating-points-v2 = <&cluster0_opp>;
86
51
};
87
52
88
53
cpu3: cpu@300 {
···
93
54
device_type = "cpu";
94
55
next-level-cache = <&L3_CA55>;
95
56
enable-method = "psci";
57
+
clocks = <&cpg CPG_CORE R9A09G057_CA55_0_CORE_CLK3>;
58
+
operating-points-v2 = <&cluster0_opp>;
96
59
};
97
60
98
61
L3_CA55: cache-controller-0 {
+16
arch/arm64/boot/dts/renesas/rzg3s-smarc-som.dtsi
+16
arch/arm64/boot/dts/renesas/rzg3s-smarc-som.dtsi
···
5
5
* Copyright (C) 2023 Renesas Electronics Corp.
6
6
*/
7
7
8
+
#include <dt-bindings/clock/renesas,r9a08g045-vbattb.h>
8
9
#include <dt-bindings/gpio/gpio.h>
9
10
#include <dt-bindings/pinctrl/rzg2l-pinctrl.h>
10
11
···
343
342
<RZG2L_PORT_PINMUX(14, 1, 7)>; /* SD2_CD# */
344
343
};
345
344
};
345
+
};
346
+
347
+
&rtc {
348
+
status = "okay";
349
+
};
350
+
351
+
&vbattb {
352
+
assigned-clocks = <&vbattb VBATTB_MUX>;
353
+
assigned-clock-parents = <&vbattb VBATTB_XC>;
354
+
quartz-load-femtofarads = <12500>;
355
+
status = "okay";
356
+
};
357
+
358
+
&vbattb_xtal {
359
+
clock-frequency = <32768>;
346
360
};
347
361
348
362
&wdt0 {
+8
arch/arm64/boot/dts/renesas/white-hawk-cpu-common.dtsi
+8
arch/arm64/boot/dts/renesas/white-hawk-cpu-common.dtsi
···
238
238
clock-frequency = <400000>;
239
239
240
240
bridge@2c {
241
+
pinctrl-0 = <&irq0_pins>;
242
+
pinctrl-names = "default";
243
+
241
244
compatible = "ti,sn65dsi86";
242
245
reg = <0x2c>;
243
246
···
342
339
i2c1_pins: i2c1 {
343
340
groups = "i2c1";
344
341
function = "i2c1";
342
+
};
343
+
344
+
irq0_pins: irq0 {
345
+
groups = "intc_ex_irq0_a";
346
+
function = "intc_ex";
345
347
};
346
348
347
349
keys_pins: keys {
+1
include/dt-bindings/clock/r9a08g045-cpg.h
+1
include/dt-bindings/clock/r9a08g045-cpg.h
+13
include/dt-bindings/clock/renesas,r9a08g045-vbattb.h
+13
include/dt-bindings/clock/renesas,r9a08g045-vbattb.h
···
1
+
/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2
+
*
3
+
* Copyright (C) 2024 Renesas Electronics Corp.
4
+
*/
5
+
#ifndef __DT_BINDINGS_CLOCK_R9A08G045_VBATTB_H__
6
+
#define __DT_BINDINGS_CLOCK_R9A08G045_VBATTB_H__
7
+
8
+
#define VBATTB_XC 0
9
+
#define VBATTB_XBYP 1
10
+
#define VBATTB_MUX 2
11
+
#define VBATTB_VBATTCLK 3
12
+
13
+
#endif /* __DT_BINDINGS_CLOCK_R9A08G045_VBATTB_H__ */