Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
Merge tag 'mtk-dts64-for-v6.13' of https://git.kernel.org/pub/scm/linux/kernel/git/mediatek/linux into soc/dt
MediaTek ARM64 DeviceTree updates for v6.13
MT8195 (also called MT8395)
- Enabled GPU support on Genio 1200 EVK
- Added sound-dai-cells for audio codec on MT8195 Cherry Chromebooks
MT8192:
- Added support Asurada Chromebook variants with Synaptics trackpad
MT8188 (also called MT8390):
- Added support for CPU DVFS, IOMMU, PWM hardware, SPMI bus,
Audio, socinfo, PCI-Express, DisplayPort, MIPI DSI, Ethernet,
Video HW Encoders (Stateful) and HW Decoders (Stateless),
JPEG HW Encoder/Decoder.
- Enabled GPU support on Genio 700 EVK
MT8183:
- Added support for Video HW Encoders (Stateful)
- Added HDMI support on MT8183 Pumpkin board
- Fixed some regulators to provide the actual description of the
power rails in MT8183 Kukui Chromebooks
- Disabled DPI display interface on MT8183 Kukui Chromebooks
to fix internal display probing
- Fixed address of EEPROM found on MT8183 Kakadu/Kodama Chromebooks
- Added SCL internal delay on I2C2 bus for improved I2C-HID devices
reliability on MT8183 Jacuzzi Chromebooks
MT7988:
- Added support for eFuses and UART controllers
Plus, addition of OF Graph support in MediaTek MMSYS and some cleanups
and dtbs_check fixes for MT8195 and for all machines using the MT6358
PMIC.
* tag 'mtk-dts64-for-v6.13' of https://git.kernel.org/pub/scm/linux/kernel/git/mediatek/linux: (55 commits)
arm64: dts: mediatek: mt8183-kukui: Drop bogus fixed regulators
arm64: dts: mediatek: mt8183-kukui-jacuzzi: Add supplies for fixed regulators
arm64: dts: mediatek: mt8183-kukui-jacuzzi: Fix DP bridge supply names
arm64: dts: mediatek: mt6358: fix dtbs_check error
arm64: dts: mediatek: mt8186-corsola: Fix IT6505 reset line polarity
arm64: dts: mt8183: Damu: add i2c2's i2c-scl-internal-delay-ns
arm64: dts: mt8183: cozmo: add i2c2's i2c-scl-internal-delay-ns
arm64: dts: mt8183: burnet: add i2c2's i2c-scl-internal-delay-ns
arm64: dts: mt8183: fennel: add i2c2's i2c-scl-internal-delay-ns
dt-bindings: arm: mediatek: mmsys: Add OF graph support for board path
arm64: dts: mediatek: mt8186-corsola: Fix GPU supply coupling max-spread
arm64: dts: mediatek: mt8195-cherry: Use correct audio codec DAI
arm64: dts: mediatek: mt8188: Fix USB3 PHY port default status
arm64: dts: mediatek: mt8173-elm-hana: Add vdd-supply to second source trackpad
arm64: dts: mediatek: mt8186-corsola-voltorb: Merge speaker codec nodes
arm64: dts: mediatek: mt8390-genio-700-evk: Enable ethernet
arm64: dts: mediatek: mt8188: Add ethernet node
arm64: dts: mediatek: mt8188: Add eDP and DP TX nodes
arm64: dts: mediatek: mt8188: Add DP-INTF nodes
arm64: dts: mediatek: mt8188: Add display nodes for vdosys1
...
Link: https://lore.kernel.org/r/20241104112625.161365-1-angelogioacchino.delregno@collabora.com
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
+1586
-133
+28
Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.yaml
+28
Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.yaml
···
93
93
'#reset-cells':
94
94
const: 1
95
95
96
+
port:
97
+
$ref: /schemas/graph.yaml#/properties/port
98
+
description:
99
+
Output port node. This port connects the MMSYS/VDOSYS output to
100
+
the first component of one display pipeline, for example one of
101
+
the available OVL or RDMA blocks.
102
+
Some MediaTek SoCs support multiple display outputs per MMSYS.
103
+
properties:
104
+
endpoint@0:
105
+
$ref: /schemas/graph.yaml#/properties/endpoint
106
+
description: Output to the primary display pipeline
107
+
108
+
endpoint@1:
109
+
$ref: /schemas/graph.yaml#/properties/endpoint
110
+
description: Output to the secondary display pipeline
111
+
112
+
endpoint@2:
113
+
$ref: /schemas/graph.yaml#/properties/endpoint
114
+
description: Output to the tertiary display pipeline
115
+
116
+
anyOf:
117
+
- required:
118
+
- endpoint@0
119
+
- required:
120
+
- endpoint@1
121
+
- required:
122
+
- endpoint@2
123
+
96
124
required:
97
125
- compatible
98
126
- reg
+2
-2
arch/arm64/boot/dts/mediatek/mt6358.dtsi
+2
-2
arch/arm64/boot/dts/mediatek/mt6358.dtsi
···
15
15
#io-channel-cells = <1>;
16
16
};
17
17
18
-
mt6358codec: mt6358codec {
18
+
mt6358codec: audio-codec {
19
19
compatible = "mediatek,mt6358-sound";
20
20
mediatek,dmic-mode = <0>; /* two-wires */
21
21
};
22
22
23
-
mt6358regulator: mt6358regulator {
23
+
mt6358regulator: regulators {
24
24
compatible = "mediatek,mt6358-regulator";
25
25
26
26
mt6358_vdram1_reg: buck_vdram1 {
+41
-1
arch/arm64/boot/dts/mediatek/mt7988a.dtsi
+41
-1
arch/arm64/boot/dts/mediatek/mt7988a.dtsi
···
86
86
#clock-cells = <1>;
87
87
};
88
88
89
-
clock-controller@1001b000 {
89
+
topckgen: clock-controller@1001b000 {
90
90
compatible = "mediatek,mt7988-topckgen", "syscon";
91
91
reg = <0 0x1001b000 0 0x1000>;
92
92
#clock-cells = <1>;
···
121
121
clock-names = "top", "main", "pwm1", "pwm2", "pwm3",
122
122
"pwm4", "pwm5", "pwm6", "pwm7", "pwm8";
123
123
#pwm-cells = <2>;
124
+
status = "disabled";
125
+
};
126
+
127
+
serial@11000000 {
128
+
compatible = "mediatek,mt7988-uart", "mediatek,mt6577-uart";
129
+
reg = <0 0x11000000 0 0x100>;
130
+
interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>;
131
+
interrupt-names = "uart", "wakeup";
132
+
clocks = <&topckgen CLK_TOP_UART_SEL>,
133
+
<&infracfg CLK_INFRA_52M_UART0_CK>;
134
+
clock-names = "baud", "bus";
135
+
status = "disabled";
136
+
};
137
+
138
+
serial@11000100 {
139
+
compatible = "mediatek,mt7988-uart", "mediatek,mt6577-uart";
140
+
reg = <0 0x11000100 0 0x100>;
141
+
interrupts = <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>;
142
+
interrupt-names = "uart", "wakeup";
143
+
clocks = <&topckgen CLK_TOP_UART_SEL>,
144
+
<&infracfg CLK_INFRA_52M_UART1_CK>;
145
+
clock-names = "baud", "bus";
146
+
status = "disabled";
147
+
};
148
+
149
+
serial@11000200 {
150
+
compatible = "mediatek,mt7988-uart", "mediatek,mt6577-uart";
151
+
reg = <0 0x11000200 0 0x100>;
152
+
interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>;
153
+
interrupt-names = "uart", "wakeup";
154
+
clocks = <&topckgen CLK_TOP_UART_SEL>,
155
+
<&infracfg CLK_INFRA_52M_UART2_CK>;
156
+
clock-names = "baud", "bus";
124
157
status = "disabled";
125
158
};
126
159
···
229
196
reg = <0 0x11f40000 0 0x1000>;
230
197
resets = <&watchdog 16>;
231
198
#clock-cells = <1>;
199
+
};
200
+
201
+
efuse@11f50000 {
202
+
compatible = "mediatek,mt7988-efuse", "mediatek,efuse";
203
+
reg = <0 0x11f50000 0 0x1000>;
204
+
#address-cells = <1>;
205
+
#size-cells = <1>;
232
206
};
233
207
234
208
clock-controller@15000000 {
+8
arch/arm64/boot/dts/mediatek/mt8173-elm-hana.dtsi
+8
arch/arm64/boot/dts/mediatek/mt8173-elm-hana.dtsi
···
49
49
interrupts-extended = <&pio 117 IRQ_TYPE_LEVEL_LOW>;
50
50
reg = <0x2c>;
51
51
hid-descr-addr = <0x0020>;
52
+
/*
53
+
* The trackpad needs a post-power-on delay of 100ms,
54
+
* but at time of writing, the power supply for it on
55
+
* this board is always on. The delay is therefore not
56
+
* added to avoid impacting the readiness of the
57
+
* trackpad.
58
+
*/
59
+
vdd-supply = <&mt6397_vgp6_reg>;
52
60
wakeup-source;
53
61
};
54
62
};
+3
arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi-burnet.dts
+3
arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi-burnet.dts
+2
arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi-cozmo.dts
+2
arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi-cozmo.dts
+3
arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi-damu.dts
+3
arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi-damu.dts
+3
arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi-fennel.dtsi
+3
arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi-fennel.dtsi
+18
-12
arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi.dtsi
+18
-12
arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi.dtsi
···
8
8
#include <arm/cros-ec-keyboard.dtsi>
9
9
10
10
/ {
11
-
pp1200_mipibrdg: pp1200-mipibrdg {
11
+
pp1000_mipibrdg: pp1000-mipibrdg {
12
12
compatible = "regulator-fixed";
13
-
regulator-name = "pp1200_mipibrdg";
13
+
regulator-name = "pp1000_mipibrdg";
14
+
regulator-min-microvolt = <1000000>;
15
+
regulator-max-microvolt = <1000000>;
14
16
pinctrl-names = "default";
15
-
pinctrl-0 = <&pp1200_mipibrdg_en>;
17
+
pinctrl-0 = <&pp1000_mipibrdg_en>;
16
18
17
19
enable-active-high;
18
20
regulator-boot-on;
19
21
20
22
gpio = <&pio 54 GPIO_ACTIVE_HIGH>;
23
+
vin-supply = <&pp1800_alw>;
21
24
};
22
25
23
26
pp1800_mipibrdg: pp1800-mipibrdg {
24
27
compatible = "regulator-fixed";
25
28
regulator-name = "pp1800_mipibrdg";
26
29
pinctrl-names = "default";
27
-
pinctrl-0 = <&pp1800_lcd_en>;
30
+
pinctrl-0 = <&pp1800_mipibrdg_en>;
28
31
29
32
enable-active-high;
30
33
regulator-boot-on;
31
34
32
35
gpio = <&pio 36 GPIO_ACTIVE_HIGH>;
36
+
vin-supply = <&pp1800_alw>;
33
37
};
34
38
35
39
pp3300_panel: pp3300-panel {
···
48
44
regulator-boot-on;
49
45
50
46
gpio = <&pio 35 GPIO_ACTIVE_HIGH>;
47
+
vin-supply = <&pp3300_alw>;
51
48
};
52
49
53
-
vddio_mipibrdg: vddio-mipibrdg {
50
+
pp3300_mipibrdg: pp3300-mipibrdg {
54
51
compatible = "regulator-fixed";
55
-
regulator-name = "vddio_mipibrdg";
52
+
regulator-name = "pp3300_mipibrdg";
56
53
pinctrl-names = "default";
57
-
pinctrl-0 = <&vddio_mipibrdg_en>;
54
+
pinctrl-0 = <&pp3300_mipibrdg_en>;
58
55
59
56
enable-active-high;
60
57
regulator-boot-on;
61
58
62
59
gpio = <&pio 37 GPIO_ACTIVE_HIGH>;
60
+
vin-supply = <&pp3300_alw>;
63
61
};
64
62
65
63
volume_buttons: volume-buttons {
···
152
146
pinctrl-0 = <&anx7625_pins>;
153
147
enable-gpios = <&pio 45 GPIO_ACTIVE_HIGH>;
154
148
reset-gpios = <&pio 73 GPIO_ACTIVE_HIGH>;
155
-
vdd10-supply = <&pp1200_mipibrdg>;
149
+
vdd10-supply = <&pp1000_mipibrdg>;
156
150
vdd18-supply = <&pp1800_mipibrdg>;
157
-
vdd33-supply = <&vddio_mipibrdg>;
151
+
vdd33-supply = <&pp3300_mipibrdg>;
158
152
159
153
ports {
160
154
#address-cells = <1>;
···
397
391
"",
398
392
"";
399
393
400
-
pp1200_mipibrdg_en: pp1200-mipibrdg-en {
394
+
pp1000_mipibrdg_en: pp1000-mipibrdg-en {
401
395
pins1 {
402
396
pinmux = <PINMUX_GPIO54__FUNC_GPIO54>;
403
397
output-low;
404
398
};
405
399
};
406
400
407
-
pp1800_lcd_en: pp1800-lcd-en {
401
+
pp1800_mipibrdg_en: pp1800-mipibrdg-en {
408
402
pins1 {
409
403
pinmux = <PINMUX_GPIO36__FUNC_GPIO36>;
410
404
output-low;
···
466
460
};
467
461
};
468
462
469
-
vddio_mipibrdg_en: vddio-mipibrdg-en {
463
+
pp3300_mipibrdg_en: pp3300-mipibrdg-en {
470
464
pins1 {
471
465
pinmux = <PINMUX_GPIO37__FUNC_GPIO37>;
472
466
output-low;
+2
-2
arch/arm64/boot/dts/mediatek/mt8183-kukui-kakadu.dtsi
+2
-2
arch/arm64/boot/dts/mediatek/mt8183-kukui-kakadu.dtsi
+1
-1
arch/arm64/boot/dts/mediatek/mt8183-kukui-katsu-sku32.dts
+1
-1
arch/arm64/boot/dts/mediatek/mt8183-kukui-katsu-sku32.dts
+1
-1
arch/arm64/boot/dts/mediatek/mt8183-kukui-katsu-sku38.dts
+1
-1
arch/arm64/boot/dts/mediatek/mt8183-kukui-katsu-sku38.dts
+2
-2
arch/arm64/boot/dts/mediatek/mt8183-kukui-kodama.dtsi
+2
-2
arch/arm64/boot/dts/mediatek/mt8183-kukui-kodama.dtsi
+2
-2
arch/arm64/boot/dts/mediatek/mt8183-kukui-krane.dtsi
+2
-2
arch/arm64/boot/dts/mediatek/mt8183-kukui-krane.dtsi
+7
-23
arch/arm64/boot/dts/mediatek/mt8183-kukui.dtsi
+7
-23
arch/arm64/boot/dts/mediatek/mt8183-kukui.dtsi
···
52
52
vin-supply = <&pp1800_alw>;
53
53
};
54
54
55
-
lcd_pp3300: regulator1 {
56
-
compatible = "regulator-fixed";
57
-
regulator-name = "lcd_pp3300";
58
-
regulator-min-microvolt = <3300000>;
59
-
regulator-max-microvolt = <3300000>;
60
-
regulator-always-on;
61
-
regulator-boot-on;
62
-
};
63
-
64
-
mmc1_fixed_power: regulator3 {
65
-
compatible = "regulator-fixed";
66
-
regulator-name = "mmc1_power";
67
-
vin-supply = <&pp3300_alw>;
68
-
};
69
-
70
-
mmc1_fixed_io: regulator4 {
71
-
compatible = "regulator-fixed";
72
-
regulator-name = "mmc1_io";
73
-
vin-supply = <&pp1800_alw>;
74
-
};
75
-
76
55
pp1800_alw: regulator5 {
77
56
compatible = "regulator-fixed";
78
57
regulator-name = "pp1800_alw";
···
269
290
};
270
291
};
271
292
293
+
&dpi0 {
294
+
/* TODO Re-enable after DP to Type-C port muxing can be described */
295
+
status = "disabled";
296
+
};
297
+
272
298
&gic {
273
299
mediatek,broken-save-restore-fw;
274
300
};
···
353
369
pinctrl-names = "default", "state_uhs";
354
370
pinctrl-0 = <&mmc1_pins_default>;
355
371
pinctrl-1 = <&mmc1_pins_uhs>;
356
-
vmmc-supply = <&mmc1_fixed_power>;
357
-
vqmmc-supply = <&mmc1_fixed_io>;
372
+
vmmc-supply = <&pp3300_alw>;
373
+
vqmmc-supply = <&pp1800_alw>;
358
374
mmc-pwrseq = <&wifi_pwrseq>;
359
375
bus-width = <4>;
360
376
max-frequency = <200000000>;
+123
arch/arm64/boot/dts/mediatek/mt8183-pumpkin.dts
+123
arch/arm64/boot/dts/mediatek/mt8183-pumpkin.dts
···
63
63
pulldown-ohm = <0>;
64
64
io-channels = <&auxadc 0>;
65
65
};
66
+
67
+
connector {
68
+
compatible = "hdmi-connector";
69
+
label = "hdmi";
70
+
type = "d";
71
+
72
+
port {
73
+
hdmi_connector_in: endpoint {
74
+
remote-endpoint = <&hdmi_connector_out>;
75
+
};
76
+
};
77
+
};
66
78
};
67
79
68
80
&auxadc {
···
132
120
pinctrl-0 = <&i2c6_pins>;
133
121
status = "okay";
134
122
clock-frequency = <100000>;
123
+
#address-cells = <1>;
124
+
#size-cells = <0>;
125
+
126
+
it66121hdmitx: hdmitx@4c {
127
+
compatible = "ite,it66121";
128
+
reg = <0x4c>;
129
+
pinctrl-names = "default";
130
+
pinctrl-0 = <&ite_pins>;
131
+
reset-gpios = <&pio 160 GPIO_ACTIVE_LOW>;
132
+
interrupt-parent = <&pio>;
133
+
interrupts = <4 IRQ_TYPE_LEVEL_LOW>;
134
+
vcn33-supply = <&mt6358_vcn33_reg>;
135
+
vcn18-supply = <&mt6358_vcn18_reg>;
136
+
vrf12-supply = <&mt6358_vrf12_reg>;
137
+
138
+
ports {
139
+
#address-cells = <1>;
140
+
#size-cells = <0>;
141
+
142
+
port@0 {
143
+
reg = <0>;
144
+
145
+
it66121_in: endpoint {
146
+
bus-width = <12>;
147
+
remote-endpoint = <&dpi_out>;
148
+
};
149
+
};
150
+
151
+
port@1 {
152
+
reg = <1>;
153
+
154
+
hdmi_connector_out: endpoint {
155
+
remote-endpoint = <&hdmi_connector_in>;
156
+
};
157
+
};
158
+
};
159
+
};
135
160
};
136
161
137
162
&keyboard {
···
411
362
input-enable;
412
363
};
413
364
};
365
+
366
+
ite_pins: ite-pins {
367
+
pins-irq {
368
+
pinmux = <PINMUX_GPIO4__FUNC_GPIO4>;
369
+
input-enable;
370
+
bias-pull-up;
371
+
};
372
+
373
+
pins-rst {
374
+
pinmux = <PINMUX_GPIO160__FUNC_GPIO160>;
375
+
output-high;
376
+
};
377
+
};
378
+
379
+
dpi_func_pins: dpi-func-pins {
380
+
pins-dpi {
381
+
pinmux = <PINMUX_GPIO12__FUNC_I2S5_BCK>,
382
+
<PINMUX_GPIO46__FUNC_I2S5_LRCK>,
383
+
<PINMUX_GPIO47__FUNC_I2S5_DO>,
384
+
<PINMUX_GPIO13__FUNC_DBPI_D0>,
385
+
<PINMUX_GPIO14__FUNC_DBPI_D1>,
386
+
<PINMUX_GPIO15__FUNC_DBPI_D2>,
387
+
<PINMUX_GPIO16__FUNC_DBPI_D3>,
388
+
<PINMUX_GPIO17__FUNC_DBPI_D4>,
389
+
<PINMUX_GPIO18__FUNC_DBPI_D5>,
390
+
<PINMUX_GPIO19__FUNC_DBPI_D6>,
391
+
<PINMUX_GPIO20__FUNC_DBPI_D7>,
392
+
<PINMUX_GPIO21__FUNC_DBPI_D8>,
393
+
<PINMUX_GPIO22__FUNC_DBPI_D9>,
394
+
<PINMUX_GPIO23__FUNC_DBPI_D10>,
395
+
<PINMUX_GPIO24__FUNC_DBPI_D11>,
396
+
<PINMUX_GPIO25__FUNC_DBPI_HSYNC>,
397
+
<PINMUX_GPIO26__FUNC_DBPI_VSYNC>,
398
+
<PINMUX_GPIO27__FUNC_DBPI_DE>,
399
+
<PINMUX_GPIO28__FUNC_DBPI_CK>;
400
+
};
401
+
};
402
+
403
+
dpi_idle_pins: dpi-idle-pins {
404
+
pins-idle {
405
+
pinmux = <PINMUX_GPIO12__FUNC_GPIO12>,
406
+
<PINMUX_GPIO46__FUNC_GPIO46>,
407
+
<PINMUX_GPIO47__FUNC_GPIO47>,
408
+
<PINMUX_GPIO13__FUNC_GPIO13>,
409
+
<PINMUX_GPIO14__FUNC_GPIO14>,
410
+
<PINMUX_GPIO15__FUNC_GPIO15>,
411
+
<PINMUX_GPIO16__FUNC_GPIO16>,
412
+
<PINMUX_GPIO17__FUNC_GPIO17>,
413
+
<PINMUX_GPIO18__FUNC_GPIO18>,
414
+
<PINMUX_GPIO19__FUNC_GPIO19>,
415
+
<PINMUX_GPIO20__FUNC_GPIO20>,
416
+
<PINMUX_GPIO21__FUNC_GPIO21>,
417
+
<PINMUX_GPIO22__FUNC_GPIO22>,
418
+
<PINMUX_GPIO23__FUNC_GPIO23>,
419
+
<PINMUX_GPIO24__FUNC_GPIO24>,
420
+
<PINMUX_GPIO25__FUNC_GPIO25>,
421
+
<PINMUX_GPIO26__FUNC_GPIO26>,
422
+
<PINMUX_GPIO27__FUNC_GPIO27>,
423
+
<PINMUX_GPIO28__FUNC_GPIO28>;
424
+
};
425
+
};
414
426
};
415
427
416
428
&pmic {
···
524
414
525
415
&dsi0 {
526
416
status = "disabled";
417
+
};
418
+
419
+
&dpi0 {
420
+
pinctrl-names = "default", "sleep";
421
+
pinctrl-0 = <&dpi_func_pins>;
422
+
pinctrl-1 = <&dpi_idle_pins>;
423
+
status = "okay";
424
+
425
+
port {
426
+
dpi_out: endpoint {
427
+
remote-endpoint = <&it66121_in>;
428
+
};
429
+
};
527
430
};
+21
arch/arm64/boot/dts/mediatek/mt8183.dtsi
+21
arch/arm64/boot/dts/mediatek/mt8183.dtsi
···
1845
1845
<&mmsys CLK_MM_DPI_MM>,
1846
1846
<&apmixedsys CLK_APMIXED_TVDPLL>;
1847
1847
clock-names = "pixel", "engine", "pll";
1848
+
1849
+
port {
1850
+
dpi_out: endpoint { };
1851
+
};
1848
1852
};
1849
1853
1850
1854
mutex: mutex@14016000 {
···
1976
1972
<&vencsys CLK_VENC_LARB>;
1977
1973
clock-names = "apb", "smi";
1978
1974
power-domains = <&spm MT8183_POWER_DOMAIN_VENC>;
1975
+
};
1976
+
1977
+
vcodec_enc: vcodec@17020000 {
1978
+
compatible = "mediatek,mt8183-vcodec-enc";
1979
+
reg = <0 0x17020000 0 0x1000>;
1980
+
interrupts = <GIC_SPI 247 IRQ_TYPE_LEVEL_LOW>;
1981
+
iommus = <&iommu M4U_PORT_VENC_REC>,
1982
+
<&iommu M4U_PORT_VENC_BSDMA>,
1983
+
<&iommu M4U_PORT_VENC_RD_COMV>,
1984
+
<&iommu M4U_PORT_VENC_CUR_LUMA>,
1985
+
<&iommu M4U_PORT_VENC_CUR_CHROMA>,
1986
+
<&iommu M4U_PORT_VENC_REF_LUMA>,
1987
+
<&iommu M4U_PORT_VENC_REF_CHROMA>;
1988
+
mediatek,scp = <&scp>;
1989
+
power-domains = <&spm MT8183_POWER_DOMAIN_VENC>;
1990
+
clocks = <&vencsys CLK_VENC_VENC>;
1991
+
clock-names = "venc_sel";
1979
1992
};
1980
1993
1981
1994
venc_jpg: jpeg-encoder@17030000 {
+5
-16
arch/arm64/boot/dts/mediatek/mt8186-corsola-voltorb.dtsi
+5
-16
arch/arm64/boot/dts/mediatek/mt8186-corsola-voltorb.dtsi
···
10
10
11
11
/ {
12
12
chassis-type = "laptop";
13
-
14
-
max98360a: max98360a {
15
-
compatible = "maxim,max98360a";
16
-
sdmode-gpios = <&pio 150 GPIO_ACTIVE_HIGH>;
17
-
#sound-dai-cells = <0>;
18
-
};
19
13
};
20
14
21
15
&cpu6 {
···
53
59
opp-hz = /bits/ 64 <2200000000>;
54
60
};
55
61
56
-
&rt1019p{
57
-
status = "disabled";
58
-
};
59
-
60
62
&sound {
61
63
compatible = "mediatek,mt8186-mt6366-rt5682s-max98360-sound";
62
-
status = "okay";
64
+
};
63
65
64
-
spk-hdmi-playback-dai-link {
65
-
codec {
66
-
sound-dai = <&it6505dptx>, <&max98360a>;
67
-
};
68
-
};
66
+
&speaker_codec {
67
+
compatible = "maxim,max98360a";
68
+
sdmode-gpios = <&pio 150 GPIO_ACTIVE_HIGH>;
69
+
/delete-property/ sdb-gpios;
69
70
};
70
71
71
72
&spmi {
+7
-7
arch/arm64/boot/dts/mediatek/mt8186-corsola.dtsi
+7
-7
arch/arm64/boot/dts/mediatek/mt8186-corsola.dtsi
···
259
259
mediatek,clk-provider = "cpu";
260
260
/* RT1019P and IT6505 connected to the same I2S line */
261
261
codec {
262
-
sound-dai = <&it6505dptx>, <&rt1019p>;
262
+
sound-dai = <&it6505dptx>, <&speaker_codec>;
263
263
};
264
264
};
265
265
};
266
266
267
-
rt1019p: speaker-codec {
267
+
speaker_codec: speaker-codec {
268
268
compatible = "realtek,rt1019p";
269
269
pinctrl-names = "default";
270
-
pinctrl-0 = <&rt1019p_pins_default>;
270
+
pinctrl-0 = <&speaker_codec_pins_default>;
271
271
#sound-dai-cells = <0>;
272
272
sdb-gpios = <&pio 150 GPIO_ACTIVE_HIGH>;
273
273
};
···
423
423
#sound-dai-cells = <0>;
424
424
ovdd-supply = <&mt6366_vsim2_reg>;
425
425
pwr18-supply = <&pp1800_dpbrdg_dx>;
426
-
reset-gpios = <&pio 177 GPIO_ACTIVE_HIGH>;
426
+
reset-gpios = <&pio 177 GPIO_ACTIVE_LOW>;
427
427
428
428
ports {
429
429
#address-cells = <1>;
···
1179
1179
};
1180
1180
};
1181
1181
1182
-
rt1019p_pins_default: rt1019p-default-pins {
1182
+
speaker_codec_pins_default: speaker-codec-default-pins {
1183
1183
pins-sdb {
1184
1184
pinmux = <PINMUX_GPIO150__FUNC_GPIO150>;
1185
1185
output-low;
···
1336
1336
regulator-allowed-modes = <MT6397_BUCK_MODE_AUTO
1337
1337
MT6397_BUCK_MODE_FORCE_PWM>;
1338
1338
regulator-coupled-with = <&mt6366_vsram_gpu_reg>;
1339
-
regulator-coupled-max-spread = <10000>;
1339
+
regulator-coupled-max-spread = <100000>;
1340
1340
};
1341
1341
1342
1342
mt6366_vproc11_reg: vproc11 {
···
1545
1545
regulator-ramp-delay = <6250>;
1546
1546
regulator-enable-ramp-delay = <240>;
1547
1547
regulator-coupled-with = <&mt6366_vgpu_reg>;
1548
-
regulator-coupled-max-spread = <10000>;
1548
+
regulator-coupled-max-spread = <100000>;
1549
1549
};
1550
1550
1551
1551
mt6366_vsram_others_reg: vsram-others {
+7
arch/arm64/boot/dts/mediatek/mt8186.dtsi
+7
arch/arm64/boot/dts/mediatek/mt8186.dtsi
···
29
29
rdma1 = &rdma1;
30
30
};
31
31
32
+
fhctl: fhctl@1000ce00 {
33
+
compatible = "mediatek,mt8186-fhctl";
34
+
clocks = <&apmixedsys CLK_APMIXED_TVDPLL>;
35
+
reg = <0 0x1000ce00 0 0x200>;
36
+
status = "disabled";
37
+
};
38
+
32
39
cci: cci {
33
40
compatible = "mediatek,mt8186-cci";
34
41
clocks = <&mcusys CLK_MCU_ARMPLL_BUS_SEL>,
-2
arch/arm64/boot/dts/mediatek/mt8188-evb.dts
-2
arch/arm64/boot/dts/mediatek/mt8188-evb.dts
+1107
-17
arch/arm64/boot/dts/mediatek/mt8188.dtsi
+1107
-17
arch/arm64/boot/dts/mediatek/mt8188.dtsi
···
9
9
#include <dt-bindings/interrupt-controller/arm-gic.h>
10
10
#include <dt-bindings/interrupt-controller/irq.h>
11
11
#include <dt-bindings/mailbox/mediatek,mt8188-gce.h>
12
+
#include <dt-bindings/memory/mediatek,mt8188-memory-port.h>
12
13
#include <dt-bindings/phy/phy.h>
13
14
#include <dt-bindings/pinctrl/mediatek,mt8188-pinfunc.h>
14
15
#include <dt-bindings/power/mediatek,mt8188-power.h>
···
22
21
interrupt-parent = <&gic>;
23
22
#address-cells = <2>;
24
23
#size-cells = <2>;
24
+
25
+
aliases {
26
+
dp-intf0 = &dp_intf0;
27
+
dp-intf1 = &dp_intf1;
28
+
ethdr0 = ðdr0;
29
+
gce0 = &gce0;
30
+
gce1 = &gce1;
31
+
merge1 = &merge1;
32
+
merge2 = &merge2;
33
+
merge3 = &merge3;
34
+
merge4 = &merge4;
35
+
merge5 = &merge5;
36
+
mutex0 = &mutex0;
37
+
mutex1 = &mutex1;
38
+
padding0 = &padding0;
39
+
padding1 = &padding1;
40
+
padding2 = &padding2;
41
+
padding3 = &padding3;
42
+
padding4 = &padding4;
43
+
padding5 = &padding5;
44
+
padding6 = &padding6;
45
+
padding7 = &padding7;
46
+
vdo1-rdma0 = &vdo1_rdma0;
47
+
vdo1-rdma1 = &vdo1_rdma1;
48
+
vdo1-rdma2 = &vdo1_rdma2;
49
+
vdo1-rdma3 = &vdo1_rdma3;
50
+
vdo1-rdma4 = &vdo1_rdma4;
51
+
vdo1-rdma5 = &vdo1_rdma5;
52
+
vdo1-rdma6 = &vdo1_rdma6;
53
+
vdo1-rdma7 = &vdo1_rdma7;
54
+
};
25
55
26
56
cpus {
27
57
#address-cells = <1>;
···
73
41
d-cache-line-size = <64>;
74
42
d-cache-sets = <128>;
75
43
next-level-cache = <&l2_0>;
44
+
performance-domains = <&performance 0>;
76
45
#cooling-cells = <2>;
77
46
};
78
47
···
92
59
d-cache-line-size = <64>;
93
60
d-cache-sets = <128>;
94
61
next-level-cache = <&l2_0>;
62
+
performance-domains = <&performance 0>;
95
63
#cooling-cells = <2>;
96
64
};
97
65
···
111
77
d-cache-line-size = <64>;
112
78
d-cache-sets = <128>;
113
79
next-level-cache = <&l2_0>;
80
+
performance-domains = <&performance 0>;
114
81
#cooling-cells = <2>;
115
82
};
116
83
···
130
95
d-cache-line-size = <64>;
131
96
d-cache-sets = <128>;
132
97
next-level-cache = <&l2_0>;
98
+
performance-domains = <&performance 0>;
133
99
#cooling-cells = <2>;
134
100
};
135
101
···
149
113
d-cache-line-size = <64>;
150
114
d-cache-sets = <128>;
151
115
next-level-cache = <&l2_0>;
116
+
performance-domains = <&performance 0>;
152
117
#cooling-cells = <2>;
153
118
};
154
119
···
168
131
d-cache-line-size = <64>;
169
132
d-cache-sets = <128>;
170
133
next-level-cache = <&l2_0>;
134
+
performance-domains = <&performance 0>;
171
135
#cooling-cells = <2>;
172
136
};
173
137
···
187
149
d-cache-line-size = <64>;
188
150
d-cache-sets = <256>;
189
151
next-level-cache = <&l2_1>;
152
+
performance-domains = <&performance 1>;
190
153
#cooling-cells = <2>;
191
154
};
192
155
···
206
167
d-cache-line-size = <64>;
207
168
d-cache-sets = <256>;
208
169
next-level-cache = <&l2_1>;
170
+
performance-domains = <&performance 1>;
209
171
#cooling-cells = <2>;
210
172
};
211
173
···
458
418
psci {
459
419
compatible = "arm,psci-1.0";
460
420
method = "smc";
421
+
};
422
+
423
+
sound: sound {
424
+
mediatek,platform = <&afe>;
425
+
status = "disabled";
461
426
};
462
427
463
428
thermal_zones: thermal-zones {
···
923
878
#address-cells = <2>;
924
879
#size-cells = <2>;
925
880
compatible = "simple-bus";
881
+
dma-ranges = <0x0 0x0 0x0 0x0 0x4 0x0>;
926
882
ranges;
883
+
884
+
performance: performance-controller@11bc10 {
885
+
compatible = "mediatek,cpufreq-hw";
886
+
reg = <0 0x0011bc10 0 0x120>, <0 0x0011bd30 0 0x120>;
887
+
#performance-domain-cells = <1>;
888
+
};
927
889
928
890
gic: interrupt-controller@c000000 {
929
891
compatible = "arm,gic-v3";
···
1008
956
#size-cells = <0>;
1009
957
#power-domain-cells = <1>;
1010
958
1011
-
power-domain@MT8188_POWER_DOMAIN_MFG1 {
959
+
mfg1: power-domain@MT8188_POWER_DOMAIN_MFG1 {
1012
960
reg = <MT8188_POWER_DOMAIN_MFG1>;
1013
-
clocks = <&topckgen CLK_APMIXED_MFGPLL>,
961
+
clocks = <&apmixedsys CLK_APMIXED_MFGPLL>,
1014
962
<&topckgen CLK_TOP_MFG_CORE_TMP>;
1015
963
clock-names = "mfg", "alt";
1016
964
mediatek,infracfg = <&infracfg_ao>;
···
1113
1061
#power-domain-cells = <0>;
1114
1062
};
1115
1063
1116
-
power-domain@MT8188_POWER_DOMAIN_VDEC1 {
1117
-
reg = <MT8188_POWER_DOMAIN_VDEC1>;
1118
-
clocks = <&vdecsys CLK_VDEC2_LARB1>;
1119
-
clock-names = "ss-vdec";
1120
-
mediatek,infracfg = <&infracfg_ao>;
1121
-
#power-domain-cells = <0>;
1122
-
};
1123
-
1124
1064
power-domain@MT8188_POWER_DOMAIN_VDEC0 {
1125
1065
reg = <MT8188_POWER_DOMAIN_VDEC0>;
1126
1066
clocks = <&vdecsys_soc CLK_VDEC1_SOC_LARB1>;
1127
-
clock-names = "ss-vdec";
1067
+
clock-names = "ss-vdec1-soc-l1";
1128
1068
mediatek,infracfg = <&infracfg_ao>;
1129
-
#power-domain-cells = <0>;
1069
+
#address-cells = <1>;
1070
+
#size-cells = <0>;
1071
+
#power-domain-cells = <1>;
1072
+
1073
+
power-domain@MT8188_POWER_DOMAIN_VDEC1 {
1074
+
reg = <MT8188_POWER_DOMAIN_VDEC1>;
1075
+
clocks = <&vdecsys CLK_VDEC2_LARB1>;
1076
+
clock-names = "ss-vdec2-l1";
1077
+
mediatek,infracfg = <&infracfg_ao>;
1078
+
#power-domain-cells = <0>;
1079
+
};
1130
1080
};
1131
1081
1132
1082
cam_vcore: power-domain@MT8188_POWER_DOMAIN_CAM_VCORE {
···
1345
1291
clock-names = "spi", "wrap";
1346
1292
};
1347
1293
1294
+
spmi: spmi@10027000 {
1295
+
compatible = "mediatek,mt8188-spmi", "mediatek,mt8195-spmi";
1296
+
reg = <0 0x10027000 0 0xe00>, <0 0x10029000 0 0x100>;
1297
+
reg-names = "pmif", "spmimst";
1298
+
assigned-clocks = <&topckgen CLK_TOP_SPMI_M_MST>;
1299
+
assigned-clock-parents = <&topckgen CLK_TOP_ULPOSC1_D10>;
1300
+
clocks = <&infracfg_ao CLK_INFRA_AO_PMIC_AP>,
1301
+
<&infracfg_ao CLK_INFRA_AO_PMIC_TMR>,
1302
+
<&topckgen CLK_TOP_SPMI_M_MST>;
1303
+
clock-names = "pmif_sys_ck", "pmif_tmr_ck", "spmimst_clk_mux";
1304
+
};
1305
+
1306
+
infra_iommu: iommu@10315000 {
1307
+
compatible = "mediatek,mt8188-iommu-infra";
1308
+
reg = <0 0x10315000 0 0x1000>;
1309
+
interrupts = <GIC_SPI 795 IRQ_TYPE_LEVEL_HIGH 0>;
1310
+
#iommu-cells = <1>;
1311
+
};
1312
+
1348
1313
gce0: mailbox@10320000 {
1349
1314
compatible = "mediatek,mt8188-gce";
1350
1315
reg = <0 0x10320000 0 0x4000>;
···
1386
1313
<0 0x10720000 0 0xe0000>;
1387
1314
reg-names = "sram", "cfg";
1388
1315
interrupts = <GIC_SPI 462 IRQ_TYPE_LEVEL_HIGH 0>;
1316
+
};
1317
+
1318
+
afe: audio-controller@10b10000 {
1319
+
compatible = "mediatek,mt8188-afe";
1320
+
reg = <0 0x10b10000 0 0x10000>;
1321
+
assigned-clocks = <&topckgen CLK_TOP_A1SYS_HP>;
1322
+
assigned-clock-parents = <&clk26m>;
1323
+
clocks = <&clk26m>,
1324
+
<&apmixedsys CLK_APMIXED_APLL1>,
1325
+
<&apmixedsys CLK_APMIXED_APLL2>,
1326
+
<&topckgen CLK_TOP_APLL12_CK_DIV0>,
1327
+
<&topckgen CLK_TOP_APLL12_CK_DIV1>,
1328
+
<&topckgen CLK_TOP_APLL12_CK_DIV2>,
1329
+
<&topckgen CLK_TOP_APLL12_CK_DIV3>,
1330
+
<&topckgen CLK_TOP_APLL12_CK_DIV9>,
1331
+
<&topckgen CLK_TOP_A1SYS_HP>,
1332
+
<&topckgen CLK_TOP_AUD_INTBUS>,
1333
+
<&topckgen CLK_TOP_AUDIO_H>,
1334
+
<&topckgen CLK_TOP_AUDIO_LOCAL_BUS>,
1335
+
<&topckgen CLK_TOP_DPTX>,
1336
+
<&topckgen CLK_TOP_I2SO1>,
1337
+
<&topckgen CLK_TOP_I2SO2>,
1338
+
<&topckgen CLK_TOP_I2SI1>,
1339
+
<&topckgen CLK_TOP_I2SI2>,
1340
+
<&adsp_audio26m CLK_AUDIODSP_AUDIO26M>,
1341
+
<&topckgen CLK_TOP_APLL1_D4>,
1342
+
<&topckgen CLK_TOP_APLL2_D4>,
1343
+
<&topckgen CLK_TOP_APLL12_CK_DIV4>,
1344
+
<&topckgen CLK_TOP_A2SYS>,
1345
+
<&topckgen CLK_TOP_AUD_IEC>;
1346
+
clock-names = "clk26m",
1347
+
"apll1",
1348
+
"apll2",
1349
+
"apll12_div0",
1350
+
"apll12_div1",
1351
+
"apll12_div2",
1352
+
"apll12_div3",
1353
+
"apll12_div9",
1354
+
"top_a1sys_hp",
1355
+
"top_aud_intbus",
1356
+
"top_audio_h",
1357
+
"top_audio_local_bus",
1358
+
"top_dptx",
1359
+
"top_i2so1",
1360
+
"top_i2so2",
1361
+
"top_i2si1",
1362
+
"top_i2si2",
1363
+
"adsp_audio_26m",
1364
+
"apll1_d4",
1365
+
"apll2_d4",
1366
+
"apll12_div4",
1367
+
"top_a2sys",
1368
+
"top_aud_iec";
1369
+
interrupts = <GIC_SPI 822 IRQ_TYPE_LEVEL_HIGH 0>;
1370
+
power-domains = <&spm MT8188_POWER_DOMAIN_AUDIO>;
1371
+
resets = <&watchdog MT8188_TOPRGU_AUDIO_SW_RST>;
1372
+
reset-names = "audiosys";
1373
+
mediatek,infracfg = <&infracfg_ao>;
1374
+
mediatek,topckgen = <&topckgen>;
1375
+
status = "disabled";
1376
+
};
1377
+
1378
+
adsp: adsp@10b80000 {
1379
+
compatible = "mediatek,mt8188-dsp";
1380
+
reg = <0 0x10b80000 0 0x2000>,
1381
+
<0 0x10d00000 0 0x80000>,
1382
+
<0 0x10b8b000 0 0x100>,
1383
+
<0 0x10b8f000 0 0x1000>;
1384
+
reg-names = "cfg", "sram", "sec", "bus";
1385
+
assigned-clocks = <&topckgen CLK_TOP_ADSP>;
1386
+
clocks = <&topckgen CLK_TOP_ADSP>,
1387
+
<&topckgen CLK_TOP_AUDIO_LOCAL_BUS>;
1388
+
clock-names = "audiodsp", "adsp_bus";
1389
+
mboxes = <&adsp_mailbox0>, <&adsp_mailbox1>;
1390
+
mbox-names = "rx", "tx";
1391
+
power-domains = <&spm MT8188_POWER_DOMAIN_ADSP>;
1392
+
status = "disabled";
1393
+
};
1394
+
1395
+
adsp_mailbox0: mailbox@10b86100 {
1396
+
compatible = "mediatek,mt8188-adsp-mbox", "mediatek,mt8186-adsp-mbox";
1397
+
reg = <0 0x10b86100 0 0x1000>;
1398
+
interrupts = <GIC_SPI 478 IRQ_TYPE_LEVEL_HIGH 0>;
1399
+
#mbox-cells = <0>;
1400
+
};
1401
+
1402
+
adsp_mailbox1: mailbox@10b87100 {
1403
+
compatible = "mediatek,mt8188-adsp-mbox", "mediatek,mt8186-adsp-mbox";
1404
+
reg = <0 0x10b87100 0 0x1000>;
1405
+
interrupts = <GIC_SPI 479 IRQ_TYPE_LEVEL_HIGH 0>;
1406
+
#mbox-cells = <0>;
1389
1407
};
1390
1408
1391
1409
adsp_audio26m: clock-controller@10b91100 {
···
1560
1396
#thermal-sensor-cells = <1>;
1561
1397
};
1562
1398
1399
+
disp_pwm0: pwm@1100e000 {
1400
+
compatible = "mediatek,mt8188-disp-pwm", "mediatek,mt8183-disp-pwm";
1401
+
reg = <0 0x1100e000 0 0x1000>;
1402
+
clocks = <&topckgen CLK_TOP_DISP_PWM0>,
1403
+
<&infracfg_ao CLK_INFRA_AO_DISP_PWM>;
1404
+
clock-names = "main", "mm";
1405
+
interrupts = <GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH 0>;
1406
+
#pwm-cells = <2>;
1407
+
status = "disabled";
1408
+
};
1409
+
1410
+
disp_pwm1: pwm@1100f000 {
1411
+
compatible = "mediatek,mt8188-disp-pwm", "mediatek,mt8183-disp-pwm";
1412
+
reg = <0 0x1100f000 0 0x1000>;
1413
+
clocks = <&topckgen CLK_TOP_DISP_PWM1>,
1414
+
<&infracfg_ao CLK_INFRA_AO_DISP_PWM1>;
1415
+
clock-names = "main", "mm";
1416
+
interrupts = <GIC_SPI 793 IRQ_TYPE_LEVEL_HIGH 0>;
1417
+
#pwm-cells = <2>;
1418
+
status = "disabled";
1419
+
};
1420
+
1563
1421
spi1: spi@11010000 {
1564
1422
compatible = "mediatek,mt8188-spi-ipm", "mediatek,spi-ipm";
1565
1423
#address-cells = <1>;
···
1645
1459
<&infracfg_ao CLK_INFRA_AO_SPI5>;
1646
1460
clock-names = "parent-clk", "sel-clk", "spi-clk";
1647
1461
status = "disabled";
1462
+
};
1463
+
1464
+
eth: ethernet@11021000 {
1465
+
compatible = "mediatek,mt8188-gmac", "mediatek,mt8195-gmac",
1466
+
"snps,dwmac-5.10a";
1467
+
reg = <0 0x11021000 0 0x4000>;
1468
+
interrupts = <GIC_SPI 716 IRQ_TYPE_LEVEL_HIGH 0>;
1469
+
interrupt-names = "macirq";
1470
+
clocks = <&pericfg_ao CLK_PERI_AO_ETHERNET>,
1471
+
<&pericfg_ao CLK_PERI_AO_ETHERNET_BUS>,
1472
+
<&topckgen CLK_TOP_SNPS_ETH_250M>,
1473
+
<&topckgen CLK_TOP_SNPS_ETH_62P4M_PTP>,
1474
+
<&topckgen CLK_TOP_SNPS_ETH_50M_RMII>,
1475
+
<&pericfg_ao CLK_PERI_AO_ETHERNET_MAC>;
1476
+
clock-names = "axi", "apb", "mac_main", "ptp_ref",
1477
+
"rmii_internal", "mac_cg";
1478
+
assigned-clocks = <&topckgen CLK_TOP_SNPS_ETH_250M>,
1479
+
<&topckgen CLK_TOP_SNPS_ETH_62P4M_PTP>,
1480
+
<&topckgen CLK_TOP_SNPS_ETH_50M_RMII>;
1481
+
assigned-clock-parents = <&topckgen CLK_TOP_ETHPLL_D2>,
1482
+
<&topckgen CLK_TOP_ETHPLL_D8>,
1483
+
<&topckgen CLK_TOP_ETHPLL_D10>;
1484
+
power-domains = <&spm MT8188_POWER_DOMAIN_ETHER>;
1485
+
mediatek,pericfg = <&infracfg_ao>;
1486
+
snps,axi-config = <&stmmac_axi_setup>;
1487
+
snps,mtl-rx-config = <&mtl_rx_setup>;
1488
+
snps,mtl-tx-config = <&mtl_tx_setup>;
1489
+
snps,txpbl = <16>;
1490
+
snps,rxpbl = <16>;
1491
+
snps,clk-csr = <0>;
1492
+
status = "disabled";
1493
+
1494
+
eth_mdio: mdio {
1495
+
compatible = "snps,dwmac-mdio";
1496
+
#address-cells = <1>;
1497
+
#size-cells = <0>;
1498
+
};
1499
+
1500
+
stmmac_axi_setup: stmmac-axi-config {
1501
+
snps,blen = <0 0 0 0 16 8 4>;
1502
+
snps,rd_osr_lmt = <0x7>;
1503
+
snps,wr_osr_lmt = <0x7>;
1504
+
};
1505
+
1506
+
mtl_rx_setup: rx-queues-config {
1507
+
snps,rx-queues-to-use = <4>;
1508
+
snps,rx-sched-sp;
1509
+
1510
+
queue0 {
1511
+
snps,dcb-algorithm;
1512
+
snps,map-to-dma-channel = <0x0>;
1513
+
};
1514
+
1515
+
queue1 {
1516
+
snps,dcb-algorithm;
1517
+
snps,map-to-dma-channel = <0x0>;
1518
+
};
1519
+
1520
+
queue2 {
1521
+
snps,dcb-algorithm;
1522
+
snps,map-to-dma-channel = <0x0>;
1523
+
};
1524
+
1525
+
queue3 {
1526
+
snps,dcb-algorithm;
1527
+
snps,map-to-dma-channel = <0x0>;
1528
+
};
1529
+
};
1530
+
1531
+
mtl_tx_setup: tx-queues-config {
1532
+
snps,tx-queues-to-use = <4>;
1533
+
snps,tx-sched-wrr;
1534
+
1535
+
queue0 {
1536
+
snps,dcb-algorithm;
1537
+
snps,priority = <0x0>;
1538
+
snps,weight = <0x10>;
1539
+
};
1540
+
1541
+
queue1 {
1542
+
snps,dcb-algorithm;
1543
+
snps,priority = <0x1>;
1544
+
snps,weight = <0x11>;
1545
+
};
1546
+
1547
+
queue2 {
1548
+
snps,dcb-algorithm;
1549
+
snps,priority = <0x2>;
1550
+
snps,weight = <0x12>;
1551
+
};
1552
+
1553
+
queue3 {
1554
+
snps,dcb-algorithm;
1555
+
snps,priority = <0x3>;
1556
+
snps,weight = <0x13>;
1557
+
};
1558
+
};
1648
1559
};
1649
1560
1650
1561
xhci1: usb@11200000 {
···
1889
1606
status = "disabled";
1890
1607
};
1891
1608
1609
+
pcie: pcie@112f0000 {
1610
+
compatible = "mediatek,mt8188-pcie", "mediatek,mt8192-pcie";
1611
+
reg = <0 0x112f0000 0 0x2000>;
1612
+
reg-names = "pcie-mac";
1613
+
ranges = <0x82000000 0 0x20000000 0 0x20000000 0 0x4000000>;
1614
+
bus-range = <0 0xff>;
1615
+
device_type = "pci";
1616
+
linux,pci-domain = <0>;
1617
+
#address-cells = <3>;
1618
+
#size-cells = <2>;
1619
+
1620
+
clocks = <&infracfg_ao CLK_INFRA_AO_PCIE_PL_P_250M_P0>,
1621
+
<&infracfg_ao CLK_INFRA_AO_PCIE_TL_26M>,
1622
+
<&infracfg_ao CLK_INFRA_AO_PCIE_TL_96M>,
1623
+
<&infracfg_ao CLK_INFRA_AO_PCIE_TL_32K>,
1624
+
<&infracfg_ao CLK_INFRA_AO_PCIE_PERI_26M>,
1625
+
<&pericfg_ao CLK_PERI_AO_PCIE_P0_FMEM>;
1626
+
clock-names = "pl_250m", "tl_26m", "tl_96m", "tl_32k",
1627
+
"peri_26m", "peri_mem";
1628
+
1629
+
#interrupt-cells = <1>;
1630
+
interrupts = <GIC_SPI 791 IRQ_TYPE_LEVEL_HIGH 0>;
1631
+
interrupt-map = <0 0 0 1 &pcie_intc 0>,
1632
+
<0 0 0 2 &pcie_intc 1>,
1633
+
<0 0 0 3 &pcie_intc 2>,
1634
+
<0 0 0 4 &pcie_intc 3>;
1635
+
interrupt-map-mask = <0 0 0 7>;
1636
+
1637
+
iommu-map = <0 &infra_iommu IFR_IOMMU_PORT_PCIE_0 0xffff>;
1638
+
iommu-map-mask = <0>;
1639
+
1640
+
phys = <&pcieport PHY_TYPE_PCIE>;
1641
+
phy-names = "pcie-phy";
1642
+
1643
+
power-domains = <&spm MT8188_POWER_DOMAIN_PEXTP_MAC_P0>;
1644
+
1645
+
resets = <&watchdog MT8188_TOPRGU_PCIE_SW_RST>;
1646
+
reset-names = "mac";
1647
+
1648
+
status = "disabled";
1649
+
1650
+
pcie_intc: interrupt-controller {
1651
+
#address-cells = <0>;
1652
+
#interrupt-cells = <1>;
1653
+
interrupt-controller;
1654
+
};
1655
+
};
1656
+
1892
1657
nor_flash: spi@1132c000 {
1893
1658
compatible = "mediatek,mt8188-nor", "mediatek,mt8186-nor";
1894
1659
reg = <0 0x1132c000 0 0x1000>;
···
1946
1615
clock-names = "spi", "sf", "axi";
1947
1616
assigned-clocks = <&topckgen CLK_TOP_SPINOR>;
1948
1617
interrupts = <GIC_SPI 825 IRQ_TYPE_LEVEL_HIGH 0>;
1618
+
#address-cells = <1>;
1619
+
#size-cells = <0>;
1620
+
status = "disabled";
1621
+
};
1622
+
1623
+
pciephy: t-phy@11c20700 {
1624
+
compatible = "mediatek,mt8188-tphy", "mediatek,generic-tphy-v3";
1625
+
ranges = <0 0 0x11c20700 0x700>;
1626
+
#address-cells = <1>;
1627
+
#size-cells = <1>;
1628
+
power-domains = <&spm MT8188_POWER_DOMAIN_PEXTP_PHY_TOP>;
1629
+
status = "disabled";
1630
+
1631
+
pcieport: pcie-phy@0 {
1632
+
reg = <0 0x700>;
1633
+
clocks = <&topckgen CLK_TOP_CFGREG_F_PCIE_PHY_REF>;
1634
+
clock-names = "ref";
1635
+
#phy-cells = <1>;
1636
+
};
1637
+
};
1638
+
1639
+
mipi_tx_config0: dsi-phy@11c80000 {
1640
+
compatible = "mediatek,mt8188-mipi-tx", "mediatek,mt8183-mipi-tx";
1641
+
reg = <0 0x11c80000 0 0x1000>;
1642
+
clocks = <&clk26m>;
1643
+
clock-output-names = "mipi_tx0_pll";
1644
+
#clock-cells = <0>;
1645
+
#phy-cells = <0>;
1646
+
status = "disabled";
1647
+
};
1648
+
1649
+
mipi_tx_config1: dsi-phy@11c90000 {
1650
+
compatible = "mediatek,mt8188-mipi-tx", "mediatek,mt8183-mipi-tx";
1651
+
reg = <0 0x11c90000 0 0x1000>;
1652
+
clocks = <&clk26m>;
1653
+
clock-output-names = "mipi_tx0_pll";
1654
+
#clock-cells = <0>;
1655
+
#phy-cells = <0>;
1949
1656
status = "disabled";
1950
1657
};
1951
1658
···
2058
1689
<&clk26m>;
2059
1690
clock-names = "ref", "da_ref";
2060
1691
#phy-cells = <1>;
2061
-
status = "disabled";
2062
1692
};
2063
1693
};
2064
1694
···
2117
1749
#address-cells = <1>;
2118
1750
#size-cells = <1>;
2119
1751
1752
+
dp_calib_data: dp-calib@1a0 {
1753
+
reg = <0x1a0 0xc>;
1754
+
};
1755
+
2120
1756
lvts_efuse_data1: lvts1-calib@1ac {
2121
1757
reg = <0x1ac 0x40>;
1758
+
};
1759
+
1760
+
socinfo-data1@7a0 {
1761
+
reg = <0x7a0 0x4>;
1762
+
};
1763
+
1764
+
socinfo-data2@7e0 {
1765
+
reg = <0x7e0 0x4>;
2122
1766
};
2123
1767
};
2124
1768
···
2158
1778
#clock-cells = <1>;
2159
1779
};
2160
1780
2161
-
vppsys0: clock-controller@14000000 {
2162
-
compatible = "mediatek,mt8188-vppsys0";
1781
+
vppsys0: syscon@14000000 {
1782
+
compatible = "mediatek,mt8188-vppsys0", "syscon";
2163
1783
reg = <0 0x14000000 0 0x1000>;
2164
1784
#clock-cells = <1>;
1785
+
};
1786
+
1787
+
vpp_smi_common: smi@14012000 {
1788
+
compatible = "mediatek,mt8188-smi-common-vpp";
1789
+
reg = <0 0x14012000 0 0x1000>;
1790
+
clocks = <&vppsys0 CLK_VPP0_SMI_COMMON_LARB4>,
1791
+
<&vppsys0 CLK_VPP0_SMI_SUB_COMMON_REORDER>;
1792
+
clock-names = "apb", "smi";
1793
+
power-domains = <&spm MT8188_POWER_DOMAIN_VPPSYS0>;
1794
+
};
1795
+
1796
+
larb4: smi@14013000 {
1797
+
compatible = "mediatek,mt8188-smi-larb";
1798
+
reg = <0 0x14013000 0 0x1000>;
1799
+
clocks = <&vppsys0 CLK_VPP0_SMI_COMMON_LARB4>,
1800
+
<&vppsys0 CLK_VPP0_SMI_COMMON_LARB4>;
1801
+
clock-names = "apb", "smi";
1802
+
power-domains = <&spm MT8188_POWER_DOMAIN_VPPSYS0>;
1803
+
mediatek,larb-id = <SMI_L4_ID>;
1804
+
mediatek,smi = <&vpp_smi_common>;
1805
+
};
1806
+
1807
+
vpp_iommu: iommu@14018000 {
1808
+
compatible = "mediatek,mt8188-iommu-vpp";
1809
+
reg = <0 0x14018000 0 0x5000>;
1810
+
clocks = <&vppsys0 CLK_VPP0_SMI_IOMMU>;
1811
+
clock-names = "bclk";
1812
+
interrupts = <GIC_SPI 594 IRQ_TYPE_LEVEL_HIGH 0>;
1813
+
power-domains = <&spm MT8188_POWER_DOMAIN_VPPSYS0>;
1814
+
#iommu-cells = <1>;
1815
+
mediatek,larbs = <&larb1 &larb3 &larb4 &larb6 &larb7 &larb23>;
2165
1816
};
2166
1817
2167
1818
wpesys: clock-controller@14e00000 {
···
2207
1796
#clock-cells = <1>;
2208
1797
};
2209
1798
2210
-
vppsys1: clock-controller@14f00000 {
2211
-
compatible = "mediatek,mt8188-vppsys1";
1799
+
larb7: smi@14e04000 {
1800
+
compatible = "mediatek,mt8188-smi-larb";
1801
+
reg = <0 0x14e04000 0 0x1000>;
1802
+
clocks = <&wpesys CLK_WPE_TOP_SMI_LARB7>,
1803
+
<&wpesys CLK_WPE_TOP_SMI_LARB7>;
1804
+
clock-names = "apb", "smi";
1805
+
power-domains = <&spm MT8188_POWER_DOMAIN_WPE>;
1806
+
mediatek,larb-id = <SMI_L7_ID>;
1807
+
mediatek,smi = <&vpp_smi_common>;
1808
+
};
1809
+
1810
+
vppsys1: syscon@14f00000 {
1811
+
compatible = "mediatek,mt8188-vppsys1", "syscon";
2212
1812
reg = <0 0x14f00000 0 0x1000>;
2213
1813
#clock-cells = <1>;
1814
+
};
1815
+
1816
+
larb5: smi@14f02000 {
1817
+
compatible = "mediatek,mt8188-smi-larb";
1818
+
reg = <0 0x14f02000 0 0x1000>;
1819
+
clocks = <&vppsys1 CLK_VPP1_GALS5>,
1820
+
<&vppsys1 CLK_VPP1_LARB5>;
1821
+
clock-names = "apb", "smi";
1822
+
power-domains = <&spm MT8188_POWER_DOMAIN_VPPSYS1>;
1823
+
mediatek,larb-id = <SMI_L5_ID>;
1824
+
mediatek,smi = <&vdo_smi_common>;
1825
+
};
1826
+
1827
+
larb6: smi@14f03000 {
1828
+
compatible = "mediatek,mt8188-smi-larb";
1829
+
reg = <0 0x14f03000 0 0x1000>;
1830
+
clocks = <&vppsys1 CLK_VPP1_GALS6>,
1831
+
<&vppsys1 CLK_VPP1_LARB6>;
1832
+
clock-names = "apb", "smi";
1833
+
power-domains = <&spm MT8188_POWER_DOMAIN_VPPSYS1>;
1834
+
mediatek,larb-id = <SMI_L6_ID>;
1835
+
mediatek,smi = <&vpp_smi_common>;
2214
1836
};
2215
1837
2216
1838
imgsys: clock-controller@15000000 {
···
2324
1880
#clock-cells = <1>;
2325
1881
};
2326
1882
1883
+
video_decoder: video-decoder@18000000 {
1884
+
compatible = "mediatek,mt8188-vcodec-dec";
1885
+
reg = <0 0x18000000 0 0x1000>, <0 0x18004000 0 0x1000>;
1886
+
ranges = <0 0 0 0x18000000 0 0x26000>;
1887
+
iommus = <&vpp_iommu M4U_PORT_L23_HW_VDEC_UFO_ENC_EXT>;
1888
+
#address-cells = <2>;
1889
+
#size-cells = <2>;
1890
+
mediatek,scp = <&scp>;
1891
+
1892
+
video-codec@10000 {
1893
+
compatible = "mediatek,mtk-vcodec-lat";
1894
+
reg = <0 0x10000 0 0x800>;
1895
+
assigned-clocks = <&topckgen CLK_TOP_VDEC>;
1896
+
assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL_D6>;
1897
+
clocks = <&topckgen CLK_TOP_VDEC>,
1898
+
<&vdecsys_soc CLK_VDEC1_SOC_VDEC>,
1899
+
<&vdecsys_soc CLK_VDEC1_SOC_LAT>,
1900
+
<&topckgen CLK_TOP_UNIVPLL_D6>;
1901
+
clock-names = "sel", "vdec", "lat", "top";
1902
+
interrupts = <GIC_SPI 708 IRQ_TYPE_LEVEL_HIGH 0>;
1903
+
iommus = <&vpp_iommu M4U_PORT_L23_HW_VDEC_LAT0_VLD_EXT>,
1904
+
<&vpp_iommu M4U_PORT_L23_HW_VDEC_LAT0_VLD2_EXT>,
1905
+
<&vpp_iommu M4U_PORT_L23_HW_VDEC_LAT0_AVC_MV_EXT>,
1906
+
<&vpp_iommu M4U_PORT_L23_HW_VDEC_LAT0_PRED_RD_EXT>,
1907
+
<&vpp_iommu M4U_PORT_L23_HW_VDEC_LAT0_TILE_EXT>,
1908
+
<&vpp_iommu M4U_PORT_L23_HW_VDEC_LAT0_WDMA_EXT>,
1909
+
<&vpp_iommu M4U_PORT_L23_HW_VDEC_UFO_ENC_EXT>,
1910
+
<&vpp_iommu M4U_PORT_L23_HW_VDEC_UFO_ENC_EXT_C>,
1911
+
<&vpp_iommu M4U_PORT_L23_HW_VDEC_MC_EXT_C>;
1912
+
power-domains = <&spm MT8188_POWER_DOMAIN_VDEC0>;
1913
+
};
1914
+
1915
+
video-codec@25000 {
1916
+
compatible = "mediatek,mtk-vcodec-core";
1917
+
reg = <0 0x25000 0 0x1000>;
1918
+
assigned-clocks = <&topckgen CLK_TOP_VDEC>;
1919
+
assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL_D6>;
1920
+
clocks = <&topckgen CLK_TOP_VDEC>,
1921
+
<&vdecsys CLK_VDEC2_VDEC>,
1922
+
<&vdecsys CLK_VDEC2_LAT>,
1923
+
<&topckgen CLK_TOP_UNIVPLL_D6>;
1924
+
clock-names = "sel", "vdec", "lat", "top";
1925
+
interrupts = <GIC_SPI 707 IRQ_TYPE_LEVEL_HIGH 0>;
1926
+
iommus = <&vdo_iommu M4U_PORT_L21_HW_VDEC_MC_EXT>,
1927
+
<&vdo_iommu M4U_PORT_L21_HW_VDEC_UFO_EXT>,
1928
+
<&vdo_iommu M4U_PORT_L21_HW_VDEC_PP_EXT>,
1929
+
<&vdo_iommu M4U_PORT_L21_HW_VDEC_PRED_RD_EXT>,
1930
+
<&vdo_iommu M4U_PORT_L21_HW_VDEC_PRED_WR_EXT>,
1931
+
<&vdo_iommu M4U_PORT_L21_HW_VDEC_PPWRAP_EXT>,
1932
+
<&vdo_iommu M4U_PORT_L21_HW_VDEC_TILE_EXT>,
1933
+
<&vdo_iommu M4U_PORT_L21_HW_VDEC_VLD_EXT>,
1934
+
<&vdo_iommu M4U_PORT_L21_HW_VDEC_VLD2_EXT>,
1935
+
<&vdo_iommu M4U_PORT_L21_HW_VDEC_AVC_MV_EXT>,
1936
+
<&vdo_iommu M4U_PORT_L21_HW_VDEC_UFO_EXT_C>;
1937
+
power-domains = <&spm MT8188_POWER_DOMAIN_VDEC1>;
1938
+
};
1939
+
};
1940
+
1941
+
larb23: smi@1800d000 {
1942
+
compatible = "mediatek,mt8188-smi-larb";
1943
+
reg = <0 0x1800d000 0 0x1000>;
1944
+
clocks = <&vdecsys_soc CLK_VDEC1_SOC_LARB1>,
1945
+
<&vdecsys_soc CLK_VDEC1_SOC_LARB1>;
1946
+
clock-names = "apb", "smi";
1947
+
power-domains = <&spm MT8188_POWER_DOMAIN_VDEC0>;
1948
+
mediatek,larb-id = <SMI_L23_ID>;
1949
+
mediatek,smi = <&vpp_smi_common>;
1950
+
};
1951
+
2327
1952
vdecsys_soc: clock-controller@1800f000 {
2328
1953
compatible = "mediatek,mt8188-vdecsys-soc";
2329
1954
reg = <0 0x1800f000 0 0x1000>;
2330
1955
#clock-cells = <1>;
1956
+
};
1957
+
1958
+
larb21: smi@1802e000 {
1959
+
compatible = "mediatek,mt8188-smi-larb";
1960
+
reg = <0 0x1802e000 0 0x1000>;
1961
+
clocks = <&vdecsys CLK_VDEC2_LARB1>,
1962
+
<&vdecsys CLK_VDEC2_LARB1>;
1963
+
clock-names = "apb", "smi";
1964
+
power-domains = <&spm MT8188_POWER_DOMAIN_VDEC1>;
1965
+
mediatek,larb-id = <SMI_L21_ID>;
1966
+
mediatek,smi = <&vdo_smi_common>;
2331
1967
};
2332
1968
2333
1969
vdecsys: clock-controller@1802f000 {
···
2422
1898
#clock-cells = <1>;
2423
1899
};
2424
1900
1901
+
larb19: smi@1a010000 {
1902
+
compatible = "mediatek,mt8188-smi-larb";
1903
+
reg = <0 0x1a010000 0 0x1000>;
1904
+
clocks = <&vencsys CLK_VENC1_VENC>,
1905
+
<&vencsys CLK_VENC1_VENC>;
1906
+
clock-names = "apb", "smi";
1907
+
power-domains = <&spm MT8188_POWER_DOMAIN_VENC>;
1908
+
mediatek,larb-id = <SMI_L19_ID>;
1909
+
mediatek,smi = <&vdo_smi_common>;
1910
+
};
1911
+
1912
+
video_encoder: video-encoder@1a020000 {
1913
+
compatible = "mediatek,mt8188-vcodec-enc";
1914
+
reg = <0 0x1a020000 0 0x10000>;
1915
+
#address-cells = <2>;
1916
+
#size-cells = <2>;
1917
+
assigned-clocks = <&topckgen CLK_TOP_VENC>;
1918
+
assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL_D4>;
1919
+
clocks = <&vencsys CLK_VENC1_VENC>;
1920
+
clock-names = "venc_sel";
1921
+
interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH 0>;
1922
+
iommus = <&vdo_iommu M4U_PORT_L19_VENC_RCPU>,
1923
+
<&vdo_iommu M4U_PORT_L19_VENC_REC>,
1924
+
<&vdo_iommu M4U_PORT_L19_VENC_BSDMA>,
1925
+
<&vdo_iommu M4U_PORT_L19_VENC_SV_COMV>,
1926
+
<&vdo_iommu M4U_PORT_L19_VENC_RD_COMV>,
1927
+
<&vdo_iommu M4U_PORT_L19_VENC_CUR_LUMA>,
1928
+
<&vdo_iommu M4U_PORT_L19_VENC_CUR_CHROMA>,
1929
+
<&vdo_iommu M4U_PORT_L19_VENC_REF_LUMA>,
1930
+
<&vdo_iommu M4U_PORT_L19_VENC_REF_CHROMA>,
1931
+
<&vdo_iommu M4U_PORT_L19_VENC_SUB_W_LUMA>,
1932
+
<&vdo_iommu M4U_PORT_L19_VENC_SUB_R_LUMA>;
1933
+
power-domains = <&spm MT8188_POWER_DOMAIN_VENC>;
1934
+
mediatek,scp = <&scp>;
1935
+
};
1936
+
1937
+
jpeg_encoder: jpeg-encoder@1a030000 {
1938
+
compatible = "mediatek,mt8188-jpgenc", "mediatek,mtk-jpgenc";
1939
+
reg = <0 0x1a030000 0 0x10000>;
1940
+
clocks = <&vencsys CLK_VENC1_JPGENC>;
1941
+
clock-names = "jpgenc";
1942
+
interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH 0>;
1943
+
iommus = <&vdo_iommu M4U_PORT_L19_JPGENC_Y_RDMA>,
1944
+
<&vdo_iommu M4U_PORT_L19_JPGENC_C_RDMA>,
1945
+
<&vdo_iommu M4U_PORT_L19_JPGENC_Q_TABLE>,
1946
+
<&vdo_iommu M4U_PORT_L19_JPGENC_BSDMA>;
1947
+
power-domains = <&spm MT8188_POWER_DOMAIN_VENC>;
1948
+
};
1949
+
1950
+
jpeg_decoder: jpeg-decoder@1a040000 {
1951
+
compatible = "mediatek,mt8188-jpgdec", "mediatek,mt2701-jpgdec";
1952
+
reg = <0 0x1a040000 0 0x10000>;
1953
+
clocks = <&vencsys CLK_VENC1_LARB>,
1954
+
<&vencsys CLK_VENC1_JPGDEC>;
1955
+
clock-names = "jpgdec-smi", "jpgdec";
1956
+
interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH 0>;
1957
+
iommus = <&vdo_iommu M4U_PORT_L19_JPGDEC_WDMA_0>,
1958
+
<&vdo_iommu M4U_PORT_L19_JPGDEC_BSDMA_0>,
1959
+
<&vdo_iommu M4U_PORT_L19_JPGDEC_WDMA_1>,
1960
+
<&vdo_iommu M4U_PORT_L19_JPGDEC_BSDMA_1>,
1961
+
<&vdo_iommu M4U_PORT_L19_JPGDEC_HUFF_OFFSET_1>,
1962
+
<&vdo_iommu M4U_PORT_L19_JPGDEC_HUFF_OFFSET_0>;
1963
+
power-domains = <&spm MT8188_POWER_DOMAIN_VDEC0>;
1964
+
};
1965
+
1966
+
ovl0: ovl@1c000000 {
1967
+
compatible = "mediatek,mt8188-disp-ovl", "mediatek,mt8183-disp-ovl";
1968
+
reg = <0 0x1c000000 0 0x1000>;
1969
+
clocks = <&vdosys0 CLK_VDO0_DISP_OVL0>;
1970
+
interrupts = <GIC_SPI 636 IRQ_TYPE_LEVEL_HIGH 0>;
1971
+
iommus = <&vdo_iommu M4U_PORT_L0_DISP_OVL0_RDMA0>;
1972
+
power-domains = <&spm MT8188_POWER_DOMAIN_VDOSYS0>;
1973
+
mediatek,gce-client-reg = <&gce0 SUBSYS_1c00XXXX 0x0000 0x1000>;
1974
+
};
1975
+
1976
+
rdma0: rdma@1c002000 {
1977
+
compatible = "mediatek,mt8188-disp-rdma", "mediatek,mt8195-disp-rdma";
1978
+
reg = <0 0x1c002000 0 0x1000>;
1979
+
clocks = <&vdosys0 CLK_VDO0_DISP_RDMA0>;
1980
+
interrupts = <GIC_SPI 638 IRQ_TYPE_LEVEL_HIGH 0>;
1981
+
iommus = <&vdo_iommu M4U_PORT_L1_DISP_RDMA0>;
1982
+
power-domains = <&spm MT8188_POWER_DOMAIN_VDOSYS0>;
1983
+
mediatek,gce-client-reg = <&gce0 SUBSYS_1c00XXXX 0x2000 0x1000>;
1984
+
};
1985
+
1986
+
color0: color@1c003000 {
1987
+
compatible = "mediatek,mt8188-disp-color", "mediatek,mt8173-disp-color";
1988
+
reg = <0 0x1c003000 0 0x1000>;
1989
+
clocks = <&vdosys0 CLK_VDO0_DISP_COLOR0>;
1990
+
interrupts = <GIC_SPI 639 IRQ_TYPE_LEVEL_HIGH 0>;
1991
+
power-domains = <&spm MT8188_POWER_DOMAIN_VDOSYS0>;
1992
+
mediatek,gce-client-reg = <&gce0 SUBSYS_1c00XXXX 0x3000 0x1000>;
1993
+
};
1994
+
1995
+
ccorr0: ccorr@1c004000 {
1996
+
compatible = "mediatek,mt8188-disp-ccorr", "mediatek,mt8192-disp-ccorr";
1997
+
reg = <0 0x1c004000 0 0x1000>;
1998
+
clocks = <&vdosys0 CLK_VDO0_DISP_CCORR0>;
1999
+
interrupts = <GIC_SPI 640 IRQ_TYPE_LEVEL_HIGH 0>;
2000
+
power-domains = <&spm MT8188_POWER_DOMAIN_VDOSYS0>;
2001
+
mediatek,gce-client-reg = <&gce0 SUBSYS_1c00XXXX 0x4000 0x1000>;
2002
+
};
2003
+
2004
+
aal0: aal@1c005000 {
2005
+
compatible = "mediatek,mt8188-disp-aal", "mediatek,mt8183-disp-aal";
2006
+
reg = <0 0x1c005000 0 0x1000>;
2007
+
clocks = <&vdosys0 CLK_VDO0_DISP_AAL0>;
2008
+
interrupts = <GIC_SPI 641 IRQ_TYPE_LEVEL_HIGH 0>;
2009
+
power-domains = <&spm MT8188_POWER_DOMAIN_VDOSYS0>;
2010
+
mediatek,gce-client-reg = <&gce0 SUBSYS_1c00XXXX 0x5000 0x1000>;
2011
+
};
2012
+
2013
+
gamma0: gamma@1c006000 {
2014
+
compatible = "mediatek,mt8188-disp-gamma", "mediatek,mt8195-disp-gamma";
2015
+
reg = <0 0x1c006000 0 0x1000>;
2016
+
clocks = <&vdosys0 CLK_VDO0_DISP_GAMMA0>;
2017
+
interrupts = <GIC_SPI 642 IRQ_TYPE_LEVEL_HIGH 0>;
2018
+
power-domains = <&spm MT8188_POWER_DOMAIN_VDOSYS0>;
2019
+
mediatek,gce-client-reg = <&gce0 SUBSYS_1c00XXXX 0x6000 0x1000>;
2020
+
};
2021
+
2022
+
dither0: dither@1c007000 {
2023
+
compatible = "mediatek,mt8188-disp-dither", "mediatek,mt8183-disp-dither";
2024
+
reg = <0 0x1c007000 0 0x1000>;
2025
+
clocks = <&vdosys0 CLK_VDO0_DISP_DITHER0>;
2026
+
interrupts = <GIC_SPI 643 IRQ_TYPE_LEVEL_HIGH 0>;
2027
+
power-domains = <&spm MT8188_POWER_DOMAIN_VDOSYS0>;
2028
+
mediatek,gce-client-reg = <&gce0 SUBSYS_1c00XXXX 0x7000 0x1000>;
2029
+
};
2030
+
2031
+
disp_dsi0: dsi@1c008000 {
2032
+
compatible = "mediatek,mt8188-dsi";
2033
+
reg = <0 0x1c008000 0 0x1000>;
2034
+
clocks = <&vdosys0 CLK_VDO0_DSI0>,
2035
+
<&vdosys0 CLK_VDO0_DSI0_DSI>,
2036
+
<&mipi_tx_config0>;
2037
+
clock-names = "engine", "digital", "hs";
2038
+
interrupts = <GIC_SPI 644 IRQ_TYPE_LEVEL_HIGH 0>;
2039
+
phys = <&mipi_tx_config0>;
2040
+
phy-names = "dphy";
2041
+
power-domains = <&spm MT8188_POWER_DOMAIN_VDOSYS0>;
2042
+
resets = <&vdosys0 MT8188_VDO0_RST_DSI0>;
2043
+
status = "disabled";
2044
+
};
2045
+
2046
+
disp_dsi1: dsi@1c012000 {
2047
+
compatible = "mediatek,mt8188-dsi";
2048
+
reg = <0 0x1c012000 0 0x1000>;
2049
+
clocks = <&vdosys0 CLK_VDO0_DSI1>,
2050
+
<&vdosys0 CLK_VDO0_DSI1_DSI>,
2051
+
<&mipi_tx_config1>;
2052
+
clock-names = "engine", "digital", "hs";
2053
+
interrupts = <GIC_SPI 654 IRQ_TYPE_LEVEL_HIGH 0>;
2054
+
phys = <&mipi_tx_config1>;
2055
+
phy-names = "dphy";
2056
+
power-domains = <&spm MT8188_POWER_DOMAIN_VDOSYS0>;
2057
+
resets = <&vdosys0 MT8188_VDO0_RST_DSI1>;
2058
+
status = "disabled";
2059
+
};
2060
+
2061
+
dp_intf0: dp-intf@1c015000 {
2062
+
compatible = "mediatek,mt8188-dp-intf";
2063
+
reg = <0 0x1c015000 0 0x1000>;
2064
+
clocks = <&vdosys0 CLK_VDO0_DP_INTF0_DP_INTF>,
2065
+
<&vdosys0 CLK_VDO0_DP_INTF0>,
2066
+
<&apmixedsys CLK_APMIXED_TVDPLL1>;
2067
+
clock-names = "pixel", "engine", "pll";
2068
+
interrupts = <GIC_SPI 657 IRQ_TYPE_LEVEL_HIGH 0>;
2069
+
power-domains = <&spm MT8188_POWER_DOMAIN_VDOSYS0>;
2070
+
status = "disabled";
2071
+
};
2072
+
2073
+
mutex0: mutex@1c016000 {
2074
+
compatible = "mediatek,mt8188-disp-mutex";
2075
+
reg = <0 0x1c016000 0 0x1000>;
2076
+
clocks = <&vdosys0 CLK_VDO0_DISP_MUTEX0>;
2077
+
interrupts = <GIC_SPI 658 IRQ_TYPE_LEVEL_HIGH 0>;
2078
+
power-domains = <&spm MT8188_POWER_DOMAIN_VDOSYS0>;
2079
+
mediatek,gce-client-reg = <&gce0 SUBSYS_1c01XXXX 0x6000 0x1000>;
2080
+
mediatek,gce-events = <CMDQ_EVENT_VDO0_DISP_STREAM_DONE_0>;
2081
+
};
2082
+
2083
+
postmask0: postmask@1c01a000 {
2084
+
compatible = "mediatek,mt8188-disp-postmask",
2085
+
"mediatek,mt8192-disp-postmask";
2086
+
reg = <0 0x1c01a000 0 0x1000>;
2087
+
clocks = <&vdosys0 CLK_VDO0_DISP_POSTMASK0>;
2088
+
interrupts = <GIC_SPI 661 IRQ_TYPE_LEVEL_HIGH 0>;
2089
+
power-domains = <&spm MT8188_POWER_DOMAIN_VDOSYS0>;
2090
+
mediatek,gce-client-reg = <&gce0 SUBSYS_1c01XXXX 0xa000 0x1000>;
2091
+
};
2092
+
2425
2093
vdosys0: syscon@1c01d000 {
2426
2094
compatible = "mediatek,mt8188-vdosys0", "syscon";
2427
2095
reg = <0 0x1c01d000 0 0x1000>;
2428
2096
#clock-cells = <1>;
2097
+
#reset-cells = <1>;
2429
2098
mboxes = <&gce0 0 CMDQ_THR_PRIO_4>;
2430
2099
mediatek,gce-client-reg = <&gce0 SUBSYS_1c01XXXX 0xd000 0x1000>;
2100
+
};
2101
+
2102
+
larb0: smi@1c022000 {
2103
+
compatible = "mediatek,mt8188-smi-larb";
2104
+
reg = <0 0x1c022000 0 0x1000>;
2105
+
clocks = <&vdosys0 CLK_VDO0_SMI_LARB>,
2106
+
<&vdosys0 CLK_VDO0_SMI_LARB>;
2107
+
clock-names = "apb", "smi";
2108
+
power-domains = <&spm MT8188_POWER_DOMAIN_VDOSYS0>;
2109
+
mediatek,larb-id = <SMI_L0_ID>;
2110
+
mediatek,smi = <&vdo_smi_common>;
2111
+
};
2112
+
2113
+
larb1: smi@1c023000 {
2114
+
compatible = "mediatek,mt8188-smi-larb";
2115
+
reg = <0 0x1c023000 0 0x1000>;
2116
+
clocks = <&vdosys0 CLK_VDO0_SMI_LARB>,
2117
+
<&vdosys0 CLK_VDO0_SMI_LARB>;
2118
+
clock-names = "apb", "smi";
2119
+
power-domains = <&spm MT8188_POWER_DOMAIN_VDOSYS0>;
2120
+
mediatek,larb-id = <SMI_L1_ID>;
2121
+
mediatek,smi = <&vpp_smi_common>;
2122
+
};
2123
+
2124
+
vdo_smi_common: smi@1c024000 {
2125
+
compatible = "mediatek,mt8188-smi-common-vdo";
2126
+
reg = <0 0x1c024000 0 0x1000>;
2127
+
clocks = <&vdosys0 CLK_VDO0_SMI_COMMON>,
2128
+
<&vdosys0 CLK_VDO0_SMI_GALS>;
2129
+
clock-names = "apb", "smi";
2130
+
power-domains = <&spm MT8188_POWER_DOMAIN_VDOSYS0>;
2131
+
};
2132
+
2133
+
vdo_iommu: iommu@1c028000 {
2134
+
compatible = "mediatek,mt8188-iommu-vdo";
2135
+
reg = <0 0x1c028000 0 0x5000>;
2136
+
clocks = <&vdosys0 CLK_VDO0_SMI_IOMMU>;
2137
+
clock-names = "bclk";
2138
+
interrupts = <GIC_SPI 673 IRQ_TYPE_LEVEL_HIGH 0>;
2139
+
power-domains = <&spm MT8188_POWER_DOMAIN_VDOSYS0>;
2140
+
#iommu-cells = <1>;
2141
+
mediatek,larbs = <&larb0 &larb2 &larb5 &larb19 &larb21>;
2431
2142
};
2432
2143
2433
2144
vdosys1: syscon@1c100000 {
···
2672
1913
#reset-cells = <1>;
2673
1914
mboxes = <&gce0 1 CMDQ_THR_PRIO_4>;
2674
1915
mediatek,gce-client-reg = <&gce0 SUBSYS_1c10XXXX 0 0x1000>;
1916
+
};
1917
+
1918
+
mutex1: mutex@1c101000 {
1919
+
compatible = "mediatek,mt8188-disp-mutex";
1920
+
reg = <0 0x1c101000 0 0x1000>;
1921
+
clocks = <&vdosys1 CLK_VDO1_DISP_MUTEX>;
1922
+
interrupts = <GIC_SPI 494 IRQ_TYPE_LEVEL_HIGH 0>;
1923
+
power-domains = <&spm MT8188_POWER_DOMAIN_VDOSYS1>;
1924
+
mediatek,gce-client-reg = <&gce0 SUBSYS_1c10XXXX 0x1000 0x1000>;
1925
+
mediatek,gce-events = <CMDQ_EVENT_VDO1_STREAM_DONE_ENG_0>;
1926
+
};
1927
+
1928
+
larb2: smi@1c102000 {
1929
+
compatible = "mediatek,mt8188-smi-larb";
1930
+
reg = <0 0x1c102000 0 0x1000>;
1931
+
clocks = <&vdosys1 CLK_VDO1_SMI_LARB2>,
1932
+
<&vdosys1 CLK_VDO1_SMI_LARB2>;
1933
+
clock-names = "apb", "smi";
1934
+
power-domains = <&spm MT8188_POWER_DOMAIN_VDOSYS1>;
1935
+
mediatek,larb-id = <SMI_L2_ID>;
1936
+
mediatek,smi = <&vdo_smi_common>;
1937
+
};
1938
+
1939
+
larb3: smi@1c103000 {
1940
+
compatible = "mediatek,mt8188-smi-larb";
1941
+
reg = <0 0x1c103000 0 0x1000>;
1942
+
clocks = <&vdosys1 CLK_VDO1_SMI_LARB3>,
1943
+
<&vdosys1 CLK_VDO1_SMI_LARB3>;
1944
+
clock-names = "apb", "smi";
1945
+
power-domains = <&spm MT8188_POWER_DOMAIN_VDOSYS1>;
1946
+
mediatek,larb-id = <SMI_L3_ID>;
1947
+
mediatek,smi = <&vpp_smi_common>;
1948
+
};
1949
+
1950
+
vdo1_rdma0: rdma@1c104000 {
1951
+
compatible = "mediatek,mt8188-vdo1-rdma", "mediatek,mt8195-vdo1-rdma";
1952
+
reg = <0 0x1c104000 0 0x1000>;
1953
+
clocks = <&vdosys1 CLK_VDO1_MDP_RDMA0>;
1954
+
interrupts = <GIC_SPI 495 IRQ_TYPE_LEVEL_HIGH 0>;
1955
+
iommus = <&vdo_iommu M4U_PORT_L2_MDP_RDMA0>;
1956
+
power-domains = <&spm MT8188_POWER_DOMAIN_VDOSYS1>;
1957
+
#dma-cells = <1>;
1958
+
mediatek,gce-client-reg = <&gce0 SUBSYS_1c10XXXX 0x4000 0x1000>;
1959
+
};
1960
+
1961
+
vdo1_rdma1: rdma@1c105000 {
1962
+
compatible = "mediatek,mt8188-vdo1-rdma", "mediatek,mt8195-vdo1-rdma";
1963
+
reg = <0 0x1c105000 0 0x1000>;
1964
+
clocks = <&vdosys1 CLK_VDO1_MDP_RDMA1>;
1965
+
interrupts = <GIC_SPI 496 IRQ_TYPE_LEVEL_HIGH 0>;
1966
+
iommus = <&vpp_iommu M4U_PORT_L3_MDP_RDMA1>;
1967
+
power-domains = <&spm MT8188_POWER_DOMAIN_VDOSYS1>;
1968
+
#dma-cells = <1>;
1969
+
mediatek,gce-client-reg = <&gce0 SUBSYS_1c10XXXX 0x5000 0x1000>;
1970
+
};
1971
+
1972
+
vdo1_rdma2: rdma@1c106000 {
1973
+
compatible = "mediatek,mt8188-vdo1-rdma", "mediatek,mt8195-vdo1-rdma";
1974
+
reg = <0 0x1c106000 0 0x1000>;
1975
+
clocks = <&vdosys1 CLK_VDO1_MDP_RDMA2>;
1976
+
interrupts = <GIC_SPI 497 IRQ_TYPE_LEVEL_HIGH 0>;
1977
+
iommus = <&vdo_iommu M4U_PORT_L2_MDP_RDMA2>;
1978
+
power-domains = <&spm MT8188_POWER_DOMAIN_VDOSYS1>;
1979
+
#dma-cells = <1>;
1980
+
mediatek,gce-client-reg = <&gce0 SUBSYS_1c10XXXX 0x6000 0x1000>;
1981
+
};
1982
+
1983
+
vdo1_rdma3: rdma@1c107000 {
1984
+
compatible = "mediatek,mt8188-vdo1-rdma", "mediatek,mt8195-vdo1-rdma";
1985
+
reg = <0 0x1c107000 0 0x1000>;
1986
+
clocks = <&vdosys1 CLK_VDO1_MDP_RDMA3>;
1987
+
interrupts = <GIC_SPI 498 IRQ_TYPE_LEVEL_HIGH 0>;
1988
+
iommus = <&vpp_iommu M4U_PORT_L3_MDP_RDMA3>;
1989
+
power-domains = <&spm MT8188_POWER_DOMAIN_VDOSYS1>;
1990
+
#dma-cells = <1>;
1991
+
mediatek,gce-client-reg = <&gce0 SUBSYS_1c10XXXX 0x7000 0x1000>;
1992
+
};
1993
+
1994
+
vdo1_rdma4: rdma@1c108000 {
1995
+
compatible = "mediatek,mt8188-vdo1-rdma", "mediatek,mt8195-vdo1-rdma";
1996
+
reg = <0 0x1c108000 0 0x1000>;
1997
+
clocks = <&vdosys1 CLK_VDO1_MDP_RDMA4>;
1998
+
interrupts = <GIC_SPI 499 IRQ_TYPE_LEVEL_HIGH 0>;
1999
+
iommus = <&vdo_iommu M4U_PORT_L2_MDP_RDMA4>;
2000
+
power-domains = <&spm MT8188_POWER_DOMAIN_VDOSYS1>;
2001
+
#dma-cells = <1>;
2002
+
mediatek,gce-client-reg = <&gce0 SUBSYS_1c10XXXX 0x8000 0x1000>;
2003
+
};
2004
+
2005
+
vdo1_rdma5: rdma@1c109000 {
2006
+
compatible = "mediatek,mt8188-vdo1-rdma", "mediatek,mt8195-vdo1-rdma";
2007
+
reg = <0 0x1c109000 0 0x1000>;
2008
+
clocks = <&vdosys1 CLK_VDO1_MDP_RDMA5>;
2009
+
interrupts = <GIC_SPI 500 IRQ_TYPE_LEVEL_HIGH 0>;
2010
+
iommus = <&vpp_iommu M4U_PORT_L3_MDP_RDMA5>;
2011
+
power-domains = <&spm MT8188_POWER_DOMAIN_VDOSYS1>;
2012
+
#dma-cells = <1>;
2013
+
mediatek,gce-client-reg = <&gce0 SUBSYS_1c10XXXX 0x9000 0x1000>;
2014
+
};
2015
+
2016
+
vdo1_rdma6: rdma@1c10a000 {
2017
+
compatible = "mediatek,mt8188-vdo1-rdma", "mediatek,mt8195-vdo1-rdma";
2018
+
reg = <0 0x1c10a000 0 0x1000>;
2019
+
clocks = <&vdosys1 CLK_VDO1_MDP_RDMA6>;
2020
+
interrupts = <GIC_SPI 501 IRQ_TYPE_LEVEL_HIGH 0>;
2021
+
iommus = <&vdo_iommu M4U_PORT_L2_MDP_RDMA6>;
2022
+
power-domains = <&spm MT8188_POWER_DOMAIN_VDOSYS1>;
2023
+
#dma-cells = <1>;
2024
+
mediatek,gce-client-reg = <&gce0 SUBSYS_1c10XXXX 0xa000 0x1000>;
2025
+
};
2026
+
2027
+
vdo1_rdma7: rdma@1c10b000 {
2028
+
compatible = "mediatek,mt8188-vdo1-rdma", "mediatek,mt8195-vdo1-rdma";
2029
+
reg = <0 0x1c10b000 0 0x1000>;
2030
+
clocks = <&vdosys1 CLK_VDO1_MDP_RDMA7>;
2031
+
interrupts = <GIC_SPI 502 IRQ_TYPE_LEVEL_HIGH 0>;
2032
+
iommus = <&vpp_iommu M4U_PORT_L3_MDP_RDMA7>;
2033
+
power-domains = <&spm MT8188_POWER_DOMAIN_VDOSYS1>;
2034
+
#dma-cells = <1>;
2035
+
mediatek,gce-client-reg = <&gce0 SUBSYS_1c10XXXX 0xb000 0x1000>;
2036
+
};
2037
+
2038
+
merge1: merge@1c10c000 {
2039
+
compatible = "mediatek,mt8188-disp-merge", "mediatek,mt8195-disp-merge";
2040
+
reg = <0 0x1c10c000 0 0x1000>;
2041
+
clocks = <&vdosys1 CLK_VDO1_VPP_MERGE0>,
2042
+
<&vdosys1 CLK_VDO1_MERGE0_DL_ASYNC>;
2043
+
clock-names = "merge", "merge_async";
2044
+
interrupts = <GIC_SPI 503 IRQ_TYPE_LEVEL_HIGH 0>;
2045
+
power-domains = <&spm MT8188_POWER_DOMAIN_VDOSYS1>;
2046
+
resets = <&vdosys1 MT8188_VDO1_RST_MERGE0_DL_ASYNC>;
2047
+
mediatek,gce-client-reg = <&gce0 SUBSYS_1c10XXXX 0xc000 0x1000>;
2048
+
mediatek,merge-mute;
2049
+
};
2050
+
2051
+
merge2: merge@1c10d000 {
2052
+
compatible = "mediatek,mt8188-disp-merge", "mediatek,mt8195-disp-merge";
2053
+
reg = <0 0x1c10d000 0 0x1000>;
2054
+
clocks = <&vdosys1 CLK_VDO1_VPP_MERGE1>,
2055
+
<&vdosys1 CLK_VDO1_MERGE1_DL_ASYNC>;
2056
+
clock-names = "merge", "merge_async";
2057
+
interrupts = <GIC_SPI 504 IRQ_TYPE_LEVEL_HIGH 0>;
2058
+
power-domains = <&spm MT8188_POWER_DOMAIN_VDOSYS1>;
2059
+
resets = <&vdosys1 MT8188_VDO1_RST_MERGE1_DL_ASYNC>;
2060
+
mediatek,gce-client-reg = <&gce0 SUBSYS_1c10XXXX 0xd000 0x1000>;
2061
+
mediatek,merge-mute;
2062
+
};
2063
+
2064
+
merge3: merge@1c10e000 {
2065
+
compatible = "mediatek,mt8188-disp-merge", "mediatek,mt8195-disp-merge";
2066
+
reg = <0 0x1c10e000 0 0x1000>;
2067
+
clocks = <&vdosys1 CLK_VDO1_VPP_MERGE2>,
2068
+
<&vdosys1 CLK_VDO1_MERGE2_DL_ASYNC>;
2069
+
clock-names = "merge", "merge_async";
2070
+
interrupts = <GIC_SPI 505 IRQ_TYPE_LEVEL_HIGH 0>;
2071
+
power-domains = <&spm MT8188_POWER_DOMAIN_VDOSYS1>;
2072
+
resets = <&vdosys1 MT8188_VDO1_RST_MERGE2_DL_ASYNC>;
2073
+
mediatek,gce-client-reg = <&gce0 SUBSYS_1c10XXXX 0xe000 0x1000>;
2074
+
mediatek,merge-mute;
2075
+
};
2076
+
2077
+
merge4: merge@1c10f000 {
2078
+
compatible = "mediatek,mt8188-disp-merge", "mediatek,mt8195-disp-merge";
2079
+
reg = <0 0x1c10f000 0 0x1000>;
2080
+
clocks = <&vdosys1 CLK_VDO1_VPP_MERGE3>,
2081
+
<&vdosys1 CLK_VDO1_MERGE3_DL_ASYNC>;
2082
+
clock-names = "merge", "merge_async";
2083
+
interrupts = <GIC_SPI 506 IRQ_TYPE_LEVEL_HIGH 0>;
2084
+
power-domains = <&spm MT8188_POWER_DOMAIN_VDOSYS1>;
2085
+
resets = <&vdosys1 MT8188_VDO1_RST_MERGE3_DL_ASYNC>;
2086
+
mediatek,gce-client-reg = <&gce0 SUBSYS_1c10XXXX 0xf000 0x1000>;
2087
+
mediatek,merge-mute;
2088
+
};
2089
+
2090
+
merge5: merge@1c110000 {
2091
+
compatible = "mediatek,mt8188-disp-merge", "mediatek,mt8195-disp-merge";
2092
+
reg = <0 0x1c110000 0 0x1000>;
2093
+
clocks = <&vdosys1 CLK_VDO1_VPP_MERGE4>,
2094
+
<&vdosys1 CLK_VDO1_MERGE4_DL_ASYNC>;
2095
+
clock-names = "merge", "merge_async";
2096
+
interrupts = <GIC_SPI 507 IRQ_TYPE_LEVEL_HIGH 0>;
2097
+
power-domains = <&spm MT8188_POWER_DOMAIN_VDOSYS1>;
2098
+
resets = <&vdosys1 MT8188_VDO1_RST_MERGE4_DL_ASYNC>;
2099
+
mediatek,gce-client-reg = <&gce0 SUBSYS_1c11XXXX 0x0000 0x1000>;
2100
+
mediatek,merge-fifo-en;
2101
+
};
2102
+
2103
+
dp_intf1: dp-intf@1c113000 {
2104
+
compatible = "mediatek,mt8188-dp-intf";
2105
+
reg = <0 0x1c113000 0 0x1000>;
2106
+
clocks = <&vdosys1 CLK_VDO1_DPINTF>,
2107
+
<&vdosys1 CLK_VDO1_DP_INTF0_MMCK>,
2108
+
<&apmixedsys CLK_APMIXED_TVDPLL2>;
2109
+
clock-names = "pixel", "engine", "pll";
2110
+
interrupts = <GIC_SPI 513 IRQ_TYPE_LEVEL_HIGH 0>;
2111
+
power-domains = <&spm MT8188_POWER_DOMAIN_VDOSYS1>;
2112
+
status = "disabled";
2113
+
};
2114
+
2115
+
ethdr0: ethdr@1c114000 {
2116
+
compatible = "mediatek,mt8188-disp-ethdr", "mediatek,mt8195-disp-ethdr";
2117
+
reg = <0 0x1c114000 0 0x1000>,
2118
+
<0 0x1c115000 0 0x1000>,
2119
+
<0 0x1c117000 0 0x1000>,
2120
+
<0 0x1c119000 0 0x1000>,
2121
+
<0 0x1c11a000 0 0x1000>,
2122
+
<0 0x1c11b000 0 0x1000>,
2123
+
<0 0x1c11c000 0 0x1000>;
2124
+
reg-names = "mixer", "vdo_fe0", "vdo_fe1", "gfx_fe0", "gfx_fe1",
2125
+
"vdo_be", "adl_ds";
2126
+
2127
+
clocks = <&vdosys1 CLK_VDO1_DISP_MIXER>,
2128
+
<&vdosys1 CLK_VDO1_HDR_VDO_FE0>,
2129
+
<&vdosys1 CLK_VDO1_HDR_VDO_FE1>,
2130
+
<&vdosys1 CLK_VDO1_HDR_GFX_FE0>,
2131
+
<&vdosys1 CLK_VDO1_HDR_GFX_FE1>,
2132
+
<&vdosys1 CLK_VDO1_HDR_VDO_BE>,
2133
+
<&vdosys1 CLK_VDO1_26M_SLOW>,
2134
+
<&vdosys1 CLK_VDO1_HDR_VDO_FE0_DL_ASYNC>,
2135
+
<&vdosys1 CLK_VDO1_HDR_VDO_FE1_DL_ASYNC>,
2136
+
<&vdosys1 CLK_VDO1_HDR_GFX_FE0_DL_ASYNC>,
2137
+
<&vdosys1 CLK_VDO1_HDR_GFX_FE1_DL_ASYNC>,
2138
+
<&vdosys1 CLK_VDO1_HDR_VDO_BE_DL_ASYNC>,
2139
+
<&topckgen CLK_TOP_ETHDR>;
2140
+
clock-names = "mixer", "vdo_fe0", "vdo_fe1", "gfx_fe0", "gfx_fe1",
2141
+
"vdo_be", "adl_ds", "vdo_fe0_async", "vdo_fe1_async",
2142
+
"gfx_fe0_async", "gfx_fe1_async", "vdo_be_async", "ethdr_top";
2143
+
2144
+
interrupts = <GIC_SPI 566 IRQ_TYPE_LEVEL_HIGH 0>;
2145
+
iommus = <&vpp_iommu M4U_PORT_L3_HDR_DS_SMI>,
2146
+
<&vpp_iommu M4U_PORT_L3_HDR_ADL_SMI>;
2147
+
power-domains = <&spm MT8188_POWER_DOMAIN_VDOSYS1>;
2148
+
resets = <&vdosys1 MT8188_VDO1_RST_HDR_VDO_FE0_DL_ASYNC>,
2149
+
<&vdosys1 MT8188_VDO1_RST_HDR_VDO_FE1_DL_ASYNC>,
2150
+
<&vdosys1 MT8188_VDO1_RST_HDR_GFX_FE0_DL_ASYNC>,
2151
+
<&vdosys1 MT8188_VDO1_RST_HDR_GFX_FE1_DL_ASYNC>,
2152
+
<&vdosys1 MT8188_VDO1_RST_HDR_VDO_BE_DL_ASYNC>;
2153
+
2154
+
mediatek,gce-client-reg = <&gce0 SUBSYS_1c11XXXX 0x4000 0x1000>,
2155
+
<&gce0 SUBSYS_1c11XXXX 0x5000 0x1000>,
2156
+
<&gce0 SUBSYS_1c11XXXX 0x7000 0x1000>,
2157
+
<&gce0 SUBSYS_1c11XXXX 0x9000 0x1000>,
2158
+
<&gce0 SUBSYS_1c11XXXX 0xa000 0x1000>,
2159
+
<&gce0 SUBSYS_1c11XXXX 0xb000 0x1000>,
2160
+
<&gce0 SUBSYS_1c11XXXX 0xc000 0x1000>;
2161
+
};
2162
+
2163
+
padding0: padding@1c11d000 {
2164
+
compatible = "mediatek,mt8188-disp-padding";
2165
+
reg = <0 0x1c11d000 0 0x1000>;
2166
+
clocks = <&vdosys1 CLK_VDO1_PADDING0>;
2167
+
power-domains = <&spm MT8188_POWER_DOMAIN_VDOSYS1>;
2168
+
mediatek,gce-client-reg = <&gce0 SUBSYS_1c11XXXX 0xd000 0x1000>;
2169
+
};
2170
+
2171
+
padding1: padding@1c11e000 {
2172
+
compatible = "mediatek,mt8188-disp-padding";
2173
+
reg = <0 0x1c11e000 0 0x1000>;
2174
+
clocks = <&vdosys1 CLK_VDO1_PADDING1>;
2175
+
power-domains = <&spm MT8188_POWER_DOMAIN_VDOSYS1>;
2176
+
mediatek,gce-client-reg = <&gce0 SUBSYS_1c11XXXX 0xe000 0x1000>;
2177
+
};
2178
+
2179
+
padding2: padding@1c11f000 {
2180
+
compatible = "mediatek,mt8188-disp-padding";
2181
+
reg = <0 0x1c11f000 0 0x1000>;
2182
+
clocks = <&vdosys1 CLK_VDO1_PADDING2>;
2183
+
power-domains = <&spm MT8188_POWER_DOMAIN_VDOSYS1>;
2184
+
mediatek,gce-client-reg = <&gce0 SUBSYS_1c11XXXX 0xf000 0x1000>;
2185
+
};
2186
+
2187
+
padding3: padding@1c120000 {
2188
+
compatible = "mediatek,mt8188-disp-padding";
2189
+
reg = <0 0x1c120000 0 0x1000>;
2190
+
clocks = <&vdosys1 CLK_VDO1_PADDING3>;
2191
+
power-domains = <&spm MT8188_POWER_DOMAIN_VDOSYS1>;
2192
+
mediatek,gce-client-reg = <&gce0 SUBSYS_1c12XXXX 0x0000 0x1000>;
2193
+
};
2194
+
2195
+
padding4: padding@1c121000 {
2196
+
compatible = "mediatek,mt8188-disp-padding";
2197
+
reg = <0 0x1c121000 0 0x1000>;
2198
+
clocks = <&vdosys1 CLK_VDO1_PADDING4>;
2199
+
power-domains = <&spm MT8188_POWER_DOMAIN_VDOSYS1>;
2200
+
mediatek,gce-client-reg = <&gce0 SUBSYS_1c12XXXX 0x1000 0x1000>;
2201
+
};
2202
+
2203
+
padding5: padding@1c122000 {
2204
+
compatible = "mediatek,mt8188-disp-padding";
2205
+
reg = <0 0x1c122000 0 0x1000>;
2206
+
clocks = <&vdosys1 CLK_VDO1_PADDING5>;
2207
+
power-domains = <&spm MT8188_POWER_DOMAIN_VDOSYS1>;
2208
+
mediatek,gce-client-reg = <&gce0 SUBSYS_1c12XXXX 0x2000 0x1000>;
2209
+
};
2210
+
2211
+
padding6: padding@1c123000 {
2212
+
compatible = "mediatek,mt8188-disp-padding";
2213
+
reg = <0 0x1c123000 0 0x1000>;
2214
+
clocks = <&vdosys1 CLK_VDO1_PADDING6>;
2215
+
power-domains = <&spm MT8188_POWER_DOMAIN_VDOSYS1>;
2216
+
mediatek,gce-client-reg = <&gce0 SUBSYS_1c12XXXX 0x3000 0x1000>;
2217
+
};
2218
+
2219
+
padding7: padding@1c124000 {
2220
+
compatible = "mediatek,mt8188-disp-padding";
2221
+
reg = <0 0x1c124000 0 0x1000>;
2222
+
clocks = <&vdosys1 CLK_VDO1_PADDING7>;
2223
+
power-domains = <&spm MT8188_POWER_DOMAIN_VDOSYS1>;
2224
+
mediatek,gce-client-reg = <&gce0 SUBSYS_1c12XXXX 0x4000 0x1000>;
2225
+
};
2226
+
2227
+
edp_tx: edp-tx@1c500000 {
2228
+
compatible = "mediatek,mt8188-edp-tx";
2229
+
reg = <0 0x1c500000 0 0x8000>;
2230
+
interrupts = <GIC_SPI 676 IRQ_TYPE_LEVEL_HIGH 0>;
2231
+
nvmem-cells = <&dp_calib_data>;
2232
+
nvmem-cell-names = "dp_calibration_data";
2233
+
power-domains = <&spm MT8188_POWER_DOMAIN_EDP_TX>;
2234
+
max-linkrate-mhz = <8100>;
2235
+
status = "disabled";
2236
+
};
2237
+
2238
+
dp_tx: dp-tx@1c600000 {
2239
+
compatible = "mediatek,mt8188-dp-tx";
2240
+
reg = <0 0x1c600000 0 0x8000>;
2241
+
interrupts = <GIC_SPI 458 IRQ_TYPE_LEVEL_HIGH 0>;
2242
+
nvmem-cells = <&dp_calib_data>;
2243
+
nvmem-cell-names = "dp_calibration_data";
2244
+
power-domains = <&spm MT8188_POWER_DOMAIN_DP_TX>;
2245
+
max-linkrate-mhz = <5400>;
2246
+
status = "disabled";
2675
2247
};
2676
2248
};
2677
2249
};
+11
arch/arm64/boot/dts/mediatek/mt8192-asurada-spherion-r0.dts
+11
arch/arm64/boot/dts/mediatek/mt8192-asurada-spherion-r0.dts
···
79
79
&touchscreen {
80
80
compatible = "elan,ekth3500";
81
81
};
82
+
83
+
&i2c2 {
84
+
/* synaptics touchpad */
85
+
trackpad@2c {
86
+
compatible = "hid-over-i2c";
87
+
reg = <0x2c>;
88
+
hid-descr-addr = <0x20>;
89
+
interrupts-extended = <&pio 15 IRQ_TYPE_LEVEL_LOW>;
90
+
wakeup-source;
91
+
};
92
+
};
+1
-3
arch/arm64/boot/dts/mediatek/mt8192-asurada.dtsi
+1
-3
arch/arm64/boot/dts/mediatek/mt8192-asurada.dtsi
···
335
335
clock-frequency = <400000>;
336
336
clock-stretch-ns = <12600>;
337
337
pinctrl-names = "default";
338
-
pinctrl-0 = <&i2c2_pins>;
338
+
pinctrl-0 = <&i2c2_pins>, <&trackpad_pins>;
339
339
340
340
trackpad@15 {
341
341
compatible = "elan,ekth3000";
342
342
reg = <0x15>;
343
343
interrupts-extended = <&pio 15 IRQ_TYPE_LEVEL_LOW>;
344
-
pinctrl-names = "default";
345
-
pinctrl-0 = <&trackpad_pins>;
346
344
vcc-supply = <&pp3300_u>;
347
345
wakeup-source;
348
346
};
+3
-3
arch/arm64/boot/dts/mediatek/mt8195-cherry.dtsi
+3
-3
arch/arm64/boot/dts/mediatek/mt8195-cherry.dtsi
···
438
438
/* Realtek RT5682i or RT5682s, sharing the same configuration */
439
439
reg = <0x1a>;
440
440
interrupts-extended = <&pio 89 IRQ_TYPE_EDGE_BOTH>;
441
-
#sound-dai-cells = <0>;
441
+
#sound-dai-cells = <1>;
442
442
realtek,jd-src = <1>;
443
443
444
444
AVDD-supply = <&mt6359_vio18_ldo_reg>;
···
1181
1181
link-name = "ETDM1_OUT_BE";
1182
1182
mediatek,clk-provider = "cpu";
1183
1183
codec {
1184
-
sound-dai = <&audio_codec>;
1184
+
sound-dai = <&audio_codec 0>;
1185
1185
};
1186
1186
};
1187
1187
···
1189
1189
link-name = "ETDM2_IN_BE";
1190
1190
mediatek,clk-provider = "cpu";
1191
1191
codec {
1192
-
sound-dai = <&audio_codec>;
1192
+
sound-dai = <&audio_codec 0>;
1193
1193
};
1194
1194
};
1195
1195
+1
-3
arch/arm64/boot/dts/mediatek/mt8195.dtsi
+1
-3
arch/arm64/boot/dts/mediatek/mt8195.dtsi
···
487
487
};
488
488
489
489
infracfg_ao: syscon@10001000 {
490
-
compatible = "mediatek,mt8195-infracfg_ao", "syscon", "simple-mfd";
490
+
compatible = "mediatek,mt8195-infracfg_ao", "syscon";
491
491
reg = <0 0x10001000 0 0x1000>;
492
492
#clock-cells = <1>;
493
493
#reset-cells = <1>;
···
3331
3331
mutex1: mutex@1c101000 {
3332
3332
compatible = "mediatek,mt8195-disp-mutex";
3333
3333
reg = <0 0x1c101000 0 0x1000>;
3334
-
reg-names = "vdo1_mutex";
3335
3334
interrupts = <GIC_SPI 494 IRQ_TYPE_LEVEL_HIGH 0>;
3336
3335
power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>;
3337
3336
clocks = <&vdosys1 CLK_VDO1_DISP_MUTEX>;
3338
-
clock-names = "vdo1_mutex";
3339
3337
mediatek,gce-client-reg = <&gce0 SUBSYS_1c10XXXX 0x1000 0x1000>;
3340
3338
mediatek,gce-events = <CMDQ_EVENT_VDO1_STREAM_DONE_ENG_0>;
3341
3339
};
+159
-33
arch/arm64/boot/dts/mediatek/mt8390-genio-700-evk.dts
+159
-33
arch/arm64/boot/dts/mediatek/mt8390-genio-700-evk.dts
···
23
23
"mediatek,mt8188";
24
24
25
25
aliases {
26
+
ethernet0 = ð
27
+
i2c0 = &i2c0;
28
+
i2c1 = &i2c1;
29
+
i2c2 = &i2c2;
30
+
i2c3 = &i2c3;
31
+
i2c4 = &i2c4;
32
+
i2c5 = &i2c5;
33
+
i2c6 = &i2c6;
34
+
mmc0 = &mmc0;
35
+
mmc1 = &mmc1;
26
36
serial0 = &uart0;
27
37
};
28
38
···
97
87
98
88
common_fixed_5v: regulator-0 {
99
89
compatible = "regulator-fixed";
100
-
regulator-name = "5v_en";
90
+
regulator-name = "vdd_5v";
101
91
regulator-min-microvolt = <5000000>;
102
92
regulator-max-microvolt = <5000000>;
103
93
gpio = <&pio 10 GPIO_ACTIVE_HIGH>;
104
94
enable-active-high;
105
95
regulator-always-on;
96
+
vin-supply = <®_vsys>;
106
97
};
107
98
108
99
edp_panel_fixed_3v3: regulator-1 {
109
100
compatible = "regulator-fixed";
110
-
regulator-name = "edp_panel_3v3";
101
+
regulator-name = "vedp_3v3";
111
102
regulator-min-microvolt = <3300000>;
112
103
regulator-max-microvolt = <3300000>;
113
104
enable-active-high;
114
105
gpio = <&pio 15 GPIO_ACTIVE_HIGH>;
115
106
pinctrl-names = "default";
116
107
pinctrl-0 = <&edp_panel_3v3_en_pins>;
108
+
vin-supply = <®_vsys>;
117
109
};
118
110
119
111
gpio_fixed_3v3: regulator-2 {
120
112
compatible = "regulator-fixed";
121
-
regulator-name = "gpio_3v3_en";
113
+
regulator-name = "ext_3v3";
122
114
regulator-min-microvolt = <3300000>;
123
115
regulator-max-microvolt = <3300000>;
124
116
gpio = <&pio 9 GPIO_ACTIVE_HIGH>;
125
117
enable-active-high;
126
118
regulator-always-on;
119
+
vin-supply = <®_vsys>;
127
120
};
128
121
122
+
/* system wide 4.2V power rail from charger */
123
+
reg_vsys: regulator-vsys {
124
+
compatible = "regulator-fixed";
125
+
regulator-name = "vsys";
126
+
regulator-always-on;
127
+
regulator-boot-on;
128
+
};
129
+
130
+
/* used by mmc2 */
129
131
sdio_fixed_1v8: regulator-3 {
130
132
compatible = "regulator-fixed";
131
-
regulator-name = "sdio_io";
133
+
regulator-name = "vio18_conn";
132
134
regulator-min-microvolt = <1800000>;
133
135
regulator-max-microvolt = <1800000>;
134
136
enable-active-high;
135
137
regulator-always-on;
136
138
};
137
139
140
+
/* used by mmc2 */
138
141
sdio_fixed_3v3: regulator-4 {
139
142
compatible = "regulator-fixed";
140
-
regulator-name = "sdio_card";
143
+
regulator-name = "wifi_3v3";
141
144
regulator-min-microvolt = <3300000>;
142
145
regulator-max-microvolt = <3300000>;
143
146
gpio = <&pio 74 GPIO_ACTIVE_HIGH>;
144
147
enable-active-high;
145
148
regulator-always-on;
149
+
vin-supply = <®_vsys>;
146
150
};
147
151
148
152
touch0_fixed_3v3: regulator-5 {
149
153
compatible = "regulator-fixed";
150
-
regulator-name = "touch_3v3";
154
+
regulator-name = "vio33_tp1";
151
155
regulator-min-microvolt = <3300000>;
152
156
regulator-max-microvolt = <3300000>;
153
157
gpio = <&pio 119 GPIO_ACTIVE_HIGH>;
154
158
enable-active-high;
159
+
vin-supply = <®_vsys>;
155
160
};
156
161
157
162
usb_hub_fixed_3v3: regulator-6 {
158
163
compatible = "regulator-fixed";
159
-
regulator-name = "usb_hub_3v3";
164
+
regulator-name = "vhub_3v3";
160
165
regulator-min-microvolt = <3300000>;
161
166
regulator-max-microvolt = <3300000>;
162
167
gpio = <&pio 112 GPIO_ACTIVE_HIGH>; /* HUB_3V3_EN */
163
168
startup-delay-us = <10000>;
164
169
enable-active-high;
170
+
vin-supply = <®_vsys>;
165
171
};
166
172
167
-
usb_hub_reset_1v8: regulator-7 {
173
+
usb_p0_vbus: regulator-7 {
168
174
compatible = "regulator-fixed";
169
-
regulator-name = "usb_hub_reset";
170
-
regulator-min-microvolt = <1800000>;
171
-
regulator-max-microvolt = <1800000>;
172
-
gpio = <&pio 7 GPIO_ACTIVE_HIGH>; /* HUB_RESET */
173
-
vin-supply = <&usb_hub_fixed_3v3>;
174
-
};
175
-
176
-
usb_p0_vbus: regulator-8 {
177
-
compatible = "regulator-fixed";
178
-
regulator-name = "usb_p0_vbus";
175
+
regulator-name = "vbus_p0";
179
176
regulator-min-microvolt = <5000000>;
180
177
regulator-max-microvolt = <5000000>;
181
178
gpio = <&pio 84 GPIO_ACTIVE_HIGH>;
182
179
enable-active-high;
180
+
vin-supply = <®_vsys>;
183
181
};
184
182
185
-
usb_p1_vbus: regulator-9 {
183
+
usb_p1_vbus: regulator-8 {
186
184
compatible = "regulator-fixed";
187
-
regulator-name = "usb_p1_vbus";
185
+
regulator-name = "vbus_p1";
188
186
regulator-min-microvolt = <5000000>;
189
187
regulator-max-microvolt = <5000000>;
190
188
gpio = <&pio 87 GPIO_ACTIVE_HIGH>;
191
189
enable-active-high;
190
+
vin-supply = <®_vsys>;
192
191
};
193
192
194
-
usb_p2_vbus: regulator-10 {
193
+
/* used by ssusb2 */
194
+
usb_p2_vbus: regulator-9 {
195
195
compatible = "regulator-fixed";
196
-
regulator-name = "usb_p2_vbus";
196
+
regulator-name = "wifi_3v3";
197
197
regulator-min-microvolt = <5000000>;
198
198
regulator-max-microvolt = <5000000>;
199
199
enable-active-high;
200
200
};
201
+
};
202
+
203
+
&gpu {
204
+
mali-supply = <&mt6359_vproc2_buck_reg>;
205
+
status = "okay";
201
206
};
202
207
203
208
&i2c0 {
···
259
234
&i2c4 {
260
235
pinctrl-names = "default";
261
236
pinctrl-0 = <&i2c4_pins>;
262
-
pinctrl-1 = <&rt1715_int_pins>;
263
237
clock-frequency = <1000000>;
264
238
status = "okay";
265
239
};
···
275
251
pinctrl-0 = <&i2c6_pins>;
276
252
clock-frequency = <400000>;
277
253
status = "okay";
254
+
};
255
+
256
+
&mfg0 {
257
+
domain-supply = <&mt6359_vproc2_buck_reg>;
258
+
};
259
+
260
+
&mfg1 {
261
+
domain-supply = <&mt6359_vsram_others_ldo_reg>;
278
262
};
279
263
280
264
&mmc0 {
···
327
295
};
328
296
329
297
&mt6359_vcn18_ldo_reg {
298
+
regulator-name = "vcn18_pmu";
330
299
regulator-always-on;
331
300
};
332
301
333
302
&mt6359_vcn33_2_bt_ldo_reg {
303
+
regulator-name = "vcn33_2_pmu";
334
304
regulator-always-on;
335
305
};
336
306
337
307
&mt6359_vcore_buck_reg {
308
+
regulator-name = "dvdd_proc_l";
338
309
regulator-always-on;
339
310
};
340
311
341
312
&mt6359_vgpu11_buck_reg {
313
+
regulator-name = "dvdd_core";
342
314
regulator-always-on;
343
315
};
344
316
345
317
&mt6359_vpa_buck_reg {
318
+
regulator-name = "vpa_pmu";
346
319
regulator-max-microvolt = <3100000>;
347
320
};
348
321
322
+
&mt6359_vproc2_buck_reg {
323
+
/* The name "vgpu" is required by mtk-regulator-coupler */
324
+
regulator-name = "vgpu";
325
+
regulator-min-microvolt = <550000>;
326
+
regulator-max-microvolt = <800000>;
327
+
regulator-coupled-with = <&mt6359_vsram_others_ldo_reg>;
328
+
regulator-coupled-max-spread = <6250>;
329
+
};
330
+
349
331
&mt6359_vpu_buck_reg {
332
+
regulator-name = "dvdd_adsp";
350
333
regulator-always-on;
351
334
};
352
335
353
336
&mt6359_vrf12_ldo_reg {
337
+
regulator-name = "va12_abb2_pmu";
354
338
regulator-always-on;
355
339
};
356
340
357
341
&mt6359_vsim1_ldo_reg {
342
+
regulator-name = "vsim1_pmu";
358
343
regulator-enable-ramp-delay = <480>;
359
344
};
360
345
346
+
&mt6359_vsram_others_ldo_reg {
347
+
/* The name "vsram_gpu" is required by mtk-regulator-coupler */
348
+
regulator-name = "vsram_gpu";
349
+
regulator-min-microvolt = <750000>;
350
+
regulator-max-microvolt = <800000>;
351
+
regulator-coupled-with = <&mt6359_vproc2_buck_reg>;
352
+
regulator-coupled-max-spread = <6250>;
353
+
};
354
+
361
355
&mt6359_vufs_ldo_reg {
356
+
regulator-name = "vufs18_pmu";
362
357
regulator-always-on;
363
358
};
364
359
365
360
&mt6359codec {
366
361
mediatek,mic-type-0 = <1>; /* ACC */
367
362
mediatek,mic-type-1 = <3>; /* DCC */
363
+
};
364
+
365
+
&pcie {
366
+
pinctrl-names = "default";
367
+
pinctrl-0 = <&pcie_pins_default>;
368
+
status = "okay";
369
+
};
370
+
371
+
&pciephy {
372
+
status = "okay";
368
373
};
369
374
370
375
&pio {
···
769
700
};
770
701
};
771
702
703
+
pcie_pins_default: pcie-default {
704
+
mux {
705
+
pinmux = <PINMUX_GPIO47__FUNC_I1_WAKEN>,
706
+
<PINMUX_GPIO48__FUNC_O_PERSTN>,
707
+
<PINMUX_GPIO49__FUNC_B1_CLKREQN>;
708
+
bias-pull-up;
709
+
};
710
+
};
711
+
772
712
rt1715_int_pins: rt1715-int-pins {
773
713
pins_cmd0_dat {
774
714
pinmux = <PINMUX_GPIO12__FUNC_B_GPIO12>;
···
892
814
};
893
815
};
894
816
817
+
ð {
818
+
phy-mode ="rgmii-id";
819
+
phy-handle = <ðernet_phy0>;
820
+
pinctrl-names = "default", "sleep";
821
+
pinctrl-0 = <ð_default_pins>;
822
+
pinctrl-1 = <ð_sleep_pins>;
823
+
mediatek,mac-wol;
824
+
snps,reset-gpio = <&pio 147 GPIO_ACTIVE_HIGH>;
825
+
snps,reset-delays-us = <0 10000 10000>;
826
+
status = "okay";
827
+
};
828
+
829
+
ð_mdio {
830
+
ethernet_phy0: ethernet-phy@1 {
831
+
compatible = "ethernet-phy-id001c.c916";
832
+
reg = <0x1>;
833
+
};
834
+
};
835
+
895
836
&pmic {
896
837
interrupt-parent = <&pio>;
897
838
interrupts = <222 IRQ_TYPE_LEVEL_HIGH>;
839
+
840
+
mt6359keys: keys {
841
+
compatible = "mediatek,mt6359-keys";
842
+
mediatek,long-press-mode = <1>;
843
+
power-off-time-sec = <0>;
844
+
845
+
power-key {
846
+
linux,keycodes = <KEY_POWER>;
847
+
wakeup-source;
848
+
};
849
+
};
898
850
};
899
851
900
852
&scp {
901
853
memory-region = <&scp_mem>;
854
+
status = "okay";
855
+
};
856
+
857
+
&spi2 {
858
+
pinctrl-0 = <&spi2_pins>;
859
+
pinctrl-names = "default";
860
+
mediatek,pad-select = <0>;
861
+
#address-cells = <1>;
862
+
#size-cells = <0>;
902
863
status = "okay";
903
864
};
904
865
···
956
839
&uart2 {
957
840
pinctrl-0 = <&uart2_pins>;
958
841
pinctrl-names = "default";
959
-
status = "okay";
960
-
};
961
-
962
-
&spi2 {
963
-
pinctrl-0 = <&spi2_pins>;
964
-
pinctrl-names = "default";
965
-
mediatek,pad-select = <0>;
966
-
#address-cells = <1>;
967
-
#size-cells = <0>;
968
842
status = "okay";
969
843
};
970
844
···
979
871
&xhci1 {
980
872
status = "okay";
981
873
vusb33-supply = <&mt6359_vusb_ldo_reg>;
982
-
vbus-supply = <&usb_hub_reset_1v8>;
874
+
#address-cells = <1>;
875
+
#size-cells = <0>;
876
+
877
+
hub_2_0: hub@1 {
878
+
compatible = "usb451,8025";
879
+
reg = <1>;
880
+
peer-hub = <&hub_3_0>;
881
+
reset-gpios = <&pio 7 GPIO_ACTIVE_HIGH>;
882
+
vdd-supply = <&usb_hub_fixed_3v3>;
883
+
};
884
+
885
+
hub_3_0: hub@2 {
886
+
compatible = "usb451,8027";
887
+
reg = <2>;
888
+
peer-hub = <&hub_2_0>;
889
+
reset-gpios = <&pio 7 GPIO_ACTIVE_HIGH>;
890
+
vdd-supply = <&usb_hub_fixed_3v3>;
891
+
};
983
892
};
984
893
985
894
&xhci2 {
986
895
status = "okay";
987
896
vusb33-supply = <&mt6359_vusb_ldo_reg>;
897
+
vbus-supply = <&sdio_fixed_3v3>; /* wifi_3v3 */
988
898
};
+18
-3
arch/arm64/boot/dts/mediatek/mt8395-genio-1200-evk.dts
+18
-3
arch/arm64/boot/dts/mediatek/mt8395-genio-1200-evk.dts
···
187
187
compatible = "snps,dwmac-mdio";
188
188
#address-cells = <1>;
189
189
#size-cells = <0>;
190
-
eth_phy0: eth-phy0@1 {
190
+
eth_phy0: ethernet-phy@1 {
191
191
compatible = "ethernet-phy-id001c.c916";
192
192
reg = <0x1>;
193
193
};
194
194
};
195
+
};
196
+
197
+
&gpu {
198
+
mali-supply = <&mt6315_7_vbuck1>;
199
+
status = "okay";
195
200
};
196
201
197
202
&i2c0 {
···
342
337
domain-supply = <&mt6315_7_vbuck1>;
343
338
};
344
339
340
+
&mfg1 {
341
+
domain-supply = <&mt6359_vsram_others_ldo_reg>;
342
+
};
343
+
345
344
&mmc0 {
346
345
status = "okay";
347
346
pinctrl-names = "default", "state_uhs";
···
414
405
415
406
&mt6359_vrf12_ldo_reg {
416
407
regulator-always-on;
408
+
};
409
+
410
+
/* for GPU SRAM */
411
+
&mt6359_vsram_others_ldo_reg {
412
+
regulator-min-microvolt = <750000>;
413
+
regulator-max-microvolt = <750000>;
417
414
};
418
415
419
416
&mt6359codec {
···
854
839
mt6315_7_vbuck1: vbuck1 {
855
840
regulator-compatible = "vbuck1";
856
841
regulator-name = "Vgpu";
857
-
regulator-min-microvolt = <300000>;
858
-
regulator-max-microvolt = <1193750>;
842
+
regulator-min-microvolt = <546000>;
843
+
regulator-max-microvolt = <787000>;
859
844
regulator-enable-ramp-delay = <256>;
860
845
regulator-allowed-modes = <0 1 2>;
861
846
};