Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
phy: ti: gmii-sel: Enable USXGMII mode for J784S4
TI's J784S4 SoC supports USXGMII mode with the CPSW9G instance's MAC
ports 1 and 2. Add USXGMII mode to the extra_modes member of J784S4's
SoC data.
Signed-off-by: Siddharth Vadapalli <s-vadapalli@ti.com>
Reviewed-by: Roger Quadros <rogerq@kernel.org>
Link: https://lore.kernel.org/r/20230331062521.529005-3-s-vadapalli@ti.com
Signed-off-by: Vinod Koul <vkoul@kernel.org>
authored by
Siddharth Vadapalli
and committed by
Vinod Koul
8d087a09
efd65880
+10
-1
+10
-1
drivers/phy/ti/phy-gmii-sel.c
+10
-1
drivers/phy/ti/phy-gmii-sel.c
···
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/* J72xx SoC specific definitions for the CONTROL port */
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#define J72XX_GMII_SEL_MODE_SGMII 3
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#define J72XX_GMII_SEL_MODE_QSGMII 4
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+
#define J72XX_GMII_SEL_MODE_USXGMII 5
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#define J72XX_GMII_SEL_MODE_QSGMII_SUB 6
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#define PHY_GMII_PORT(n) BIT((n) - 1)
···
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goto unsupported;
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else
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gmii_sel_mode = J72XX_GMII_SEL_MODE_SGMII;
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+
break;
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+
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case PHY_INTERFACE_MODE_USXGMII:
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if (!(soc_data->extra_modes & BIT(PHY_INTERFACE_MODE_USXGMII)))
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goto unsupported;
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else
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gmii_sel_mode = J72XX_GMII_SEL_MODE_USXGMII;
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break;
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default:
···
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struct phy_gmii_sel_soc_data phy_gmii_sel_cpsw9g_soc_j784s4 = {
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.use_of_data = true,
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.regfields = phy_gmii_sel_fields_am654,
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-
.extra_modes = BIT(PHY_INTERFACE_MODE_QSGMII),
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.extra_modes = BIT(PHY_INTERFACE_MODE_QSGMII) |
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BIT(PHY_INTERFACE_MODE_USXGMII),
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.num_ports = 8,
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.num_qsgmii_main_ports = 2,
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};