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phy: ti: gmii-sel: Add support for CPSW9G GMII SEL in J784S4

Each of the CPSW9G ports in TI's J784S4 SoC support modes such as QSGMII.

Add a new compatible for it and allow the usage of "ti,qsgmii-main-ports"
property for J784S4.

Signed-off-by: Siddharth Vadapalli <s-vadapalli@ti.com>
Reviewed-by: Roger Quadros <rogerq@kernel.org>
Link: https://lore.kernel.org/r/20230331062521.529005-2-s-vadapalli@ti.com
Signed-off-by: Vinod Koul <vkoul@kernel.org>

authored by

Siddharth Vadapalli and committed by
Vinod Koul efd65880 2de2e49b

+13
+13
drivers/phy/ti/phy-gmii-sel.c
··· 235 235 .num_qsgmii_main_ports = 2, 236 236 }; 237 237 238 + static const 239 + struct phy_gmii_sel_soc_data phy_gmii_sel_cpsw9g_soc_j784s4 = { 240 + .use_of_data = true, 241 + .regfields = phy_gmii_sel_fields_am654, 242 + .extra_modes = BIT(PHY_INTERFACE_MODE_QSGMII), 243 + .num_ports = 8, 244 + .num_qsgmii_main_ports = 2, 245 + }; 246 + 238 247 static const struct of_device_id phy_gmii_sel_id_table[] = { 239 248 { 240 249 .compatible = "ti,am3352-phy-gmii-sel", ··· 272 263 { 273 264 .compatible = "ti,j721e-cpsw9g-phy-gmii-sel", 274 265 .data = &phy_gmii_sel_cpsw9g_soc_j721e, 266 + }, 267 + { 268 + .compatible = "ti,j784s4-cpsw9g-phy-gmii-sel", 269 + .data = &phy_gmii_sel_cpsw9g_soc_j784s4, 275 270 }, 276 271 {} 277 272 };