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git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
interconnect: qcom: sm8250: Retire DEFINE_QBCM
The struct definition macros are hard to read and compare, expand them.
Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Reviewed-by: Bjorn Andersson <quic_bjorande@quicinc.com>
Link: https://lore.kernel.org/r/20230811-topic-icc_retire_macrosd-v1-18-c03aaeffc769@linaro.org
Signed-off-by: Georgi Djakov <djakov@kernel.org>
authored by
Konrad Dybcio
and committed by
Georgi Djakov
8e509d66
670699a4
+240
-27
+240
-27
drivers/interconnect/qcom/sm8250.c
+240
-27
drivers/interconnect/qcom/sm8250.c
···
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.buswidth = 4,
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};
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1398
-
DEFINE_QBCM(bcm_acv, "ACV", false, &ebi);
1399
-
DEFINE_QBCM(bcm_mc0, "MC0", true, &ebi);
1400
-
DEFINE_QBCM(bcm_sh0, "SH0", true, &qns_llcc);
1401
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DEFINE_QBCM(bcm_mm0, "MM0", true, &qns_mem_noc_hf);
1402
-
DEFINE_QBCM(bcm_ce0, "CE0", false, &qxm_crypto);
1403
-
DEFINE_QBCM(bcm_mm1, "MM1", false, &qnm_camnoc_hf, &qxm_mdp0, &qxm_mdp1);
1404
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DEFINE_QBCM(bcm_sh2, "SH2", false, &alm_gpu_tcu, &alm_sys_tcu);
1405
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DEFINE_QBCM(bcm_mm2, "MM2", false, &qns_mem_noc_sf);
1406
-
DEFINE_QBCM(bcm_qup0, "QUP0", false, &qup0_core_master, &qup1_core_master, &qup2_core_master);
1407
-
DEFINE_QBCM(bcm_sh3, "SH3", false, &qnm_cmpnoc);
1408
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DEFINE_QBCM(bcm_mm3, "MM3", false, &qnm_camnoc_icp, &qnm_camnoc_sf, &qnm_video0, &qnm_video1, &qnm_video_cvp);
1409
-
DEFINE_QBCM(bcm_sh4, "SH4", false, &chm_apps);
1410
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DEFINE_QBCM(bcm_sn0, "SN0", true, &qns_gemnoc_sf);
1411
-
DEFINE_QBCM(bcm_co0, "CO0", false, &qns_cdsp_mem_noc);
1412
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DEFINE_QBCM(bcm_cn0, "CN0", true, &qnm_snoc, &xm_qdss_dap, &qhs_a1_noc_cfg, &qhs_a2_noc_cfg, &qhs_ahb2phy0, &qhs_ahb2phy1, &qhs_aoss, &qhs_camera_cfg, &qhs_clk_ctl, &qhs_compute_dsp, &qhs_cpr_cx, &qhs_cpr_mmcx, &qhs_cpr_mx, &qhs_crypto0_cfg, &qhs_cx_rdpm, &qhs_dcc_cfg, &qhs_ddrss_cfg, &qhs_display_cfg, &qhs_gpuss_cfg, &qhs_imem_cfg, &qhs_ipa, &qhs_ipc_router, &qhs_lpass_cfg, &qhs_mnoc_cfg, &qhs_npu_cfg, &qhs_pcie0_cfg, &qhs_pcie1_cfg, &qhs_pcie_modem_cfg, &qhs_pdm, &qhs_pimem_cfg, &qhs_prng, &qhs_qdss_cfg, &qhs_qspi, &qhs_qup0, &qhs_qup1, &qhs_qup2, &qhs_sdc2, &qhs_sdc4, &qhs_snoc_cfg, &qhs_tcsr, &qhs_tlmm0, &qhs_tlmm1, &qhs_tlmm2, &qhs_tsif, &qhs_ufs_card_cfg, &qhs_ufs_mem_cfg, &qhs_usb3_0, &qhs_usb3_1, &qhs_venus_cfg, &qhs_vsense_ctrl_cfg, &qns_cnoc_a2noc, &srvc_cnoc);
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DEFINE_QBCM(bcm_sn1, "SN1", false, &qxs_imem);
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DEFINE_QBCM(bcm_sn2, "SN2", false, &qns_gemnoc_gc);
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DEFINE_QBCM(bcm_co2, "CO2", false, &qnm_npu);
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DEFINE_QBCM(bcm_sn3, "SN3", false, &qxs_pimem);
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DEFINE_QBCM(bcm_sn4, "SN4", false, &xs_qdss_stm);
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DEFINE_QBCM(bcm_sn5, "SN5", false, &xs_pcie_modem);
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DEFINE_QBCM(bcm_sn6, "SN6", false, &xs_pcie_0, &xs_pcie_1);
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DEFINE_QBCM(bcm_sn7, "SN7", false, &qnm_aggre1_noc);
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DEFINE_QBCM(bcm_sn8, "SN8", false, &qnm_aggre2_noc);
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DEFINE_QBCM(bcm_sn9, "SN9", false, &qnm_gemnoc_pcie);
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DEFINE_QBCM(bcm_sn11, "SN11", false, &qnm_gemnoc);
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DEFINE_QBCM(bcm_sn12, "SN12", false, &qns_pcie_modem_mem_noc, &qns_pcie_mem_noc);
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+
static struct qcom_icc_bcm bcm_acv = {
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+
.name = "ACV",
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+
.keepalive = false,
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+
.num_nodes = 1,
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+
.nodes = { &ebi },
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+
};
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+
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+
static struct qcom_icc_bcm bcm_mc0 = {
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.name = "MC0",
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+
.keepalive = true,
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+
.num_nodes = 1,
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.nodes = { &ebi },
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+
};
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+
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static struct qcom_icc_bcm bcm_sh0 = {
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.name = "SH0",
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+
.keepalive = true,
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+
.num_nodes = 1,
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.nodes = { &qns_llcc },
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+
};
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+
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static struct qcom_icc_bcm bcm_mm0 = {
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.name = "MM0",
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.keepalive = true,
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.num_nodes = 1,
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.nodes = { &qns_mem_noc_hf },
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};
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+
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static struct qcom_icc_bcm bcm_ce0 = {
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.name = "CE0",
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+
.keepalive = false,
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+
.num_nodes = 1,
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.nodes = { &qxm_crypto },
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};
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+
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static struct qcom_icc_bcm bcm_mm1 = {
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.name = "MM1",
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.keepalive = false,
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+
.num_nodes = 3,
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.nodes = { &qnm_camnoc_hf, &qxm_mdp0, &qxm_mdp1 },
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};
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+
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static struct qcom_icc_bcm bcm_sh2 = {
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.name = "SH2",
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.keepalive = false,
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.num_nodes = 2,
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.nodes = { &alm_gpu_tcu, &alm_sys_tcu },
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};
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+
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static struct qcom_icc_bcm bcm_mm2 = {
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.name = "MM2",
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.keepalive = false,
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.num_nodes = 1,
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.nodes = { &qns_mem_noc_sf },
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};
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+
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static struct qcom_icc_bcm bcm_qup0 = {
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.name = "QUP0",
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.keepalive = false,
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.num_nodes = 3,
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.nodes = { &qup0_core_master, &qup1_core_master, &qup2_core_master },
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};
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+
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static struct qcom_icc_bcm bcm_sh3 = {
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.name = "SH3",
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.keepalive = false,
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.num_nodes = 1,
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.nodes = { &qnm_cmpnoc },
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};
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static struct qcom_icc_bcm bcm_mm3 = {
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.name = "MM3",
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.keepalive = false,
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.num_nodes = 5,
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.nodes = { &qnm_camnoc_icp, &qnm_camnoc_sf, &qnm_video0, &qnm_video1, &qnm_video_cvp },
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};
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static struct qcom_icc_bcm bcm_sh4 = {
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.name = "SH4",
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.keepalive = false,
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.num_nodes = 1,
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.nodes = { &chm_apps },
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};
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static struct qcom_icc_bcm bcm_sn0 = {
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.name = "SN0",
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.keepalive = true,
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.num_nodes = 1,
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.nodes = { &qns_gemnoc_sf },
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};
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static struct qcom_icc_bcm bcm_co0 = {
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.name = "CO0",
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.keepalive = false,
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.num_nodes = 1,
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.nodes = { &qns_cdsp_mem_noc },
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};
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+
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static struct qcom_icc_bcm bcm_cn0 = {
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.name = "CN0",
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.keepalive = true,
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.num_nodes = 52,
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.nodes = { &qnm_snoc,
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&xm_qdss_dap,
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&qhs_a1_noc_cfg,
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&qhs_a2_noc_cfg,
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&qhs_ahb2phy0,
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&qhs_ahb2phy1,
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&qhs_aoss,
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&qhs_camera_cfg,
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&qhs_clk_ctl,
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&qhs_compute_dsp,
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&qhs_cpr_cx,
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&qhs_cpr_mmcx,
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&qhs_cpr_mx,
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&qhs_crypto0_cfg,
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&qhs_cx_rdpm,
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&qhs_dcc_cfg,
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&qhs_ddrss_cfg,
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&qhs_display_cfg,
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&qhs_gpuss_cfg,
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&qhs_imem_cfg,
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&qhs_ipa,
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&qhs_ipc_router,
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&qhs_lpass_cfg,
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&qhs_mnoc_cfg,
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&qhs_npu_cfg,
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&qhs_pcie0_cfg,
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&qhs_pcie1_cfg,
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&qhs_pcie_modem_cfg,
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&qhs_pdm,
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&qhs_pimem_cfg,
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&qhs_prng,
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&qhs_qdss_cfg,
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&qhs_qspi,
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&qhs_qup0,
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&qhs_qup1,
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&qhs_qup2,
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&qhs_sdc2,
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&qhs_sdc4,
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&qhs_snoc_cfg,
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&qhs_tcsr,
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&qhs_tlmm0,
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&qhs_tlmm1,
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&qhs_tlmm2,
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&qhs_tsif,
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&qhs_ufs_card_cfg,
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&qhs_ufs_mem_cfg,
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&qhs_usb3_0,
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&qhs_usb3_1,
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&qhs_venus_cfg,
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&qhs_vsense_ctrl_cfg,
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&qns_cnoc_a2noc,
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&srvc_cnoc
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},
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};
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static struct qcom_icc_bcm bcm_sn1 = {
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.name = "SN1",
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.keepalive = false,
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.num_nodes = 1,
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.nodes = { &qxs_imem },
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};
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+
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static struct qcom_icc_bcm bcm_sn2 = {
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.name = "SN2",
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.keepalive = false,
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.num_nodes = 1,
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.nodes = { &qns_gemnoc_gc },
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};
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+
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static struct qcom_icc_bcm bcm_co2 = {
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.name = "CO2",
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.keepalive = false,
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+
.num_nodes = 1,
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.nodes = { &qnm_npu },
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};
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+
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static struct qcom_icc_bcm bcm_sn3 = {
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.name = "SN3",
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.keepalive = false,
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.num_nodes = 1,
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.nodes = { &qxs_pimem },
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};
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+
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static struct qcom_icc_bcm bcm_sn4 = {
1584
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.name = "SN4",
1585
+
.keepalive = false,
1586
+
.num_nodes = 1,
1587
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.nodes = { &xs_qdss_stm },
1588
+
};
1589
+
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static struct qcom_icc_bcm bcm_sn5 = {
1591
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.name = "SN5",
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.keepalive = false,
1593
+
.num_nodes = 1,
1594
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.nodes = { &xs_pcie_modem },
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+
};
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+
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static struct qcom_icc_bcm bcm_sn6 = {
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.name = "SN6",
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.keepalive = false,
1600
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.num_nodes = 2,
1601
+
.nodes = { &xs_pcie_0, &xs_pcie_1 },
1602
+
};
1603
+
1604
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static struct qcom_icc_bcm bcm_sn7 = {
1605
+
.name = "SN7",
1606
+
.keepalive = false,
1607
+
.num_nodes = 1,
1608
+
.nodes = { &qnm_aggre1_noc },
1609
+
};
1610
+
1611
+
static struct qcom_icc_bcm bcm_sn8 = {
1612
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.name = "SN8",
1613
+
.keepalive = false,
1614
+
.num_nodes = 1,
1615
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.nodes = { &qnm_aggre2_noc },
1616
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};
1617
+
1618
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static struct qcom_icc_bcm bcm_sn9 = {
1619
+
.name = "SN9",
1620
+
.keepalive = false,
1621
+
.num_nodes = 1,
1622
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.nodes = { &qnm_gemnoc_pcie },
1623
+
};
1624
+
1625
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static struct qcom_icc_bcm bcm_sn11 = {
1626
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.name = "SN11",
1627
+
.keepalive = false,
1628
+
.num_nodes = 1,
1629
+
.nodes = { &qnm_gemnoc },
1630
+
};
1631
+
1632
+
static struct qcom_icc_bcm bcm_sn12 = {
1633
+
.name = "SN12",
1634
+
.keepalive = false,
1635
+
.num_nodes = 2,
1636
+
.nodes = { &qns_pcie_modem_mem_noc, &qns_pcie_mem_noc },
1637
+
};
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static struct qcom_icc_bcm * const aggre1_noc_bcms[] = {
1427
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&bcm_sn12,