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phy: rockchip: samsung-hdptx: Enable lane output in common helper

In preparation to support FRL mode, move the PHY lane output enablement
from the TMDS specific configuration to the common *_post_enable_lane()
helper and make sure it gets turned off in *_phy_disable().

Signed-off-by: Cristian Ciocaltea <cristian.ciocaltea@collabora.com>
Link: https://patch.msgid.link/20260113-phy-hdptx-frl-v6-5-8d5f97419c0b@collabora.com
Signed-off-by: Vinod Koul <vkoul@kernel.org>

authored by

Cristian Ciocaltea and committed by
Vinod Koul 8e8aa072 925f26a4

+3 -1
+3 -1
drivers/phy/rockchip/phy-rockchip-samsung-hdptx.c
··· 797 797 HDPTX_I_BIAS_EN | HDPTX_I_BGR_EN; 798 798 regmap_write(hdptx->grf, GRF_HDPTX_CON0, val); 799 799 800 + regmap_write(hdptx->regmap, LNTOP_REG(0207), 0x0f); 801 + 800 802 ret = regmap_read_poll_timeout(hdptx->grf, GRF_HDPTX_STATUS, val, 801 803 (val & HDPTX_O_PHY_RDY) && 802 804 (val & HDPTX_O_PLL_LOCK_DONE), ··· 852 850 usleep_range(20, 30); 853 851 reset_control_deassert(hdptx->rsts[RST_APB].rstc); 854 852 853 + regmap_write(hdptx->regmap, LNTOP_REG(0207), 0x0); 855 854 regmap_write(hdptx->regmap, LANE_REG(0300), 0x82); 856 855 regmap_write(hdptx->regmap, SB_REG(010f), 0xc1); 857 856 regmap_write(hdptx->regmap, SB_REG(0110), 0x1); ··· 1030 1027 } 1031 1028 1032 1029 regmap_write(hdptx->regmap, LNTOP_REG(0206), 0x07); 1033 - regmap_write(hdptx->regmap, LNTOP_REG(0207), 0x0f); 1034 1030 1035 1031 rk_hdptx_multi_reg_write(hdptx, rk_hdptx_common_lane_init_seq); 1036 1032 rk_hdptx_multi_reg_write(hdptx, rk_hdptx_tmds_lane_init_seq);