Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
drm/amd/pm: Check feature support using IP version
Instead of ASIC type, use GC and MP1 IP versions for feature support checks.
Signed-off-by: Lijo Lazar <lijo.lazar@amd.com>
Reviewed-by: Kevin Wang <kevinyang.wang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
authored by
Lijo Lazar
and committed by
Alex Deucher
8ecad8d6
e3026a05
+40
-33
+40
-33
drivers/gpu/drm/amd/pm/amdgpu_pm.c
+40
-33
drivers/gpu/drm/amd/pm/amdgpu_pm.c
···
1954
1954
uint32_t mask, enum amdgpu_device_attr_states *states)
1955
1955
{
1956
1956
struct device_attribute *dev_attr = &attr->dev_attr;
1957
+
uint32_t mp1_ver = adev->ip_versions[MP1_HWIP][0];
1958
+
uint32_t gc_ver = adev->ip_versions[GC_HWIP][0];
1957
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const char *attr_name = dev_attr->attr.name;
1958
-
enum amd_asic_type asic_type = adev->asic_type;
1959
1960
1960
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if (!(attr->flags & mask)) {
1961
1962
*states = ATTR_STATE_UNSUPPORTED;
···
1966
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#define DEVICE_ATTR_IS(_name) (!strcmp(attr_name, #_name))
1967
1966
1968
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if (DEVICE_ATTR_IS(pp_dpm_socclk)) {
1969
-
if (asic_type < CHIP_VEGA10)
1968
+
if (gc_ver < IP_VERSION(9, 0, 0))
1970
1969
*states = ATTR_STATE_UNSUPPORTED;
1971
1970
} else if (DEVICE_ATTR_IS(pp_dpm_dcefclk)) {
1972
-
if (asic_type < CHIP_VEGA10 ||
1973
-
asic_type == CHIP_ARCTURUS ||
1974
-
asic_type == CHIP_ALDEBARAN)
1971
+
if (gc_ver < IP_VERSION(9, 0, 0) ||
1972
+
gc_ver == IP_VERSION(9, 4, 1) ||
1973
+
gc_ver == IP_VERSION(9, 4, 2))
1975
1974
*states = ATTR_STATE_UNSUPPORTED;
1976
1975
} else if (DEVICE_ATTR_IS(pp_dpm_fclk)) {
1977
-
if (asic_type < CHIP_VEGA20)
1976
+
if (mp1_ver < IP_VERSION(10, 0, 0))
1978
1977
*states = ATTR_STATE_UNSUPPORTED;
1979
1978
} else if (DEVICE_ATTR_IS(pp_od_clk_voltage)) {
1980
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*states = ATTR_STATE_UNSUPPORTED;
1981
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if (amdgpu_dpm_is_overdrive_supported(adev))
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*states = ATTR_STATE_SUPPORTED;
1983
1982
} else if (DEVICE_ATTR_IS(mem_busy_percent)) {
1984
-
if (adev->flags & AMD_IS_APU || asic_type == CHIP_VEGA10)
1983
+
if (adev->flags & AMD_IS_APU || gc_ver == IP_VERSION(9, 0, 1))
1985
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*states = ATTR_STATE_UNSUPPORTED;
1986
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} else if (DEVICE_ATTR_IS(pcie_bw)) {
1987
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/* PCIe Perf counters won't work on APU nodes */
1988
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if (adev->flags & AMD_IS_APU)
1989
1988
*states = ATTR_STATE_UNSUPPORTED;
1990
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} else if (DEVICE_ATTR_IS(unique_id)) {
1991
-
if (asic_type != CHIP_VEGA10 &&
1992
-
asic_type != CHIP_VEGA20 &&
1993
-
asic_type != CHIP_ARCTURUS &&
1994
-
asic_type != CHIP_ALDEBARAN)
1990
+
if (gc_ver != IP_VERSION(9, 0, 1) &&
1991
+
gc_ver != IP_VERSION(9, 4, 0) &&
1992
+
gc_ver != IP_VERSION(9, 4, 1) &&
1993
+
gc_ver != IP_VERSION(9, 4, 2))
1995
1994
*states = ATTR_STATE_UNSUPPORTED;
1996
1995
} else if (DEVICE_ATTR_IS(pp_features)) {
1997
-
if (adev->flags & AMD_IS_APU || asic_type < CHIP_VEGA10)
1996
+
if (adev->flags & AMD_IS_APU || gc_ver < IP_VERSION(9, 0, 0))
1998
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*states = ATTR_STATE_UNSUPPORTED;
1999
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} else if (DEVICE_ATTR_IS(gpu_metrics)) {
2000
-
if (asic_type < CHIP_VEGA12)
1999
+
if (gc_ver < IP_VERSION(9, 1, 0))
2001
2000
*states = ATTR_STATE_UNSUPPORTED;
2002
2001
} else if (DEVICE_ATTR_IS(pp_dpm_vclk)) {
2003
-
if (!(asic_type == CHIP_VANGOGH || asic_type == CHIP_SIENNA_CICHLID))
2002
+
if (!(gc_ver == IP_VERSION(10, 3, 1) ||
2003
+
gc_ver == IP_VERSION(10, 3, 0)))
2004
2004
*states = ATTR_STATE_UNSUPPORTED;
2005
2005
} else if (DEVICE_ATTR_IS(pp_dpm_dclk)) {
2006
-
if (!(asic_type == CHIP_VANGOGH || asic_type == CHIP_SIENNA_CICHLID))
2006
+
if (!(gc_ver == IP_VERSION(10, 3, 1) ||
2007
+
gc_ver == IP_VERSION(10, 3, 0)))
2007
2008
*states = ATTR_STATE_UNSUPPORTED;
2008
2009
} else if (DEVICE_ATTR_IS(pp_power_profile_mode)) {
2009
2010
if (amdgpu_dpm_get_power_profile_mode(adev, NULL) == -EOPNOTSUPP)
2010
2011
*states = ATTR_STATE_UNSUPPORTED;
2011
2012
}
2012
2013
2013
-
switch (asic_type) {
2014
-
case CHIP_ARCTURUS:
2015
-
case CHIP_ALDEBARAN:
2014
+
switch (gc_ver) {
2015
+
case IP_VERSION(9, 4, 1):
2016
+
case IP_VERSION(9, 4, 2):
2016
2017
/* the Mi series card does not support standalone mclk/socclk/fclk level setting */
2017
2018
if (DEVICE_ATTR_IS(pp_dpm_mclk) ||
2018
2019
DEVICE_ATTR_IS(pp_dpm_socclk) ||
···
2029
2026
2030
2027
if (DEVICE_ATTR_IS(pp_dpm_dcefclk)) {
2031
2028
/* SMU MP1 does not support dcefclk level setting */
2032
-
if (asic_type >= CHIP_NAVI10) {
2029
+
if (gc_ver >= IP_VERSION(10, 0, 0)) {
2033
2030
dev_attr->attr.mode &= ~S_IWUGO;
2034
2031
dev_attr->store = NULL;
2035
2032
}
···
2867
2864
char *buf)
2868
2865
{
2869
2866
struct amdgpu_device *adev = dev_get_drvdata(dev);
2867
+
uint32_t gc_ver = adev->ip_versions[GC_HWIP][0];
2870
2868
2871
-
if (adev->asic_type == CHIP_VANGOGH)
2869
+
if (gc_ver == IP_VERSION(10, 3, 1))
2872
2870
return sysfs_emit(buf, "%s\n",
2873
2871
to_sensor_dev_attr(attr)->index == PP_PWR_TYPE_FAST ?
2874
2872
"fastPPT" : "slowPPT");
···
3181
3177
struct device *dev = kobj_to_dev(kobj);
3182
3178
struct amdgpu_device *adev = dev_get_drvdata(dev);
3183
3179
umode_t effective_mode = attr->mode;
3180
+
uint32_t gc_ver = adev->ip_versions[GC_HWIP][0];
3184
3181
3185
3182
/* under multi-vf mode, the hwmon attributes are all not supported */
3186
3183
if (amdgpu_sriov_vf(adev) && !amdgpu_sriov_is_pp_one_vf(adev))
···
3250
3245
attr == &sensor_dev_attr_pwm1_enable.dev_attr.attr)) /* can't manage state */
3251
3246
effective_mode &= ~S_IWUSR;
3252
3247
3248
+
/* not implemented yet for GC 10.3.1 APUs */
3253
3249
if (((adev->family == AMDGPU_FAMILY_SI) ||
3254
-
((adev->flags & AMD_IS_APU) &&
3255
-
(adev->asic_type != CHIP_VANGOGH))) && /* not implemented yet */
3250
+
((adev->flags & AMD_IS_APU) && (gc_ver != IP_VERSION(10, 3, 1)))) &&
3256
3251
(attr == &sensor_dev_attr_power1_cap_max.dev_attr.attr ||
3257
-
attr == &sensor_dev_attr_power1_cap_min.dev_attr.attr||
3252
+
attr == &sensor_dev_attr_power1_cap_min.dev_attr.attr ||
3258
3253
attr == &sensor_dev_attr_power1_cap.dev_attr.attr ||
3259
3254
attr == &sensor_dev_attr_power1_cap_default.dev_attr.attr))
3260
3255
return 0;
3261
3256
3257
+
/* not implemented yet for APUs having <= GC 9.3.0 */
3262
3258
if (((adev->family == AMDGPU_FAMILY_SI) ||
3263
-
((adev->flags & AMD_IS_APU) &&
3264
-
(adev->asic_type < CHIP_RENOIR))) && /* not implemented yet */
3259
+
((adev->flags & AMD_IS_APU) && (gc_ver < IP_VERSION(9, 3, 0)))) &&
3265
3260
(attr == &sensor_dev_attr_power1_average.dev_attr.attr))
3266
3261
return 0;
3267
3262
···
3299
3294
return 0;
3300
3295
3301
3296
/* only SOC15 dGPUs support hotspot and mem temperatures */
3302
-
if (((adev->flags & AMD_IS_APU) ||
3303
-
adev->asic_type < CHIP_VEGA10) &&
3297
+
if (((adev->flags & AMD_IS_APU) || gc_ver < IP_VERSION(9, 0, 0)) &&
3304
3298
(attr == &sensor_dev_attr_temp2_crit.dev_attr.attr ||
3305
3299
attr == &sensor_dev_attr_temp2_crit_hyst.dev_attr.attr ||
3306
3300
attr == &sensor_dev_attr_temp3_crit.dev_attr.attr ||
···
3314
3310
return 0;
3315
3311
3316
3312
/* only Vangogh has fast PPT limit and power labels */
3317
-
if (!(adev->asic_type == CHIP_VANGOGH) &&
3313
+
if (!(gc_ver == IP_VERSION(10, 3, 1)) &&
3318
3314
(attr == &sensor_dev_attr_power2_average.dev_attr.attr ||
3319
-
attr == &sensor_dev_attr_power2_cap_max.dev_attr.attr ||
3315
+
attr == &sensor_dev_attr_power2_cap_max.dev_attr.attr ||
3320
3316
attr == &sensor_dev_attr_power2_cap_min.dev_attr.attr ||
3321
-
attr == &sensor_dev_attr_power2_cap.dev_attr.attr ||
3322
-
attr == &sensor_dev_attr_power2_cap_default.dev_attr.attr ||
3323
-
attr == &sensor_dev_attr_power2_label.dev_attr.attr))
3317
+
attr == &sensor_dev_attr_power2_cap.dev_attr.attr ||
3318
+
attr == &sensor_dev_attr_power2_cap_default.dev_attr.attr ||
3319
+
attr == &sensor_dev_attr_power2_label.dev_attr.attr))
3324
3320
return 0;
3325
3321
3326
3322
return effective_mode;
···
3425
3421
3426
3422
static int amdgpu_debugfs_pm_info_pp(struct seq_file *m, struct amdgpu_device *adev)
3427
3423
{
3424
+
uint32_t mp1_ver = adev->ip_versions[MP1_HWIP][0];
3425
+
uint32_t gc_ver = adev->ip_versions[GC_HWIP][0];
3428
3426
uint32_t value;
3429
3427
uint64_t value64 = 0;
3430
3428
uint32_t query = 0;
···
3473
3467
if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_ENABLED_SMC_FEATURES_MASK, (void *)&value64, &size))
3474
3468
seq_printf(m, "SMC Feature Mask: 0x%016llx\n", value64);
3475
3469
3476
-
if (adev->asic_type > CHIP_VEGA20) {
3470
+
/* ASICs greater than CHIP_VEGA20 supports these sensors */
3471
+
if (gc_ver != IP_VERSION(9, 4, 0) && mp1_ver > IP_VERSION(9, 0, 0)) {
3477
3472
/* VCN clocks */
3478
3473
if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_VCN_POWER_STATE, (void *)&value, &size)) {
3479
3474
if (!value) {