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drm/amdgpu/vcn3: send smu interface type

For VCN FW to detect ASIC type, in order to use different mailbox registers.

V2: simplify codes and fix format issue.

Signed-off-by: Boyuan Zhang <boyuan.zhang@amd.com>
Acked-by Huang Rui <ray.huang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

authored by

Boyuan Zhang and committed by
Alex Deucher
e3026a05 a63e6b83

+12
+7
drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.h
··· 159 159 #define AMDGPU_VCN_MULTI_QUEUE_FLAG (1 << 8) 160 160 #define AMDGPU_VCN_SW_RING_FLAG (1 << 9) 161 161 #define AMDGPU_VCN_FW_LOGGING_FLAG (1 << 10) 162 + #define AMDGPU_VCN_SMU_VERSION_INFO_FLAG (1 << 11) 162 163 163 164 #define AMDGPU_VCN_IB_FLAG_DECODE_BUFFER 0x00000001 164 165 #define AMDGPU_VCN_CMD_FLAG_MSG_BUFFER 0x00000001 ··· 280 279 uint32_t size; 281 280 }; 282 281 282 + struct amdgpu_fw_shared_smu_interface_info { 283 + uint8_t smu_interface_type; 284 + uint8_t padding[3]; 285 + }; 286 + 283 287 struct amdgpu_fw_shared { 284 288 uint32_t present_flag_0; 285 289 uint8_t pad[44]; ··· 293 287 struct amdgpu_fw_shared_multi_queue multi_queue; 294 288 struct amdgpu_fw_shared_sw_ring sw_ring; 295 289 struct amdgpu_fw_shared_fw_logging fw_log; 290 + struct amdgpu_fw_shared_smu_interface_info smu_interface_info; 296 291 }; 297 292 298 293 struct amdgpu_vcn_fwlog {
+5
drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c
··· 219 219 cpu_to_le32(AMDGPU_VCN_MULTI_QUEUE_FLAG) | 220 220 cpu_to_le32(AMDGPU_VCN_FW_SHARED_FLAG_0_RB); 221 221 fw_shared->sw_ring.is_enabled = cpu_to_le32(DEC_SW_RING_ENABLED); 222 + fw_shared->present_flag_0 |= AMDGPU_VCN_SMU_VERSION_INFO_FLAG; 223 + if (adev->ip_versions[UVD_HWIP][0] == IP_VERSION(3, 1, 2)) 224 + fw_shared->smu_interface_info.smu_interface_type = 2; 225 + else if (adev->ip_versions[UVD_HWIP][0] == IP_VERSION(3, 1, 1)) 226 + fw_shared->smu_interface_info.smu_interface_type = 1; 222 227 223 228 if (amdgpu_vcnfw_log) 224 229 amdgpu_vcn_fwlog_init(&adev->vcn.inst[i]);