tjh.dev / kernel
Linux kernel mirror (for testing) git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
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Merge tag 'sunxi-dt-for-6.4-1' of https://git.kernel.org/pub/scm/linux/kernel/git/sunxi/linux into soc/dt

- added D1 crypto node
- enabled DVFS on OrangePi PC2 board
- added GPIO line names on Nezha D1 board
- added suniv USB nodes and enabled on licheepi-nano
- new suniv boards: PopStick v1.1 and Lctech Pi
- added Allwinner T113-s DTSI
- added MangoPi MQ-R T113-s board variant
- swapped DMA names for A23, A31, A33, D1, H3, H5, V3s

* tag 'sunxi-dt-for-6.4-1' of https://git.kernel.org/pub/scm/linux/kernel/git/sunxi/linux:
riscv: dts: allwinner: d1: Switch dma-names order for snps,dw-apb-uart nodes
ARM: dts: sunxi: h3/h5: Switch dma-names order for snps,dw-apb-uart nodes
ARM: dts: sun8i: v3s: Switch dma-names order for snps,dw-apb-uart nodes
ARM: dts: sun8i: a23/a33: Switch dma-names order for snps,dw-apb-uart nodes
ARM: dts: sun6i: a31: Switch dma-names order for snps,dw-apb-uart nodes
ARM: dts: sunxi: add MangoPi MQ-R-T113 board
dt-bindings: arm: sunxi: document MangoPi MQ-R board names
ARM: dts: sunxi: add Allwinner T113-s SoC .dtsi
dts: add riscv include prefix link
ARM: dts: suniv: Add Lctech Pi F1C200s devicetree
ARM: dts: suniv: add device tree for PopStick v1.1
dt-binding: arm: sunxi: add two board compatible strings
dt-bindings: vendor-prefixes: add Source Parts and Lctech names
ARM: dts: suniv: licheepi-nano: enable USB
ARM: dts: suniv: add USB-related device nodes
riscv: dts: nezha-d1: add gpio-line-names
arm64: dts: allwinner: h5: OrangePi PC2: add OPP table to enable DVFS
riscv: dts: allwinner: d1: Add crypto engine node

Link: https://lore.kernel.org/r/20230408125156.GA17050@jernej-laptop
Signed-off-by: Arnd Bergmann <arnd@arndb.de>

Arnd Bergmann 8f09b5ec 58982e1d

+565 -25
+18
Documentation/devicetree/bindings/arm/sunxi.yaml
··· 366 366 - const: lamobo,lamobo-r1 367 367 - const: allwinner,sun7i-a20 368 368 369 + - description: Lctech Pi F1C200s 370 + items: 371 + - const: lctech,pi-f1c200s 372 + - const: allwinner,suniv-f1c200s 373 + - const: allwinner,suniv-f1c100s 374 + 369 375 - description: Libre Computer Board ALL-H3-CC H2+ 370 376 items: 371 377 - const: libretech,all-h3-cc-h2-plus ··· 813 807 - const: sinlinx,sina33 814 808 - const: allwinner,sun8i-a33 815 809 810 + - description: SourceParts PopStick v1.1 811 + items: 812 + - const: sourceparts,popstick-v1.1 813 + - const: sourceparts,popstick 814 + - const: allwinner,suniv-f1c200s 815 + - const: allwinner,suniv-f1c100s 816 + 816 817 - description: SL631 Action Camera with IMX179 817 818 items: 818 819 - const: allwinner,sl631-imx179 ··· 855 842 items: 856 843 - const: wexler,tab7200 857 844 - const: allwinner,sun7i-a20 845 + 846 + - description: MangoPi MQ-R board 847 + items: 848 + - const: widora,mangopi-mq-r-t113 849 + - const: allwinner,sun8i-t113s 858 850 859 851 - description: WITS A31 Colombus Evaluation Board 860 852 items:
+5
Documentation/devicetree/bindings/riscv/sunxi.yaml
··· 64 64 - const: widora,mangopi-mq-pro 65 65 - const: allwinner,sun20i-d1 66 66 67 + - description: MangoPi MQ-R board 68 + items: 69 + - const: widora,mangopi-mq-r-f133 70 + - const: allwinner,sun20i-d1s 71 + 67 72 additionalProperties: true 68 73 69 74 ...
+4
Documentation/devicetree/bindings/vendor-prefixes.yaml
··· 725 725 description: Lantiq Semiconductor 726 726 "^lattice,.*": 727 727 description: Lattice Semiconductor 728 + "^lctech,.*": 729 + description: Shenzen LC Technology Co., Ltd. 728 730 "^leadtek,.*": 729 731 description: Shenzhen Leadtek Technology Co., Ltd. 730 732 "^leez,.*": ··· 1251 1249 description: Solomon Systech Limited 1252 1250 "^sony,.*": 1253 1251 description: Sony Corporation 1252 + "^sourceparts,.*": 1253 + description: Source Parts Inc. 1254 1254 "^spansion,.*": 1255 1255 description: Spansion Inc. 1256 1256 "^sparkfun,.*":
+4 -1
arch/arm/boot/dts/Makefile
··· 1411 1411 sun8i-s3-elimo-initium.dtb \ 1412 1412 sun8i-s3-lichee-zero-plus.dtb \ 1413 1413 sun8i-s3-pinecube.dtb \ 1414 + sun8i-t113s-mangopi-mq-r-t113.dtb \ 1414 1415 sun8i-t3-cqa3t-bv3.dtb \ 1415 1416 sun8i-v3-sl631-imx179.dtb \ 1416 1417 sun8i-v3s-licheepi-zero.dtb \ ··· 1421 1420 sun9i-a80-optimus.dtb \ 1422 1421 sun9i-a80-cubieboard4.dtb 1423 1422 dtb-$(CONFIG_MACH_SUNIV) += \ 1424 - suniv-f1c100s-licheepi-nano.dtb 1423 + suniv-f1c100s-licheepi-nano.dtb \ 1424 + suniv-f1c200s-lctech-pi.dtb \ 1425 + suniv-f1c200s-popstick-v1.1.dtb 1425 1426 dtb-$(CONFIG_ARCH_TEGRA_2x_SOC) += \ 1426 1427 tegra20-acer-a500-picasso.dtb \ 1427 1428 tegra20-asus-tf101.dtb \
+6 -6
arch/arm/boot/dts/sun6i-a31.dtsi
··· 822 822 clocks = <&ccu CLK_APB2_UART0>; 823 823 resets = <&ccu RST_APB2_UART0>; 824 824 dmas = <&dma 6>, <&dma 6>; 825 - dma-names = "rx", "tx"; 825 + dma-names = "tx", "rx"; 826 826 status = "disabled"; 827 827 }; 828 828 ··· 835 835 clocks = <&ccu CLK_APB2_UART1>; 836 836 resets = <&ccu RST_APB2_UART1>; 837 837 dmas = <&dma 7>, <&dma 7>; 838 - dma-names = "rx", "tx"; 838 + dma-names = "tx", "rx"; 839 839 status = "disabled"; 840 840 }; 841 841 ··· 848 848 clocks = <&ccu CLK_APB2_UART2>; 849 849 resets = <&ccu RST_APB2_UART2>; 850 850 dmas = <&dma 8>, <&dma 8>; 851 - dma-names = "rx", "tx"; 851 + dma-names = "tx", "rx"; 852 852 status = "disabled"; 853 853 }; 854 854 ··· 861 861 clocks = <&ccu CLK_APB2_UART3>; 862 862 resets = <&ccu RST_APB2_UART3>; 863 863 dmas = <&dma 9>, <&dma 9>; 864 - dma-names = "rx", "tx"; 864 + dma-names = "tx", "rx"; 865 865 status = "disabled"; 866 866 }; 867 867 ··· 874 874 clocks = <&ccu CLK_APB2_UART4>; 875 875 resets = <&ccu RST_APB2_UART4>; 876 876 dmas = <&dma 10>, <&dma 10>; 877 - dma-names = "rx", "tx"; 877 + dma-names = "tx", "rx"; 878 878 status = "disabled"; 879 879 }; 880 880 ··· 887 887 clocks = <&ccu CLK_APB2_UART5>; 888 888 resets = <&ccu RST_APB2_UART5>; 889 889 dmas = <&dma 22>, <&dma 22>; 890 - dma-names = "rx", "tx"; 890 + dma-names = "tx", "rx"; 891 891 status = "disabled"; 892 892 }; 893 893
+5 -5
arch/arm/boot/dts/sun8i-a23-a33.dtsi
··· 490 490 clocks = <&ccu CLK_BUS_UART0>; 491 491 resets = <&ccu RST_BUS_UART0>; 492 492 dmas = <&dma 6>, <&dma 6>; 493 - dma-names = "rx", "tx"; 493 + dma-names = "tx", "rx"; 494 494 status = "disabled"; 495 495 }; 496 496 ··· 503 503 clocks = <&ccu CLK_BUS_UART1>; 504 504 resets = <&ccu RST_BUS_UART1>; 505 505 dmas = <&dma 7>, <&dma 7>; 506 - dma-names = "rx", "tx"; 506 + dma-names = "tx", "rx"; 507 507 status = "disabled"; 508 508 }; 509 509 ··· 516 516 clocks = <&ccu CLK_BUS_UART2>; 517 517 resets = <&ccu RST_BUS_UART2>; 518 518 dmas = <&dma 8>, <&dma 8>; 519 - dma-names = "rx", "tx"; 519 + dma-names = "tx", "rx"; 520 520 status = "disabled"; 521 521 }; 522 522 ··· 529 529 clocks = <&ccu CLK_BUS_UART3>; 530 530 resets = <&ccu RST_BUS_UART3>; 531 531 dmas = <&dma 9>, <&dma 9>; 532 - dma-names = "rx", "tx"; 532 + dma-names = "tx", "rx"; 533 533 status = "disabled"; 534 534 }; 535 535 ··· 542 542 clocks = <&ccu CLK_BUS_UART4>; 543 543 resets = <&ccu RST_BUS_UART4>; 544 544 dmas = <&dma 10>, <&dma 10>; 545 - dma-names = "rx", "tx"; 545 + dma-names = "tx", "rx"; 546 546 status = "disabled"; 547 547 }; 548 548
+35
arch/arm/boot/dts/sun8i-t113s-mangopi-mq-r-t113.dts
··· 1 + // SPDX-License-Identifier: (GPL-2.0+ or MIT) 2 + // Copyright (C) 2022 Arm Ltd. 3 + 4 + #include <dt-bindings/interrupt-controller/irq.h> 5 + 6 + /dts-v1/; 7 + 8 + #include "sun8i-t113s.dtsi" 9 + #include "sunxi-d1s-t113-mangopi-mq-r.dtsi" 10 + 11 + / { 12 + model = "MangoPi MQ-R-T113"; 13 + compatible = "widora,mangopi-mq-r-t113", "allwinner,sun8i-t113s"; 14 + 15 + aliases { 16 + ethernet0 = &rtl8189ftv; 17 + }; 18 + }; 19 + 20 + &cpu0 { 21 + cpu-supply = <&reg_vcc_core>; 22 + }; 23 + 24 + &cpu1 { 25 + cpu-supply = <&reg_vcc_core>; 26 + }; 27 + 28 + &mmc1 { 29 + rtl8189ftv: wifi@1 { 30 + reg = <1>; 31 + interrupt-parent = <&pio>; 32 + interrupts = <6 10 IRQ_TYPE_LEVEL_LOW>; /* PG10 = WL_WAKE_AP */ 33 + interrupt-names = "host-wake"; 34 + }; 35 + };
+59
arch/arm/boot/dts/sun8i-t113s.dtsi
··· 1 + // SPDX-License-Identifier: (GPL-2.0+ or MIT) 2 + // Copyright (C) 2022 Arm Ltd. 3 + 4 + #define SOC_PERIPHERAL_IRQ(nr) GIC_SPI nr 5 + 6 + #include <dt-bindings/interrupt-controller/arm-gic.h> 7 + #include <riscv/allwinner/sunxi-d1s-t113.dtsi> 8 + #include <riscv/allwinner/sunxi-d1-t113.dtsi> 9 + 10 + / { 11 + interrupt-parent = <&gic>; 12 + 13 + cpus { 14 + #address-cells = <1>; 15 + #size-cells = <0>; 16 + 17 + cpu0: cpu@0 { 18 + compatible = "arm,cortex-a7"; 19 + device_type = "cpu"; 20 + reg = <0>; 21 + clocks = <&ccu CLK_CPUX>; 22 + clock-names = "cpu"; 23 + }; 24 + 25 + cpu1: cpu@1 { 26 + compatible = "arm,cortex-a7"; 27 + device_type = "cpu"; 28 + reg = <1>; 29 + clocks = <&ccu CLK_CPUX>; 30 + clock-names = "cpu"; 31 + }; 32 + }; 33 + 34 + gic: interrupt-controller@1c81000 { 35 + compatible = "arm,gic-400"; 36 + reg = <0x03021000 0x1000>, 37 + <0x03022000 0x2000>, 38 + <0x03024000 0x2000>, 39 + <0x03026000 0x2000>; 40 + interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; 41 + interrupt-controller; 42 + #interrupt-cells = <3>; 43 + }; 44 + 45 + timer { 46 + compatible = "arm,armv7-timer"; 47 + interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 48 + <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 49 + <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 50 + <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; 51 + }; 52 + 53 + pmu { 54 + compatible = "arm,cortex-a7-pmu"; 55 + interrupts = <GIC_SPI 172 IRQ_TYPE_LEVEL_HIGH>, 56 + <GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>; 57 + interrupt-affinity = <&cpu0>, <&cpu1>; 58 + }; 59 + };
+3 -3
arch/arm/boot/dts/sun8i-v3s.dtsi
··· 479 479 reg-io-width = <4>; 480 480 clocks = <&ccu CLK_BUS_UART0>; 481 481 dmas = <&dma 6>, <&dma 6>; 482 - dma-names = "rx", "tx"; 482 + dma-names = "tx", "rx"; 483 483 resets = <&ccu RST_BUS_UART0>; 484 484 status = "disabled"; 485 485 }; ··· 492 492 reg-io-width = <4>; 493 493 clocks = <&ccu CLK_BUS_UART1>; 494 494 dmas = <&dma 7>, <&dma 7>; 495 - dma-names = "rx", "tx"; 495 + dma-names = "tx", "rx"; 496 496 resets = <&ccu RST_BUS_UART1>; 497 497 status = "disabled"; 498 498 }; ··· 505 505 reg-io-width = <4>; 506 506 clocks = <&ccu CLK_BUS_UART2>; 507 507 dmas = <&dma 8>, <&dma 8>; 508 - dma-names = "rx", "tx"; 508 + dma-names = "tx", "rx"; 509 509 resets = <&ccu RST_BUS_UART2>; 510 510 pinctrl-0 = <&uart2_pins>; 511 511 pinctrl-names = "default";
+16
arch/arm/boot/dts/suniv-f1c100s-licheepi-nano.dts
··· 6 6 /dts-v1/; 7 7 #include "suniv-f1c100s.dtsi" 8 8 9 + #include <dt-bindings/gpio/gpio.h> 10 + 9 11 / { 10 12 model = "Lichee Pi Nano"; 11 13 compatible = "licheepi,licheepi-nano", "allwinner,suniv-f1c100s"; ··· 52 50 }; 53 51 }; 54 52 53 + &otg_sram { 54 + status = "okay"; 55 + }; 56 + 55 57 &uart0 { 56 58 pinctrl-names = "default"; 57 59 pinctrl-0 = <&uart0_pe_pins>; 60 + status = "okay"; 61 + }; 62 + 63 + &usb_otg { 64 + dr_mode = "otg"; 65 + status = "okay"; 66 + }; 67 + 68 + &usbphy { 69 + usb0_id_det-gpios = <&pio 4 2 GPIO_ACTIVE_HIGH>; /* PE2 */ 58 70 status = "okay"; 59 71 };
+32
arch/arm/boot/dts/suniv-f1c100s.dtsi
··· 133 133 #size-cells = <0>; 134 134 }; 135 135 136 + usb_otg: usb@1c13000 { 137 + compatible = "allwinner,suniv-f1c100s-musb"; 138 + reg = <0x01c13000 0x0400>; 139 + clocks = <&ccu CLK_BUS_OTG>; 140 + resets = <&ccu RST_BUS_OTG>; 141 + interrupts = <26>; 142 + interrupt-names = "mc"; 143 + phys = <&usbphy 0>; 144 + phy-names = "usb"; 145 + extcon = <&usbphy 0>; 146 + allwinner,sram = <&otg_sram 1>; 147 + status = "disabled"; 148 + }; 149 + 150 + usbphy: phy@1c13400 { 151 + compatible = "allwinner,suniv-f1c100s-usb-phy"; 152 + reg = <0x01c13400 0x10>; 153 + reg-names = "phy_ctrl"; 154 + clocks = <&ccu CLK_USB_PHY0>; 155 + clock-names = "usb0_phy"; 156 + resets = <&ccu RST_USB_PHY0>; 157 + reset-names = "usb0_reset"; 158 + #phy-cells = <1>; 159 + status = "disabled"; 160 + }; 161 + 136 162 ccu: clock@1c20000 { 137 163 compatible = "allwinner,suniv-f1c100s-ccu"; 138 164 reg = <0x01c20000 0x400>; ··· 206 180 uart0_pe_pins: uart0-pe-pins { 207 181 pins = "PE0", "PE1"; 208 182 function = "uart0"; 183 + }; 184 + 185 + /omit-if-no-ref/ 186 + uart1_pa_pins: uart1-pa-pins { 187 + pins = "PA2", "PA3"; 188 + function = "uart1"; 209 189 }; 210 190 }; 211 191
+76
arch/arm/boot/dts/suniv-f1c200s-lctech-pi.dts
··· 1 + // SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2 + /* 3 + * Copyright 2022 Arm Ltd, 4 + * based on work: 5 + * Copyright 2022 Icenowy Zheng <uwu@icenowy.me> 6 + */ 7 + 8 + /dts-v1/; 9 + #include "suniv-f1c100s.dtsi" 10 + 11 + #include <dt-bindings/gpio/gpio.h> 12 + 13 + / { 14 + model = "Lctech Pi F1C200s"; 15 + compatible = "lctech,pi-f1c200s", "allwinner,suniv-f1c200s", 16 + "allwinner,suniv-f1c100s"; 17 + 18 + aliases { 19 + serial0 = &uart1; 20 + }; 21 + 22 + chosen { 23 + stdout-path = "serial0:115200n8"; 24 + }; 25 + 26 + reg_vcc3v3: regulator-3v3 { 27 + compatible = "regulator-fixed"; 28 + regulator-name = "vcc3v3"; 29 + regulator-min-microvolt = <3300000>; 30 + regulator-max-microvolt = <3300000>; 31 + }; 32 + }; 33 + 34 + &mmc0 { 35 + broken-cd; 36 + bus-width = <4>; 37 + disable-wp; 38 + vmmc-supply = <&reg_vcc3v3>; 39 + status = "okay"; 40 + }; 41 + 42 + &otg_sram { 43 + status = "okay"; 44 + }; 45 + 46 + &spi0 { 47 + pinctrl-names = "default"; 48 + pinctrl-0 = <&spi0_pc_pins>; 49 + status = "okay"; 50 + 51 + flash@0 { 52 + compatible = "spi-nand"; 53 + reg = <0>; 54 + spi-max-frequency = <40000000>; 55 + }; 56 + }; 57 + 58 + &uart1 { 59 + pinctrl-names = "default"; 60 + pinctrl-0 = <&uart1_pa_pins>; 61 + status = "okay"; 62 + }; 63 + 64 + /* 65 + * This is a Type-C socket, but CC1/2 are not connected, and VBUS is connected 66 + * to Vin, which supplies the board. Host mode works (if the board is powered 67 + * otherwise), but peripheral is probably the intention. 68 + */ 69 + &usb_otg { 70 + dr_mode = "peripheral"; 71 + status = "okay"; 72 + }; 73 + 74 + &usbphy { 75 + status = "okay"; 76 + };
+81
arch/arm/boot/dts/suniv-f1c200s-popstick-v1.1.dts
··· 1 + // SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2 + /* 3 + * Copyright 2022 Icenowy Zheng <uwu@icenowy.me> 4 + */ 5 + 6 + /dts-v1/; 7 + #include "suniv-f1c100s.dtsi" 8 + 9 + #include <dt-bindings/gpio/gpio.h> 10 + #include <dt-bindings/leds/common.h> 11 + 12 + / { 13 + model = "Popcorn Computer PopStick v1.1"; 14 + compatible = "sourceparts,popstick-v1.1", "sourceparts,popstick", 15 + "allwinner,suniv-f1c200s", "allwinner,suniv-f1c100s"; 16 + 17 + aliases { 18 + serial0 = &uart0; 19 + }; 20 + 21 + chosen { 22 + stdout-path = "serial0:115200n8"; 23 + }; 24 + 25 + leds { 26 + compatible = "gpio-leds"; 27 + 28 + led { 29 + function = LED_FUNCTION_STATUS; 30 + color = <LED_COLOR_ID_GREEN>; 31 + gpios = <&pio 4 6 GPIO_ACTIVE_HIGH>; /* PE6 */ 32 + linux,default-trigger = "heartbeat"; 33 + }; 34 + }; 35 + 36 + reg_vcc3v3: regulator-3v3 { 37 + compatible = "regulator-fixed"; 38 + regulator-name = "vcc3v3"; 39 + regulator-min-microvolt = <3300000>; 40 + regulator-max-microvolt = <3300000>; 41 + }; 42 + }; 43 + 44 + &mmc0 { 45 + cd-gpios = <&pio 4 3 GPIO_ACTIVE_LOW>; /* PE3 */ 46 + bus-width = <4>; 47 + disable-wp; 48 + vmmc-supply = <&reg_vcc3v3>; 49 + status = "okay"; 50 + }; 51 + 52 + &otg_sram { 53 + status = "okay"; 54 + }; 55 + 56 + &spi0 { 57 + pinctrl-names = "default"; 58 + pinctrl-0 = <&spi0_pc_pins>; 59 + status = "okay"; 60 + 61 + flash@0 { 62 + compatible = "spi-nand"; 63 + reg = <0>; 64 + spi-max-frequency = <40000000>; 65 + }; 66 + }; 67 + 68 + &uart0 { 69 + pinctrl-names = "default"; 70 + pinctrl-0 = <&uart0_pe_pins>; 71 + status = "okay"; 72 + }; 73 + 74 + &usb_otg { 75 + dr_mode = "peripheral"; 76 + status = "okay"; 77 + }; 78 + 79 + &usbphy { 80 + status = "okay"; 81 + };
+126
arch/arm/boot/dts/sunxi-d1s-t113-mangopi-mq-r.dtsi
··· 1 + // SPDX-License-Identifier: (GPL-2.0+ or MIT) 2 + // Copyright (C) 2022 Arm Ltd. 3 + /* 4 + * Common peripherals and configurations for MangoPi MQ-R boards. 5 + */ 6 + 7 + #include <dt-bindings/gpio/gpio.h> 8 + #include <dt-bindings/leds/common.h> 9 + 10 + / { 11 + aliases { 12 + serial3 = &uart3; 13 + }; 14 + 15 + chosen { 16 + stdout-path = "serial3:115200n8"; 17 + }; 18 + 19 + leds { 20 + compatible = "gpio-leds"; 21 + 22 + led-0 { 23 + color = <LED_COLOR_ID_BLUE>; 24 + function = LED_FUNCTION_STATUS; 25 + gpios = <&pio 3 22 GPIO_ACTIVE_LOW>; /* PD22 */ 26 + }; 27 + }; 28 + 29 + /* board wide 5V supply directly from the USB-C socket */ 30 + reg_vcc5v: regulator-5v { 31 + compatible = "regulator-fixed"; 32 + regulator-name = "vcc-5v"; 33 + regulator-min-microvolt = <5000000>; 34 + regulator-max-microvolt = <5000000>; 35 + regulator-always-on; 36 + }; 37 + 38 + /* SY8008 DC/DC regulator on the board */ 39 + reg_3v3: regulator-3v3 { 40 + compatible = "regulator-fixed"; 41 + regulator-name = "vcc-3v3"; 42 + regulator-min-microvolt = <3300000>; 43 + regulator-max-microvolt = <3300000>; 44 + vin-supply = <&reg_vcc5v>; 45 + }; 46 + 47 + /* SY8008 DC/DC regulator on the board, also supplying VDD-SYS */ 48 + reg_vcc_core: regulator-core { 49 + compatible = "regulator-fixed"; 50 + regulator-name = "vcc-core"; 51 + regulator-min-microvolt = <880000>; 52 + regulator-max-microvolt = <880000>; 53 + vin-supply = <&reg_vcc5v>; 54 + }; 55 + 56 + /* XC6206 LDO on the board */ 57 + reg_avdd2v8: regulator-avdd { 58 + compatible = "regulator-fixed"; 59 + regulator-name = "avdd2v8"; 60 + regulator-min-microvolt = <2800000>; 61 + regulator-max-microvolt = <2800000>; 62 + vin-supply = <&reg_3v3>; 63 + }; 64 + 65 + wifi_pwrseq: wifi-pwrseq { 66 + compatible = "mmc-pwrseq-simple"; 67 + reset-gpios = <&pio 6 12 GPIO_ACTIVE_LOW>; /* PG12 */ 68 + }; 69 + }; 70 + 71 + &dcxo { 72 + clock-frequency = <24000000>; 73 + }; 74 + 75 + &ehci1 { 76 + status = "okay"; 77 + }; 78 + 79 + &mmc0 { 80 + pinctrl-0 = <&mmc0_pins>; 81 + pinctrl-names = "default"; 82 + vmmc-supply = <&reg_3v3>; 83 + cd-gpios = <&pio 5 6 GPIO_ACTIVE_LOW>; 84 + disable-wp; 85 + bus-width = <4>; 86 + status = "okay"; 87 + }; 88 + 89 + &mmc1 { 90 + pinctrl-0 = <&mmc1_pins>; 91 + pinctrl-names = "default"; 92 + vmmc-supply = <&reg_3v3>; 93 + non-removable; 94 + bus-width = <4>; 95 + mmc-pwrseq = <&wifi_pwrseq>; 96 + status = "okay"; 97 + }; 98 + 99 + &ohci1 { 100 + status = "okay"; 101 + }; 102 + 103 + &pio { 104 + vcc-pb-supply = <&reg_3v3>; 105 + vcc-pd-supply = <&reg_3v3>; 106 + vcc-pe-supply = <&reg_avdd2v8>; 107 + vcc-pf-supply = <&reg_3v3>; 108 + vcc-pg-supply = <&reg_3v3>; 109 + }; 110 + 111 + &uart3 { 112 + pinctrl-names = "default"; 113 + pinctrl-0 = <&uart3_pb_pins>; 114 + status = "okay"; 115 + }; 116 + 117 + /* The USB-C socket has its CC pins pulled to GND, so is hardwired as a UFP. */ 118 + &usb_otg { 119 + dr_mode = "peripheral"; 120 + status = "okay"; 121 + }; 122 + 123 + &usbphy { 124 + usb1_vbus-supply = <&reg_vcc5v>; 125 + status = "okay"; 126 + };
+4 -4
arch/arm/boot/dts/sunxi-h3-h5.dtsi
··· 710 710 clocks = <&ccu CLK_BUS_UART0>; 711 711 resets = <&ccu RST_BUS_UART0>; 712 712 dmas = <&dma 6>, <&dma 6>; 713 - dma-names = "rx", "tx"; 713 + dma-names = "tx", "rx"; 714 714 status = "disabled"; 715 715 }; 716 716 ··· 723 723 clocks = <&ccu CLK_BUS_UART1>; 724 724 resets = <&ccu RST_BUS_UART1>; 725 725 dmas = <&dma 7>, <&dma 7>; 726 - dma-names = "rx", "tx"; 726 + dma-names = "tx", "rx"; 727 727 status = "disabled"; 728 728 }; 729 729 ··· 736 736 clocks = <&ccu CLK_BUS_UART2>; 737 737 resets = <&ccu RST_BUS_UART2>; 738 738 dmas = <&dma 8>, <&dma 8>; 739 - dma-names = "rx", "tx"; 739 + dma-names = "tx", "rx"; 740 740 status = "disabled"; 741 741 }; 742 742 ··· 749 749 clocks = <&ccu CLK_BUS_UART3>; 750 750 resets = <&ccu RST_BUS_UART3>; 751 751 dmas = <&dma 9>, <&dma 9>; 752 - dma-names = "rx", "tx"; 752 + dma-names = "tx", "rx"; 753 753 status = "disabled"; 754 754 }; 755 755
+1
arch/arm64/boot/dts/allwinner/sun50i-h5-orangepi-pc2.dts
··· 3 3 4 4 /dts-v1/; 5 5 #include "sun50i-h5.dtsi" 6 + #include "sun50i-h5-cpu-opp.dtsi" 6 7 7 8 #include <dt-bindings/gpio/gpio.h> 8 9 #include <dt-bindings/input/input.h>
+72
arch/riscv/boot/dts/allwinner/sun20i-d1-nezha.dts
··· 1 1 // SPDX-License-Identifier: (GPL-2.0+ or MIT) 2 2 // Copyright (C) 2021-2022 Samuel Holland <samuel@sholland.org> 3 3 4 + /* 5 + * gpio line names 6 + * 7 + * The Nezha-D1 has a 40-pin IO header. Some of these pins are routed 8 + * directly to pads on the SoC, others come from an 8-bit pcf857x IO 9 + * expander. Therefore, these line names are specified in two places: 10 + * one set for the pcf857x, and one set for the pio controller. 11 + * 12 + * Lines which are routed to the 40-pin header are named as follows: 13 + * <pin#> [<pin name>] 14 + * where: 15 + * <pin#> is the actual pin number of the 40-pin header 16 + * <pin name> is the name of the pin by function/gpio# 17 + * 18 + * For details regarding pin numbers and names see the schematics (under 19 + * "IO EXPAND"): 20 + * http://dl.linux-sunxi.org/D1/D1_Nezha_development_board_schematic_diagram_20210224.pdf 21 + */ 22 + 4 23 #include <dt-bindings/gpio/gpio.h> 5 24 #include <dt-bindings/input/input.h> 6 25 ··· 109 90 gpio-controller; 110 91 #gpio-cells = <2>; 111 92 #interrupt-cells = <2>; 93 + gpio-line-names = 94 + "pin13 [gpio8]", 95 + "pin16 [gpio10]", 96 + "pin18 [gpio11]", 97 + "pin26 [gpio17]", 98 + "pin22 [gpio14]", 99 + "pin28 [gpio19]", 100 + "pin37 [gpio23]", 101 + "pin11 [gpio6]"; 112 102 }; 113 103 }; 114 104 ··· 191 163 usb0_vbus-supply = <&reg_usbvbus>; 192 164 usb1_vbus-supply = <&reg_vcc>; 193 165 status = "okay"; 166 + }; 167 + 168 + &pio { 169 + gpio-line-names = 170 + /* Port A */ 171 + "", "", "", "", "", "", "", "", 172 + "", "", "", "", "", "", "", "", 173 + "", "", "", "", "", "", "", "", 174 + "", "", "", "", "", "", "", "", 175 + /* Port B */ 176 + "pin5 [gpio2/twi2-sck]", 177 + "pin3 [gpio1/twi2-sda]", 178 + "", 179 + "pin38 [gpio24/i2s2-din]", 180 + "pin40 [gpio25/i2s2-dout]", 181 + "pin12 [gpio7/i2s-clk]", 182 + "pin35 [gpio22/i2s2-lrck]", 183 + "", 184 + "pin8 [gpio4/uart0-txd]", 185 + "pin10 [gpio5/uart0-rxd]", 186 + "", 187 + "", 188 + "pin15 [gpio9]", 189 + "", "", "", "", 190 + "", "", "", "", "", "", "", "", 191 + "", "", "", "", "", "", "", "", 192 + /* Port C */ 193 + "", 194 + "pin31 [gpio21]", 195 + "", "", "", "", "", "", 196 + "", "", "", "", "", "", "", "", 197 + "", "", "", "", "", "", "", "", 198 + "", "", "", "", "", "", "", "", 199 + /* Port D */ 200 + "", "", "", "", "", "", "", "", 201 + "", "", 202 + "pin24 [gpio16/spi1-ce0]", 203 + "pin23 [gpio15/spi1-clk]", 204 + "pin19 [gpio12/spi1-mosi]", 205 + "pin21 [gpio13/spi1-miso]", 206 + "pin27 [gpio18/spi1-hold]", 207 + "pin29 [gpio20/spi1-wp]", 208 + "", "", "", "", "", "", 209 + "pin7 [gpio3/pwm]"; 194 210 };
+18 -6
arch/riscv/boot/dts/allwinner/sunxi-d1s-t113.dtsi
··· 211 211 clocks = <&ccu CLK_BUS_UART0>; 212 212 resets = <&ccu RST_BUS_UART0>; 213 213 dmas = <&dma 14>, <&dma 14>; 214 - dma-names = "rx", "tx"; 214 + dma-names = "tx", "rx"; 215 215 status = "disabled"; 216 216 }; 217 217 ··· 224 224 clocks = <&ccu CLK_BUS_UART1>; 225 225 resets = <&ccu RST_BUS_UART1>; 226 226 dmas = <&dma 15>, <&dma 15>; 227 - dma-names = "rx", "tx"; 227 + dma-names = "tx", "rx"; 228 228 status = "disabled"; 229 229 }; 230 230 ··· 237 237 clocks = <&ccu CLK_BUS_UART2>; 238 238 resets = <&ccu RST_BUS_UART2>; 239 239 dmas = <&dma 16>, <&dma 16>; 240 - dma-names = "rx", "tx"; 240 + dma-names = "tx", "rx"; 241 241 status = "disabled"; 242 242 }; 243 243 ··· 250 250 clocks = <&ccu CLK_BUS_UART3>; 251 251 resets = <&ccu RST_BUS_UART3>; 252 252 dmas = <&dma 17>, <&dma 17>; 253 - dma-names = "rx", "tx"; 253 + dma-names = "tx", "rx"; 254 254 status = "disabled"; 255 255 }; 256 256 ··· 263 263 clocks = <&ccu CLK_BUS_UART4>; 264 264 resets = <&ccu RST_BUS_UART4>; 265 265 dmas = <&dma 18>, <&dma 18>; 266 - dma-names = "rx", "tx"; 266 + dma-names = "tx", "rx"; 267 267 status = "disabled"; 268 268 }; 269 269 ··· 276 276 clocks = <&ccu CLK_BUS_UART5>; 277 277 resets = <&ccu RST_BUS_UART5>; 278 278 dmas = <&dma 19>, <&dma 19>; 279 - dma-names = "rx", "tx"; 279 + dma-names = "tx", "rx"; 280 280 status = "disabled"; 281 281 }; 282 282 ··· 365 365 reg = <0x3006000 0x1000>; 366 366 #address-cells = <1>; 367 367 #size-cells = <1>; 368 + }; 369 + 370 + crypto: crypto@3040000 { 371 + compatible = "allwinner,sun20i-d1-crypto"; 372 + reg = <0x3040000 0x800>; 373 + interrupts = <SOC_PERIPHERAL_IRQ(52) IRQ_TYPE_LEVEL_HIGH>; 374 + clocks = <&ccu CLK_BUS_CE>, 375 + <&ccu CLK_CE>, 376 + <&ccu CLK_MBUS_CE>, 377 + <&rtc CLK_IOSC>; 378 + clock-names = "bus", "mod", "ram", "trng"; 379 + resets = <&ccu RST_BUS_CE>; 368 380 }; 369 381 370 382 mbus: dram-controller@3102000 {