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spi: sh-msiof: SIFCTR bitfield conversion

Convert MSIOF FIFO Control Register field accesses to use the
FIELD_PREP() bitfield access macro.

This gets rid of explicit shifts and custom field preparation macros.

Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://patch.msgid.link/0bf4c366381a8999c9755285272897300852bc18.1747401908.git.geert+renesas@glider.be
Signed-off-by: Mark Brown <broonie@kernel.org>

authored by

Geert Uytterhoeven and committed by
Mark Brown 8f3903b3 bd8d6658

+23 -25
+23 -25
drivers/spi/spi-sh-msiof.c
··· 135 135 #define SICTR_RXRST BIT(0) /* Receive Reset */ 136 136 137 137 /* SIFCTR */ 138 - #define SIFCTR_TFWM_MASK GENMASK(31, 29) /* Transmit FIFO Watermark */ 139 - #define SIFCTR_TFWM_64 (0UL << 29) /* Transfer Request when 64 empty stages */ 140 - #define SIFCTR_TFWM_32 (1UL << 29) /* Transfer Request when 32 empty stages */ 141 - #define SIFCTR_TFWM_24 (2UL << 29) /* Transfer Request when 24 empty stages */ 142 - #define SIFCTR_TFWM_16 (3UL << 29) /* Transfer Request when 16 empty stages */ 143 - #define SIFCTR_TFWM_12 (4UL << 29) /* Transfer Request when 12 empty stages */ 144 - #define SIFCTR_TFWM_8 (5UL << 29) /* Transfer Request when 8 empty stages */ 145 - #define SIFCTR_TFWM_4 (6UL << 29) /* Transfer Request when 4 empty stages */ 146 - #define SIFCTR_TFWM_1 (7UL << 29) /* Transfer Request when 1 empty stage */ 147 - #define SIFCTR_TFUA_MASK GENMASK(26, 20) /* Transmit FIFO Usable Area */ 148 - #define SIFCTR_TFUA_SHIFT 20 149 - #define SIFCTR_TFUA(i) ((i) << SIFCTR_TFUA_SHIFT) 150 - #define SIFCTR_RFWM_MASK GENMASK(15, 13) /* Receive FIFO Watermark */ 151 - #define SIFCTR_RFWM_1 (0 << 13) /* Transfer Request when 1 valid stages */ 152 - #define SIFCTR_RFWM_4 (1 << 13) /* Transfer Request when 4 valid stages */ 153 - #define SIFCTR_RFWM_8 (2 << 13) /* Transfer Request when 8 valid stages */ 154 - #define SIFCTR_RFWM_16 (3 << 13) /* Transfer Request when 16 valid stages */ 155 - #define SIFCTR_RFWM_32 (4 << 13) /* Transfer Request when 32 valid stages */ 156 - #define SIFCTR_RFWM_64 (5 << 13) /* Transfer Request when 64 valid stages */ 157 - #define SIFCTR_RFWM_128 (6 << 13) /* Transfer Request when 128 valid stages */ 158 - #define SIFCTR_RFWM_256 (7 << 13) /* Transfer Request when 256 valid stages */ 159 - #define SIFCTR_RFUA_MASK GENMASK(12, 4) /* Receive FIFO Usable Area (0x40 = full) */ 160 - #define SIFCTR_RFUA_SHIFT 4 161 - #define SIFCTR_RFUA(i) ((i) << SIFCTR_RFUA_SHIFT) 138 + #define SIFCTR_TFWM GENMASK(31, 29) /* Transmit FIFO Watermark */ 139 + #define SIFCTR_TFWM_64 0U /* Transfer Request when 64 empty stages */ 140 + #define SIFCTR_TFWM_32 1U /* Transfer Request when 32 empty stages */ 141 + #define SIFCTR_TFWM_24 2U /* Transfer Request when 24 empty stages */ 142 + #define SIFCTR_TFWM_16 3U /* Transfer Request when 16 empty stages */ 143 + #define SIFCTR_TFWM_12 4U /* Transfer Request when 12 empty stages */ 144 + #define SIFCTR_TFWM_8 5U /* Transfer Request when 8 empty stages */ 145 + #define SIFCTR_TFWM_4 6U /* Transfer Request when 4 empty stages */ 146 + #define SIFCTR_TFWM_1 7U /* Transfer Request when 1 empty stage */ 147 + #define SIFCTR_TFUA GENMASK(26, 20) /* Transmit FIFO Usable Area */ 148 + #define SIFCTR_RFWM GENMASK(15, 13) /* Receive FIFO Watermark */ 149 + #define SIFCTR_RFWM_1 0U /* Transfer Request when 1 valid stages */ 150 + #define SIFCTR_RFWM_4 1U /* Transfer Request when 4 valid stages */ 151 + #define SIFCTR_RFWM_8 2U /* Transfer Request when 8 valid stages */ 152 + #define SIFCTR_RFWM_16 3U /* Transfer Request when 16 valid stages */ 153 + #define SIFCTR_RFWM_32 4U /* Transfer Request when 32 valid stages */ 154 + #define SIFCTR_RFWM_64 5U /* Transfer Request when 64 valid stages */ 155 + #define SIFCTR_RFWM_128 6U /* Transfer Request when 128 valid stages */ 156 + #define SIFCTR_RFWM_256 7U /* Transfer Request when 256 valid stages */ 157 + #define SIFCTR_RFUA GENMASK(12, 4) /* Receive FIFO Usable Area (0x40 = full) */ 162 158 163 159 /* SISTR */ 164 160 #define SISTR_TFEMP BIT(29) /* Transmit FIFO Empty */ ··· 807 811 } 808 812 809 813 /* 1 stage FIFO watermarks for DMA */ 810 - sh_msiof_write(p, SIFCTR, SIFCTR_TFWM_1 | SIFCTR_RFWM_1); 814 + sh_msiof_write(p, SIFCTR, 815 + FIELD_PREP(SIFCTR_TFWM, SIFCTR_TFWM_1) | 816 + FIELD_PREP(SIFCTR_RFWM, SIFCTR_RFWM_1)); 811 817 812 818 /* setup msiof transfer mode registers (32-bit words) */ 813 819 sh_msiof_spi_set_mode_regs(p, tx, rx, 32, len / 4);