Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
Merge tag 'phy-for-6.3' of git://git.kernel.org/pub/scm/linux/kernel/git/phy/linux-phy
Pull phy updates from Vinod Koul:
"This features a bunch of new device support, a couple of new drivers,
yaml conversion and updates of a few drivers.
Core support:
- New devm_of_phy_optional_get() API with users and conversion
New hardware support:
- Mediatek MT7986 phy support
- Qualcomm SM8550 UFS, PCIe, combo phy support, SM6115 / SM4250 USB3
phy support, SM6350 combo phy support, SM6125 UFS PHY support amd
SM8350 & SM8450 combo phy support
- Qualcomm SNPS eUSB2 eUSB2 repeater drivers
- Allwinner F1C100s USB PHY support
- Tegra xusb support for Tegra234
Updates:
- Yaml conversion for Qualcomm pcie2 phy and usb-hsic-phy
- G4 mode support in Qualcomm UFS phy and support for various SoCs
- Yaml conversion for Meson usb2 phy
- TI Type C support for usb phy for j721
- Yaml conversion for Tegra xusb binding"
* tag 'phy-for-6.3' of git://git.kernel.org/pub/scm/linux/kernel/git/phy/linux-phy: (106 commits)
phy: qcom: phy-qcom-snps-eusb2: Add support for eUSB2 repeater
phy: qcom: Add QCOM SNPS eUSB2 repeater driver
dt-bindings: phy: qcom,snps-eusb2-phy: Add phys property for the repeater
dt-bindings: phy: Add qcom,snps-eusb2-repeater schema file
dt-bindings: phy: amlogic,g12a-usb3-pcie-phy: add missing optional phy-supply property
phy: rockchip-typec: Fix unsigned comparison with less than zero
phy: rockchip-typec: fix tcphy_get_mode error case
phy: qcom: snps-eusb2: Add missing headers
phy: qcom-qmp-combo: Add support for SM8550
phy: qcom-qmp: Add v6 DP register offsets
phy: qcom-qmp: pcs-usb: Add v6 register offsets
dt-bindings: phy: qcom,sc8280xp-qmp-usb43dp: Document SM8550 compatible
phy: qcom: Add QCOM SNPS eUSB2 driver
dt-bindings: phy: Add qcom,snps-eusb2-phy schema file
phy: qcom-qmp-pcie: Add support for SM8550 g3x2 and g4x2 PCIEs
phy: qcom-qmp: qserdes-lane-shared: Add v6 register offsets
phy: qcom-qmp: qserdes-txrx: Add v6.20 register offsets
phy: qcom-qmp: pcs-pcie: Add v6.20 register offsets
phy: qcom-qmp: pcs-pcie: Add v6 register offsets
phy: qcom-qmp: pcs: Add v6.20 register offsets
...
+6570
-1491
+83
Documentation/devicetree/bindings/phy/allwinner,suniv-f1c100s-usb-phy.yaml
+83
Documentation/devicetree/bindings/phy/allwinner,suniv-f1c100s-usb-phy.yaml
···
1
+
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2
+
%YAML 1.2
3
+
---
4
+
$id: http://devicetree.org/schemas/phy/allwinner,suniv-f1c100s-usb-phy.yaml#
5
+
$schema: http://devicetree.org/meta-schemas/core.yaml#
6
+
7
+
title: Allwinner F1C100s USB PHY
8
+
9
+
maintainers:
10
+
- Chen-Yu Tsai <wens@csie.org>
11
+
- Maxime Ripard <mripard@kernel.org>
12
+
13
+
properties:
14
+
"#phy-cells":
15
+
const: 1
16
+
17
+
compatible:
18
+
const: allwinner,suniv-f1c100s-usb-phy
19
+
20
+
reg:
21
+
maxItems: 1
22
+
description: PHY Control registers
23
+
24
+
reg-names:
25
+
const: phy_ctrl
26
+
27
+
clocks:
28
+
maxItems: 1
29
+
description: USB OTG PHY bus clock
30
+
31
+
clock-names:
32
+
const: usb0_phy
33
+
34
+
resets:
35
+
maxItems: 1
36
+
description: USB OTG reset
37
+
38
+
reset-names:
39
+
const: usb0_reset
40
+
41
+
usb0_id_det-gpios:
42
+
maxItems: 1
43
+
description: GPIO to the USB OTG ID pin
44
+
45
+
usb0_vbus_det-gpios:
46
+
maxItems: 1
47
+
description: GPIO to the USB OTG VBUS detect pin
48
+
49
+
usb0_vbus_power-supply:
50
+
description: Power supply to detect the USB OTG VBUS
51
+
52
+
usb0_vbus-supply:
53
+
description: Regulator controlling USB OTG VBUS
54
+
55
+
required:
56
+
- "#phy-cells"
57
+
- compatible
58
+
- clocks
59
+
- clock-names
60
+
- reg
61
+
- reg-names
62
+
- resets
63
+
- reset-names
64
+
65
+
additionalProperties: false
66
+
67
+
examples:
68
+
- |
69
+
#include <dt-bindings/gpio/gpio.h>
70
+
#include <dt-bindings/clock/suniv-ccu-f1c100s.h>
71
+
#include <dt-bindings/reset/suniv-ccu-f1c100s.h>
72
+
73
+
phy@1c13400 {
74
+
compatible = "allwinner,suniv-f1c100s-usb-phy";
75
+
reg = <0x01c13400 0x10>;
76
+
reg-names = "phy_ctrl";
77
+
clocks = <&ccu CLK_USB_PHY0>;
78
+
clock-names = "usb0_phy";
79
+
resets = <&ccu RST_USB_PHY0>;
80
+
reset-names = "usb0_reset";
81
+
#phy-cells = <1>;
82
+
usb0_id_det-gpios = <&pio 4 2 GPIO_ACTIVE_HIGH>;
83
+
};
+5
Documentation/devicetree/bindings/phy/amlogic,g12a-usb3-pcie-phy.yaml
+5
Documentation/devicetree/bindings/phy/amlogic,g12a-usb3-pcie-phy.yaml
+56
Documentation/devicetree/bindings/phy/amlogic,meson-gxl-usb2-phy.yaml
+56
Documentation/devicetree/bindings/phy/amlogic,meson-gxl-usb2-phy.yaml
···
1
+
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2
+
%YAML 1.2
3
+
---
4
+
$id: http://devicetree.org/schemas/phy/amlogic,meson-gxl-usb2-phy.yaml#
5
+
$schema: http://devicetree.org/meta-schemas/core.yaml#
6
+
7
+
title: Amlogic Meson GXL USB2 PHY
8
+
9
+
maintainers:
10
+
- Neil Armstrong <neil.armstrong@linaro.org>
11
+
12
+
properties:
13
+
compatible:
14
+
const: amlogic,meson-gxl-usb2-phy
15
+
16
+
reg:
17
+
maxItems: 1
18
+
19
+
clocks:
20
+
maxItems: 1
21
+
22
+
clock-names:
23
+
items:
24
+
- const: phy
25
+
26
+
resets:
27
+
maxItems: 1
28
+
29
+
reset-names:
30
+
items:
31
+
- const: phy
32
+
33
+
"#phy-cells":
34
+
const: 0
35
+
36
+
phy-supply: true
37
+
38
+
required:
39
+
- compatible
40
+
- reg
41
+
- "#phy-cells"
42
+
43
+
additionalProperties: false
44
+
45
+
examples:
46
+
- |
47
+
phy@78000 {
48
+
compatible = "amlogic,meson-gxl-usb2-phy";
49
+
reg = <0x78000 0x20>;
50
+
clocks = <&xtal>;
51
+
clock-names = "phy";
52
+
resets = <&phy_reset>;
53
+
reset-names = "phy";
54
+
#phy-cells = <0>;
55
+
phy-supply = <&usb2_supply>;
56
+
};
+1
Documentation/devicetree/bindings/phy/mediatek,tphy.yaml
+1
Documentation/devicetree/bindings/phy/mediatek,tphy.yaml
-21
Documentation/devicetree/bindings/phy/meson-gxl-usb2-phy.txt
-21
Documentation/devicetree/bindings/phy/meson-gxl-usb2-phy.txt
···
1
-
* Amlogic Meson GXL and GXM USB2 PHY binding
2
-
3
-
Required properties:
4
-
- compatible: Should be "amlogic,meson-gxl-usb2-phy"
5
-
- reg: The base address and length of the registers
6
-
- #phys-cells: must be 0 (see phy-bindings.txt in this directory)
7
-
8
-
Optional properties:
9
-
- clocks: a phandle to the clock of this PHY
10
-
- clock-names: must be "phy"
11
-
- resets: a phandle to the reset line of this PHY
12
-
- reset-names: must be "phy"
13
-
- phy-supply: see phy-bindings.txt in this directory
14
-
15
-
16
-
Example:
17
-
usb2_phy0: phy@78000 {
18
-
compatible = "amlogic,meson-gxl-usb2-phy";
19
-
#phy-cells = <0>;
20
-
reg = <0x0 0x78000 0x0 0x20>;
21
-
};
-779
Documentation/devicetree/bindings/phy/nvidia,tegra124-xusb-padctl.txt
-779
Documentation/devicetree/bindings/phy/nvidia,tegra124-xusb-padctl.txt
···
1
-
Device tree binding for NVIDIA Tegra XUSB pad controller
2
-
========================================================
3
-
4
-
The Tegra XUSB pad controller manages a set of I/O lanes (with differential
5
-
signals) which connect directly to pins/pads on the SoC package. Each lane
6
-
is controlled by a HW block referred to as a "pad" in the Tegra hardware
7
-
documentation. Each such "pad" may control either one or multiple lanes,
8
-
and thus contains any logic common to all its lanes. Each lane can be
9
-
separately configured and powered up.
10
-
11
-
Some of the lanes are high-speed lanes, which can be used for PCIe, SATA or
12
-
super-speed USB. Other lanes are for various types of low-speed, full-speed
13
-
or high-speed USB (such as UTMI, ULPI and HSIC). The XUSB pad controller
14
-
contains a software-configurable mux that sits between the I/O controller
15
-
ports (e.g. PCIe) and the lanes.
16
-
17
-
In addition to per-lane configuration, USB 3.0 ports may require additional
18
-
settings on a per-board basis.
19
-
20
-
Pads will be represented as children of the top-level XUSB pad controller
21
-
device tree node. Each lane exposed by the pad will be represented by its
22
-
own subnode and can be referenced by users of the lane using the standard
23
-
PHY bindings, as described by the phy-bindings.txt file in this directory.
24
-
25
-
The Tegra hardware documentation refers to the connection between the XUSB
26
-
pad controller and the XUSB controller as "ports". This is confusing since
27
-
"port" is typically used to denote the physical USB receptacle. The device
28
-
tree binding in this document uses the term "port" to refer to the logical
29
-
abstraction of the signals that are routed to a USB receptacle (i.e. a PHY
30
-
for the USB signal, the VBUS power supply, the USB 2.0 companion port for
31
-
USB 3.0 receptacles, ...).
32
-
33
-
Required properties:
34
-
--------------------
35
-
- compatible: Must be:
36
-
- Tegra124: "nvidia,tegra124-xusb-padctl"
37
-
- Tegra132: "nvidia,tegra132-xusb-padctl", "nvidia,tegra124-xusb-padctl"
38
-
- Tegra210: "nvidia,tegra210-xusb-padctl"
39
-
- Tegra186: "nvidia,tegra186-xusb-padctl"
40
-
- Tegra194: "nvidia,tegra194-xusb-padctl"
41
-
- reg: Physical base address and length of the controller's registers.
42
-
- resets: Must contain an entry for each entry in reset-names.
43
-
- reset-names: Must include the following entries:
44
-
- "padctl"
45
-
46
-
For Tegra124:
47
-
- avdd-pll-utmip-supply: UTMI PLL power supply. Must supply 1.8 V.
48
-
- avdd-pll-erefe-supply: PLLE reference PLL power supply. Must supply 1.05 V.
49
-
- avdd-pex-pll-supply: PCIe/USB3 PLL power supply. Must supply 1.05 V.
50
-
- hvdd-pex-pll-e-supply: High-voltage PLLE power supply. Must supply 3.3 V.
51
-
52
-
For Tegra210:
53
-
- avdd-pll-utmip-supply: UTMI PLL power supply. Must supply 1.8 V.
54
-
- avdd-pll-uerefe-supply: PLLE reference PLL power supply. Must supply 1.05 V.
55
-
- dvdd-pex-pll-supply: PCIe/USB3 PLL power supply. Must supply 1.05 V.
56
-
- hvdd-pex-pll-e-supply: High-voltage PLLE power supply. Must supply 1.8 V.
57
-
- nvidia,pmc: phandle and specifier referring to the Tegra210 PMC node.
58
-
59
-
For Tegra186:
60
-
- avdd-pll-erefeut-supply: UPHY brick and reference clock as well as UTMI PHY
61
-
power supply. Must supply 1.8 V.
62
-
- avdd-usb-supply: USB I/Os, VBUS, ID, REXT, D+/D- power supply. Must supply
63
-
3.3 V.
64
-
- vclamp-usb-supply: Bias rail for USB pad. Must supply 1.8 V.
65
-
- vddio-hsic-supply: HSIC PHY power supply. Must supply 1.2 V.
66
-
67
-
For Tegra194:
68
-
- avdd-usb-supply: USB I/Os, VBUS, ID, REXT, D+/D- power supply. Must supply
69
-
3.3 V.
70
-
- vclamp-usb-supply: Bias rail for USB pad. Must supply 1.8 V.
71
-
72
-
Pad nodes:
73
-
==========
74
-
75
-
A required child node named "pads" contains a list of subnodes, one for each
76
-
of the pads exposed by the XUSB pad controller. Each pad may need additional
77
-
resources that can be referenced in its pad node.
78
-
79
-
The "status" property is used to enable or disable the use of a pad. If set
80
-
to "disabled", the pad will not be used on the given board. In order to use
81
-
the pad and any of its lanes, this property must be set to "okay".
82
-
83
-
For Tegra124 and Tegra132, the following pads exist: usb2, ulpi, hsic, pcie
84
-
and sata. No extra resources are required for operation of these pads.
85
-
86
-
For Tegra210, the following pads exist: usb2, hsic, pcie and sata. Below is
87
-
a description of the properties of each pad.
88
-
89
-
UTMI pad:
90
-
---------
91
-
92
-
Required properties:
93
-
- clocks: Must contain an entry for each entry in clock-names.
94
-
- clock-names: Must contain the following entries:
95
-
- "trk": phandle and specifier referring to the USB2 tracking clock
96
-
97
-
HSIC pad:
98
-
---------
99
-
100
-
Required properties:
101
-
- clocks: Must contain an entry for each entry in clock-names.
102
-
- clock-names: Must contain the following entries:
103
-
- "trk": phandle and specifier referring to the HSIC tracking clock
104
-
105
-
PCIe pad:
106
-
---------
107
-
108
-
Required properties:
109
-
- clocks: Must contain an entry for each entry in clock-names.
110
-
- clock-names: Must contain the following entries:
111
-
- "pll": phandle and specifier referring to the PLLE
112
-
- resets: Must contain an entry for each entry in reset-names.
113
-
- reset-names: Must contain the following entries:
114
-
- "phy": reset for the PCIe UPHY block
115
-
116
-
SATA pad:
117
-
---------
118
-
119
-
Required properties:
120
-
- resets: Must contain an entry for each entry in reset-names.
121
-
- reset-names: Must contain the following entries:
122
-
- "phy": reset for the SATA UPHY block
123
-
124
-
125
-
PHY nodes:
126
-
==========
127
-
128
-
Each pad node has a child named "lanes" that contains one or more children of
129
-
its own, each representing one of the lanes controlled by the pad.
130
-
131
-
Required properties:
132
-
--------------------
133
-
- status: Defines the operation status of the PHY. Valid values are:
134
-
- "disabled": the PHY is disabled
135
-
- "okay": the PHY is enabled
136
-
- #phy-cells: Should be 0. Since each lane represents a single PHY, there is
137
-
no need for an additional specifier.
138
-
- nvidia,function: The output function of the PHY. See below for a list of
139
-
valid functions per SoC generation.
140
-
141
-
For Tegra124 and Tegra132, the list of valid PHY nodes is given below:
142
-
- usb2: usb2-0, usb2-1, usb2-2
143
-
- functions: "snps", "xusb", "uart"
144
-
- ulpi: ulpi-0
145
-
- functions: "snps", "xusb"
146
-
- hsic: hsic-0, hsic-1
147
-
- functions: "snps", "xusb"
148
-
- pcie: pcie-0, pcie-1, pcie-2, pcie-3, pcie-4
149
-
- functions: "pcie", "usb3-ss"
150
-
- sata: sata-0
151
-
- functions: "usb3-ss", "sata"
152
-
153
-
For Tegra210, the list of valid PHY nodes is given below:
154
-
- usb2: usb2-0, usb2-1, usb2-2, usb2-3
155
-
- functions: "snps", "xusb", "uart"
156
-
- hsic: hsic-0, hsic-1
157
-
- functions: "snps", "xusb"
158
-
- pcie: pcie-0, pcie-1, pcie-2, pcie-3, pcie-4, pcie-5, pcie-6
159
-
- functions: "pcie-x1", "usb3-ss", "pcie-x4"
160
-
- sata: sata-0
161
-
- functions: "usb3-ss", "sata"
162
-
163
-
For Tegra194, the list of valid PHY nodes is given below:
164
-
- usb2: usb2-0, usb2-1, usb2-2, usb2-3
165
-
- functions: "xusb"
166
-
- usb3: usb3-0, usb3-1, usb3-2, usb3-3
167
-
- functions: "xusb"
168
-
169
-
Port nodes:
170
-
===========
171
-
172
-
A required child node named "ports" contains a list of all the ports exposed
173
-
by the XUSB pad controller. Per-port configuration is only required for USB.
174
-
175
-
USB2 ports:
176
-
-----------
177
-
178
-
Required properties:
179
-
- status: Defines the operation status of the port. Valid values are:
180
-
- "disabled": the port is disabled
181
-
- "okay": the port is enabled
182
-
- mode: A string that determines the mode in which to run the port. Valid
183
-
values are:
184
-
- "host": for USB host mode
185
-
- "device": for USB device mode
186
-
- "otg": for USB OTG mode
187
-
188
-
Required properties for OTG/Peripheral capable USB2 ports:
189
-
- usb-role-switch: Boolean property to indicate that the port support OTG or
190
-
peripheral mode. If present, the port supports switching between USB host
191
-
and peripheral roles. Connector should be added as subnode.
192
-
See usb/usb-conn-gpio.txt.
193
-
194
-
Optional properties:
195
-
- nvidia,internal: A boolean property whose presence determines that a port
196
-
is internal. In the absence of this property the port is considered to be
197
-
external.
198
-
- vbus-supply: phandle to a regulator supplying the VBUS voltage.
199
-
200
-
ULPI ports:
201
-
-----------
202
-
203
-
Optional properties:
204
-
- status: Defines the operation status of the port. Valid values are:
205
-
- "disabled": the port is disabled
206
-
- "okay": the port is enabled
207
-
- nvidia,internal: A boolean property whose presence determines that a port
208
-
is internal. In the absence of this property the port is considered to be
209
-
external.
210
-
- vbus-supply: phandle to a regulator supplying the VBUS voltage.
211
-
212
-
HSIC ports:
213
-
-----------
214
-
215
-
Required properties:
216
-
- status: Defines the operation status of the port. Valid values are:
217
-
- "disabled": the port is disabled
218
-
- "okay": the port is enabled
219
-
220
-
Optional properties:
221
-
- vbus-supply: phandle to a regulator supplying the VBUS voltage.
222
-
223
-
Super-speed USB ports:
224
-
----------------------
225
-
226
-
Required properties:
227
-
- status: Defines the operation status of the port. Valid values are:
228
-
- "disabled": the port is disabled
229
-
- "okay": the port is enabled
230
-
- nvidia,usb2-companion: A single cell that specifies the physical port number
231
-
to map this super-speed USB port to. The range of valid port numbers varies
232
-
with the SoC generation:
233
-
- 0-2: for Tegra124 and Tegra132
234
-
- 0-3: for Tegra210
235
-
236
-
Optional properties:
237
-
- nvidia,internal: A boolean property whose presence determines that a port
238
-
is internal. In the absence of this property the port is considered to be
239
-
external.
240
-
241
-
- maximum-speed: Only for Tegra194. A string property that specifies maximum
242
-
supported speed of a usb3 port. Valid values are:
243
-
- "super-speed-plus": default, the usb3 port supports USB 3.1 Gen 2 speed.
244
-
- "super-speed": the usb3 port supports USB 3.1 Gen 1 speed only.
245
-
246
-
For Tegra124 and Tegra132, the XUSB pad controller exposes the following
247
-
ports:
248
-
- 3x USB2: usb2-0, usb2-1, usb2-2
249
-
- 1x ULPI: ulpi-0
250
-
- 2x HSIC: hsic-0, hsic-1
251
-
- 2x super-speed USB: usb3-0, usb3-1
252
-
253
-
For Tegra210, the XUSB pad controller exposes the following ports:
254
-
- 4x USB2: usb2-0, usb2-1, usb2-2, usb2-3
255
-
- 2x HSIC: hsic-0, hsic-1
256
-
- 4x super-speed USB: usb3-0, usb3-1, usb3-2, usb3-3
257
-
258
-
For Tegra194, the XUSB pad controller exposes the following ports:
259
-
- 4x USB2: usb2-0, usb2-1, usb2-2, usb2-3
260
-
- 4x super-speed USB: usb3-0, usb3-1, usb3-2, usb3-3
261
-
262
-
Examples:
263
-
=========
264
-
265
-
Tegra124 and Tegra132:
266
-
----------------------
267
-
268
-
SoC include:
269
-
270
-
padctl@7009f000 {
271
-
/* for Tegra124 */
272
-
compatible = "nvidia,tegra124-xusb-padctl";
273
-
/* for Tegra132 */
274
-
compatible = "nvidia,tegra132-xusb-padctl",
275
-
"nvidia,tegra124-xusb-padctl";
276
-
reg = <0x0 0x7009f000 0x0 0x1000>;
277
-
resets = <&tegra_car 142>;
278
-
reset-names = "padctl";
279
-
280
-
pads {
281
-
usb2 {
282
-
status = "disabled";
283
-
284
-
lanes {
285
-
usb2-0 {
286
-
status = "disabled";
287
-
#phy-cells = <0>;
288
-
};
289
-
290
-
usb2-1 {
291
-
status = "disabled";
292
-
#phy-cells = <0>;
293
-
};
294
-
295
-
usb2-2 {
296
-
status = "disabled";
297
-
#phy-cells = <0>;
298
-
};
299
-
};
300
-
};
301
-
302
-
ulpi {
303
-
status = "disabled";
304
-
305
-
lanes {
306
-
ulpi-0 {
307
-
status = "disabled";
308
-
#phy-cells = <0>;
309
-
};
310
-
};
311
-
};
312
-
313
-
hsic {
314
-
status = "disabled";
315
-
316
-
lanes {
317
-
hsic-0 {
318
-
status = "disabled";
319
-
#phy-cells = <0>;
320
-
};
321
-
322
-
hsic-1 {
323
-
status = "disabled";
324
-
#phy-cells = <0>;
325
-
};
326
-
};
327
-
};
328
-
329
-
pcie {
330
-
status = "disabled";
331
-
332
-
lanes {
333
-
pcie-0 {
334
-
status = "disabled";
335
-
#phy-cells = <0>;
336
-
};
337
-
338
-
pcie-1 {
339
-
status = "disabled";
340
-
#phy-cells = <0>;
341
-
};
342
-
343
-
pcie-2 {
344
-
status = "disabled";
345
-
#phy-cells = <0>;
346
-
};
347
-
348
-
pcie-3 {
349
-
status = "disabled";
350
-
#phy-cells = <0>;
351
-
};
352
-
353
-
pcie-4 {
354
-
status = "disabled";
355
-
#phy-cells = <0>;
356
-
};
357
-
};
358
-
};
359
-
360
-
sata {
361
-
status = "disabled";
362
-
363
-
lanes {
364
-
sata-0 {
365
-
status = "disabled";
366
-
#phy-cells = <0>;
367
-
};
368
-
};
369
-
};
370
-
};
371
-
372
-
ports {
373
-
usb2-0 {
374
-
status = "disabled";
375
-
};
376
-
377
-
usb2-1 {
378
-
status = "disabled";
379
-
};
380
-
381
-
usb2-2 {
382
-
status = "disabled";
383
-
};
384
-
385
-
ulpi-0 {
386
-
status = "disabled";
387
-
};
388
-
389
-
hsic-0 {
390
-
status = "disabled";
391
-
};
392
-
393
-
hsic-1 {
394
-
status = "disabled";
395
-
};
396
-
397
-
usb3-0 {
398
-
status = "disabled";
399
-
};
400
-
401
-
usb3-1 {
402
-
status = "disabled";
403
-
};
404
-
};
405
-
};
406
-
407
-
Board file:
408
-
409
-
padctl@7009f000 {
410
-
status = "okay";
411
-
412
-
pads {
413
-
usb2 {
414
-
status = "okay";
415
-
416
-
lanes {
417
-
usb2-0 {
418
-
nvidia,function = "xusb";
419
-
status = "okay";
420
-
};
421
-
422
-
usb2-1 {
423
-
nvidia,function = "xusb";
424
-
status = "okay";
425
-
};
426
-
427
-
usb2-2 {
428
-
nvidia,function = "xusb";
429
-
status = "okay";
430
-
};
431
-
};
432
-
};
433
-
434
-
pcie {
435
-
status = "okay";
436
-
437
-
lanes {
438
-
pcie-0 {
439
-
nvidia,function = "usb3-ss";
440
-
status = "okay";
441
-
};
442
-
443
-
pcie-2 {
444
-
nvidia,function = "pcie";
445
-
status = "okay";
446
-
};
447
-
448
-
pcie-4 {
449
-
nvidia,function = "pcie";
450
-
status = "okay";
451
-
};
452
-
};
453
-
};
454
-
455
-
sata {
456
-
status = "okay";
457
-
458
-
lanes {
459
-
sata-0 {
460
-
nvidia,function = "sata";
461
-
status = "okay";
462
-
};
463
-
};
464
-
};
465
-
};
466
-
467
-
ports {
468
-
/* Micro A/B */
469
-
usb2-0 {
470
-
status = "okay";
471
-
mode = "otg";
472
-
};
473
-
474
-
/* Mini PCIe */
475
-
usb2-1 {
476
-
status = "okay";
477
-
mode = "host";
478
-
};
479
-
480
-
/* USB3 */
481
-
usb2-2 {
482
-
status = "okay";
483
-
mode = "host";
484
-
485
-
vbus-supply = <&vdd_usb3_vbus>;
486
-
};
487
-
488
-
usb3-0 {
489
-
nvidia,port = <2>;
490
-
status = "okay";
491
-
};
492
-
};
493
-
};
494
-
495
-
Tegra210:
496
-
---------
497
-
498
-
SoC include:
499
-
500
-
padctl@7009f000 {
501
-
compatible = "nvidia,tegra210-xusb-padctl";
502
-
reg = <0x0 0x7009f000 0x0 0x1000>;
503
-
resets = <&tegra_car 142>;
504
-
reset-names = "padctl";
505
-
506
-
status = "disabled";
507
-
508
-
pads {
509
-
usb2 {
510
-
clocks = <&tegra_car TEGRA210_CLK_USB2_TRK>;
511
-
clock-names = "trk";
512
-
status = "disabled";
513
-
514
-
lanes {
515
-
usb2-0 {
516
-
status = "disabled";
517
-
#phy-cells = <0>;
518
-
};
519
-
520
-
usb2-1 {
521
-
status = "disabled";
522
-
#phy-cells = <0>;
523
-
};
524
-
525
-
usb2-2 {
526
-
status = "disabled";
527
-
#phy-cells = <0>;
528
-
};
529
-
530
-
usb2-3 {
531
-
status = "disabled";
532
-
#phy-cells = <0>;
533
-
};
534
-
};
535
-
};
536
-
537
-
hsic {
538
-
clocks = <&tegra_car TEGRA210_CLK_HSIC_TRK>;
539
-
clock-names = "trk";
540
-
status = "disabled";
541
-
542
-
lanes {
543
-
hsic-0 {
544
-
status = "disabled";
545
-
#phy-cells = <0>;
546
-
};
547
-
548
-
hsic-1 {
549
-
status = "disabled";
550
-
#phy-cells = <0>;
551
-
};
552
-
};
553
-
};
554
-
555
-
pcie {
556
-
clocks = <&tegra_car TEGRA210_CLK_PLL_E>;
557
-
clock-names = "pll";
558
-
resets = <&tegra_car 205>;
559
-
reset-names = "phy";
560
-
status = "disabled";
561
-
562
-
lanes {
563
-
pcie-0 {
564
-
status = "disabled";
565
-
#phy-cells = <0>;
566
-
};
567
-
568
-
pcie-1 {
569
-
status = "disabled";
570
-
#phy-cells = <0>;
571
-
};
572
-
573
-
pcie-2 {
574
-
status = "disabled";
575
-
#phy-cells = <0>;
576
-
};
577
-
578
-
pcie-3 {
579
-
status = "disabled";
580
-
#phy-cells = <0>;
581
-
};
582
-
583
-
pcie-4 {
584
-
status = "disabled";
585
-
#phy-cells = <0>;
586
-
};
587
-
588
-
pcie-5 {
589
-
status = "disabled";
590
-
#phy-cells = <0>;
591
-
};
592
-
593
-
pcie-6 {
594
-
status = "disabled";
595
-
#phy-cells = <0>;
596
-
};
597
-
};
598
-
};
599
-
600
-
sata {
601
-
clocks = <&tegra_car TEGRA210_CLK_PLL_E>;
602
-
clock-names = "pll";
603
-
resets = <&tegra_car 204>;
604
-
reset-names = "phy";
605
-
status = "disabled";
606
-
607
-
lanes {
608
-
sata-0 {
609
-
status = "disabled";
610
-
#phy-cells = <0>;
611
-
};
612
-
};
613
-
};
614
-
};
615
-
616
-
ports {
617
-
usb2-0 {
618
-
status = "disabled";
619
-
};
620
-
621
-
usb2-1 {
622
-
status = "disabled";
623
-
};
624
-
625
-
usb2-2 {
626
-
status = "disabled";
627
-
};
628
-
629
-
usb2-3 {
630
-
status = "disabled";
631
-
};
632
-
633
-
hsic-0 {
634
-
status = "disabled";
635
-
};
636
-
637
-
hsic-1 {
638
-
status = "disabled";
639
-
};
640
-
641
-
usb3-0 {
642
-
status = "disabled";
643
-
};
644
-
645
-
usb3-1 {
646
-
status = "disabled";
647
-
};
648
-
649
-
usb3-2 {
650
-
status = "disabled";
651
-
};
652
-
653
-
usb3-3 {
654
-
status = "disabled";
655
-
};
656
-
};
657
-
};
658
-
659
-
Board file:
660
-
661
-
padctl@7009f000 {
662
-
status = "okay";
663
-
664
-
pads {
665
-
usb2 {
666
-
status = "okay";
667
-
668
-
lanes {
669
-
usb2-0 {
670
-
nvidia,function = "xusb";
671
-
status = "okay";
672
-
};
673
-
674
-
usb2-1 {
675
-
nvidia,function = "xusb";
676
-
status = "okay";
677
-
};
678
-
679
-
usb2-2 {
680
-
nvidia,function = "xusb";
681
-
status = "okay";
682
-
};
683
-
684
-
usb2-3 {
685
-
nvidia,function = "xusb";
686
-
status = "okay";
687
-
};
688
-
};
689
-
};
690
-
691
-
pcie {
692
-
status = "okay";
693
-
694
-
lanes {
695
-
pcie-0 {
696
-
nvidia,function = "pcie-x1";
697
-
status = "okay";
698
-
};
699
-
700
-
pcie-1 {
701
-
nvidia,function = "pcie-x4";
702
-
status = "okay";
703
-
};
704
-
705
-
pcie-2 {
706
-
nvidia,function = "pcie-x4";
707
-
status = "okay";
708
-
};
709
-
710
-
pcie-3 {
711
-
nvidia,function = "pcie-x4";
712
-
status = "okay";
713
-
};
714
-
715
-
pcie-4 {
716
-
nvidia,function = "pcie-x4";
717
-
status = "okay";
718
-
};
719
-
720
-
pcie-5 {
721
-
nvidia,function = "usb3-ss";
722
-
status = "okay";
723
-
};
724
-
725
-
pcie-6 {
726
-
nvidia,function = "usb3-ss";
727
-
status = "okay";
728
-
};
729
-
};
730
-
};
731
-
732
-
sata {
733
-
status = "okay";
734
-
735
-
lanes {
736
-
sata-0 {
737
-
nvidia,function = "sata";
738
-
status = "okay";
739
-
};
740
-
};
741
-
};
742
-
};
743
-
744
-
ports {
745
-
usb2-0 {
746
-
status = "okay";
747
-
mode = "otg";
748
-
};
749
-
750
-
usb2-1 {
751
-
status = "okay";
752
-
vbus-supply = <&vdd_5v0_rtl>;
753
-
mode = "host";
754
-
};
755
-
756
-
usb2-2 {
757
-
status = "okay";
758
-
vbus-supply = <&vdd_usb_vbus>;
759
-
mode = "host";
760
-
};
761
-
762
-
usb2-3 {
763
-
status = "okay";
764
-
mode = "host";
765
-
};
766
-
767
-
usb3-0 {
768
-
status = "okay";
769
-
nvidia,lanes = "pcie-6";
770
-
nvidia,port = <1>;
771
-
};
772
-
773
-
usb3-1 {
774
-
status = "okay";
775
-
nvidia,lanes = "pcie-5";
776
-
nvidia,port = <2>;
777
-
};
778
-
};
779
-
};
+654
Documentation/devicetree/bindings/phy/nvidia,tegra124-xusb-padctl.yaml
+654
Documentation/devicetree/bindings/phy/nvidia,tegra124-xusb-padctl.yaml
···
1
+
# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
2
+
%YAML 1.2
3
+
---
4
+
$id: http://devicetree.org/schemas/phy/nvidia,tegra124-xusb-padctl.yaml#
5
+
$schema: http://devicetree.org/meta-schemas/core.yaml#
6
+
7
+
title: NVIDIA Tegra124 XUSB pad controller
8
+
9
+
maintainers:
10
+
- Thierry Reding <thierry.reding@gmail.com>
11
+
- Jon Hunter <jonathanh@nvidia.com>
12
+
13
+
description: |
14
+
The Tegra XUSB pad controller manages a set of I/O lanes (with differential
15
+
signals) which connect directly to pins/pads on the SoC package. Each lane
16
+
is controlled by a HW block referred to as a "pad" in the Tegra hardware
17
+
documentation. Each such "pad" may control either one or multiple lanes,
18
+
and thus contains any logic common to all its lanes. Each lane can be
19
+
separately configured and powered up.
20
+
21
+
Some of the lanes are high-speed lanes, which can be used for PCIe, SATA or
22
+
super-speed USB. Other lanes are for various types of low-speed, full-speed
23
+
or high-speed USB (such as UTMI, ULPI and HSIC). The XUSB pad controller
24
+
contains a software-configurable mux that sits between the I/O controller
25
+
ports (e.g. PCIe) and the lanes.
26
+
27
+
In addition to per-lane configuration, USB 3.0 ports may require additional
28
+
settings on a per-board basis.
29
+
30
+
Pads will be represented as children of the top-level XUSB pad controller
31
+
device tree node. Each lane exposed by the pad will be represented by its
32
+
own subnode and can be referenced by users of the lane using the standard
33
+
PHY bindings, as described by the phy-bindings.txt file in this directory.
34
+
35
+
The Tegra hardware documentation refers to the connection between the XUSB
36
+
pad controller and the XUSB controller as "ports". This is confusing since
37
+
"port" is typically used to denote the physical USB receptacle. The device
38
+
tree binding in this document uses the term "port" to refer to the logical
39
+
abstraction of the signals that are routed to a USB receptacle (i.e. a PHY
40
+
for the USB signal, the VBUS power supply, the USB 2.0 companion port for
41
+
USB 3.0 receptacles, ...).
42
+
43
+
properties:
44
+
compatible:
45
+
oneOf:
46
+
- enum:
47
+
- nvidia,tegra124-xusb-padctl
48
+
49
+
- items:
50
+
- const: nvidia,tegra132-xusb-padctl
51
+
- const: nvidia,tegra124-xusb-padctl
52
+
53
+
reg:
54
+
maxItems: 1
55
+
56
+
interrupts:
57
+
items:
58
+
- description: XUSB pad controller interrupt
59
+
60
+
resets:
61
+
items:
62
+
- description: pad controller reset
63
+
64
+
reset-names:
65
+
items:
66
+
- const: padctl
67
+
68
+
avdd-pll-utmip-supply:
69
+
description: UTMI PLL power supply. Must supply 1.8 V.
70
+
71
+
avdd-pll-erefe-supply:
72
+
description: PLLE reference PLL power supply. Must supply 1.05 V.
73
+
74
+
avdd-pex-pll-supply:
75
+
description: PCIe/USB3 PLL power supply. Must supply 1.05 V.
76
+
77
+
hvdd-pex-pll-e-supply:
78
+
description: High-voltage PLLE power supply. Must supply 3.3 V.
79
+
80
+
pads:
81
+
description: A required child node named "pads" contains a list of
82
+
subnodes, one for each of the pads exposed by the XUSB pad controller.
83
+
Each pad may need additional resources that can be referenced in its
84
+
pad node.
85
+
86
+
The "status" property is used to enable or disable the use of a pad.
87
+
If set to "disabled", the pad will not be used on the given board. In
88
+
order to use the pad and any of its lanes, this property must be set
89
+
to "okay" or be absent.
90
+
type: object
91
+
additionalProperties: false
92
+
properties:
93
+
usb2:
94
+
type: object
95
+
additionalProperties: false
96
+
properties:
97
+
clocks:
98
+
items:
99
+
- description: USB2 tracking clock
100
+
101
+
clock-names:
102
+
items:
103
+
- const: trk
104
+
105
+
lanes:
106
+
type: object
107
+
additionalProperties: false
108
+
properties:
109
+
usb2-0:
110
+
type: object
111
+
additionalProperties: false
112
+
properties:
113
+
"#phy-cells":
114
+
const: 0
115
+
116
+
nvidia,function:
117
+
description: Function selection for this lane.
118
+
$ref: /schemas/types.yaml#/definitions/string
119
+
enum: [ snps, xusb, uart ]
120
+
121
+
usb2-1:
122
+
type: object
123
+
additionalProperties: false
124
+
properties:
125
+
"#phy-cells":
126
+
const: 0
127
+
128
+
nvidia,function:
129
+
description: Function selection for this lane.
130
+
$ref: /schemas/types.yaml#/definitions/string
131
+
enum: [ snps, xusb, uart ]
132
+
133
+
usb2-2:
134
+
type: object
135
+
additionalProperties: false
136
+
properties:
137
+
"#phy-cells":
138
+
const: 0
139
+
140
+
nvidia,function:
141
+
description: Function selection for this lane.
142
+
$ref: /schemas/types.yaml#/definitions/string
143
+
enum: [ snps, xusb, uart ]
144
+
145
+
ulpi:
146
+
type: object
147
+
additionalProperties: false
148
+
properties:
149
+
lanes:
150
+
type: object
151
+
additionalProperties: false
152
+
properties:
153
+
ulpi-0:
154
+
type: object
155
+
additionalProperties: false
156
+
properties:
157
+
"#phy-cells":
158
+
const: 0
159
+
160
+
nvidia,function:
161
+
description: Function selection for this lane.
162
+
$ref: /schemas/types.yaml#/definitions/string
163
+
enum: [ snps, xusb ]
164
+
165
+
hsic:
166
+
type: object
167
+
additionalProperties: false
168
+
properties:
169
+
clocks:
170
+
items:
171
+
- description: HSIC tracking clock
172
+
173
+
clock-names:
174
+
items:
175
+
- const: trk
176
+
177
+
lanes:
178
+
type: object
179
+
additionalProperties: false
180
+
properties:
181
+
hsic-0:
182
+
type: object
183
+
additionalProperties: false
184
+
properties:
185
+
"#phy-cells":
186
+
const: 0
187
+
188
+
nvidia,function:
189
+
description: Function selection for this lane.
190
+
$ref: /schemas/types.yaml#/definitions/string
191
+
enum: [ snps, xusb ]
192
+
193
+
hsic-1:
194
+
type: object
195
+
additionalProperties: false
196
+
properties:
197
+
"#phy-cells":
198
+
const: 0
199
+
200
+
nvidia,function:
201
+
description: Function selection for this lane.
202
+
$ref: /schemas/types.yaml#/definitions/string
203
+
enum: [ snps, xusb ]
204
+
205
+
pcie:
206
+
type: object
207
+
additionalProperties: false
208
+
properties:
209
+
clocks:
210
+
items:
211
+
- description: PLLE clock
212
+
213
+
clock-names:
214
+
items:
215
+
- const: pll
216
+
217
+
resets:
218
+
items:
219
+
- description: reset for the PCIe UPHY block
220
+
221
+
reset-names:
222
+
items:
223
+
- const: phy
224
+
225
+
lanes:
226
+
type: object
227
+
additionalProperties: false
228
+
properties:
229
+
pcie-0:
230
+
type: object
231
+
additionalProperties: false
232
+
properties:
233
+
"#phy-cells":
234
+
const: 0
235
+
236
+
nvidia,function:
237
+
description: Function selection for this lane.
238
+
$ref: /schemas/types.yaml#/definitions/string
239
+
enum: [ pcie, usb3-ss ]
240
+
241
+
pcie-1:
242
+
type: object
243
+
additionalProperties: false
244
+
properties:
245
+
"#phy-cells":
246
+
const: 0
247
+
248
+
nvidia,function:
249
+
description: Function selection for this lane.
250
+
$ref: /schemas/types.yaml#/definitions/string
251
+
enum: [ pcie, usb3-ss ]
252
+
253
+
pcie-2:
254
+
type: object
255
+
additionalProperties: false
256
+
properties:
257
+
"#phy-cells":
258
+
const: 0
259
+
260
+
nvidia,function:
261
+
description: Function selection for this lane.
262
+
$ref: /schemas/types.yaml#/definitions/string
263
+
enum: [ pcie, usb3-ss ]
264
+
265
+
pcie-3:
266
+
type: object
267
+
additionalProperties: false
268
+
properties:
269
+
"#phy-cells":
270
+
const: 0
271
+
272
+
nvidia,function:
273
+
description: Function selection for this lane.
274
+
$ref: /schemas/types.yaml#/definitions/string
275
+
enum: [ pcie, usb3-ss ]
276
+
277
+
pcie-4:
278
+
type: object
279
+
additionalProperties: false
280
+
properties:
281
+
"#phy-cells":
282
+
const: 0
283
+
284
+
nvidia,function:
285
+
description: Function selection for this lane.
286
+
$ref: /schemas/types.yaml#/definitions/string
287
+
enum: [ pcie, usb3-ss ]
288
+
289
+
sata:
290
+
type: object
291
+
additionalProperties: false
292
+
properties:
293
+
resets:
294
+
items:
295
+
- description: reset for the SATA UPHY block
296
+
297
+
reset-names:
298
+
items:
299
+
- const: phy
300
+
301
+
lanes:
302
+
type: object
303
+
additionalProperties: false
304
+
properties:
305
+
sata-0:
306
+
type: object
307
+
additionalProperties: false
308
+
properties:
309
+
"#phy-cells":
310
+
const: 0
311
+
312
+
nvidia,function:
313
+
description: Function selection for this lane.
314
+
$ref: /schemas/types.yaml#/definitions/string
315
+
enum: [ sata, usb3-ss ]
316
+
317
+
ports:
318
+
description: A required child node named "ports" contains a list of
319
+
subnodes, one for each of the ports exposed by the XUSB pad controller.
320
+
Each port may need additional resources that can be referenced in its
321
+
port node.
322
+
323
+
The "status" property is used to enable or disable the use of a port.
324
+
If set to "disabled", the port will not be used on the given board. In
325
+
order to use the port, this property must be set to "okay".
326
+
type: object
327
+
additionalProperties: false
328
+
properties:
329
+
usb2-0:
330
+
type: object
331
+
additionalProperties: false
332
+
properties:
333
+
# no need to further describe this because the connector will
334
+
# match on gpio-usb-b-connector or usb-b-connector and cause
335
+
# that binding to be selected for the subnode
336
+
connector:
337
+
type: object
338
+
339
+
mode:
340
+
description: A string that determines the mode in which to
341
+
run the port.
342
+
$ref: /schemas/types.yaml#/definitions/string
343
+
enum: [ host, peripheral, otg ]
344
+
345
+
nvidia,internal:
346
+
description: A boolean property whose presence determines
347
+
that a port is internal. In the absence of this property
348
+
the port is considered to be external.
349
+
$ref: /schemas/types.yaml#/definitions/flag
350
+
351
+
usb-role-switch:
352
+
description: |
353
+
A boolean property whole presence indicates that the port
354
+
supports OTG or peripheral mode. If present, the port
355
+
supports switching between USB host and peripheral roles.
356
+
A connector must be added as a subnode in that case.
357
+
358
+
See ../connector/usb-connector.yaml.
359
+
360
+
vbus-supply:
361
+
description: A phandle to the regulator supplying the VBUS
362
+
voltage.
363
+
364
+
usb2-1:
365
+
type: object
366
+
additionalProperties: false
367
+
properties:
368
+
# no need to further describe this because the connector will
369
+
# match on gpio-usb-b-connector or usb-b-connector and cause
370
+
# that binding to be selected for the subnode
371
+
connector:
372
+
type: object
373
+
374
+
mode:
375
+
description: A string that determines the mode in which to
376
+
run the port.
377
+
$ref: /schemas/types.yaml#/definitions/string
378
+
enum: [ host, peripheral, otg ]
379
+
380
+
nvidia,internal:
381
+
description: A boolean property whose presence determines
382
+
that a port is internal. In the absence of this property
383
+
the port is considered to be external.
384
+
$ref: /schemas/types.yaml#/definitions/flag
385
+
386
+
usb-role-switch:
387
+
description: |
388
+
A boolean property whole presence indicates that the port
389
+
supports OTG or peripheral mode. If present, the port
390
+
supports switching between USB host and peripheral roles.
391
+
A connector must be added as a subnode in that case.
392
+
393
+
See ../connector/usb-connector.yaml.
394
+
395
+
vbus-supply:
396
+
description: A phandle to the regulator supplying the VBUS
397
+
voltage.
398
+
399
+
usb2-2:
400
+
type: object
401
+
additionalProperties: false
402
+
properties:
403
+
# no need to further describe this because the connector will
404
+
# match on gpio-usb-b-connector or usb-b-connector and cause
405
+
# that binding to be selected for the subnode
406
+
connector:
407
+
type: object
408
+
409
+
mode:
410
+
description: A string that determines the mode in which to
411
+
run the port.
412
+
$ref: /schemas/types.yaml#/definitions/string
413
+
enum: [ host, peripheral, otg ]
414
+
415
+
nvidia,internal:
416
+
description: A boolean property whose presence determines
417
+
that a port is internal. In the absence of this property
418
+
the port is considered to be external.
419
+
$ref: /schemas/types.yaml#/definitions/flag
420
+
421
+
usb-role-switch:
422
+
description: |
423
+
A boolean property whole presence indicates that the port
424
+
supports OTG or peripheral mode. If present, the port
425
+
supports switching between USB host and peripheral roles.
426
+
A connector must be added as a subnode in that case.
427
+
428
+
See ../connector/usb-connector.yaml.
429
+
430
+
vbus-supply:
431
+
description: A phandle to the regulator supplying the VBUS
432
+
voltage.
433
+
434
+
ulpi-0:
435
+
type: object
436
+
additionalProperties: false
437
+
properties:
438
+
nvidia,internal:
439
+
description: A boolean property whose presence determines
440
+
that a port is internal. In the absence of this property
441
+
the port is considered to be external.
442
+
$ref: /schemas/types.yaml#/definitions/flag
443
+
444
+
vbus-supply:
445
+
description: A phandle to the regulator supplying the VBUS
446
+
voltage.
447
+
448
+
hsic-0:
449
+
type: object
450
+
additionalProperties: false
451
+
properties:
452
+
vbus-supply:
453
+
description: A phandle to the regulator supplying the VBUS
454
+
voltage.
455
+
456
+
hsic-1:
457
+
type: object
458
+
additionalProperties: false
459
+
properties:
460
+
vbus-supply:
461
+
description: A phandle to the regulator supplying the VBUS
462
+
voltage.
463
+
464
+
usb3-0:
465
+
type: object
466
+
additionalProperties: false
467
+
properties:
468
+
nvidia,internal:
469
+
description: A boolean property whose presence determines
470
+
that a port is internal. In the absence of this property
471
+
the port is considered to be external.
472
+
$ref: /schemas/types.yaml#/definitions/flag
473
+
474
+
nvidia,usb2-companion:
475
+
description: A single cell that specifies the physical port
476
+
number to map this super-speed USB port to. The range of
477
+
valid port numbers varies with the SoC generation.
478
+
$ref: /schemas/types.yaml#/definitions/uint32
479
+
enum: [ 0, 1, 2 ]
480
+
481
+
vbus-supply:
482
+
description: A phandle to the regulator supplying the VBUS
483
+
voltage.
484
+
485
+
usb3-1:
486
+
type: object
487
+
additionalProperties: false
488
+
properties:
489
+
nvidia,internal:
490
+
description: A boolean property whose presence determines
491
+
that a port is internal. In the absence of this property
492
+
the port is considered to be external.
493
+
$ref: /schemas/types.yaml#/definitions/flag
494
+
495
+
nvidia,usb2-companion:
496
+
description: A single cell that specifies the physical port
497
+
number to map this super-speed USB port to. The range of
498
+
valid port numbers varies with the SoC generation.
499
+
$ref: /schemas/types.yaml#/definitions/uint32
500
+
enum: [ 0, 1, 2 ]
501
+
502
+
vbus-supply:
503
+
description: A phandle to the regulator supplying the VBUS
504
+
voltage.
505
+
506
+
additionalProperties: false
507
+
508
+
required:
509
+
- compatible
510
+
- reg
511
+
- resets
512
+
- reset-names
513
+
- avdd-pll-utmip-supply
514
+
- avdd-pll-erefe-supply
515
+
- avdd-pex-pll-supply
516
+
- hvdd-pex-pll-e-supply
517
+
518
+
examples:
519
+
# Tegra124 and Tegra132
520
+
- |
521
+
#include <dt-bindings/interrupt-controller/arm-gic.h>
522
+
523
+
padctl@7009f000 {
524
+
compatible = "nvidia,tegra124-xusb-padctl";
525
+
reg = <0x7009f000 0x1000>;
526
+
interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
527
+
resets = <&tegra_car 142>;
528
+
reset-names = "padctl";
529
+
530
+
avdd-pll-utmip-supply = <&vddio_1v8>;
531
+
avdd-pll-erefe-supply = <&avdd_1v05_run>;
532
+
avdd-pex-pll-supply = <&vdd_1v05_run>;
533
+
hvdd-pex-pll-e-supply = <&vdd_3v3_lp0>;
534
+
535
+
pads {
536
+
usb2 {
537
+
lanes {
538
+
usb2-0 {
539
+
nvidia,function = "xusb";
540
+
#phy-cells = <0>;
541
+
};
542
+
543
+
usb2-1 {
544
+
nvidia,function = "xusb";
545
+
#phy-cells = <0>;
546
+
};
547
+
548
+
usb2-2 {
549
+
nvidia,function = "xusb";
550
+
#phy-cells = <0>;
551
+
};
552
+
};
553
+
};
554
+
555
+
ulpi {
556
+
lanes {
557
+
ulpi-0 {
558
+
status = "disabled";
559
+
#phy-cells = <0>;
560
+
};
561
+
};
562
+
};
563
+
564
+
hsic {
565
+
lanes {
566
+
hsic-0 {
567
+
status = "disabled";
568
+
#phy-cells = <0>;
569
+
};
570
+
571
+
hsic-1 {
572
+
status = "disabled";
573
+
#phy-cells = <0>;
574
+
};
575
+
};
576
+
};
577
+
578
+
pcie {
579
+
lanes {
580
+
pcie-0 {
581
+
nvidia,function = "usb3-ss";
582
+
#phy-cells = <0>;
583
+
};
584
+
585
+
pcie-1 {
586
+
status = "disabled";
587
+
#phy-cells = <0>;
588
+
};
589
+
590
+
pcie-2 {
591
+
nvidia,function = "pcie";
592
+
#phy-cells = <0>;
593
+
};
594
+
595
+
pcie-3 {
596
+
status = "disabled";
597
+
#phy-cells = <0>;
598
+
};
599
+
600
+
pcie-4 {
601
+
nvidia,function = "pcie";
602
+
#phy-cells = <0>;
603
+
};
604
+
};
605
+
};
606
+
607
+
sata {
608
+
lanes {
609
+
sata-0 {
610
+
nvidia,function = "sata";
611
+
#phy-cells = <0>;
612
+
};
613
+
};
614
+
};
615
+
};
616
+
617
+
ports {
618
+
/* Micro A/B */
619
+
usb2-0 {
620
+
mode = "otg";
621
+
};
622
+
623
+
/* Mini PCIe */
624
+
usb2-1 {
625
+
mode = "host";
626
+
};
627
+
628
+
/* USB3 */
629
+
usb2-2 {
630
+
vbus-supply = <&vdd_usb3_vbus>;
631
+
mode = "host";
632
+
};
633
+
634
+
ulpi-0 {
635
+
status = "disabled";
636
+
};
637
+
638
+
hsic-0 {
639
+
status = "disabled";
640
+
};
641
+
642
+
hsic-1 {
643
+
status = "disabled";
644
+
};
645
+
646
+
usb3-0 {
647
+
nvidia,usb2-companion = <2>;
648
+
};
649
+
650
+
usb3-1 {
651
+
status = "disabled";
652
+
};
653
+
};
654
+
};
+544
Documentation/devicetree/bindings/phy/nvidia,tegra186-xusb-padctl.yaml
+544
Documentation/devicetree/bindings/phy/nvidia,tegra186-xusb-padctl.yaml
···
1
+
# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
2
+
%YAML 1.2
3
+
---
4
+
$id: http://devicetree.org/schemas/phy/nvidia,tegra186-xusb-padctl.yaml#
5
+
$schema: http://devicetree.org/meta-schemas/core.yaml#
6
+
7
+
title: NVIDIA Tegra186 XUSB pad controller
8
+
9
+
maintainers:
10
+
- Thierry Reding <thierry.reding@gmail.com>
11
+
- Jon Hunter <jonathanh@nvidia.com>
12
+
13
+
description: |
14
+
The Tegra XUSB pad controller manages a set of I/O lanes (with differential
15
+
signals) which connect directly to pins/pads on the SoC package. Each lane
16
+
is controlled by a HW block referred to as a "pad" in the Tegra hardware
17
+
documentation. Each such "pad" may control either one or multiple lanes,
18
+
and thus contains any logic common to all its lanes. Each lane can be
19
+
separately configured and powered up.
20
+
21
+
Some of the lanes are high-speed lanes, which can be used for PCIe, SATA or
22
+
super-speed USB. Other lanes are for various types of low-speed, full-speed
23
+
or high-speed USB (such as UTMI, ULPI and HSIC). The XUSB pad controller
24
+
contains a software-configurable mux that sits between the I/O controller
25
+
ports (e.g. PCIe) and the lanes.
26
+
27
+
In addition to per-lane configuration, USB 3.0 ports may require additional
28
+
settings on a per-board basis.
29
+
30
+
Pads will be represented as children of the top-level XUSB pad controller
31
+
device tree node. Each lane exposed by the pad will be represented by its
32
+
own subnode and can be referenced by users of the lane using the standard
33
+
PHY bindings, as described by the phy-bindings.txt file in this directory.
34
+
35
+
The Tegra hardware documentation refers to the connection between the XUSB
36
+
pad controller and the XUSB controller as "ports". This is confusing since
37
+
"port" is typically used to denote the physical USB receptacle. The device
38
+
tree binding in this document uses the term "port" to refer to the logical
39
+
abstraction of the signals that are routed to a USB receptacle (i.e. a PHY
40
+
for the USB signal, the VBUS power supply, the USB 2.0 companion port for
41
+
USB 3.0 receptacles, ...).
42
+
43
+
properties:
44
+
compatible:
45
+
const: nvidia,tegra186-xusb-padctl
46
+
47
+
reg:
48
+
items:
49
+
- description: pad controller registers
50
+
- description: AO registers
51
+
52
+
interrupts:
53
+
items:
54
+
- description: XUSB pad controller interrupt
55
+
56
+
reg-names:
57
+
items:
58
+
- const: padctl
59
+
- const: ao
60
+
61
+
resets:
62
+
items:
63
+
- description: pad controller reset
64
+
65
+
reset-names:
66
+
items:
67
+
- const: padctl
68
+
69
+
avdd-pll-erefeut-supply:
70
+
description: UPHY brick and reference clock as well as UTMI PHY
71
+
power supply. Must supply 1.8 V.
72
+
73
+
avdd-usb-supply:
74
+
description: USB I/Os, VBUS, ID, REXT, D+/D- power supply. Must
75
+
supply 3.3 V.
76
+
77
+
vclamp-usb-supply:
78
+
description: Bias rail for USB pad. Must supply 1.8 V.
79
+
80
+
vddio-hsic-supply:
81
+
description: HSIC PHY power supply. Must supply 1.2 V.
82
+
83
+
pads:
84
+
description: A required child node named "pads" contains a list of
85
+
subnodes, one for each of the pads exposed by the XUSB pad controller.
86
+
Each pad may need additional resources that can be referenced in its
87
+
pad node.
88
+
89
+
The "status" property is used to enable or disable the use of a pad.
90
+
If set to "disabled", the pad will not be used on the given board. In
91
+
order to use the pad and any of its lanes, this property must be set
92
+
to "okay" or be absent.
93
+
type: object
94
+
additionalProperties: false
95
+
properties:
96
+
usb2:
97
+
type: object
98
+
additionalProperties: false
99
+
properties:
100
+
clocks:
101
+
items:
102
+
- description: USB2 tracking clock
103
+
104
+
clock-names:
105
+
items:
106
+
- const: trk
107
+
108
+
lanes:
109
+
type: object
110
+
additionalProperties: false
111
+
properties:
112
+
usb2-0:
113
+
type: object
114
+
additionalProperties: false
115
+
properties:
116
+
"#phy-cells":
117
+
const: 0
118
+
119
+
nvidia,function:
120
+
description: Function selection for this lane.
121
+
$ref: /schemas/types.yaml#/definitions/string
122
+
enum: [ xusb ]
123
+
124
+
usb2-1:
125
+
type: object
126
+
additionalProperties: false
127
+
properties:
128
+
"#phy-cells":
129
+
const: 0
130
+
131
+
nvidia,function:
132
+
description: Function selection for this lane.
133
+
$ref: /schemas/types.yaml#/definitions/string
134
+
enum: [ xusb ]
135
+
136
+
usb2-2:
137
+
type: object
138
+
additionalProperties: false
139
+
properties:
140
+
"#phy-cells":
141
+
const: 0
142
+
143
+
nvidia,function:
144
+
description: Function selection for this lane.
145
+
$ref: /schemas/types.yaml#/definitions/string
146
+
enum: [ xusb ]
147
+
148
+
hsic:
149
+
type: object
150
+
additionalProperties: false
151
+
properties:
152
+
clocks:
153
+
items:
154
+
- description: HSIC tracking clock
155
+
156
+
clock-names:
157
+
items:
158
+
- const: trk
159
+
160
+
lanes:
161
+
type: object
162
+
additionalProperties: false
163
+
properties:
164
+
hsic-0:
165
+
type: object
166
+
additionalProperties: false
167
+
properties:
168
+
"#phy-cells":
169
+
const: 0
170
+
171
+
nvidia,function:
172
+
description: Function selection for this lane.
173
+
$ref: /schemas/types.yaml#/definitions/string
174
+
enum: [ xusb ]
175
+
176
+
usb3:
177
+
type: object
178
+
additionalProperties: false
179
+
properties:
180
+
lanes:
181
+
type: object
182
+
additionalProperties: false
183
+
properties:
184
+
usb3-0:
185
+
type: object
186
+
additionalProperties: false
187
+
properties:
188
+
"#phy-cells":
189
+
const: 0
190
+
191
+
nvidia,function:
192
+
description: Function selection for this lane.
193
+
$ref: /schemas/types.yaml#/definitions/string
194
+
enum: [ xusb ]
195
+
196
+
usb3-1:
197
+
type: object
198
+
additionalProperties: false
199
+
properties:
200
+
"#phy-cells":
201
+
const: 0
202
+
203
+
nvidia,function:
204
+
description: Function selection for this lane.
205
+
$ref: /schemas/types.yaml#/definitions/string
206
+
enum: [ xusb ]
207
+
208
+
usb3-2:
209
+
type: object
210
+
additionalProperties: false
211
+
properties:
212
+
"#phy-cells":
213
+
const: 0
214
+
215
+
nvidia,function:
216
+
description: Function selection for this lane.
217
+
$ref: /schemas/types.yaml#/definitions/string
218
+
enum: [ xusb ]
219
+
220
+
ports:
221
+
description: A required child node named "ports" contains a list of
222
+
subnodes, one for each of the ports exposed by the XUSB pad controller.
223
+
Each port may need additional resources that can be referenced in its
224
+
port node.
225
+
226
+
The "status" property is used to enable or disable the use of a port.
227
+
If set to "disabled", the port will not be used on the given board. In
228
+
order to use the port, this property must be set to "okay".
229
+
type: object
230
+
additionalProperties: false
231
+
properties:
232
+
usb2-0:
233
+
type: object
234
+
additionalProperties: false
235
+
properties:
236
+
# no need to further describe this because the connector will
237
+
# match on gpio-usb-b-connector or usb-b-connector and cause
238
+
# that binding to be selected for the subnode
239
+
connector:
240
+
type: object
241
+
242
+
mode:
243
+
description: A string that determines the mode in which to
244
+
run the port.
245
+
$ref: /schemas/types.yaml#/definitions/string
246
+
enum: [ host, peripheral, otg ]
247
+
248
+
nvidia,internal:
249
+
description: A boolean property whose presence determines
250
+
that a port is internal. In the absence of this property
251
+
the port is considered to be external.
252
+
$ref: /schemas/types.yaml#/definitions/flag
253
+
254
+
usb-role-switch:
255
+
description: |
256
+
A boolean property whole presence indicates that the port
257
+
supports OTG or peripheral mode. If present, the port
258
+
supports switching between USB host and peripheral roles.
259
+
A connector must be added as a subnode in that case.
260
+
261
+
See ../connector/usb-connector.yaml.
262
+
263
+
vbus-supply:
264
+
description: A phandle to the regulator supplying the VBUS
265
+
voltage.
266
+
267
+
dependencies:
268
+
usb-role-switch: [ connector ]
269
+
270
+
usb2-1:
271
+
type: object
272
+
additionalProperties: false
273
+
properties:
274
+
# no need to further describe this because the connector will
275
+
# match on gpio-usb-b-connector or usb-b-connector and cause
276
+
# that binding to be selected for the subnode
277
+
connector:
278
+
type: object
279
+
280
+
mode:
281
+
description: A string that determines the mode in which to
282
+
run the port.
283
+
$ref: /schemas/types.yaml#/definitions/string
284
+
enum: [ host, peripheral, otg ]
285
+
286
+
nvidia,internal:
287
+
description: A boolean property whose presence determines
288
+
that a port is internal. In the absence of this property
289
+
the port is considered to be external.
290
+
$ref: /schemas/types.yaml#/definitions/flag
291
+
292
+
usb-role-switch:
293
+
description: |
294
+
A boolean property whole presence indicates that the port
295
+
supports OTG or peripheral mode. If present, the port
296
+
supports switching between USB host and peripheral roles.
297
+
A connector must be added as a subnode in that case.
298
+
299
+
See ../connector/usb-connector.yaml.
300
+
301
+
vbus-supply:
302
+
description: A phandle to the regulator supplying the VBUS
303
+
voltage.
304
+
305
+
dependencies:
306
+
usb-role-switch: [ connector ]
307
+
308
+
usb2-2:
309
+
type: object
310
+
additionalProperties: false
311
+
properties:
312
+
# no need to further describe this because the connector will
313
+
# match on gpio-usb-b-connector or usb-b-connector and cause
314
+
# that binding to be selected for the subnode
315
+
connector:
316
+
type: object
317
+
318
+
mode:
319
+
description: A string that determines the mode in which to
320
+
run the port.
321
+
$ref: /schemas/types.yaml#/definitions/string
322
+
enum: [ host, peripheral, otg ]
323
+
324
+
nvidia,internal:
325
+
description: A boolean property whose presence determines
326
+
that a port is internal. In the absence of this property
327
+
the port is considered to be external.
328
+
$ref: /schemas/types.yaml#/definitions/flag
329
+
330
+
usb-role-switch:
331
+
description: |
332
+
A boolean property whole presence indicates that the port
333
+
supports OTG or peripheral mode. If present, the port
334
+
supports switching between USB host and peripheral roles.
335
+
A connector must be added as a subnode in that case.
336
+
337
+
See ../connector/usb-connector.yaml.
338
+
339
+
vbus-supply:
340
+
description: A phandle to the regulator supplying the VBUS
341
+
voltage.
342
+
343
+
dependencies:
344
+
usb-role-switch: [ connector ]
345
+
346
+
hsic-0:
347
+
type: object
348
+
additionalProperties: false
349
+
350
+
usb3-0:
351
+
type: object
352
+
additionalProperties: false
353
+
properties:
354
+
nvidia,internal:
355
+
description: A boolean property whose presence determines
356
+
that a port is internal. In the absence of this property
357
+
the port is considered to be external.
358
+
$ref: /schemas/types.yaml#/definitions/flag
359
+
360
+
nvidia,usb2-companion:
361
+
description: A single cell that specifies the physical port
362
+
number to map this super-speed USB port to. The range of
363
+
valid port numbers varies with the SoC generation.
364
+
$ref: /schemas/types.yaml#/definitions/uint32
365
+
enum: [ 0, 1, 2, 3 ]
366
+
367
+
vbus-supply:
368
+
description: A phandle to the regulator supplying the VBUS
369
+
voltage.
370
+
371
+
usb3-1:
372
+
type: object
373
+
additionalProperties: false
374
+
properties:
375
+
nvidia,internal:
376
+
description: A boolean property whose presence determines
377
+
that a port is internal. In the absence of this property
378
+
the port is considered to be external.
379
+
$ref: /schemas/types.yaml#/definitions/flag
380
+
381
+
nvidia,usb2-companion:
382
+
description: A single cell that specifies the physical port
383
+
number to map this super-speed USB port to. The range of
384
+
valid port numbers varies with the SoC generation.
385
+
$ref: /schemas/types.yaml#/definitions/uint32
386
+
enum: [ 0, 1, 2, 3 ]
387
+
388
+
vbus-supply:
389
+
description: A phandle to the regulator supplying the VBUS
390
+
voltage.
391
+
392
+
usb3-2:
393
+
type: object
394
+
additionalProperties: false
395
+
properties:
396
+
nvidia,internal:
397
+
description: A boolean property whose presence determines
398
+
that a port is internal. In the absence of this property
399
+
the port is considered to be external.
400
+
$ref: /schemas/types.yaml#/definitions/flag
401
+
402
+
nvidia,usb2-companion:
403
+
description: A single cell that specifies the physical port
404
+
number to map this super-speed USB port to. The range of
405
+
valid port numbers varies with the SoC generation.
406
+
$ref: /schemas/types.yaml#/definitions/uint32
407
+
enum: [ 0, 1, 2, 3 ]
408
+
409
+
vbus-supply:
410
+
description: A phandle to the regulator supplying the VBUS
411
+
voltage.
412
+
413
+
additionalProperties: false
414
+
415
+
required:
416
+
- compatible
417
+
- reg
418
+
- resets
419
+
- reset-names
420
+
- avdd-pll-erefeut-supply
421
+
- avdd-usb-supply
422
+
- vclamp-usb-supply
423
+
- vddio-hsic-supply
424
+
425
+
examples:
426
+
- |
427
+
#include <dt-bindings/clock/tegra186-clock.h>
428
+
#include <dt-bindings/gpio/tegra186-gpio.h>
429
+
#include <dt-bindings/interrupt-controller/arm-gic.h>
430
+
#include <dt-bindings/reset/tegra186-reset.h>
431
+
432
+
padctl@3520000 {
433
+
compatible = "nvidia,tegra186-xusb-padctl";
434
+
reg = <0x03520000 0x1000>,
435
+
<0x03540000 0x1000>;
436
+
reg-names = "padctl", "ao";
437
+
interrupts = <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>;
438
+
439
+
resets = <&bpmp TEGRA186_RESET_XUSB_PADCTL>;
440
+
reset-names = "padctl";
441
+
442
+
avdd-pll-erefeut-supply = <&vdd_1v8_pll>;
443
+
avdd-usb-supply = <&vdd_3v3_sys>;
444
+
vclamp-usb-supply = <&vdd_1v8>;
445
+
vddio-hsic-supply = <&gnd>;
446
+
447
+
pads {
448
+
usb2 {
449
+
clocks = <&bpmp TEGRA186_CLK_USB2_TRK>;
450
+
clock-names = "trk";
451
+
452
+
lanes {
453
+
usb2-0 {
454
+
nvidia,function = "xusb";
455
+
#phy-cells = <0>;
456
+
};
457
+
458
+
usb2-1 {
459
+
nvidia,function = "xusb";
460
+
#phy-cells = <0>;
461
+
};
462
+
463
+
usb2-2 {
464
+
nvidia,function = "xusb";
465
+
#phy-cells = <0>;
466
+
};
467
+
};
468
+
};
469
+
470
+
hsic {
471
+
clocks = <&bpmp TEGRA186_CLK_HSIC_TRK>;
472
+
clock-names = "trk";
473
+
status = "disabled";
474
+
475
+
lanes {
476
+
hsic-0 {
477
+
status = "disabled";
478
+
#phy-cells = <0>;
479
+
};
480
+
};
481
+
};
482
+
483
+
usb3 {
484
+
lanes {
485
+
usb3-0 {
486
+
nvidia,function = "xusb";
487
+
#phy-cells = <0>;
488
+
};
489
+
490
+
usb3-1 {
491
+
nvidia,function = "xusb";
492
+
#phy-cells = <0>;
493
+
};
494
+
495
+
usb3-2 {
496
+
nvidia,function = "xusb";
497
+
#phy-cells = <0>;
498
+
};
499
+
};
500
+
};
501
+
};
502
+
503
+
ports {
504
+
usb2-0 {
505
+
mode = "otg";
506
+
vbus-supply = <&vdd_usb0>;
507
+
usb-role-switch;
508
+
509
+
connector {
510
+
compatible = "gpio-usb-b-connector",
511
+
"usb-b-connector";
512
+
label = "micro-USB";
513
+
type = "micro";
514
+
vbus-gpios = <&gpio TEGRA186_MAIN_GPIO(X, 7) GPIO_ACTIVE_LOW>;
515
+
id-gpios = <&pmic 0 GPIO_ACTIVE_HIGH>;
516
+
};
517
+
};
518
+
519
+
usb2-1 {
520
+
vbus-supply = <&vdd_usb1>;
521
+
mode = "host";
522
+
};
523
+
524
+
usb2-2 {
525
+
status = "disabled";
526
+
};
527
+
528
+
hsic-0 {
529
+
status = "disabled";
530
+
};
531
+
532
+
usb3-0 {
533
+
nvidia,usb2-companion = <1>;
534
+
};
535
+
536
+
usb3-1 {
537
+
status = "disabled";
538
+
};
539
+
540
+
usb3-2 {
541
+
status = "disabled";
542
+
};
543
+
};
544
+
};
+632
Documentation/devicetree/bindings/phy/nvidia,tegra194-xusb-padctl.yaml
+632
Documentation/devicetree/bindings/phy/nvidia,tegra194-xusb-padctl.yaml
···
1
+
# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
2
+
%YAML 1.2
3
+
---
4
+
$id: http://devicetree.org/schemas/phy/nvidia,tegra194-xusb-padctl.yaml#
5
+
$schema: http://devicetree.org/meta-schemas/core.yaml#
6
+
7
+
title: NVIDIA Tegra194 XUSB pad controller
8
+
9
+
maintainers:
10
+
- Thierry Reding <thierry.reding@gmail.com>
11
+
- Jon Hunter <jonathanh@nvidia.com>
12
+
13
+
description: |
14
+
The Tegra XUSB pad controller manages a set of I/O lanes (with differential
15
+
signals) which connect directly to pins/pads on the SoC package. Each lane
16
+
is controlled by a HW block referred to as a "pad" in the Tegra hardware
17
+
documentation. Each such "pad" may control either one or multiple lanes,
18
+
and thus contains any logic common to all its lanes. Each lane can be
19
+
separately configured and powered up.
20
+
21
+
Some of the lanes are high-speed lanes, which can be used for PCIe, SATA or
22
+
super-speed USB. Other lanes are for various types of low-speed, full-speed
23
+
or high-speed USB (such as UTMI, ULPI and HSIC). The XUSB pad controller
24
+
contains a software-configurable mux that sits between the I/O controller
25
+
ports (e.g. PCIe) and the lanes.
26
+
27
+
In addition to per-lane configuration, USB 3.0 ports may require additional
28
+
settings on a per-board basis.
29
+
30
+
Pads will be represented as children of the top-level XUSB pad controller
31
+
device tree node. Each lane exposed by the pad will be represented by its
32
+
own subnode and can be referenced by users of the lane using the standard
33
+
PHY bindings, as described by the phy-bindings.txt file in this directory.
34
+
35
+
The Tegra hardware documentation refers to the connection between the XUSB
36
+
pad controller and the XUSB controller as "ports". This is confusing since
37
+
"port" is typically used to denote the physical USB receptacle. The device
38
+
tree binding in this document uses the term "port" to refer to the logical
39
+
abstraction of the signals that are routed to a USB receptacle (i.e. a PHY
40
+
for the USB signal, the VBUS power supply, the USB 2.0 companion port for
41
+
USB 3.0 receptacles, ...).
42
+
43
+
properties:
44
+
compatible:
45
+
enum:
46
+
- nvidia,tegra194-xusb-padctl
47
+
- nvidia,tegra234-xusb-padctl
48
+
49
+
reg:
50
+
items:
51
+
- description: pad controller registers
52
+
- description: AO registers
53
+
54
+
reg-names:
55
+
items:
56
+
- const: padctl
57
+
- const: ao
58
+
59
+
interrupts:
60
+
items:
61
+
- description: XUSB pad controller interrupt
62
+
63
+
resets:
64
+
items:
65
+
- description: pad controller reset
66
+
67
+
reset-names:
68
+
items:
69
+
- const: padctl
70
+
71
+
avdd-usb-supply:
72
+
description: USB I/Os, VBUS, ID, REXT, D+/D- power supply. Must
73
+
supply 3.3 V.
74
+
75
+
vclamp-usb-supply:
76
+
description: Bias rail for USB pad. Must supply 1.8 V.
77
+
78
+
pads:
79
+
description: A required child node named "pads" contains a list of
80
+
subnodes, one for each of the pads exposed by the XUSB pad controller.
81
+
Each pad may need additional resources that can be referenced in its
82
+
pad node.
83
+
84
+
The "status" property is used to enable or disable the use of a pad.
85
+
If set to "disabled", the pad will not be used on the given board. In
86
+
order to use the pad and any of its lanes, this property must be set
87
+
to "okay" or absent.
88
+
type: object
89
+
additionalProperties: false
90
+
properties:
91
+
usb2:
92
+
type: object
93
+
additionalProperties: false
94
+
properties:
95
+
clocks:
96
+
items:
97
+
- description: USB2 tracking clock
98
+
99
+
clock-names:
100
+
items:
101
+
- const: trk
102
+
103
+
lanes:
104
+
type: object
105
+
additionalProperties: false
106
+
properties:
107
+
usb2-0:
108
+
type: object
109
+
additionalProperties: false
110
+
properties:
111
+
"#phy-cells":
112
+
const: 0
113
+
114
+
nvidia,function:
115
+
description: Function selection for this lane.
116
+
$ref: /schemas/types.yaml#/definitions/string
117
+
enum: [ xusb ]
118
+
119
+
usb2-1:
120
+
type: object
121
+
additionalProperties: false
122
+
properties:
123
+
"#phy-cells":
124
+
const: 0
125
+
126
+
nvidia,function:
127
+
description: Function selection for this lane.
128
+
$ref: /schemas/types.yaml#/definitions/string
129
+
enum: [ xusb ]
130
+
131
+
usb2-2:
132
+
type: object
133
+
additionalProperties: false
134
+
properties:
135
+
"#phy-cells":
136
+
const: 0
137
+
138
+
nvidia,function:
139
+
description: Function selection for this lane.
140
+
$ref: /schemas/types.yaml#/definitions/string
141
+
enum: [ xusb ]
142
+
143
+
usb2-3:
144
+
type: object
145
+
additionalProperties: false
146
+
properties:
147
+
"#phy-cells":
148
+
const: 0
149
+
150
+
nvidia,function:
151
+
description: Function selection for this lane.
152
+
$ref: /schemas/types.yaml#/definitions/string
153
+
enum: [ xusb ]
154
+
155
+
usb3:
156
+
type: object
157
+
additionalProperties: false
158
+
properties:
159
+
lanes:
160
+
type: object
161
+
additionalProperties: false
162
+
properties:
163
+
usb3-0:
164
+
type: object
165
+
additionalProperties: false
166
+
properties:
167
+
"#phy-cells":
168
+
const: 0
169
+
170
+
nvidia,function:
171
+
description: Function selection for this lane.
172
+
$ref: /schemas/types.yaml#/definitions/string
173
+
enum: [ xusb ]
174
+
175
+
usb3-1:
176
+
type: object
177
+
additionalProperties: false
178
+
properties:
179
+
"#phy-cells":
180
+
const: 0
181
+
182
+
nvidia,function:
183
+
description: Function selection for this lane.
184
+
$ref: /schemas/types.yaml#/definitions/string
185
+
enum: [ xusb ]
186
+
187
+
usb3-2:
188
+
type: object
189
+
additionalProperties: false
190
+
properties:
191
+
"#phy-cells":
192
+
const: 0
193
+
194
+
nvidia,function:
195
+
description: Function selection for this lane.
196
+
$ref: /schemas/types.yaml#/definitions/string
197
+
enum: [ xusb ]
198
+
199
+
usb3-3:
200
+
type: object
201
+
additionalProperties: false
202
+
properties:
203
+
"#phy-cells":
204
+
const: 0
205
+
206
+
nvidia,function:
207
+
description: Function selection for this lane.
208
+
$ref: /schemas/types.yaml#/definitions/string
209
+
enum: [ xusb ]
210
+
211
+
ports:
212
+
description: A required child node named "ports" contains a list of
213
+
subnodes, one for each of the ports exposed by the XUSB pad controller.
214
+
Each port may need additional resources that can be referenced in its
215
+
port node.
216
+
217
+
The "status" property is used to enable or disable the use of a port.
218
+
If set to "disabled", the port will not be used on the given board. In
219
+
order to use the port, this property must be set to "okay".
220
+
type: object
221
+
additionalProperties: false
222
+
properties:
223
+
usb2-0:
224
+
type: object
225
+
additionalProperties: false
226
+
properties:
227
+
# no need to further describe this because the connector will
228
+
# match on gpio-usb-b-connector or usb-b-connector and cause
229
+
# that binding to be selected for the subnode
230
+
connector:
231
+
type: object
232
+
233
+
mode:
234
+
description: A string that determines the mode in which to
235
+
run the port.
236
+
$ref: /schemas/types.yaml#/definitions/string
237
+
enum: [ host, peripheral, otg ]
238
+
239
+
nvidia,internal:
240
+
description: A boolean property whose presence determines
241
+
that a port is internal. In the absence of this property
242
+
the port is considered to be external.
243
+
$ref: /schemas/types.yaml#/definitions/flag
244
+
245
+
usb-role-switch:
246
+
description: |
247
+
A boolean property whole presence indicates that the port
248
+
supports OTG or peripheral mode. If present, the port
249
+
supports switching between USB host and peripheral roles.
250
+
A connector must be added as a subnode in that case.
251
+
252
+
See ../connector/usb-connector.yaml.
253
+
254
+
vbus-supply:
255
+
description: A phandle to the regulator supplying the VBUS
256
+
voltage.
257
+
258
+
dependencies:
259
+
usb-role-switch: [ connector ]
260
+
261
+
usb2-1:
262
+
type: object
263
+
additionalProperties: false
264
+
properties:
265
+
# no need to further describe this because the connector will
266
+
# match on gpio-usb-b-connector or usb-b-connector and cause
267
+
# that binding to be selected for the subnode
268
+
connector:
269
+
type: object
270
+
271
+
mode:
272
+
description: A string that determines the mode in which to
273
+
run the port.
274
+
$ref: /schemas/types.yaml#/definitions/string
275
+
enum: [ host, peripheral, otg ]
276
+
277
+
nvidia,internal:
278
+
description: A boolean property whose presence determines
279
+
that a port is internal. In the absence of this property
280
+
the port is considered to be external.
281
+
$ref: /schemas/types.yaml#/definitions/flag
282
+
283
+
usb-role-switch:
284
+
description: |
285
+
A boolean property whole presence indicates that the port
286
+
supports OTG or peripheral mode. If present, the port
287
+
supports switching between USB host and peripheral roles.
288
+
A connector must be added as a subnode in that case.
289
+
290
+
See ../connector/usb-connector.yaml.
291
+
292
+
vbus-supply:
293
+
description: A phandle to the regulator supplying the VBUS
294
+
voltage.
295
+
296
+
dependencies:
297
+
usb-role-switch: [ connector ]
298
+
299
+
usb2-2:
300
+
type: object
301
+
additionalProperties: false
302
+
properties:
303
+
# no need to further describe this because the connector will
304
+
# match on gpio-usb-b-connector or usb-b-connector and cause
305
+
# that binding to be selected for the subnode
306
+
connector:
307
+
type: object
308
+
309
+
mode:
310
+
description: A string that determines the mode in which to
311
+
run the port.
312
+
$ref: /schemas/types.yaml#/definitions/string
313
+
enum: [ host, peripheral, otg ]
314
+
315
+
nvidia,internal:
316
+
description: A boolean property whose presence determines
317
+
that a port is internal. In the absence of this property
318
+
the port is considered to be external.
319
+
$ref: /schemas/types.yaml#/definitions/flag
320
+
321
+
usb-role-switch:
322
+
description: |
323
+
A boolean property whole presence indicates that the port
324
+
supports OTG or peripheral mode. If present, the port
325
+
supports switching between USB host and peripheral roles.
326
+
A connector must be added as a subnode in that case.
327
+
328
+
See ../connector/usb-connector.yaml.
329
+
330
+
vbus-supply:
331
+
description: A phandle to the regulator supplying the VBUS
332
+
voltage.
333
+
334
+
dependencies:
335
+
usb-role-switch: [ connector ]
336
+
337
+
usb2-3:
338
+
type: object
339
+
additionalProperties: false
340
+
properties:
341
+
# no need to further describe this because the connector will
342
+
# match on gpio-usb-b-connector or usb-b-connector and cause
343
+
# that binding to be selected for the subnode
344
+
connector:
345
+
type: object
346
+
347
+
mode:
348
+
description: A string that determines the mode in which to
349
+
run the port.
350
+
$ref: /schemas/types.yaml#/definitions/string
351
+
enum: [ host, peripheral, otg ]
352
+
353
+
nvidia,internal:
354
+
description: A boolean property whose presence determines
355
+
that a port is internal. In the absence of this property
356
+
the port is considered to be external.
357
+
$ref: /schemas/types.yaml#/definitions/flag
358
+
359
+
usb-role-switch:
360
+
description: |
361
+
A boolean property whole presence indicates that the port
362
+
supports OTG or peripheral mode. If present, the port
363
+
supports switching between USB host and peripheral roles.
364
+
A connector must be added as a subnode in that case.
365
+
366
+
See ../connector/usb-connector.yaml.
367
+
368
+
vbus-supply:
369
+
description: A phandle to the regulator supplying the VBUS
370
+
voltage.
371
+
372
+
dependencies:
373
+
usb-role-switch: [ connector ]
374
+
375
+
usb3-0:
376
+
type: object
377
+
additionalProperties: false
378
+
properties:
379
+
maximum-speed:
380
+
description: A string property that specifies the maximum
381
+
supported speed of a USB3 port.
382
+
$ref: /schemas/types.yaml#/definitions/string
383
+
oneOf:
384
+
- description: The USB3 port supports USB 3.1 Gen 2 speed.
385
+
This is the default.
386
+
const: super-speed-plus
387
+
- description: The USB3 port supports USB 3.1 Gen 1 speed
388
+
only.
389
+
const: super-speed
390
+
391
+
nvidia,internal:
392
+
description: A boolean property whose presence determines
393
+
that a port is internal. In the absence of this property
394
+
the port is considered to be external.
395
+
$ref: /schemas/types.yaml#/definitions/flag
396
+
397
+
nvidia,usb2-companion:
398
+
description: A single cell that specifies the physical port
399
+
number to map this super-speed USB port to. The range of
400
+
valid port numbers varies with the SoC generation.
401
+
$ref: /schemas/types.yaml#/definitions/uint32
402
+
enum: [ 0, 1, 2, 3 ]
403
+
404
+
vbus-supply:
405
+
description: A phandle to the regulator supplying the VBUS
406
+
voltage.
407
+
408
+
usb3-1:
409
+
type: object
410
+
additionalProperties: false
411
+
properties:
412
+
maximum-speed:
413
+
description: A string property that specifies the maximum
414
+
supported speed of a USB3 port.
415
+
$ref: /schemas/types.yaml#/definitions/string
416
+
oneOf:
417
+
- description: The USB3 port supports USB 3.1 Gen 2 speed.
418
+
This is the default.
419
+
const: super-speed-plus
420
+
- description: The USB3 port supports USB 3.1 Gen 1 speed
421
+
only.
422
+
const: super-speed
423
+
424
+
nvidia,internal:
425
+
description: A boolean property whose presence determines
426
+
that a port is internal. In the absence of this property
427
+
the port is considered to be external.
428
+
$ref: /schemas/types.yaml#/definitions/flag
429
+
430
+
nvidia,usb2-companion:
431
+
description: A single cell that specifies the physical port
432
+
number to map this super-speed USB port to. The range of
433
+
valid port numbers varies with the SoC generation.
434
+
$ref: /schemas/types.yaml#/definitions/uint32
435
+
enum: [ 0, 1, 2, 3 ]
436
+
437
+
vbus-supply:
438
+
description: A phandle to the regulator supplying the VBUS
439
+
voltage.
440
+
441
+
usb3-2:
442
+
type: object
443
+
additionalProperties: false
444
+
properties:
445
+
maximum-speed:
446
+
description: A string property that specifies the maximum
447
+
supported speed of a USB3 port.
448
+
$ref: /schemas/types.yaml#/definitions/string
449
+
oneOf:
450
+
- description: The USB3 port supports USB 3.1 Gen 2 speed.
451
+
This is the default.
452
+
const: super-speed-plus
453
+
- description: The USB3 port supports USB 3.1 Gen 1 speed
454
+
only.
455
+
const: super-speed
456
+
457
+
nvidia,internal:
458
+
description: A boolean property whose presence determines
459
+
that a port is internal. In the absence of this property
460
+
the port is considered to be external.
461
+
$ref: /schemas/types.yaml#/definitions/flag
462
+
463
+
nvidia,usb2-companion:
464
+
description: A single cell that specifies the physical port
465
+
number to map this super-speed USB port to. The range of
466
+
valid port numbers varies with the SoC generation.
467
+
$ref: /schemas/types.yaml#/definitions/uint32
468
+
enum: [ 0, 1, 2, 3 ]
469
+
470
+
vbus-supply:
471
+
description: A phandle to the regulator supplying the VBUS
472
+
voltage.
473
+
474
+
usb3-3:
475
+
type: object
476
+
additionalProperties: false
477
+
properties:
478
+
maximum-speed:
479
+
description: A string property that specifies the maximum
480
+
supported speed of a USB3 port.
481
+
$ref: /schemas/types.yaml#/definitions/string
482
+
oneOf:
483
+
- description: The USB3 port supports USB 3.1 Gen 2 speed.
484
+
This is the default.
485
+
const: super-speed-plus
486
+
- description: The USB3 port supports USB 3.1 Gen 1 speed
487
+
only.
488
+
const: super-speed
489
+
490
+
nvidia,internal:
491
+
description: A boolean property whose presence determines
492
+
that a port is internal. In the absence of this property
493
+
the port is considered to be external.
494
+
$ref: /schemas/types.yaml#/definitions/flag
495
+
496
+
nvidia,usb2-companion:
497
+
description: A single cell that specifies the physical port
498
+
number to map this super-speed USB port to. The range of
499
+
valid port numbers varies with the SoC generation.
500
+
$ref: /schemas/types.yaml#/definitions/uint32
501
+
enum: [ 0, 1, 2, 3 ]
502
+
503
+
vbus-supply:
504
+
description: A phandle to the regulator supplying the VBUS
505
+
voltage.
506
+
507
+
additionalProperties: false
508
+
509
+
required:
510
+
- compatible
511
+
- reg
512
+
- resets
513
+
- reset-names
514
+
- avdd-usb-supply
515
+
- vclamp-usb-supply
516
+
517
+
examples:
518
+
- |
519
+
#include <dt-bindings/clock/tegra194-clock.h>
520
+
#include <dt-bindings/gpio/tegra194-gpio.h>
521
+
#include <dt-bindings/interrupt-controller/arm-gic.h>
522
+
#include <dt-bindings/reset/tegra194-reset.h>
523
+
524
+
padctl@3520000 {
525
+
compatible = "nvidia,tegra194-xusb-padctl";
526
+
reg = <0x03520000 0x1000>,
527
+
<0x03540000 0x1000>;
528
+
reg-names = "padctl", "ao";
529
+
interrupts = <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>;
530
+
531
+
resets = <&bpmp TEGRA194_RESET_XUSB_PADCTL>;
532
+
reset-names = "padctl";
533
+
534
+
avdd-usb-supply = <&vdd_usb_3v3>;
535
+
vclamp-usb-supply = <&vdd_1v8ao>;
536
+
537
+
pads {
538
+
usb2 {
539
+
clocks = <&bpmp TEGRA194_CLK_USB2_TRK>;
540
+
clock-names = "trk";
541
+
542
+
lanes {
543
+
usb2-0 {
544
+
nvidia,function = "xusb";
545
+
status = "disabled";
546
+
#phy-cells = <0>;
547
+
};
548
+
549
+
usb2-1 {
550
+
nvidia,function = "xusb";
551
+
#phy-cells = <0>;
552
+
};
553
+
554
+
usb2-2 {
555
+
nvidia,function = "xusb";
556
+
status = "disabled";
557
+
#phy-cells = <0>;
558
+
};
559
+
560
+
usb2-3 {
561
+
nvidia,function = "xusb";
562
+
#phy-cells = <0>;
563
+
};
564
+
};
565
+
};
566
+
567
+
usb3 {
568
+
lanes {
569
+
usb3-0 {
570
+
nvidia,function = "xusb";
571
+
#phy-cells = <0>;
572
+
};
573
+
574
+
usb3-1 {
575
+
nvidia,function = "xusb";
576
+
status = "disabled";
577
+
#phy-cells = <0>;
578
+
};
579
+
580
+
usb3-2 {
581
+
nvidia,function = "xusb";
582
+
status = "disabled";
583
+
#phy-cells = <0>;
584
+
};
585
+
586
+
usb3-3 {
587
+
nvidia,function = "xusb";
588
+
#phy-cells = <0>;
589
+
};
590
+
};
591
+
};
592
+
};
593
+
594
+
ports {
595
+
usb2-0 {
596
+
status = "disabled";
597
+
};
598
+
599
+
usb2-1 {
600
+
vbus-supply = <&vdd_5v0_sys>;
601
+
mode = "host";
602
+
};
603
+
604
+
usb2-2 {
605
+
status = "disabled";
606
+
};
607
+
608
+
usb2-3 {
609
+
vbus-supply = <&vdd_5v_sata>;
610
+
mode = "host";
611
+
};
612
+
613
+
usb3-0 {
614
+
vbus-supply = <&vdd_5v0_sys>;
615
+
nvidia,usb2-companion = <1>;
616
+
};
617
+
618
+
usb3-1 {
619
+
status = "disabled";
620
+
};
621
+
622
+
usb3-2 {
623
+
status = "disabled";
624
+
};
625
+
626
+
usb3-3 {
627
+
maximum-speed = "super-speed";
628
+
vbus-supply = <&vdd_5v0_sys>;
629
+
nvidia,usb2-companion = <3>;
630
+
};
631
+
};
632
+
};
+786
Documentation/devicetree/bindings/phy/nvidia,tegra210-xusb-padctl.yaml
+786
Documentation/devicetree/bindings/phy/nvidia,tegra210-xusb-padctl.yaml
···
1
+
# SPDX-License-Identifier: GPL-2.0-only or BSD-2-Clause
2
+
%YAML 1.2
3
+
---
4
+
$id: http://devicetree.org/schemas/phy/nvidia,tegra210-xusb-padctl.yaml#
5
+
$schema: http://devicetree.org/meta-schemas/core.yaml#
6
+
7
+
title: NVIDIA Tegra210 XUSB pad controller
8
+
9
+
maintainers:
10
+
- Thierry Reding <thierry.reding@gmail.com>
11
+
- Jon Hunter <jonathanh@nvidia.com>
12
+
13
+
description: |
14
+
The Tegra XUSB pad controller manages a set of I/O lanes (with differential
15
+
signals) which connect directly to pins/pads on the SoC package. Each lane
16
+
is controlled by a HW block referred to as a "pad" in the Tegra hardware
17
+
documentation. Each such "pad" may control either one or multiple lanes,
18
+
and thus contains any logic common to all its lanes. Each lane can be
19
+
separately configured and powered up.
20
+
21
+
Some of the lanes are high-speed lanes, which can be used for PCIe, SATA or
22
+
super-speed USB. Other lanes are for various types of low-speed, full-speed
23
+
or high-speed USB (such as UTMI, ULPI and HSIC). The XUSB pad controller
24
+
contains a software-configurable mux that sits between the I/O controller
25
+
ports (e.g. PCIe) and the lanes.
26
+
27
+
In addition to per-lane configuration, USB 3.0 ports may require additional
28
+
settings on a per-board basis.
29
+
30
+
Pads will be represented as children of the top-level XUSB pad controller
31
+
device tree node. Each lane exposed by the pad will be represented by its
32
+
own subnode and can be referenced by users of the lane using the standard
33
+
PHY bindings, as described by the phy-bindings.txt file in this directory.
34
+
35
+
The Tegra hardware documentation refers to the connection between the XUSB
36
+
pad controller and the XUSB controller as "ports". This is confusing since
37
+
"port" is typically used to denote the physical USB receptacle. The device
38
+
tree binding in this document uses the term "port" to refer to the logical
39
+
abstraction of the signals that are routed to a USB receptacle (i.e. a PHY
40
+
for the USB signal, the VBUS power supply, the USB 2.0 companion port for
41
+
USB 3.0 receptacles, ...).
42
+
43
+
properties:
44
+
compatible:
45
+
const: nvidia,tegra210-xusb-padctl
46
+
47
+
reg:
48
+
maxItems: 1
49
+
50
+
resets:
51
+
items:
52
+
- description: pad controller reset
53
+
54
+
interrupts:
55
+
items:
56
+
- description: XUSB pad controller interrupt
57
+
58
+
reset-names:
59
+
items:
60
+
- const: padctl
61
+
62
+
avdd-pll-utmip-supply:
63
+
description: UTMI PLL power supply. Must supply 1.8 V.
64
+
65
+
avdd-pll-uerefe-supply:
66
+
description: PLLE reference PLL power supply. Must supply 1.05 V.
67
+
68
+
dvdd-pex-pll-supply:
69
+
description: PCIe/USB3 PLL power supply. Must supply 1.05 V.
70
+
71
+
hvdd-pex-pll-e-supply:
72
+
description: High-voltage PLLE power supply. Must supply 1.8 V.
73
+
74
+
nvidia,pmc:
75
+
description: phandle to the Tegra Power Management Controller (PMC) node
76
+
$ref: /schemas/types.yaml#/definitions/phandle
77
+
78
+
pads:
79
+
description: A required child node named "pads" contains a list of
80
+
subnodes, one for each of the pads exposed by the XUSB pad controller.
81
+
Each pad may need additional resources that can be referenced in its
82
+
pad node.
83
+
84
+
The "status" property is used to enable or disable the use of a pad.
85
+
If set to "disabled", the pad will not be used on the given board. In
86
+
order to use the pad and any of its lanes, this property must be set
87
+
to "okay" or be absent.
88
+
type: object
89
+
additionalProperties: false
90
+
properties:
91
+
usb2:
92
+
type: object
93
+
additionalProperties: false
94
+
properties:
95
+
clocks:
96
+
items:
97
+
- description: USB2 tracking clock
98
+
99
+
clock-names:
100
+
items:
101
+
- const: trk
102
+
103
+
lanes:
104
+
type: object
105
+
additionalProperties: false
106
+
properties:
107
+
usb2-0:
108
+
type: object
109
+
additionalProperties: false
110
+
properties:
111
+
"#phy-cells":
112
+
const: 0
113
+
114
+
nvidia,function:
115
+
description: Function selection for this lane.
116
+
$ref: /schemas/types.yaml#/definitions/string
117
+
enum: [ snps, xusb, uart ]
118
+
119
+
usb2-1:
120
+
type: object
121
+
additionalProperties: false
122
+
properties:
123
+
"#phy-cells":
124
+
const: 0
125
+
126
+
nvidia,function:
127
+
description: Function selection for this lane.
128
+
$ref: /schemas/types.yaml#/definitions/string
129
+
enum: [ snps, xusb, uart ]
130
+
131
+
usb2-2:
132
+
type: object
133
+
additionalProperties: false
134
+
properties:
135
+
"#phy-cells":
136
+
const: 0
137
+
138
+
nvidia,function:
139
+
description: Function selection for this lane.
140
+
$ref: /schemas/types.yaml#/definitions/string
141
+
enum: [ snps, xusb, uart ]
142
+
143
+
usb2-3:
144
+
type: object
145
+
additionalProperties: false
146
+
properties:
147
+
"#phy-cells":
148
+
const: 0
149
+
150
+
nvidia,function:
151
+
description: Function selection for this lane.
152
+
$ref: /schemas/types.yaml#/definitions/string
153
+
enum: [ snps, xusb, uart ]
154
+
155
+
hsic:
156
+
type: object
157
+
additionalProperties: false
158
+
properties:
159
+
clocks:
160
+
items:
161
+
- description: HSIC tracking clock
162
+
163
+
clock-names:
164
+
items:
165
+
- const: trk
166
+
167
+
lanes:
168
+
type: object
169
+
additionalProperties: false
170
+
properties:
171
+
hsic-0:
172
+
type: object
173
+
additionalProperties: false
174
+
properties:
175
+
"#phy-cells":
176
+
const: 0
177
+
178
+
nvidia,function:
179
+
description: Function selection for this lane.
180
+
$ref: /schemas/types.yaml#/definitions/string
181
+
enum: [ snps, xusb ]
182
+
183
+
hsic-1:
184
+
type: object
185
+
additionalProperties: false
186
+
properties:
187
+
"#phy-cells":
188
+
const: 0
189
+
190
+
nvidia,function:
191
+
description: Function selection for this lane.
192
+
$ref: /schemas/types.yaml#/definitions/string
193
+
enum: [ snps, xusb ]
194
+
195
+
pcie:
196
+
type: object
197
+
additionalProperties: false
198
+
properties:
199
+
clocks:
200
+
items:
201
+
- description: PCIe PLL clock source
202
+
203
+
clock-names:
204
+
items:
205
+
- const: pll
206
+
207
+
resets:
208
+
items:
209
+
- description: PCIe PHY reset
210
+
211
+
reset-names:
212
+
items:
213
+
- const: phy
214
+
215
+
lanes:
216
+
type: object
217
+
additionalProperties: false
218
+
properties:
219
+
pcie-0:
220
+
type: object
221
+
additionalProperties: false
222
+
properties:
223
+
"#phy-cells":
224
+
const: 0
225
+
226
+
nvidia,function:
227
+
description: Function selection for this lane.
228
+
$ref: /schemas/types.yaml#/definitions/string
229
+
enum: [ pcie-x1, usb3-ss, pcie-x4 ]
230
+
231
+
pcie-1:
232
+
type: object
233
+
additionalProperties: false
234
+
properties:
235
+
"#phy-cells":
236
+
const: 0
237
+
238
+
nvidia,function:
239
+
description: Function selection for this lane.
240
+
$ref: /schemas/types.yaml#/definitions/string
241
+
enum: [ pcie-x1, usb3-ss, pcie-x4 ]
242
+
243
+
pcie-2:
244
+
type: object
245
+
additionalProperties: false
246
+
properties:
247
+
"#phy-cells":
248
+
const: 0
249
+
250
+
nvidia,function:
251
+
description: Function selection for this lane.
252
+
$ref: /schemas/types.yaml#/definitions/string
253
+
enum: [ pcie-x1, usb3-ss, pcie-x4 ]
254
+
255
+
pcie-3:
256
+
type: object
257
+
additionalProperties: false
258
+
properties:
259
+
"#phy-cells":
260
+
const: 0
261
+
262
+
nvidia,function:
263
+
description: Function selection for this lane.
264
+
$ref: /schemas/types.yaml#/definitions/string
265
+
enum: [ pcie-x1, usb3-ss, pcie-x4 ]
266
+
267
+
pcie-4:
268
+
type: object
269
+
additionalProperties: false
270
+
properties:
271
+
"#phy-cells":
272
+
const: 0
273
+
274
+
nvidia,function:
275
+
description: Function selection for this lane.
276
+
$ref: /schemas/types.yaml#/definitions/string
277
+
enum: [ pcie-x1, usb3-ss, pcie-x4 ]
278
+
279
+
pcie-5:
280
+
type: object
281
+
additionalProperties: false
282
+
properties:
283
+
"#phy-cells":
284
+
const: 0
285
+
286
+
nvidia,function:
287
+
description: Function selection for this lane.
288
+
$ref: /schemas/types.yaml#/definitions/string
289
+
enum: [ pcie-x1, usb3-ss, pcie-x4 ]
290
+
291
+
pcie-6:
292
+
type: object
293
+
additionalProperties: false
294
+
properties:
295
+
"#phy-cells":
296
+
const: 0
297
+
298
+
nvidia,function:
299
+
description: Function selection for this lane.
300
+
$ref: /schemas/types.yaml#/definitions/string
301
+
enum: [ pcie-x1, usb3-ss, pcie-x4 ]
302
+
303
+
sata:
304
+
type: object
305
+
additionalProperties: false
306
+
properties:
307
+
clocks:
308
+
items:
309
+
- description: SATA PLL clock source
310
+
311
+
clock-names:
312
+
items:
313
+
- const: pll
314
+
315
+
resets:
316
+
items:
317
+
- description: SATA PHY reset
318
+
319
+
reset-names:
320
+
items:
321
+
- const: phy
322
+
323
+
lanes:
324
+
type: object
325
+
additionalProperties: false
326
+
properties:
327
+
sata-0:
328
+
type: object
329
+
additionalProperties: false
330
+
properties:
331
+
"#phy-cells":
332
+
const: 0
333
+
334
+
nvidia,function:
335
+
description: Function selection for this lane.
336
+
$ref: /schemas/types.yaml#/definitions/string
337
+
enum: [ usb3-ss, sata ]
338
+
339
+
ports:
340
+
description: A required child node named "ports" contains a list of
341
+
subnodes, one for each of the ports exposed by the XUSB pad controller.
342
+
Each port may need additional resources that can be referenced in its
343
+
port node.
344
+
345
+
The "status" property is used to enable or disable the use of a port.
346
+
If set to "disabled", the port will not be used on the given board. In
347
+
order to use the port, this property must be set to "okay".
348
+
type: object
349
+
additionalProperties: false
350
+
properties:
351
+
usb2-0:
352
+
type: object
353
+
additionalProperties: false
354
+
properties:
355
+
# no need to further describe this because the connector will
356
+
# match on gpio-usb-b-connector or usb-b-connector and cause
357
+
# that binding to be selected for the subnode
358
+
connector:
359
+
type: object
360
+
361
+
mode:
362
+
description: A string that determines the mode in which to
363
+
run the port.
364
+
$ref: /schemas/types.yaml#/definitions/string
365
+
enum: [ host, peripheral, otg ]
366
+
367
+
nvidia,internal:
368
+
description: A boolean property whose presence determines
369
+
that a port is internal. In the absence of this property
370
+
the port is considered to be external.
371
+
$ref: /schemas/types.yaml#/definitions/flag
372
+
373
+
usb-role-switch:
374
+
description: |
375
+
A boolean property whole presence indicates that the port
376
+
supports OTG or peripheral mode. If present, the port
377
+
supports switching between USB host and peripheral roles.
378
+
A connector must be added as a subnode in that case.
379
+
380
+
See ../connector/usb-connector.yaml.
381
+
382
+
vbus-supply:
383
+
description: A phandle to the regulator supplying the VBUS
384
+
voltage.
385
+
386
+
dependencies:
387
+
usb-role-switch: [ connector ]
388
+
389
+
usb2-1:
390
+
type: object
391
+
additionalProperties: false
392
+
properties:
393
+
# no need to further describe this because the connector will
394
+
# match on gpio-usb-b-connector or usb-b-connector and cause
395
+
# that binding to be selected for the subnode
396
+
connector:
397
+
type: object
398
+
399
+
mode:
400
+
description: A string that determines the mode in which to
401
+
run the port.
402
+
$ref: /schemas/types.yaml#/definitions/string
403
+
enum: [ host, peripheral, otg ]
404
+
405
+
nvidia,internal:
406
+
description: A boolean property whose presence determines
407
+
that a port is internal. In the absence of this property
408
+
the port is considered to be external.
409
+
$ref: /schemas/types.yaml#/definitions/flag
410
+
411
+
usb-role-switch:
412
+
description: |
413
+
A boolean property whole presence indicates that the port
414
+
supports OTG or peripheral mode. If present, the port
415
+
supports switching between USB host and peripheral roles.
416
+
A connector must be added as a subnode in that case.
417
+
418
+
See ../connector/usb-connector.yaml.
419
+
420
+
vbus-supply:
421
+
description: A phandle to the regulator supplying the VBUS
422
+
voltage.
423
+
424
+
dependencies:
425
+
usb-role-switch: [ connector ]
426
+
427
+
usb2-2:
428
+
type: object
429
+
additionalProperties: false
430
+
properties:
431
+
# no need to further describe this because the connector will
432
+
# match on gpio-usb-b-connector or usb-b-connector and cause
433
+
# that binding to be selected for the subnode
434
+
connector:
435
+
type: object
436
+
437
+
mode:
438
+
description: A string that determines the mode in which to
439
+
run the port.
440
+
$ref: /schemas/types.yaml#/definitions/string
441
+
enum: [ host, peripheral, otg ]
442
+
443
+
nvidia,internal:
444
+
description: A boolean property whose presence determines
445
+
that a port is internal. In the absence of this property
446
+
the port is considered to be external.
447
+
$ref: /schemas/types.yaml#/definitions/flag
448
+
449
+
usb-role-switch:
450
+
description: |
451
+
A boolean property whole presence indicates that the port
452
+
supports OTG or peripheral mode. If present, the port
453
+
supports switching between USB host and peripheral roles.
454
+
A connector must be added as a subnode in that case.
455
+
456
+
See ../connector/usb-connector.yaml.
457
+
458
+
vbus-supply:
459
+
description: A phandle to the regulator supplying the VBUS
460
+
voltage.
461
+
462
+
dependencies:
463
+
usb-role-switch: [ connector ]
464
+
465
+
usb2-3:
466
+
type: object
467
+
additionalProperties: false
468
+
properties:
469
+
# no need to further describe this because the connector will
470
+
# match on gpio-usb-b-connector or usb-b-connector and cause
471
+
# that binding to be selected for the subnode
472
+
connector:
473
+
type: object
474
+
475
+
mode:
476
+
description: A string that determines the mode in which to
477
+
run the port.
478
+
$ref: /schemas/types.yaml#/definitions/string
479
+
enum: [ host, peripheral, otg ]
480
+
481
+
nvidia,internal:
482
+
description: A boolean property whose presence determines
483
+
that a port is internal. In the absence of this property
484
+
the port is considered to be external.
485
+
$ref: /schemas/types.yaml#/definitions/flag
486
+
487
+
usb-role-switch:
488
+
description: |
489
+
A boolean property whole presence indicates that the port
490
+
supports OTG or peripheral mode. If present, the port
491
+
supports switching between USB host and peripheral roles.
492
+
A connector must be added as a subnode in that case.
493
+
494
+
See ../connector/usb-connector.yaml.
495
+
496
+
vbus-supply:
497
+
description: A phandle to the regulator supplying the VBUS
498
+
voltage.
499
+
500
+
dependencies:
501
+
usb-role-switch: [ connector ]
502
+
503
+
hsic-0:
504
+
type: object
505
+
additionalProperties: false
506
+
properties:
507
+
vbus-supply:
508
+
description: A phandle to the regulator supplying the VBUS
509
+
voltage.
510
+
511
+
hsic-1:
512
+
type: object
513
+
additionalProperties: false
514
+
properties:
515
+
vbus-supply:
516
+
description: A phandle to the regulator supplying the VBUS
517
+
voltage.
518
+
519
+
usb3-0:
520
+
type: object
521
+
additionalProperties: false
522
+
properties:
523
+
nvidia,internal:
524
+
description: A boolean property whose presence determines
525
+
that a port is internal. In the absence of this property
526
+
the port is considered to be external.
527
+
$ref: /schemas/types.yaml#/definitions/flag
528
+
529
+
nvidia,usb2-companion:
530
+
description: A single cell that specifies the physical port
531
+
number to map this super-speed USB port to. The range of
532
+
valid port numbers varies with the SoC generation.
533
+
$ref: /schemas/types.yaml#/definitions/uint32
534
+
enum: [ 0, 1, 2, 3 ]
535
+
536
+
vbus-supply:
537
+
description: A phandle to the regulator supplying the VBUS
538
+
voltage.
539
+
540
+
usb3-1:
541
+
type: object
542
+
additionalProperties: false
543
+
properties:
544
+
nvidia,internal:
545
+
description: A boolean property whose presence determines
546
+
that a port is internal. In the absence of this property
547
+
the port is considered to be external.
548
+
$ref: /schemas/types.yaml#/definitions/flag
549
+
550
+
nvidia,usb2-companion:
551
+
description: A single cell that specifies the physical port
552
+
number to map this super-speed USB port to. The range of
553
+
valid port numbers varies with the SoC generation.
554
+
$ref: /schemas/types.yaml#/definitions/uint32
555
+
enum: [ 0, 1, 2, 3 ]
556
+
557
+
vbus-supply:
558
+
description: A phandle to the regulator supplying the VBUS
559
+
voltage.
560
+
561
+
usb3-2:
562
+
type: object
563
+
additionalProperties: false
564
+
properties:
565
+
nvidia,internal:
566
+
description: A boolean property whose presence determines
567
+
that a port is internal. In the absence of this property
568
+
the port is considered to be external.
569
+
$ref: /schemas/types.yaml#/definitions/flag
570
+
571
+
nvidia,usb2-companion:
572
+
description: A single cell that specifies the physical port
573
+
number to map this super-speed USB port to. The range of
574
+
valid port numbers varies with the SoC generation.
575
+
$ref: /schemas/types.yaml#/definitions/uint32
576
+
enum: [ 0, 1, 2, 3 ]
577
+
578
+
vbus-supply:
579
+
description: A phandle to the regulator supplying the VBUS
580
+
voltage.
581
+
582
+
usb3-3:
583
+
type: object
584
+
additionalProperties: false
585
+
properties:
586
+
nvidia,internal:
587
+
description: A boolean property whose presence determines
588
+
that a port is internal. In the absence of this property
589
+
the port is considered to be external.
590
+
$ref: /schemas/types.yaml#/definitions/flag
591
+
592
+
nvidia,usb2-companion:
593
+
description: A single cell that specifies the physical port
594
+
number to map this super-speed USB port to. The range of
595
+
valid port numbers varies with the SoC generation.
596
+
$ref: /schemas/types.yaml#/definitions/uint32
597
+
enum: [ 0, 1, 2, 3 ]
598
+
599
+
vbus-supply:
600
+
description: A phandle to the regulator supplying the VBUS
601
+
voltage.
602
+
603
+
additionalProperties: false
604
+
605
+
required:
606
+
- avdd-pll-utmip-supply
607
+
- avdd-pll-uerefe-supply
608
+
- dvdd-pex-pll-supply
609
+
- hvdd-pex-pll-e-supply
610
+
611
+
examples:
612
+
- |
613
+
#include <dt-bindings/clock/tegra210-car.h>
614
+
#include <dt-bindings/gpio/tegra-gpio.h>
615
+
#include <dt-bindings/interrupt-controller/arm-gic.h>
616
+
617
+
padctl@7009f000 {
618
+
compatible = "nvidia,tegra210-xusb-padctl";
619
+
reg = <0x7009f000 0x1000>;
620
+
interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
621
+
resets = <&tegra_car 142>;
622
+
reset-names = "padctl";
623
+
624
+
avdd-pll-utmip-supply = <&vdd_1v8>;
625
+
avdd-pll-uerefe-supply = <&vdd_pex_1v05>;
626
+
dvdd-pex-pll-supply = <&vdd_pex_1v05>;
627
+
hvdd-pex-pll-e-supply = <&vdd_1v8>;
628
+
629
+
pads {
630
+
usb2 {
631
+
clocks = <&tegra_car TEGRA210_CLK_USB2_TRK>;
632
+
clock-names = "trk";
633
+
634
+
lanes {
635
+
usb2-0 {
636
+
nvidia,function = "xusb";
637
+
#phy-cells = <0>;
638
+
};
639
+
640
+
usb2-1 {
641
+
nvidia,function = "xusb";
642
+
#phy-cells = <0>;
643
+
};
644
+
645
+
usb2-2 {
646
+
nvidia,function = "xusb";
647
+
#phy-cells = <0>;
648
+
};
649
+
650
+
usb2-3 {
651
+
nvidia,function = "xusb";
652
+
#phy-cells = <0>;
653
+
};
654
+
};
655
+
};
656
+
657
+
hsic {
658
+
clocks = <&tegra_car TEGRA210_CLK_HSIC_TRK>;
659
+
clock-names = "trk";
660
+
status = "disabled";
661
+
662
+
lanes {
663
+
hsic-0 {
664
+
status = "disabled";
665
+
#phy-cells = <0>;
666
+
};
667
+
668
+
hsic-1 {
669
+
status = "disabled";
670
+
#phy-cells = <0>;
671
+
};
672
+
};
673
+
};
674
+
675
+
pcie {
676
+
clocks = <&tegra_car TEGRA210_CLK_PLL_E>;
677
+
clock-names = "pll";
678
+
resets = <&tegra_car 205>;
679
+
reset-names = "phy";
680
+
681
+
lanes {
682
+
pcie-0 {
683
+
nvidia,function = "pcie-x1";
684
+
#phy-cells = <0>;
685
+
};
686
+
687
+
pcie-1 {
688
+
nvidia,function = "pcie-x4";
689
+
#phy-cells = <0>;
690
+
};
691
+
692
+
pcie-2 {
693
+
nvidia,function = "pcie-x4";
694
+
#phy-cells = <0>;
695
+
};
696
+
697
+
pcie-3 {
698
+
nvidia,function = "pcie-x4";
699
+
#phy-cells = <0>;
700
+
};
701
+
702
+
pcie-4 {
703
+
nvidia,function = "pcie-x4";
704
+
#phy-cells = <0>;
705
+
};
706
+
707
+
pcie-5 {
708
+
nvidia,function = "usb3-ss";
709
+
#phy-cells = <0>;
710
+
};
711
+
712
+
pcie-6 {
713
+
nvidia,function = "usb3-ss";
714
+
#phy-cells = <0>;
715
+
};
716
+
};
717
+
};
718
+
719
+
sata {
720
+
clocks = <&tegra_car TEGRA210_CLK_PLL_E>;
721
+
clock-names = "pll";
722
+
resets = <&tegra_car 204>;
723
+
reset-names = "phy";
724
+
725
+
lanes {
726
+
sata-0 {
727
+
nvidia,function = "sata";
728
+
#phy-cells = <0>;
729
+
};
730
+
};
731
+
};
732
+
};
733
+
734
+
ports {
735
+
usb2-0 {
736
+
mode = "peripheral";
737
+
usb-role-switch;
738
+
739
+
connector {
740
+
compatible = "gpio-usb-b-connector",
741
+
"usb-b-connector";
742
+
label = "micro-USB";
743
+
type = "micro";
744
+
vbus-gpios = <&gpio TEGRA_GPIO(CC, 4) GPIO_ACTIVE_LOW>;
745
+
};
746
+
};
747
+
748
+
usb2-1 {
749
+
vbus-supply = <&vdd_5v0_rtl>;
750
+
mode = "host";
751
+
};
752
+
753
+
usb2-2 {
754
+
vbus-supply = <&vdd_usb_vbus>;
755
+
mode = "host";
756
+
};
757
+
758
+
usb2-3 {
759
+
mode = "host";
760
+
};
761
+
762
+
hsic-0 {
763
+
status = "disabled";
764
+
};
765
+
766
+
hsic-1 {
767
+
status = "disabled";
768
+
};
769
+
770
+
usb3-0 {
771
+
nvidia,usb2-companion = <1>;
772
+
};
773
+
774
+
usb3-1 {
775
+
nvidia,usb2-companion = <2>;
776
+
};
777
+
778
+
usb3-2 {
779
+
status = "disabled";
780
+
};
781
+
782
+
usb3-3 {
783
+
status = "disabled";
784
+
};
785
+
};
786
+
};
+3
Documentation/devicetree/bindings/phy/qcom,msm8996-qmp-ufs-phy.yaml
+3
Documentation/devicetree/bindings/phy/qcom,msm8996-qmp-ufs-phy.yaml
+3
Documentation/devicetree/bindings/phy/qcom,msm8996-qmp-usb3-phy.yaml
+3
Documentation/devicetree/bindings/phy/qcom,msm8996-qmp-usb3-phy.yaml
···
30
30
- qcom,sdm845-qmp-usb3-uni-phy
31
31
- qcom,sdx55-qmp-usb3-uni-phy
32
32
- qcom,sdx65-qmp-usb3-uni-phy
33
+
- qcom,sm6115-qmp-usb3-phy
33
34
- qcom,sm8150-qmp-usb3-phy
34
35
- qcom,sm8150-qmp-usb3-uni-phy
35
36
- qcom,sm8250-qmp-usb3-phy
···
254
253
contains:
255
254
enum:
256
255
- qcom,qcm2290-qmp-usb3-phy
256
+
- qcom,sm6115-qmp-usb3-phy
257
257
then:
258
258
properties:
259
259
clocks:
···
323
321
- qcom,sc8180x-qmp-usb3-phy
324
322
- qcom,sdx55-qmp-usb3-uni-phy
325
323
- qcom,sdx65-qmp-usb3-uni-phy
324
+
- qcom,sm6115-qmp-usb3-phy
326
325
- qcom,sm8150-qmp-usb3-uni-phy
327
326
- qcom,sm8250-qmp-usb3-phy
328
327
then:
+86
Documentation/devicetree/bindings/phy/qcom,pcie2-phy.yaml
+86
Documentation/devicetree/bindings/phy/qcom,pcie2-phy.yaml
···
1
+
# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
2
+
%YAML 1.2
3
+
---
4
+
$id: http://devicetree.org/schemas/phy/qcom,pcie2-phy.yaml#
5
+
$schema: http://devicetree.org/meta-schemas/core.yaml#
6
+
7
+
title: Qualcomm PCIe2 PHY controller
8
+
9
+
maintainers:
10
+
- Vinod Koul <vkoul@kernel.org>
11
+
12
+
description:
13
+
The Qualcomm PCIe2 PHY is a Synopsys based phy found in a number of Qualcomm
14
+
platforms.
15
+
16
+
properties:
17
+
compatible:
18
+
items:
19
+
- const: qcom,qcs404-pcie2-phy
20
+
- const: qcom,pcie2-phy
21
+
22
+
reg:
23
+
items:
24
+
- description: PHY register set
25
+
26
+
clocks:
27
+
items:
28
+
- description: a clock-specifier pair for the "pipe" clock
29
+
30
+
clock-output-names:
31
+
maxItems: 1
32
+
33
+
"#clock-cells":
34
+
const: 0
35
+
36
+
"#phy-cells":
37
+
const: 0
38
+
39
+
vdda-vp-supply:
40
+
description: low voltage regulator
41
+
42
+
vdda-vph-supply:
43
+
description: high voltage regulator
44
+
45
+
resets:
46
+
maxItems: 2
47
+
48
+
reset-names:
49
+
items:
50
+
- const: phy
51
+
- const: pipe
52
+
53
+
required:
54
+
- compatible
55
+
- reg
56
+
- clocks
57
+
- clock-output-names
58
+
- "#clock-cells"
59
+
- "#phy-cells"
60
+
- vdda-vp-supply
61
+
- vdda-vph-supply
62
+
- resets
63
+
- reset-names
64
+
65
+
additionalProperties: false
66
+
67
+
examples:
68
+
- |
69
+
#include <dt-bindings/clock/qcom,gcc-qcs404.h>
70
+
phy@7786000 {
71
+
compatible = "qcom,qcs404-pcie2-phy", "qcom,pcie2-phy";
72
+
reg = <0x07786000 0xb8>;
73
+
74
+
clocks = <&gcc GCC_PCIE_0_PIPE_CLK>;
75
+
resets = <&gcc GCC_PCIEPHY_0_PHY_BCR>,
76
+
<&gcc GCC_PCIE_0_PIPE_ARES>;
77
+
reset-names = "phy", "pipe";
78
+
79
+
vdda-vp-supply = <&vreg_l3_1p05>;
80
+
vdda-vph-supply = <&vreg_l5_1p8>;
81
+
82
+
clock-output-names = "pcie_0_pipe_clk";
83
+
#clock-cells = <0>;
84
+
#phy-cells = <0>;
85
+
};
86
+
...
+79
-69
Documentation/devicetree/bindings/phy/qcom,qusb2-phy.yaml
+79
-69
Documentation/devicetree/bindings/phy/qcom,qusb2-phy.yaml
···
82
82
Phandle to TCSR syscon register region.
83
83
$ref: /schemas/types.yaml#/definitions/phandle
84
84
85
-
if:
86
-
properties:
87
-
compatible:
88
-
contains:
89
-
const: qcom,qusb2-v2-phy
90
-
then:
91
-
properties:
92
-
qcom,imp-res-offset-value:
93
-
description:
94
-
It is a 6 bit value that specifies offset to be
95
-
added to PHY refgen RESCODE via IMP_CTRL1 register. It is a PHY
96
-
tuning parameter that may vary for different boards of same SOC.
97
-
$ref: /schemas/types.yaml#/definitions/uint32
98
-
minimum: 0
99
-
maximum: 63
100
-
default: 0
85
+
qcom,imp-res-offset-value:
86
+
description:
87
+
It is a 6 bit value that specifies offset to be
88
+
added to PHY refgen RESCODE via IMP_CTRL1 register. It is a PHY
89
+
tuning parameter that may vary for different boards of same SOC.
90
+
$ref: /schemas/types.yaml#/definitions/uint32
91
+
minimum: 0
92
+
maximum: 63
93
+
default: 0
101
94
102
-
qcom,bias-ctrl-value:
103
-
description:
104
-
It is a 6 bit value that specifies bias-ctrl-value. It is a PHY
105
-
tuning parameter that may vary for different boards of same SOC.
106
-
$ref: /schemas/types.yaml#/definitions/uint32
107
-
minimum: 0
108
-
maximum: 63
109
-
default: 32
95
+
qcom,bias-ctrl-value:
96
+
description:
97
+
It is a 6 bit value that specifies bias-ctrl-value. It is a PHY
98
+
tuning parameter that may vary for different boards of same SOC.
99
+
$ref: /schemas/types.yaml#/definitions/uint32
100
+
minimum: 0
101
+
maximum: 63
102
+
default: 32
110
103
111
-
qcom,charge-ctrl-value:
112
-
description:
113
-
It is a 2 bit value that specifies charge-ctrl-value. It is a PHY
114
-
tuning parameter that may vary for different boards of same SOC.
115
-
$ref: /schemas/types.yaml#/definitions/uint32
116
-
minimum: 0
117
-
maximum: 3
118
-
default: 0
104
+
qcom,charge-ctrl-value:
105
+
description:
106
+
It is a 2 bit value that specifies charge-ctrl-value. It is a PHY
107
+
tuning parameter that may vary for different boards of same SOC.
108
+
$ref: /schemas/types.yaml#/definitions/uint32
109
+
minimum: 0
110
+
maximum: 3
111
+
default: 0
119
112
120
-
qcom,hstx-trim-value:
121
-
description:
122
-
It is a 4 bit value that specifies tuning for HSTX
123
-
output current.
124
-
Possible range is - 15mA to 24mA (stepsize of 600 uA).
125
-
See dt-bindings/phy/phy-qcom-qusb2.h for applicable values.
126
-
$ref: /schemas/types.yaml#/definitions/uint32
127
-
minimum: 0
128
-
maximum: 15
129
-
default: 3
113
+
qcom,hstx-trim-value:
114
+
description:
115
+
It is a 4 bit value that specifies tuning for HSTX
116
+
output current.
117
+
Possible range is - 15mA to 24mA (stepsize of 600 uA).
118
+
See dt-bindings/phy/phy-qcom-qusb2.h for applicable values.
119
+
$ref: /schemas/types.yaml#/definitions/uint32
120
+
minimum: 0
121
+
maximum: 15
122
+
default: 3
130
123
131
-
qcom,preemphasis-level:
132
-
description:
133
-
It is a 2 bit value that specifies pre-emphasis level.
134
-
Possible range is 0 to 15% (stepsize of 5%).
135
-
See dt-bindings/phy/phy-qcom-qusb2.h for applicable values.
136
-
$ref: /schemas/types.yaml#/definitions/uint32
137
-
minimum: 0
138
-
maximum: 3
139
-
default: 2
124
+
qcom,preemphasis-level:
125
+
description:
126
+
It is a 2 bit value that specifies pre-emphasis level.
127
+
Possible range is 0 to 15% (stepsize of 5%).
128
+
See dt-bindings/phy/phy-qcom-qusb2.h for applicable values.
129
+
$ref: /schemas/types.yaml#/definitions/uint32
130
+
minimum: 0
131
+
maximum: 3
132
+
default: 2
140
133
141
-
qcom,preemphasis-width:
142
-
description:
143
-
It is a 1 bit value that specifies how long the HSTX
144
-
pre-emphasis (specified using qcom,preemphasis-level) must be in
145
-
effect. Duration could be half-bit of full-bit.
146
-
See dt-bindings/phy/phy-qcom-qusb2.h for applicable values.
147
-
$ref: /schemas/types.yaml#/definitions/uint32
148
-
minimum: 0
149
-
maximum: 1
150
-
default: 0
134
+
qcom,preemphasis-width:
135
+
description:
136
+
It is a 1 bit value that specifies how long the HSTX
137
+
pre-emphasis (specified using qcom,preemphasis-level) must be in
138
+
effect. Duration could be half-bit of full-bit.
139
+
See dt-bindings/phy/phy-qcom-qusb2.h for applicable values.
140
+
$ref: /schemas/types.yaml#/definitions/uint32
141
+
minimum: 0
142
+
maximum: 1
143
+
default: 0
151
144
152
-
qcom,hsdisc-trim-value:
153
-
description:
154
-
It is a 2 bit value tuning parameter that control disconnect
155
-
threshold and may vary for different boards of same SOC.
156
-
$ref: /schemas/types.yaml#/definitions/uint32
157
-
minimum: 0
158
-
maximum: 3
159
-
default: 0
145
+
qcom,hsdisc-trim-value:
146
+
description:
147
+
It is a 2 bit value tuning parameter that control disconnect
148
+
threshold and may vary for different boards of same SOC.
149
+
$ref: /schemas/types.yaml#/definitions/uint32
150
+
minimum: 0
151
+
maximum: 3
152
+
default: 0
160
153
161
154
required:
162
155
- compatible
···
161
168
- vdda-pll-supply
162
169
- vdda-phy-dpdm-supply
163
170
- resets
171
+
172
+
allOf:
173
+
- if:
174
+
not:
175
+
properties:
176
+
compatible:
177
+
contains:
178
+
const: qcom,qusb2-v2-phy
179
+
then:
180
+
properties:
181
+
qcom,imp-res-offset-value: false
182
+
qcom,bias-ctrl-value: false
183
+
qcom,charge-ctrl-value: false
184
+
qcom,hstx-trim-value: false
185
+
qcom,preemphasis-level: false
186
+
qcom,preemphasis-width: false
187
+
qcom,hsdisc-trim-value: false
164
188
165
189
additionalProperties: false
166
190
+73
-16
Documentation/devicetree/bindings/phy/qcom,sc7180-qmp-usb3-dp-phy.yaml
+73
-16
Documentation/devicetree/bindings/phy/qcom,sc7180-qmp-usb3-dp-phy.yaml
···
19
19
20
20
properties:
21
21
compatible:
22
-
enum:
23
-
- qcom,sc7180-qmp-usb3-dp-phy
24
-
- qcom,sc7280-qmp-usb3-dp-phy
25
-
- qcom,sc8180x-qmp-usb3-dp-phy
26
-
- qcom,sdm845-qmp-usb3-dp-phy
27
-
- qcom,sm8250-qmp-usb3-dp-phy
22
+
oneOf:
23
+
- enum:
24
+
- qcom,sc7180-qmp-usb3-dp-phy
25
+
- qcom,sc8180x-qmp-usb3-dp-phy
26
+
- qcom,sdm845-qmp-usb3-dp-phy
27
+
- qcom,sm8250-qmp-usb3-dp-phy
28
+
- items:
29
+
- enum:
30
+
- qcom,sc7280-qmp-usb3-dp-phy
31
+
- const: qcom,sm8250-qmp-usb3-dp-phy
32
+
28
33
reg:
29
34
items:
30
35
- description: Address and length of PHY's USB serdes block.
···
51
46
ranges: true
52
47
53
48
clocks:
54
-
items:
55
-
- description: Phy aux clock.
56
-
- description: Phy config clock.
57
-
- description: 19.2 MHz ref clk.
58
-
- description: Phy common block aux clock.
49
+
minItems: 3
50
+
maxItems: 4
59
51
60
52
clock-names:
61
-
items:
62
-
- const: aux
63
-
- const: cfg_ahb
64
-
- const: ref
65
-
- const: com_aux
53
+
minItems: 3
54
+
maxItems: 4
66
55
67
56
power-domains:
68
57
maxItems: 1
···
164
165
- reset-names
165
166
- vdda-phy-supply
166
167
- vdda-pll-supply
168
+
169
+
allOf:
170
+
- if:
171
+
properties:
172
+
compatible:
173
+
enum:
174
+
- qcom,sc7180-qmp-usb3-dp-phy
175
+
- qcom,sdm845-qmp-usb3-dp-phy
176
+
then:
177
+
properties:
178
+
clocks:
179
+
items:
180
+
- description: Phy aux clock
181
+
- description: Phy config clock
182
+
- description: 19.2 MHz ref clk
183
+
- description: Phy common block aux clock
184
+
clock-names:
185
+
items:
186
+
- const: aux
187
+
- const: cfg_ahb
188
+
- const: ref
189
+
- const: com_aux
190
+
191
+
- if:
192
+
properties:
193
+
compatible:
194
+
enum:
195
+
- qcom,sc8180x-qmp-usb3-dp-phy
196
+
then:
197
+
properties:
198
+
clocks:
199
+
items:
200
+
- description: Phy aux clock
201
+
- description: 19.2 MHz ref clk
202
+
- description: Phy common block aux clock
203
+
clock-names:
204
+
items:
205
+
- const: aux
206
+
- const: ref
207
+
- const: com_aux
208
+
209
+
- if:
210
+
properties:
211
+
compatible:
212
+
enum:
213
+
- qcom,sm8250-qmp-usb3-dp-phy
214
+
then:
215
+
properties:
216
+
clocks:
217
+
items:
218
+
- description: Phy aux clock
219
+
- description: Board XO source
220
+
- description: Phy common block aux clock
221
+
clock-names:
222
+
items:
223
+
- const: aux
224
+
- const: ref_clk_src
225
+
- const: com_aux
167
226
168
227
additionalProperties: false
169
228
+51
-1
Documentation/devicetree/bindings/phy/qcom,sc8280xp-qmp-pcie-phy.yaml
+51
-1
Documentation/devicetree/bindings/phy/qcom,sc8280xp-qmp-pcie-phy.yaml
···
19
19
- qcom,sc8280xp-qmp-gen3x1-pcie-phy
20
20
- qcom,sc8280xp-qmp-gen3x2-pcie-phy
21
21
- qcom,sc8280xp-qmp-gen3x4-pcie-phy
22
+
- qcom,sm8350-qmp-gen3x1-pcie-phy
23
+
- qcom,sm8550-qmp-gen3x2-pcie-phy
24
+
- qcom,sm8550-qmp-gen4x2-pcie-phy
22
25
23
26
reg:
24
27
minItems: 1
25
28
maxItems: 2
26
29
27
30
clocks:
31
+
minItems: 5
28
32
maxItems: 6
29
33
30
34
clock-names:
35
+
minItems: 5
31
36
items:
32
37
- const: aux
33
38
- const: cfg_ahb
···
45
40
maxItems: 1
46
41
47
42
resets:
48
-
maxItems: 1
43
+
minItems: 1
44
+
maxItems: 2
49
45
50
46
reset-names:
47
+
minItems: 1
51
48
items:
52
49
- const: phy
50
+
- const: phy_nocsr
53
51
54
52
vdda-phy-supply: true
55
53
56
54
vdda-pll-supply: true
55
+
56
+
vdda-qref-supply: true
57
57
58
58
qcom,4ln-config-sel:
59
59
description: PCIe 4-lane configuration
···
112
102
else:
113
103
properties:
114
104
reg:
105
+
maxItems: 1
106
+
107
+
- if:
108
+
properties:
109
+
compatible:
110
+
contains:
111
+
enum:
112
+
- qcom,sm8350-qmp-gen3x1-pcie-phy
113
+
- qcom,sm8550-qmp-gen3x2-pcie-phy
114
+
- qcom,sm8550-qmp-gen4x2-pcie-phy
115
+
then:
116
+
properties:
117
+
clocks:
118
+
maxItems: 5
119
+
clock-names:
120
+
maxItems: 5
121
+
else:
122
+
properties:
123
+
clocks:
124
+
minItems: 6
125
+
clock-names:
126
+
minItems: 6
127
+
128
+
- if:
129
+
properties:
130
+
compatible:
131
+
contains:
132
+
enum:
133
+
- qcom,sm8550-qmp-gen4x2-pcie-phy
134
+
then:
135
+
properties:
136
+
resets:
137
+
minItems: 2
138
+
reset-names:
139
+
minItems: 2
140
+
else:
141
+
properties:
142
+
resets:
143
+
maxItems: 1
144
+
reset-names:
115
145
maxItems: 1
116
146
117
147
examples:
+5
Documentation/devicetree/bindings/phy/qcom,sc8280xp-qmp-ufs-phy.yaml
+5
Documentation/devicetree/bindings/phy/qcom,sc8280xp-qmp-ufs-phy.yaml
···
17
17
compatible:
18
18
enum:
19
19
- qcom,sc8280xp-qmp-ufs-phy
20
+
- qcom,sm6125-qmp-ufs-phy
21
+
- qcom,sm8550-qmp-ufs-phy
20
22
21
23
reg:
22
24
maxItems: 1
···
44
42
vdda-phy-supply: true
45
43
46
44
vdda-pll-supply: true
45
+
46
+
"#clock-cells":
47
+
const: 1
47
48
48
49
"#phy-cells":
49
50
const: 0
+4
Documentation/devicetree/bindings/phy/qcom,sc8280xp-qmp-usb43dp-phy.yaml
+4
Documentation/devicetree/bindings/phy/qcom,sc8280xp-qmp-usb43dp-phy.yaml
+79
Documentation/devicetree/bindings/phy/qcom,snps-eusb2-phy.yaml
+79
Documentation/devicetree/bindings/phy/qcom,snps-eusb2-phy.yaml
···
1
+
# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
2
+
%YAML 1.2
3
+
---
4
+
$id: http://devicetree.org/schemas/phy/qcom,snps-eusb2-phy.yaml#
5
+
$schema: http://devicetree.org/meta-schemas/core.yaml#
6
+
7
+
title: Qualcomm SNPS eUSB2 phy controller
8
+
9
+
maintainers:
10
+
- Abel Vesa <abel.vesa@linaro.org>
11
+
12
+
description:
13
+
eUSB2 controller supports LS/FS/HS usb connectivity on Qualcomm chipsets.
14
+
15
+
properties:
16
+
compatible:
17
+
const: qcom,sm8550-snps-eusb2-phy
18
+
19
+
reg:
20
+
maxItems: 1
21
+
22
+
"#phy-cells":
23
+
const: 0
24
+
25
+
clocks:
26
+
items:
27
+
- description: ref
28
+
29
+
clock-names:
30
+
items:
31
+
- const: ref
32
+
33
+
resets:
34
+
maxItems: 1
35
+
36
+
phys:
37
+
maxItems: 1
38
+
description:
39
+
Phandle to eUSB2 to USB 2.0 repeater
40
+
41
+
vdd-supply:
42
+
description:
43
+
Phandle to 0.88V regulator supply to PHY digital circuit.
44
+
45
+
vdda12-supply:
46
+
description:
47
+
Phandle to 1.2V regulator supply to PHY refclk pll block.
48
+
49
+
required:
50
+
- compatible
51
+
- reg
52
+
- "#phy-cells"
53
+
- clocks
54
+
- clock-names
55
+
- vdd-supply
56
+
- vdda12-supply
57
+
- resets
58
+
59
+
additionalProperties: false
60
+
61
+
examples:
62
+
- |
63
+
#include <dt-bindings/clock/qcom,sm8550-gcc.h>
64
+
#include <dt-bindings/clock/qcom,rpmh.h>
65
+
#include <dt-bindings/clock/qcom,sm8550-tcsr.h>
66
+
67
+
usb_1_hsphy: phy@88e3000 {
68
+
compatible = "qcom,sm8550-snps-eusb2-phy";
69
+
reg = <0x88e3000 0x154>;
70
+
#phy-cells = <0>;
71
+
72
+
clocks = <&tcsrcc TCSR_USB2_CLKREF_EN>;
73
+
clock-names = "ref";
74
+
75
+
vdd-supply = <&vreg_l1e_0p88>;
76
+
vdda12-supply = <&vreg_l3e_1p2>;
77
+
78
+
resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>;
79
+
};
+52
Documentation/devicetree/bindings/phy/qcom,snps-eusb2-repeater.yaml
+52
Documentation/devicetree/bindings/phy/qcom,snps-eusb2-repeater.yaml
···
1
+
# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
2
+
%YAML 1.2
3
+
---
4
+
$id: http://devicetree.org/schemas/phy/qcom,snps-eusb2-repeater.yaml#
5
+
$schema: http://devicetree.org/meta-schemas/core.yaml#
6
+
7
+
title: Qualcomm Synopsis eUSB2 to USB 2.0 repeater
8
+
9
+
maintainers:
10
+
- Abel Vesa <abel.vesa@linaro.org>
11
+
12
+
description:
13
+
eUSB2 repeater converts between eUSB2 and USB 2.0 signaling levels and
14
+
allows a eUSB2 PHY to connect to legacy USB 2.0 products
15
+
16
+
properties:
17
+
compatible:
18
+
const: qcom,pm8550b-eusb2-repeater
19
+
20
+
reg:
21
+
maxItems: 1
22
+
23
+
"#phy-cells":
24
+
const: 0
25
+
26
+
vdd18-supply: true
27
+
28
+
vdd3-supply: true
29
+
30
+
required:
31
+
- compatible
32
+
- reg
33
+
- "#phy-cells"
34
+
35
+
additionalProperties: false
36
+
37
+
examples:
38
+
- |
39
+
#include <dt-bindings/spmi/spmi.h>
40
+
41
+
pmic@7 {
42
+
reg = <0x7 SPMI_USID>;
43
+
#address-cells = <1>;
44
+
#size-cells = <0>;
45
+
46
+
pm8550b_eusb2_repeater: phy@fd00 {
47
+
compatible = "qcom,pm8550b-eusb2-repeater";
48
+
reg = <0xfd00>;
49
+
#phy-cells = <0>;
50
+
};
51
+
};
52
+
...
-65
Documentation/devicetree/bindings/phy/qcom,usb-hsic-phy.txt
-65
Documentation/devicetree/bindings/phy/qcom,usb-hsic-phy.txt
···
1
-
Qualcomm's USB HSIC PHY
2
-
3
-
PROPERTIES
4
-
5
-
- compatible:
6
-
Usage: required
7
-
Value type: <string>
8
-
Definition: Should contain "qcom,usb-hsic-phy" and more specifically one of the
9
-
following:
10
-
11
-
"qcom,usb-hsic-phy-mdm9615"
12
-
"qcom,usb-hsic-phy-msm8974"
13
-
14
-
- #phy-cells:
15
-
Usage: required
16
-
Value type: <u32>
17
-
Definition: Should contain 0
18
-
19
-
- clocks:
20
-
Usage: required
21
-
Value type: <prop-encoded-array>
22
-
Definition: Should contain clock specifier for phy, calibration and
23
-
a calibration sleep clock
24
-
25
-
- clock-names:
26
-
Usage: required
27
-
Value type: <stringlist>
28
-
Definition: Should contain "phy, "cal" and "cal_sleep"
29
-
30
-
- pinctrl-names:
31
-
Usage: required
32
-
Value type: <stringlist>
33
-
Definition: Should contain "init" and "default" in that order
34
-
35
-
- pinctrl-0:
36
-
Usage: required
37
-
Value type: <prop-encoded-array>
38
-
Definition: List of pinctrl settings to apply to keep HSIC pins in a glitch
39
-
free state
40
-
41
-
- pinctrl-1:
42
-
Usage: required
43
-
Value type: <prop-encoded-array>
44
-
Definition: List of pinctrl settings to apply to mux out the HSIC pins
45
-
46
-
EXAMPLE
47
-
48
-
usb-controller {
49
-
ulpi {
50
-
phy {
51
-
compatible = "qcom,usb-hsic-phy-msm8974",
52
-
"qcom,usb-hsic-phy";
53
-
#phy-cells = <0>;
54
-
pinctrl-names = "init", "default";
55
-
pinctrl-0 = <&hsic_sleep>;
56
-
pinctrl-1 = <&hsic_default>;
57
-
clocks = <&gcc GCC_USB_HSIC_CLK>,
58
-
<&gcc GCC_USB_HSIC_IO_CAL_CLK>,
59
-
<&gcc GCC_USB_HSIC_IO_CAL_SLEEP_CLK>;
60
-
clock-names = "phy", "cal", "cal_sleep";
61
-
assigned-clocks = <&gcc GCC_USB_HSIC_IO_CAL_CLK>;
62
-
assigned-clock-rates = <960000>;
63
-
};
64
-
};
65
-
};
+67
Documentation/devicetree/bindings/phy/qcom,usb-hsic-phy.yaml
+67
Documentation/devicetree/bindings/phy/qcom,usb-hsic-phy.yaml
···
1
+
# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
2
+
%YAML 1.2
3
+
---
4
+
$id: http://devicetree.org/schemas/phy/qcom,usb-hsic-phy.yaml#
5
+
$schema: http://devicetree.org/meta-schemas/core.yaml#
6
+
7
+
title: Qualcomm USB HSIC PHY Controller
8
+
9
+
maintainers:
10
+
- Bjorn Andersson <andersson@kernel.org>
11
+
- Vinod Koul <vkoul@kernel.org>
12
+
13
+
properties:
14
+
compatible:
15
+
items:
16
+
- enum:
17
+
- qcom,usb-hsic-phy-mdm9615
18
+
- qcom,usb-hsic-phy-msm8974
19
+
- const: qcom,usb-hsic-phy
20
+
21
+
clocks:
22
+
maxItems: 3
23
+
24
+
clock-names:
25
+
items:
26
+
- const: phy
27
+
- const: cal
28
+
- const: cal_sleep
29
+
30
+
"#phy-cells":
31
+
const: 0
32
+
33
+
pinctrl-0: true
34
+
pinctrl-1: true
35
+
36
+
pinctrl-names:
37
+
items:
38
+
- const: init
39
+
- const: default
40
+
41
+
required:
42
+
- compatible
43
+
- clocks
44
+
- clock-names
45
+
- "#phy-cells"
46
+
- pinctrl-0
47
+
- pinctrl-1
48
+
- pinctrl-names
49
+
50
+
additionalProperties: false
51
+
52
+
examples:
53
+
- |
54
+
#include <dt-bindings/clock/qcom,gcc-msm8974.h>
55
+
56
+
phy {
57
+
compatible = "qcom,usb-hsic-phy-msm8974",
58
+
"qcom,usb-hsic-phy";
59
+
clocks = <&gcc GCC_USB_HSIC_CLK>,
60
+
<&gcc GCC_USB_HSIC_IO_CAL_CLK>,
61
+
<&gcc GCC_USB_HSIC_IO_CAL_SLEEP_CLK>;
62
+
clock-names = "phy", "cal", "cal_sleep";
63
+
#phy-cells = <0>;
64
+
pinctrl-names = "init", "default";
65
+
pinctrl-0 = <&hsic_sleep>;
66
+
pinctrl-1 = <&hsic_default>;
67
+
};
+20
-13
Documentation/devicetree/bindings/phy/qcom,usb-snps-femto-v2.yaml
+20
-13
Documentation/devicetree/bindings/phy/qcom,usb-snps-femto-v2.yaml
···
14
14
15
15
properties:
16
16
compatible:
17
-
enum:
18
-
- qcom,usb-snps-hs-5nm-phy
19
-
- qcom,usb-snps-hs-7nm-phy
20
-
- qcom,sc7280-usb-hs-phy
21
-
- qcom,sc8180x-usb-hs-phy
22
-
- qcom,sc8280xp-usb-hs-phy
23
-
- qcom,sm6375-usb-hs-phy
24
-
- qcom,sm8150-usb-hs-phy
25
-
- qcom,sm8250-usb-hs-phy
26
-
- qcom,sm8350-usb-hs-phy
27
-
- qcom,sm8450-usb-hs-phy
28
-
- qcom,usb-snps-femto-v2-phy
17
+
oneOf:
18
+
- enum:
19
+
- qcom,sc8180x-usb-hs-phy
20
+
- qcom,usb-snps-femto-v2-phy
21
+
- items:
22
+
- enum:
23
+
- qcom,sc8280xp-usb-hs-phy
24
+
- const: qcom,usb-snps-hs-5nm-phy
25
+
- items:
26
+
- enum:
27
+
- qcom,sc7280-usb-hs-phy
28
+
- qcom,sdx55-usb-hs-phy
29
+
- qcom,sdx65-usb-hs-phy
30
+
- qcom,sm6375-usb-hs-phy
31
+
- qcom,sm8150-usb-hs-phy
32
+
- qcom,sm8250-usb-hs-phy
33
+
- qcom,sm8350-usb-hs-phy
34
+
- qcom,sm8450-usb-hs-phy
35
+
- const: qcom,usb-snps-hs-7nm-phy
29
36
30
37
reg:
31
38
maxItems: 1
···
167
160
#include <dt-bindings/clock/qcom,rpmh.h>
168
161
#include <dt-bindings/clock/qcom,gcc-sm8150.h>
169
162
phy@88e2000 {
170
-
compatible = "qcom,sm8150-usb-hs-phy";
163
+
compatible = "qcom,sm8150-usb-hs-phy", "qcom,usb-snps-hs-7nm-phy";
171
164
reg = <0x088e2000 0x400>;
172
165
#phy-cells = <0>;
173
166
-42
Documentation/devicetree/bindings/phy/qcom-pcie2-phy.txt
-42
Documentation/devicetree/bindings/phy/qcom-pcie2-phy.txt
···
1
-
Qualcomm PCIe2 PHY controller
2
-
=============================
3
-
4
-
The Qualcomm PCIe2 PHY is a Synopsys based phy found in a number of Qualcomm
5
-
platforms.
6
-
7
-
Required properties:
8
-
- compatible: compatible list, should be:
9
-
"qcom,qcs404-pcie2-phy", "qcom,pcie2-phy"
10
-
11
-
- reg: offset and length of the PHY register set.
12
-
- #phy-cells: must be 0.
13
-
14
-
- clocks: a clock-specifier pair for the "pipe" clock
15
-
16
-
- vdda-vp-supply: phandle to low voltage regulator
17
-
- vdda-vph-supply: phandle to high voltage regulator
18
-
19
-
- resets: reset-specifier pairs for the "phy" and "pipe" resets
20
-
- reset-names: list of resets, should contain:
21
-
"phy" and "pipe"
22
-
23
-
- clock-output-names: name of the outgoing clock signal from the PHY PLL
24
-
- #clock-cells: must be 0
25
-
26
-
Example:
27
-
phy@7786000 {
28
-
compatible = "qcom,qcs404-pcie2-phy", "qcom,pcie2-phy";
29
-
reg = <0x07786000 0xb8>;
30
-
31
-
clocks = <&gcc GCC_PCIE_0_PIPE_CLK>;
32
-
resets = <&gcc GCC_PCIEPHY_0_PHY_BCR>,
33
-
<&gcc GCC_PCIE_0_PIPE_ARES>;
34
-
reset-names = "phy", "pipe";
35
-
36
-
vdda-vp-supply = <&vreg_l3_1p05>;
37
-
vdda-vph-supply = <&vreg_l5_1p8>;
38
-
39
-
clock-output-names = "pcie_0_pipe_clk";
40
-
#clock-cells = <0>;
41
-
#phy-cells = <0>;
42
-
};
+1
Documentation/devicetree/bindings/phy/ti,tcan104x-can.yaml
+1
Documentation/devicetree/bindings/phy/ti,tcan104x-can.yaml
+14
-10
Documentation/driver-api/phy/phy.rst
+14
-10
Documentation/driver-api/phy/phy.rst
···
103
103
::
104
104
105
105
struct phy *phy_get(struct device *dev, const char *string);
106
-
struct phy *phy_optional_get(struct device *dev, const char *string);
107
106
struct phy *devm_phy_get(struct device *dev, const char *string);
108
107
struct phy *devm_phy_optional_get(struct device *dev,
109
108
const char *string);
109
+
struct phy *devm_of_phy_get(struct device *dev, struct device_node *np,
110
+
const char *con_id);
111
+
struct phy *devm_of_phy_optional_get(struct device *dev,
112
+
struct device_node *np,
113
+
const char *con_id);
110
114
struct phy *devm_of_phy_get_by_index(struct device *dev,
111
115
struct device_node *np,
112
116
int index);
113
117
114
-
phy_get, phy_optional_get, devm_phy_get and devm_phy_optional_get can
115
-
be used to get the PHY. In the case of dt boot, the string arguments
118
+
phy_get, devm_phy_get and devm_phy_optional_get can be used to get the PHY.
119
+
In the case of dt boot, the string arguments
116
120
should contain the phy name as given in the dt data and in the case of
117
121
non-dt boot, it should contain the label of the PHY. The two
118
122
devm_phy_get associates the device with the PHY using devres on
119
123
successful PHY get. On driver detach, release function is invoked on
120
-
the devres data and devres data is freed. phy_optional_get and
121
-
devm_phy_optional_get should be used when the phy is optional. These
122
-
two functions will never return -ENODEV, but instead returns NULL when
123
-
the phy cannot be found.Some generic drivers, such as ehci, may use multiple
124
-
phys and for such drivers referencing phy(s) by name(s) does not make sense. In
125
-
this case, devm_of_phy_get_by_index can be used to get a phy reference based on
126
-
the index.
124
+
the devres data and devres data is freed.
125
+
The _optional_get variants should be used when the phy is optional. These
126
+
functions will never return -ENODEV, but instead return NULL when
127
+
the phy cannot be found.
128
+
Some generic drivers, such as ehci, may use multiple phys. In this case,
129
+
devm_of_phy_get or devm_of_phy_get_by_index can be used to get a phy
130
+
reference based on name or index.
127
131
128
132
It should be noted that NULL is a valid phy reference. All phy
129
133
consumer calls on the NULL phy become NOPs. That is the release calls,
+4
-5
drivers/net/ethernet/freescale/fman/fman_memac.c
+4
-5
drivers/net/ethernet/freescale/fman/fman_memac.c
···
1155
1155
else
1156
1156
memac->sgmii_pcs = pcs;
1157
1157
1158
-
memac->serdes = devm_of_phy_get(mac_dev->dev, mac_node, "serdes");
1159
-
err = PTR_ERR(memac->serdes);
1160
-
if (err == -ENODEV || err == -ENOSYS) {
1158
+
memac->serdes = devm_of_phy_optional_get(mac_dev->dev, mac_node,
1159
+
"serdes");
1160
+
if (!memac->serdes) {
1161
1161
dev_dbg(mac_dev->dev, "could not get (optional) serdes\n");
1162
-
memac->serdes = NULL;
1163
1162
} else if (IS_ERR(memac->serdes)) {
1164
-
dev_err_probe(mac_dev->dev, err, "could not get serdes\n");
1163
+
err = PTR_ERR(memac->serdes);
1165
1164
goto _return_fm_mac_free;
1166
1165
}
1167
1166
+2
-3
drivers/net/ethernet/microchip/lan966x/lan966x_main.c
+2
-3
drivers/net/ethernet/microchip/lan966x/lan966x_main.c
···
1154
1154
lan966x->ports[p]->config.portmode = phy_mode;
1155
1155
lan966x->ports[p]->fwnode = fwnode_handle_get(portnp);
1156
1156
1157
-
serdes = devm_of_phy_get(lan966x->dev, to_of_node(portnp), NULL);
1158
-
if (PTR_ERR(serdes) == -ENODEV)
1159
-
serdes = NULL;
1157
+
serdes = devm_of_phy_optional_get(lan966x->dev,
1158
+
to_of_node(portnp), NULL);
1160
1159
if (IS_ERR(serdes)) {
1161
1160
err = PTR_ERR(serdes);
1162
1161
goto cleanup_ports;
+1
-4
drivers/pci/controller/pci-tegra.c
+1
-4
drivers/pci/controller/pci-tegra.c
+24
-35
drivers/phy/allwinner/phy-sun4i-usb.c
+24
-35
drivers/phy/allwinner/phy-sun4i-usb.c
···
99
99
#define DEBOUNCE_TIME msecs_to_jiffies(50)
100
100
#define POLL_TIME msecs_to_jiffies(250)
101
101
102
-
enum sun4i_usb_phy_type {
103
-
sun4i_a10_phy,
104
-
sun6i_a31_phy,
105
-
sun8i_a33_phy,
106
-
sun8i_a83t_phy,
107
-
sun8i_h3_phy,
108
-
sun8i_r40_phy,
109
-
sun8i_v3s_phy,
110
-
sun50i_a64_phy,
111
-
sun50i_h6_phy,
112
-
};
113
-
114
102
struct sun4i_usb_phy_cfg {
115
103
int num_phys;
116
104
int hsic_index;
117
-
enum sun4i_usb_phy_type type;
118
105
u32 disc_thresh;
119
106
u32 hci_phy_ctl_clear;
120
107
u8 phyctl_offset;
121
108
bool dedicated_clocks;
122
109
bool phy0_dual_route;
123
110
bool needs_phy2_siddq;
111
+
bool siddq_in_base;
112
+
bool poll_vbusen;
124
113
int missing_phys;
125
114
};
126
115
···
241
252
SUNXI_AHB_INCRX_ALIGN_EN | SUNXI_ULPI_BYPASS_EN;
242
253
243
254
/* A83T USB2 is HSIC */
244
-
if (phy_data->cfg->type == sun8i_a83t_phy && phy->index == 2)
255
+
if (phy_data->cfg->hsic_index &&
256
+
phy->index == phy_data->cfg->hsic_index)
245
257
bits |= SUNXI_EHCI_HS_FORCE | SUNXI_HSIC_CONNECT_INT |
246
258
SUNXI_HSIC;
247
259
···
330
340
writel(val, phy->pmu + REG_HCI_PHY_CTL);
331
341
}
332
342
333
-
if (data->cfg->type == sun8i_a83t_phy ||
334
-
data->cfg->type == sun50i_h6_phy) {
343
+
if (data->cfg->siddq_in_base) {
335
344
if (phy->index == 0) {
336
345
val = readl(data->base + data->cfg->phyctl_offset);
337
346
val |= PHY_CTL_VBUSVLDEXT;
···
374
385
struct sun4i_usb_phy_data *data = to_sun4i_usb_phy_data(phy);
375
386
376
387
if (phy->index == 0) {
377
-
if (data->cfg->type == sun8i_a83t_phy ||
378
-
data->cfg->type == sun50i_h6_phy) {
388
+
if (data->cfg->siddq_in_base) {
379
389
void __iomem *phyctl = data->base +
380
390
data->cfg->phyctl_offset;
381
391
···
454
466
* vbus using the N_VBUSEN pin on the pmic, so we must poll
455
467
* when using the pmic for vbus-det _and_ we're driving vbus.
456
468
*/
457
-
if ((data->cfg->type == sun6i_a31_phy ||
458
-
data->cfg->type == sun8i_a33_phy) &&
459
-
data->vbus_power_supply && data->phys[0].regulator_on)
469
+
if (data->cfg->poll_vbusen && data->vbus_power_supply &&
470
+
data->phys[0].regulator_on)
460
471
return true;
461
472
462
473
return false;
···
905
918
return 0;
906
919
}
907
920
921
+
static const struct sun4i_usb_phy_cfg suniv_f1c100s_cfg = {
922
+
.num_phys = 1,
923
+
.disc_thresh = 3,
924
+
.phyctl_offset = REG_PHYCTL_A10,
925
+
.dedicated_clocks = true,
926
+
};
927
+
908
928
static const struct sun4i_usb_phy_cfg sun4i_a10_cfg = {
909
929
.num_phys = 3,
910
-
.type = sun4i_a10_phy,
911
930
.disc_thresh = 3,
912
931
.phyctl_offset = REG_PHYCTL_A10,
913
932
.dedicated_clocks = false,
···
921
928
922
929
static const struct sun4i_usb_phy_cfg sun5i_a13_cfg = {
923
930
.num_phys = 2,
924
-
.type = sun4i_a10_phy,
925
931
.disc_thresh = 2,
926
932
.phyctl_offset = REG_PHYCTL_A10,
927
933
.dedicated_clocks = false,
···
928
936
929
937
static const struct sun4i_usb_phy_cfg sun6i_a31_cfg = {
930
938
.num_phys = 3,
931
-
.type = sun6i_a31_phy,
932
939
.disc_thresh = 3,
933
940
.phyctl_offset = REG_PHYCTL_A10,
934
941
.dedicated_clocks = true,
942
+
.poll_vbusen = true,
935
943
};
936
944
937
945
static const struct sun4i_usb_phy_cfg sun7i_a20_cfg = {
938
946
.num_phys = 3,
939
-
.type = sun4i_a10_phy,
940
947
.disc_thresh = 2,
941
948
.phyctl_offset = REG_PHYCTL_A10,
942
949
.dedicated_clocks = false,
···
943
952
944
953
static const struct sun4i_usb_phy_cfg sun8i_a23_cfg = {
945
954
.num_phys = 2,
946
-
.type = sun6i_a31_phy,
947
955
.disc_thresh = 3,
948
956
.phyctl_offset = REG_PHYCTL_A10,
949
957
.dedicated_clocks = true,
958
+
.poll_vbusen = true,
950
959
};
951
960
952
961
static const struct sun4i_usb_phy_cfg sun8i_a33_cfg = {
953
962
.num_phys = 2,
954
-
.type = sun8i_a33_phy,
955
963
.disc_thresh = 3,
956
964
.phyctl_offset = REG_PHYCTL_A33,
957
965
.dedicated_clocks = true,
966
+
.poll_vbusen = true,
958
967
};
959
968
960
969
static const struct sun4i_usb_phy_cfg sun8i_a83t_cfg = {
961
970
.num_phys = 3,
962
971
.hsic_index = 2,
963
-
.type = sun8i_a83t_phy,
964
972
.phyctl_offset = REG_PHYCTL_A33,
965
973
.dedicated_clocks = true,
974
+
.siddq_in_base = true,
966
975
};
967
976
968
977
static const struct sun4i_usb_phy_cfg sun8i_h3_cfg = {
969
978
.num_phys = 4,
970
-
.type = sun8i_h3_phy,
971
979
.disc_thresh = 3,
972
980
.phyctl_offset = REG_PHYCTL_A33,
973
981
.dedicated_clocks = true,
···
976
986
977
987
static const struct sun4i_usb_phy_cfg sun8i_r40_cfg = {
978
988
.num_phys = 3,
979
-
.type = sun8i_r40_phy,
980
989
.disc_thresh = 3,
981
990
.phyctl_offset = REG_PHYCTL_A33,
982
991
.dedicated_clocks = true,
···
985
996
986
997
static const struct sun4i_usb_phy_cfg sun8i_v3s_cfg = {
987
998
.num_phys = 1,
988
-
.type = sun8i_v3s_phy,
989
999
.disc_thresh = 3,
990
1000
.phyctl_offset = REG_PHYCTL_A33,
991
1001
.dedicated_clocks = true,
···
994
1006
995
1007
static const struct sun4i_usb_phy_cfg sun20i_d1_cfg = {
996
1008
.num_phys = 2,
997
-
.type = sun50i_h6_phy,
998
1009
.phyctl_offset = REG_PHYCTL_A33,
999
1010
.dedicated_clocks = true,
1000
1011
.hci_phy_ctl_clear = PHY_CTL_SIDDQ,
1001
1012
.phy0_dual_route = true,
1013
+
.siddq_in_base = true,
1002
1014
};
1003
1015
1004
1016
static const struct sun4i_usb_phy_cfg sun50i_a64_cfg = {
1005
1017
.num_phys = 2,
1006
-
.type = sun50i_a64_phy,
1007
1018
.disc_thresh = 3,
1008
1019
.phyctl_offset = REG_PHYCTL_A33,
1009
1020
.dedicated_clocks = true,
···
1012
1025
1013
1026
static const struct sun4i_usb_phy_cfg sun50i_h6_cfg = {
1014
1027
.num_phys = 4,
1015
-
.type = sun50i_h6_phy,
1016
1028
.phyctl_offset = REG_PHYCTL_A33,
1017
1029
.dedicated_clocks = true,
1018
1030
.phy0_dual_route = true,
1019
1031
.missing_phys = BIT(1) | BIT(2),
1032
+
.siddq_in_base = true,
1020
1033
};
1021
1034
1022
1035
static const struct sun4i_usb_phy_cfg sun50i_h616_cfg = {
1023
1036
.num_phys = 4,
1024
-
.type = sun50i_h6_phy,
1025
1037
.disc_thresh = 3,
1026
1038
.phyctl_offset = REG_PHYCTL_A33,
1027
1039
.dedicated_clocks = true,
1028
1040
.phy0_dual_route = true,
1029
1041
.hci_phy_ctl_clear = PHY_CTL_SIDDQ,
1030
1042
.needs_phy2_siddq = true,
1043
+
.siddq_in_base = true,
1031
1044
};
1032
1045
1033
1046
static const struct of_device_id sun4i_usb_phy_of_match[] = {
···
1046
1059
.data = &sun50i_a64_cfg},
1047
1060
{ .compatible = "allwinner,sun50i-h6-usb-phy", .data = &sun50i_h6_cfg },
1048
1061
{ .compatible = "allwinner,sun50i-h616-usb-phy", .data = &sun50i_h616_cfg },
1062
+
{ .compatible = "allwinner,suniv-f1c100s-usb-phy",
1063
+
.data = &suniv_f1c100s_cfg },
1049
1064
{ },
1050
1065
};
1051
1066
MODULE_DEVICE_TABLE(of, sun4i_usb_phy_of_match);
+2
-2
drivers/phy/mediatek/phy-mtk-io.h
+2
-2
drivers/phy/mediatek/phy-mtk-io.h
···
39
39
/* field @mask shall be constant and continuous */
40
40
#define mtk_phy_update_field(reg, mask, val) \
41
41
({ \
42
-
typeof(mask) mask_ = (mask); \
43
-
mtk_phy_update_bits(reg, mask_, FIELD_PREP(mask_, val)); \
42
+
BUILD_BUG_ON_MSG(!__builtin_constant_p(mask), "mask is not constant"); \
43
+
mtk_phy_update_bits(reg, mask, FIELD_PREP(mask, val)); \
44
44
})
45
45
46
46
#endif
+4
drivers/phy/phy-can-transceiver.c
+4
drivers/phy/phy-can-transceiver.c
+30
-21
drivers/phy/phy-core.c
+30
-21
drivers/phy/phy-core.c
···
767
767
EXPORT_SYMBOL_GPL(phy_get);
768
768
769
769
/**
770
-
* phy_optional_get() - lookup and obtain a reference to an optional phy.
771
-
* @dev: device that requests this phy
772
-
* @string: the phy name as given in the dt data or the name of the controller
773
-
* port for non-dt case
774
-
*
775
-
* Returns the phy driver, after getting a refcount to it; or
776
-
* NULL if there is no such phy. The caller is responsible for
777
-
* calling phy_put() to release that count.
778
-
*/
779
-
struct phy *phy_optional_get(struct device *dev, const char *string)
780
-
{
781
-
struct phy *phy = phy_get(dev, string);
782
-
783
-
if (PTR_ERR(phy) == -ENODEV)
784
-
phy = NULL;
785
-
786
-
return phy;
787
-
}
788
-
EXPORT_SYMBOL_GPL(phy_optional_get);
789
-
790
-
/**
791
770
* devm_phy_get() - lookup and obtain a reference to a phy.
792
771
* @dev: device that requests this phy
793
772
* @string: the phy name as given in the dt data or phy device name
···
857
878
return phy;
858
879
}
859
880
EXPORT_SYMBOL_GPL(devm_of_phy_get);
881
+
882
+
/**
883
+
* devm_of_phy_optional_get() - lookup and obtain a reference to an optional
884
+
* phy.
885
+
* @dev: device that requests this phy
886
+
* @np: node containing the phy
887
+
* @con_id: name of the phy from device's point of view
888
+
*
889
+
* Gets the phy using of_phy_get(), and associates a device with it using
890
+
* devres. On driver detach, release function is invoked on the devres data,
891
+
* then, devres data is freed. This differs to devm_of_phy_get() in
892
+
* that if the phy does not exist, it is not considered an error and
893
+
* -ENODEV will not be returned. Instead the NULL phy is returned,
894
+
* which can be passed to all other phy consumer calls.
895
+
*/
896
+
struct phy *devm_of_phy_optional_get(struct device *dev, struct device_node *np,
897
+
const char *con_id)
898
+
{
899
+
struct phy *phy = devm_of_phy_get(dev, np, con_id);
900
+
901
+
if (PTR_ERR(phy) == -ENODEV)
902
+
phy = NULL;
903
+
904
+
if (IS_ERR(phy))
905
+
dev_err_probe(dev, PTR_ERR(phy), "failed to get PHY %pOF:%s",
906
+
np, con_id);
907
+
908
+
return phy;
909
+
}
910
+
EXPORT_SYMBOL_GPL(devm_of_phy_optional_get);
860
911
861
912
/**
862
913
* devm_of_phy_get_by_index() - lookup and obtain a reference to a phy by index.
+64
-4
drivers/phy/qualcomm/Kconfig
+64
-4
drivers/phy/qualcomm/Kconfig
···
50
50
Enable this to support the Qualcomm PCIe PHY, used with the Synopsys
51
51
based PCIe controller.
52
52
53
-
config PHY_QCOM_QMP
54
-
tristate "Qualcomm QMP PHY Driver"
53
+
menuconfig PHY_QCOM_QMP
54
+
tristate "Qualcomm QMP PHY Drivers"
55
55
depends on OF && COMMON_CLK && (ARCH_QCOM || COMPILE_TEST)
56
+
57
+
if PHY_QCOM_QMP
58
+
59
+
config PHY_QCOM_QMP_COMBO
60
+
tristate "Qualcomm QMP Combo PHY Driver"
61
+
default PHY_QCOM_QMP
56
62
select GENERIC_PHY
57
63
select MFD_SYSCON
58
64
help
59
-
Enable this to support the QMP PHY transceiver that is used
60
-
with controllers such as PCIe, UFS, and USB on Qualcomm chips.
65
+
Enable this to support the QMP Combo PHY transceiver that is used
66
+
with USB3 and DisplayPort controllers on Qualcomm chips.
67
+
68
+
config PHY_QCOM_QMP_PCIE
69
+
tristate "Qualcomm QMP PCIe PHY Driver"
70
+
depends on PCI || COMPILE_TEST
71
+
select GENERIC_PHY
72
+
default PHY_QCOM_QMP
73
+
help
74
+
Enable this to support the QMP PCIe PHY transceiver that is used
75
+
with PCIe controllers on Qualcomm chips.
76
+
77
+
config PHY_QCOM_QMP_PCIE_8996
78
+
tristate "Qualcomm QMP PCIe 8996 PHY Driver"
79
+
depends on PCI || COMPILE_TEST
80
+
select GENERIC_PHY
81
+
default PHY_QCOM_QMP
82
+
help
83
+
Enable this to support the QMP PCIe PHY transceiver that is used
84
+
with PCIe controllers on Qualcomm msm8996 chips.
85
+
86
+
config PHY_QCOM_QMP_UFS
87
+
tristate "Qualcomm QMP UFS PHY Driver"
88
+
select GENERIC_PHY
89
+
default PHY_QCOM_QMP
90
+
help
91
+
Enable this to support the QMP UFS PHY transceiver that is used
92
+
with UFS controllers on Qualcomm chips.
93
+
94
+
config PHY_QCOM_QMP_USB
95
+
tristate "Qualcomm QMP USB PHY Driver"
96
+
select GENERIC_PHY
97
+
default PHY_QCOM_QMP
98
+
help
99
+
Enable this to support the QMP USB PHY transceiver that is used
100
+
with USB3 controllers on Qualcomm chips.
101
+
102
+
endif # PHY_QCOM_QMP
61
103
62
104
config PHY_QCOM_QUSB2
63
105
tristate "Qualcomm QUSB2 PHY Driver"
···
111
69
controllers on Qualcomm chips. This driver supports the high-speed
112
70
PHY which is usually paired with either the ChipIdea or Synopsys DWC3
113
71
USB IPs on MSM SOCs.
72
+
73
+
config PHY_QCOM_SNPS_EUSB2
74
+
tristate "Qualcomm SNPS eUSB2 PHY Driver"
75
+
depends on OF && (ARCH_QCOM || COMPILE_TEST)
76
+
select GENERIC_PHY
77
+
help
78
+
Enable support for the USB high-speed SNPS eUSB2 phy on Qualcomm
79
+
chipsets. The PHY is paired with a Synopsys DWC3 USB controller
80
+
on Qualcomm SOCs.
81
+
82
+
config PHY_QCOM_EUSB2_REPEATER
83
+
tristate "Qualcomm SNPS eUSB2 Repeater Driver"
84
+
depends on OF && (ARCH_QCOM || COMPILE_TEST)
85
+
select GENERIC_PHY
86
+
help
87
+
Enable support for the USB high-speed SNPS eUSB2 repeater on Qualcomm
88
+
PMICs. The repeater is paired with a Synopsys eUSB2 Phy
89
+
on Qualcomm SOCs.
114
90
115
91
config PHY_QCOM_USB_HS
116
92
tristate "Qualcomm USB HS PHY module"
+8
-6
drivers/phy/qualcomm/Makefile
+8
-6
drivers/phy/qualcomm/Makefile
···
5
5
obj-$(CONFIG_PHY_QCOM_IPQ4019_USB) += phy-qcom-ipq4019-usb.o
6
6
obj-$(CONFIG_PHY_QCOM_IPQ806X_SATA) += phy-qcom-ipq806x-sata.o
7
7
obj-$(CONFIG_PHY_QCOM_PCIE2) += phy-qcom-pcie2.o
8
-
obj-$(CONFIG_PHY_QCOM_QMP) += \
9
-
phy-qcom-qmp-combo.o \
10
-
phy-qcom-qmp-pcie.o \
11
-
phy-qcom-qmp-pcie-msm8996.o \
12
-
phy-qcom-qmp-ufs.o \
13
-
phy-qcom-qmp-usb.o
8
+
9
+
obj-$(CONFIG_PHY_QCOM_QMP_COMBO) += phy-qcom-qmp-combo.o
10
+
obj-$(CONFIG_PHY_QCOM_QMP_PCIE) += phy-qcom-qmp-pcie.o
11
+
obj-$(CONFIG_PHY_QCOM_QMP_PCIE_8996) += phy-qcom-qmp-pcie-msm8996.o
12
+
obj-$(CONFIG_PHY_QCOM_QMP_UFS) += phy-qcom-qmp-ufs.o
13
+
obj-$(CONFIG_PHY_QCOM_QMP_USB) += phy-qcom-qmp-usb.o
14
14
15
15
obj-$(CONFIG_PHY_QCOM_QUSB2) += phy-qcom-qusb2.o
16
+
obj-$(CONFIG_PHY_QCOM_SNPS_EUSB2) += phy-qcom-snps-eusb2.o
17
+
obj-$(CONFIG_PHY_QCOM_EUSB2_REPEATER) += phy-qcom-eusb2-repeater.o
16
18
obj-$(CONFIG_PHY_QCOM_USB_HS) += phy-qcom-usb-hs.o
17
19
obj-$(CONFIG_PHY_QCOM_USB_HSIC) += phy-qcom-usb-hsic.o
18
20
obj-$(CONFIG_PHY_QCOM_USB_HS_28NM) += phy-qcom-usb-hs-28nm.o
+259
drivers/phy/qualcomm/phy-qcom-eusb2-repeater.c
+259
drivers/phy/qualcomm/phy-qcom-eusb2-repeater.c
···
1
+
// SPDX-License-Identifier: GPL-2.0
2
+
/*
3
+
* Copyright (c) 2023, Linaro Limited
4
+
*/
5
+
6
+
#include <linux/module.h>
7
+
#include <linux/platform_device.h>
8
+
#include <linux/regulator/consumer.h>
9
+
#include <linux/regmap.h>
10
+
#include <linux/of.h>
11
+
#include <linux/of_device.h>
12
+
#include <linux/phy/phy.h>
13
+
14
+
/* eUSB2 status registers */
15
+
#define EUSB2_RPTR_STATUS 0x08
16
+
#define RPTR_OK BIT(7)
17
+
18
+
/* eUSB2 control registers */
19
+
#define EUSB2_EN_CTL1 0x46
20
+
#define EUSB2_RPTR_EN BIT(7)
21
+
22
+
#define EUSB2_FORCE_EN_5 0xe8
23
+
#define F_CLK_19P2M_EN BIT(6)
24
+
25
+
#define EUSB2_FORCE_VAL_5 0xeD
26
+
#define V_CLK_19P2M_EN BIT(6)
27
+
28
+
#define EUSB2_TUNE_IUSB2 0x51
29
+
#define EUSB2_TUNE_SQUELCH_U 0x54
30
+
#define EUSB2_TUNE_USB2_PREEM 0x57
31
+
32
+
#define QCOM_EUSB2_REPEATER_INIT_CFG(o, v) \
33
+
{ \
34
+
.offset = o, \
35
+
.val = v, \
36
+
}
37
+
38
+
struct eusb2_repeater_init_tbl {
39
+
unsigned int offset;
40
+
unsigned int val;
41
+
};
42
+
43
+
struct eusb2_repeater_cfg {
44
+
const struct eusb2_repeater_init_tbl *init_tbl;
45
+
int init_tbl_num;
46
+
const char * const *vreg_list;
47
+
int num_vregs;
48
+
};
49
+
50
+
struct eusb2_repeater {
51
+
struct device *dev;
52
+
struct regmap *regmap;
53
+
struct phy *phy;
54
+
struct regulator_bulk_data *vregs;
55
+
const struct eusb2_repeater_cfg *cfg;
56
+
u16 base;
57
+
enum phy_mode mode;
58
+
};
59
+
60
+
static const char * const pm8550b_vreg_l[] = {
61
+
"vdd18", "vdd3",
62
+
};
63
+
64
+
static const struct eusb2_repeater_init_tbl pm8550b_init_tbl[] = {
65
+
QCOM_EUSB2_REPEATER_INIT_CFG(EUSB2_TUNE_IUSB2, 0x8),
66
+
QCOM_EUSB2_REPEATER_INIT_CFG(EUSB2_TUNE_SQUELCH_U, 0x3),
67
+
QCOM_EUSB2_REPEATER_INIT_CFG(EUSB2_TUNE_USB2_PREEM, 0x5),
68
+
};
69
+
70
+
static const struct eusb2_repeater_cfg pm8550b_eusb2_cfg = {
71
+
.init_tbl = pm8550b_init_tbl,
72
+
.init_tbl_num = ARRAY_SIZE(pm8550b_init_tbl),
73
+
.vreg_list = pm8550b_vreg_l,
74
+
.num_vregs = ARRAY_SIZE(pm8550b_vreg_l),
75
+
};
76
+
77
+
static int eusb2_repeater_init_vregs(struct eusb2_repeater *rptr)
78
+
{
79
+
int num = rptr->cfg->num_vregs;
80
+
struct device *dev = rptr->dev;
81
+
int i;
82
+
83
+
rptr->vregs = devm_kcalloc(dev, num, sizeof(*rptr->vregs), GFP_KERNEL);
84
+
if (!rptr->vregs)
85
+
return -ENOMEM;
86
+
87
+
for (i = 0; i < num; i++)
88
+
rptr->vregs[i].supply = rptr->cfg->vreg_list[i];
89
+
90
+
return devm_regulator_bulk_get(dev, num, rptr->vregs);
91
+
}
92
+
93
+
static int eusb2_repeater_init(struct phy *phy)
94
+
{
95
+
struct eusb2_repeater *rptr = phy_get_drvdata(phy);
96
+
const struct eusb2_repeater_init_tbl *init_tbl = rptr->cfg->init_tbl;
97
+
int num = rptr->cfg->init_tbl_num;
98
+
u32 val;
99
+
int ret;
100
+
int i;
101
+
102
+
ret = regulator_bulk_enable(rptr->cfg->num_vregs, rptr->vregs);
103
+
if (ret)
104
+
return ret;
105
+
106
+
regmap_update_bits(rptr->regmap, rptr->base + EUSB2_EN_CTL1,
107
+
EUSB2_RPTR_EN, EUSB2_RPTR_EN);
108
+
109
+
for (i = 0; i < num; i++)
110
+
regmap_update_bits(rptr->regmap,
111
+
rptr->base + init_tbl[i].offset,
112
+
init_tbl[i].val, init_tbl[i].val);
113
+
114
+
ret = regmap_read_poll_timeout(rptr->regmap,
115
+
rptr->base + EUSB2_RPTR_STATUS, val,
116
+
val & RPTR_OK, 10, 5);
117
+
if (ret)
118
+
dev_err(rptr->dev, "initialization timed-out\n");
119
+
120
+
return ret;
121
+
}
122
+
123
+
static int eusb2_repeater_set_mode(struct phy *phy,
124
+
enum phy_mode mode, int submode)
125
+
{
126
+
struct eusb2_repeater *rptr = phy_get_drvdata(phy);
127
+
128
+
switch (mode) {
129
+
case PHY_MODE_USB_HOST:
130
+
/*
131
+
* CM.Lx is prohibited when repeater is already into Lx state as
132
+
* per eUSB 1.2 Spec. Below implement software workaround until
133
+
* PHY and controller is fixing seen observation.
134
+
*/
135
+
regmap_update_bits(rptr->regmap, rptr->base + EUSB2_FORCE_EN_5,
136
+
F_CLK_19P2M_EN, F_CLK_19P2M_EN);
137
+
regmap_update_bits(rptr->regmap, rptr->base + EUSB2_FORCE_VAL_5,
138
+
V_CLK_19P2M_EN, V_CLK_19P2M_EN);
139
+
break;
140
+
case PHY_MODE_USB_DEVICE:
141
+
/*
142
+
* In device mode clear host mode related workaround as there
143
+
* is no repeater reset available, and enable/disable of
144
+
* repeater doesn't clear previous value due to shared
145
+
* regulators (say host <-> device mode switch).
146
+
*/
147
+
regmap_update_bits(rptr->regmap, rptr->base + EUSB2_FORCE_EN_5,
148
+
F_CLK_19P2M_EN, 0);
149
+
regmap_update_bits(rptr->regmap, rptr->base + EUSB2_FORCE_VAL_5,
150
+
V_CLK_19P2M_EN, 0);
151
+
break;
152
+
default:
153
+
return -EINVAL;
154
+
}
155
+
156
+
return 0;
157
+
}
158
+
159
+
static int eusb2_repeater_exit(struct phy *phy)
160
+
{
161
+
struct eusb2_repeater *rptr = phy_get_drvdata(phy);
162
+
163
+
return regulator_bulk_disable(rptr->cfg->num_vregs, rptr->vregs);
164
+
}
165
+
166
+
static const struct phy_ops eusb2_repeater_ops = {
167
+
.init = eusb2_repeater_init,
168
+
.exit = eusb2_repeater_exit,
169
+
.set_mode = eusb2_repeater_set_mode,
170
+
.owner = THIS_MODULE,
171
+
};
172
+
173
+
static int eusb2_repeater_probe(struct platform_device *pdev)
174
+
{
175
+
struct eusb2_repeater *rptr;
176
+
struct device *dev = &pdev->dev;
177
+
struct phy_provider *phy_provider;
178
+
struct device_node *np = dev->of_node;
179
+
u32 res;
180
+
int ret;
181
+
182
+
rptr = devm_kzalloc(dev, sizeof(*rptr), GFP_KERNEL);
183
+
if (!rptr)
184
+
return -ENOMEM;
185
+
186
+
rptr->dev = dev;
187
+
dev_set_drvdata(dev, rptr);
188
+
189
+
rptr->cfg = of_device_get_match_data(dev);
190
+
if (!rptr->cfg)
191
+
return -EINVAL;
192
+
193
+
rptr->regmap = dev_get_regmap(dev->parent, NULL);
194
+
if (!rptr->regmap)
195
+
return -ENODEV;
196
+
197
+
ret = of_property_read_u32(np, "reg", &res);
198
+
if (ret < 0)
199
+
return ret;
200
+
201
+
rptr->base = res;
202
+
203
+
ret = eusb2_repeater_init_vregs(rptr);
204
+
if (ret < 0) {
205
+
dev_err(dev, "unable to get supplies\n");
206
+
return ret;
207
+
}
208
+
209
+
rptr->phy = devm_phy_create(dev, np, &eusb2_repeater_ops);
210
+
if (IS_ERR(rptr->phy)) {
211
+
dev_err(dev, "failed to create PHY: %d\n", ret);
212
+
return PTR_ERR(rptr->phy);
213
+
}
214
+
215
+
phy_set_drvdata(rptr->phy, rptr);
216
+
217
+
phy_provider = devm_of_phy_provider_register(dev, of_phy_simple_xlate);
218
+
if (IS_ERR(phy_provider))
219
+
return PTR_ERR(phy_provider);
220
+
221
+
dev_info(dev, "Registered Qcom-eUSB2 repeater\n");
222
+
223
+
return 0;
224
+
}
225
+
226
+
static int eusb2_repeater_remove(struct platform_device *pdev)
227
+
{
228
+
struct eusb2_repeater *rptr = platform_get_drvdata(pdev);
229
+
230
+
if (!rptr)
231
+
return 0;
232
+
233
+
eusb2_repeater_exit(rptr->phy);
234
+
235
+
return 0;
236
+
}
237
+
238
+
static const struct of_device_id eusb2_repeater_of_match_table[] = {
239
+
{
240
+
.compatible = "qcom,pm8550b-eusb2-repeater",
241
+
.data = &pm8550b_eusb2_cfg,
242
+
},
243
+
{ },
244
+
};
245
+
MODULE_DEVICE_TABLE(of, eusb2_repeater_of_match_table);
246
+
247
+
static struct platform_driver eusb2_repeater_driver = {
248
+
.probe = eusb2_repeater_probe,
249
+
.remove = eusb2_repeater_remove,
250
+
.driver = {
251
+
.name = "qcom-eusb2-repeater",
252
+
.of_match_table = eusb2_repeater_of_match_table,
253
+
},
254
+
};
255
+
256
+
module_platform_driver(eusb2_repeater_driver);
257
+
258
+
MODULE_DESCRIPTION("Qualcomm PMIC eUSB2 Repeater driver");
259
+
MODULE_LICENSE("GPL");
+5
-1
drivers/phy/qualcomm/phy-qcom-pcie2.c
+5
-1
drivers/phy/qualcomm/phy-qcom-pcie2.c
···
243
243
fixed->fixed_rate = 250000000;
244
244
fixed->hw.init = &init;
245
245
246
-
return devm_clk_hw_register(qphy->dev, &fixed->hw);
246
+
ret = devm_clk_hw_register(qphy->dev, &fixed->hw);
247
+
if (ret < 0)
248
+
return ret;
249
+
250
+
return devm_of_clk_add_hw_provider(qphy->dev, of_clk_hw_simple_get, &fixed->hw);
247
251
}
248
252
249
253
static int qcom_pcie2_phy_probe(struct platform_device *pdev)
+724
-26
drivers/phy/qualcomm/phy-qcom-qmp-combo.c
+724
-26
drivers/phy/qualcomm/phy-qcom-qmp-combo.c
···
23
23
#include <dt-bindings/phy/phy-qcom-qmp.h>
24
24
25
25
#include "phy-qcom-qmp.h"
26
+
#include "phy-qcom-qmp-pcs-misc-v3.h"
27
+
#include "phy-qcom-qmp-pcs-usb-v4.h"
28
+
#include "phy-qcom-qmp-pcs-usb-v5.h"
29
+
#include "phy-qcom-qmp-pcs-usb-v6.h"
26
30
27
31
/* QPHY_SW_RESET bit */
28
32
#define SW_RESET BIT(0)
···
59
55
60
56
/* QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR register bits */
61
57
#define IRQ_CLEAR BIT(0)
62
-
63
-
/* QPHY_PCS_LFPS_RXTERM_IRQ_STATUS register bits */
64
-
#define RCVR_DETECT BIT(0)
65
58
66
59
/* QPHY_V3_PCS_MISC_CLAMP_ENABLE register bits */
67
60
#define CLAMP_EN BIT(0) /* enables i/o clamp_n */
···
97
96
QPHY_PCS_STATUS,
98
97
QPHY_PCS_AUTONOMOUS_MODE_CTRL,
99
98
QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR,
100
-
QPHY_PCS_LFPS_RXTERM_IRQ_STATUS,
101
99
QPHY_PCS_POWER_DOWN_CONTROL,
102
100
/* Keep last to ensure regs_layout arrays are properly initialized */
103
101
QPHY_LAYOUT_SIZE
104
102
};
105
103
106
104
static const unsigned int qmp_v3_usb3phy_regs_layout[QPHY_LAYOUT_SIZE] = {
107
-
[QPHY_SW_RESET] = 0x00,
108
-
[QPHY_START_CTRL] = 0x08,
109
-
[QPHY_PCS_STATUS] = 0x174,
110
-
[QPHY_PCS_POWER_DOWN_CONTROL] = 0x04,
111
-
[QPHY_PCS_AUTONOMOUS_MODE_CTRL] = 0x0d8,
112
-
[QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR] = 0x0dc,
113
-
[QPHY_PCS_LFPS_RXTERM_IRQ_STATUS] = 0x170,
105
+
[QPHY_SW_RESET] = QPHY_V3_PCS_SW_RESET,
106
+
[QPHY_START_CTRL] = QPHY_V3_PCS_START_CONTROL,
107
+
[QPHY_PCS_STATUS] = QPHY_V3_PCS_PCS_STATUS,
108
+
[QPHY_PCS_POWER_DOWN_CONTROL] = QPHY_V3_PCS_POWER_DOWN_CONTROL,
109
+
[QPHY_PCS_AUTONOMOUS_MODE_CTRL] = QPHY_V3_PCS_AUTONOMOUS_MODE_CTRL,
110
+
[QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR] = QPHY_V3_PCS_LFPS_RXTERM_IRQ_CLEAR,
114
111
};
115
112
116
113
static const unsigned int qmp_v4_usb3phy_regs_layout[QPHY_LAYOUT_SIZE] = {
117
-
[QPHY_SW_RESET] = 0x00,
118
-
[QPHY_START_CTRL] = 0x44,
119
-
[QPHY_PCS_STATUS] = 0x14,
120
-
[QPHY_PCS_POWER_DOWN_CONTROL] = 0x40,
114
+
[QPHY_SW_RESET] = QPHY_V4_PCS_SW_RESET,
115
+
[QPHY_START_CTRL] = QPHY_V4_PCS_START_CONTROL,
116
+
[QPHY_PCS_STATUS] = QPHY_V4_PCS_PCS_STATUS1,
117
+
[QPHY_PCS_POWER_DOWN_CONTROL] = QPHY_V4_PCS_POWER_DOWN_CONTROL,
121
118
122
119
/* In PCS_USB */
123
-
[QPHY_PCS_AUTONOMOUS_MODE_CTRL] = 0x008,
124
-
[QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR] = 0x014,
120
+
[QPHY_PCS_AUTONOMOUS_MODE_CTRL] = QPHY_V4_PCS_USB3_AUTONOMOUS_MODE_CTRL,
121
+
[QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR] = QPHY_V4_PCS_USB3_LFPS_RXTERM_IRQ_CLEAR,
125
122
};
126
123
127
124
static const struct qmp_phy_init_tbl qmp_v3_usb3_serdes_tbl[] = {
···
310
311
QMP_PHY_INIT_CFG(QPHY_V3_PCS_RXEQTRAINING_RUN_TIME, 0x13),
311
312
};
312
313
314
+
static const struct qmp_phy_init_tbl sm6350_usb3_rx_tbl[] = {
315
+
QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_FO_GAIN, 0x0b),
316
+
QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0f),
317
+
QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4e),
318
+
QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL4, 0x18),
319
+
QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x77),
320
+
QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80),
321
+
QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_CNTRL, 0x03),
322
+
QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_DEGLITCH_CNTRL, 0x16),
323
+
QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_MODE_00, 0x05),
324
+
QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x75),
325
+
};
326
+
327
+
static const struct qmp_phy_init_tbl sm6350_usb3_pcs_tbl[] = {
328
+
/* FLL settings */
329
+
QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL2, 0x83),
330
+
QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_L, 0x09),
331
+
QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_H_TOL, 0xa2),
332
+
QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_MAN_CODE, 0x40),
333
+
QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL1, 0x02),
334
+
335
+
/* Lock Det settings */
336
+
QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG1, 0xd1),
337
+
QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG2, 0x1f),
338
+
QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG3, 0x47),
339
+
QMP_PHY_INIT_CFG(QPHY_V3_PCS_POWER_STATE_CONFIG2, 0x1b),
340
+
341
+
QMP_PHY_INIT_CFG(QPHY_V3_PCS_RX_SIGDET_LVL, 0xcc),
342
+
QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V0, 0x9f),
343
+
QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V1, 0x9f),
344
+
QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V2, 0xb7),
345
+
QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V3, 0x4e),
346
+
QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V4, 0x65),
347
+
QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_LS, 0x6b),
348
+
QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V0, 0x15),
349
+
QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V0, 0x0d),
350
+
QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V1, 0x15),
351
+
QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V1, 0x0d),
352
+
QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V2, 0x15),
353
+
QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V2, 0x0d),
354
+
QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V3, 0x15),
355
+
QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V3, 0x1d),
356
+
QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V4, 0x15),
357
+
QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V4, 0x0d),
358
+
QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_LS, 0x15),
359
+
QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_LS, 0x0d),
360
+
361
+
QMP_PHY_INIT_CFG(QPHY_V3_PCS_RATE_SLEW_CNTRL, 0x02),
362
+
QMP_PHY_INIT_CFG(QPHY_V3_PCS_PWRUP_RESET_DLY_TIME_AUXCLK, 0x04),
363
+
QMP_PHY_INIT_CFG(QPHY_V3_PCS_TSYNC_RSYNC_TIME, 0x44),
364
+
QMP_PHY_INIT_CFG(QPHY_V3_PCS_PWRUP_RESET_DLY_TIME_AUXCLK, 0x04),
365
+
QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_P1U2_L, 0xe7),
366
+
QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_P1U2_H, 0x03),
367
+
QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_U3_L, 0x40),
368
+
QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_U3_H, 0x00),
369
+
QMP_PHY_INIT_CFG(QPHY_V3_PCS_RXEQTRAINING_WAIT_TIME, 0x75),
370
+
QMP_PHY_INIT_CFG(QPHY_V3_PCS_LFPS_TX_ECSTART_EQTLOCK, 0x86),
371
+
QMP_PHY_INIT_CFG(QPHY_V3_PCS_RXEQTRAINING_RUN_TIME, 0x13),
372
+
QMP_PHY_INIT_CFG(QPHY_V3_PCS_LFPS_DET_HIGH_COUNT_VAL, 0x04),
373
+
374
+
QMP_PHY_INIT_CFG(QPHY_V3_PCS_REFGEN_REQ_CONFIG1, 0x21),
375
+
QMP_PHY_INIT_CFG(QPHY_V3_PCS_REFGEN_REQ_CONFIG2, 0x60),
376
+
};
377
+
313
378
static const struct qmp_phy_init_tbl sm8150_usb3_serdes_tbl[] = {
314
379
QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_EN_CENTER, 0x01),
315
380
QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_PER1, 0x31),
···
557
494
QMP_PHY_INIT_CFG(QPHY_V4_PCS_USB3_RXEQTRAINING_DFE_TIME_S2, 0x07),
558
495
};
559
496
497
+
static const struct qmp_phy_init_tbl sm8350_usb3_tx_tbl[] = {
498
+
QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_TX, 0x00),
499
+
QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_RX, 0x00),
500
+
QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_OFFSET_TX, 0x16),
501
+
QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_OFFSET_RX, 0x0e),
502
+
QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_1, 0x35),
503
+
QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_3, 0x3f),
504
+
QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_4, 0x7f),
505
+
QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_5, 0x3f),
506
+
QMP_PHY_INIT_CFG(QSERDES_V5_TX_RCV_DETECT_LVL_2, 0x12),
507
+
QMP_PHY_INIT_CFG(QSERDES_V5_TX_PI_QEC_CTRL, 0x21),
508
+
};
509
+
510
+
static const struct qmp_phy_init_tbl sm8350_usb3_rx_tbl[] = {
511
+
QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FO_GAIN, 0x0a),
512
+
QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SO_GAIN, 0x05),
513
+
QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FASTLOCK_FO_GAIN, 0x2f),
514
+
QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x7f),
515
+
QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FASTLOCK_COUNT_LOW, 0xff),
516
+
QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FASTLOCK_COUNT_HIGH, 0x0f),
517
+
QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_PI_CONTROLS, 0x99),
518
+
QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_THRESH1, 0x08),
519
+
QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_THRESH2, 0x08),
520
+
QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_GAIN1, 0x00),
521
+
QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_GAIN2, 0x04),
522
+
QMP_PHY_INIT_CFG(QSERDES_V5_RX_VGA_CAL_CNTRL1, 0x54),
523
+
QMP_PHY_INIT_CFG(QSERDES_V5_RX_VGA_CAL_CNTRL2, 0x0f),
524
+
QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0f),
525
+
QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4a),
526
+
QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL4, 0x0a),
527
+
QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_IDAC_TSETTLE_LOW, 0xc0),
528
+
QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_IDAC_TSETTLE_HIGH, 0x00),
529
+
QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x47),
530
+
QMP_PHY_INIT_CFG(QSERDES_V5_RX_SIGDET_CNTRL, 0x04),
531
+
QMP_PHY_INIT_CFG(QSERDES_V5_RX_SIGDET_DEGLITCH_CNTRL, 0x0e),
532
+
QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_LOW, 0xbb),
533
+
QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH, 0x7b),
534
+
QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH2, 0xbb),
535
+
QMP_PHY_INIT_CFG_LANE(QSERDES_V5_RX_RX_MODE_00_HIGH3, 0x3d, 1),
536
+
QMP_PHY_INIT_CFG_LANE(QSERDES_V5_RX_RX_MODE_00_HIGH3, 0x3c, 2),
537
+
QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH4, 0xdb),
538
+
QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_LOW, 0x64),
539
+
QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH, 0x24),
540
+
QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH2, 0xd2),
541
+
QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH3, 0x13),
542
+
QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH4, 0xa9),
543
+
QMP_PHY_INIT_CFG(QSERDES_V5_RX_DFE_EN_TIMER, 0x04),
544
+
QMP_PHY_INIT_CFG(QSERDES_V5_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38),
545
+
QMP_PHY_INIT_CFG(QSERDES_V5_RX_AUX_DATA_TCOARSE_TFINE, 0xa0),
546
+
QMP_PHY_INIT_CFG(QSERDES_V5_RX_DCC_CTRL1, 0x0c),
547
+
QMP_PHY_INIT_CFG(QSERDES_V5_RX_GM_CAL, 0x00),
548
+
QMP_PHY_INIT_CFG(QSERDES_V5_RX_VTH_CODE, 0x10),
549
+
};
550
+
551
+
static const struct qmp_phy_init_tbl sm8350_usb3_pcs_tbl[] = {
552
+
QMP_PHY_INIT_CFG(QPHY_V4_PCS_RCVR_DTCT_DLY_P1U2_L, 0xe7),
553
+
QMP_PHY_INIT_CFG(QPHY_V4_PCS_RCVR_DTCT_DLY_P1U2_H, 0x03),
554
+
QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG1, 0xd0),
555
+
QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG2, 0x07),
556
+
QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG3, 0x20),
557
+
QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG6, 0x13),
558
+
QMP_PHY_INIT_CFG(QPHY_V4_PCS_REFGEN_REQ_CONFIG1, 0x21),
559
+
QMP_PHY_INIT_CFG(QPHY_V4_PCS_RX_SIGDET_LVL, 0xaa),
560
+
QMP_PHY_INIT_CFG(QPHY_V4_PCS_CDR_RESET_TIME, 0x0a),
561
+
QMP_PHY_INIT_CFG(QPHY_V4_PCS_ALIGN_DETECT_CONFIG1, 0x88),
562
+
QMP_PHY_INIT_CFG(QPHY_V4_PCS_ALIGN_DETECT_CONFIG2, 0x13),
563
+
QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCS_TX_RX_CONFIG, 0x0c),
564
+
QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG1, 0x4b),
565
+
QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG5, 0x10),
566
+
};
567
+
568
+
static const struct qmp_phy_init_tbl sm8350_usb3_pcs_usb_tbl[] = {
569
+
QMP_PHY_INIT_CFG(QPHY_V5_PCS_USB3_RCVR_DTCT_DLY_U3_L, 0x40),
570
+
QMP_PHY_INIT_CFG(QPHY_V5_PCS_USB3_RCVR_DTCT_DLY_U3_H, 0x00),
571
+
QMP_PHY_INIT_CFG(QPHY_V5_PCS_USB3_LFPS_DET_HIGH_COUNT_VAL, 0xf8),
572
+
QMP_PHY_INIT_CFG(QPHY_V5_PCS_USB3_RXEQTRAINING_DFE_TIME_S2, 0x07),
573
+
};
574
+
575
+
static const struct qmp_phy_init_tbl sm8550_usb3_serdes_tbl[] = {
576
+
QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_STEP_SIZE1_MODE1, 0xc0),
577
+
QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_STEP_SIZE2_MODE1, 0x01),
578
+
QMP_PHY_INIT_CFG(QSERDES_V6_COM_CP_CTRL_MODE1, 0x02),
579
+
QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_RCTRL_MODE1, 0x16),
580
+
QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_CCTRL_MODE1, 0x36),
581
+
QMP_PHY_INIT_CFG(QSERDES_V6_COM_CORECLK_DIV_MODE1, 0x04),
582
+
QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP1_MODE1, 0x16),
583
+
QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP2_MODE1, 0x41),
584
+
QMP_PHY_INIT_CFG(QSERDES_V6_COM_DEC_START_MODE1, 0x41),
585
+
QMP_PHY_INIT_CFG(QSERDES_V6_COM_DEC_START_MSB_MODE1, 0x00),
586
+
QMP_PHY_INIT_CFG(QSERDES_V6_COM_DIV_FRAC_START1_MODE1, 0x55),
587
+
QMP_PHY_INIT_CFG(QSERDES_V6_COM_DIV_FRAC_START2_MODE1, 0x75),
588
+
QMP_PHY_INIT_CFG(QSERDES_V6_COM_DIV_FRAC_START3_MODE1, 0x01),
589
+
QMP_PHY_INIT_CFG(QSERDES_V6_COM_HSCLK_SEL_1, 0x01),
590
+
QMP_PHY_INIT_CFG(QSERDES_V6_COM_VCO_TUNE1_MODE1, 0x25),
591
+
QMP_PHY_INIT_CFG(QSERDES_V6_COM_VCO_TUNE2_MODE1, 0x02),
592
+
QMP_PHY_INIT_CFG(QSERDES_V6_COM_BIN_VCOCAL_CMP_CODE1_MODE1, 0x5c),
593
+
QMP_PHY_INIT_CFG(QSERDES_V6_COM_BIN_VCOCAL_CMP_CODE2_MODE1, 0x0f),
594
+
QMP_PHY_INIT_CFG(QSERDES_V6_COM_BIN_VCOCAL_CMP_CODE1_MODE0, 0x5c),
595
+
QMP_PHY_INIT_CFG(QSERDES_V6_COM_BIN_VCOCAL_CMP_CODE2_MODE0, 0x0f),
596
+
QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_STEP_SIZE1_MODE0, 0xc0),
597
+
QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_STEP_SIZE2_MODE0, 0x01),
598
+
QMP_PHY_INIT_CFG(QSERDES_V6_COM_CP_CTRL_MODE0, 0x02),
599
+
QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_RCTRL_MODE0, 0x16),
600
+
QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_CCTRL_MODE0, 0x36),
601
+
QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP1_MODE0, 0x08),
602
+
QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP2_MODE0, 0x1a),
603
+
QMP_PHY_INIT_CFG(QSERDES_V6_COM_DEC_START_MODE0, 0x41),
604
+
QMP_PHY_INIT_CFG(QSERDES_V6_COM_DEC_START_MSB_MODE0, 0x00),
605
+
QMP_PHY_INIT_CFG(QSERDES_V6_COM_DIV_FRAC_START1_MODE0, 0x55),
606
+
QMP_PHY_INIT_CFG(QSERDES_V6_COM_DIV_FRAC_START2_MODE0, 0x75),
607
+
QMP_PHY_INIT_CFG(QSERDES_V6_COM_DIV_FRAC_START3_MODE0, 0x01),
608
+
QMP_PHY_INIT_CFG(QSERDES_V6_COM_VCO_TUNE1_MODE0, 0x25),
609
+
QMP_PHY_INIT_CFG(QSERDES_V6_COM_VCO_TUNE2_MODE0, 0x02),
610
+
QMP_PHY_INIT_CFG(QSERDES_V6_COM_BG_TIMER, 0x0a),
611
+
QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_EN_CENTER, 0x01),
612
+
QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_PER1, 0x62),
613
+
QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_PER2, 0x02),
614
+
QMP_PHY_INIT_CFG(QSERDES_V6_COM_SYSCLK_BUF_ENABLE, 0x0c),
615
+
QMP_PHY_INIT_CFG(QSERDES_V6_COM_SYSCLK_EN_SEL, 0x1a),
616
+
QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP_CFG, 0x14),
617
+
QMP_PHY_INIT_CFG(QSERDES_V6_COM_VCO_TUNE_MAP, 0x04),
618
+
QMP_PHY_INIT_CFG(QSERDES_V6_COM_CORE_CLK_EN, 0x20),
619
+
QMP_PHY_INIT_CFG(QSERDES_V6_COM_CMN_CONFIG_1, 0x16),
620
+
QMP_PHY_INIT_CFG(QSERDES_V6_COM_AUTO_GAIN_ADJ_CTRL_1, 0xb6),
621
+
QMP_PHY_INIT_CFG(QSERDES_V6_COM_AUTO_GAIN_ADJ_CTRL_2, 0x4b),
622
+
QMP_PHY_INIT_CFG(QSERDES_V6_COM_AUTO_GAIN_ADJ_CTRL_3, 0x37),
623
+
QMP_PHY_INIT_CFG(QSERDES_V6_COM_ADDITIONAL_MISC, 0x0c),
624
+
};
625
+
626
+
static const struct qmp_phy_init_tbl sm8550_usb3_tx_tbl[] = {
627
+
QMP_PHY_INIT_CFG(QSERDES_V6_TX_RES_CODE_LANE_TX, 0x00),
628
+
QMP_PHY_INIT_CFG(QSERDES_V6_TX_RES_CODE_LANE_RX, 0x00),
629
+
QMP_PHY_INIT_CFG(QSERDES_V6_TX_RES_CODE_LANE_OFFSET_TX, 0x1f),
630
+
QMP_PHY_INIT_CFG(QSERDES_V6_TX_RES_CODE_LANE_OFFSET_RX, 0x09),
631
+
QMP_PHY_INIT_CFG(QSERDES_V6_TX_LANE_MODE_1, 0xf5),
632
+
QMP_PHY_INIT_CFG(QSERDES_V6_TX_LANE_MODE_3, 0x3f),
633
+
QMP_PHY_INIT_CFG(QSERDES_V6_TX_LANE_MODE_4, 0x3f),
634
+
QMP_PHY_INIT_CFG(QSERDES_V6_TX_LANE_MODE_5, 0x5f),
635
+
QMP_PHY_INIT_CFG(QSERDES_V6_TX_RCV_DETECT_LVL_2, 0x12),
636
+
QMP_PHY_INIT_CFG_LANE(QSERDES_V6_TX_PI_QEC_CTRL, 0x21, 1),
637
+
QMP_PHY_INIT_CFG_LANE(QSERDES_V6_TX_PI_QEC_CTRL, 0x05, 2),
638
+
};
639
+
640
+
static const struct qmp_phy_init_tbl sm8550_usb3_rx_tbl[] = {
641
+
QMP_PHY_INIT_CFG(QSERDES_V6_RX_UCDR_FO_GAIN, 0x0a),
642
+
QMP_PHY_INIT_CFG(QSERDES_V6_RX_UCDR_SO_GAIN, 0x06),
643
+
QMP_PHY_INIT_CFG(QSERDES_V6_RX_UCDR_FASTLOCK_FO_GAIN, 0x2f),
644
+
QMP_PHY_INIT_CFG(QSERDES_V6_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x7f),
645
+
QMP_PHY_INIT_CFG(QSERDES_V6_RX_UCDR_FASTLOCK_COUNT_LOW, 0xff),
646
+
QMP_PHY_INIT_CFG(QSERDES_V6_RX_UCDR_FASTLOCK_COUNT_HIGH, 0x0f),
647
+
QMP_PHY_INIT_CFG(QSERDES_V6_RX_UCDR_PI_CONTROLS, 0x99),
648
+
QMP_PHY_INIT_CFG(QSERDES_V6_RX_UCDR_SB2_THRESH1, 0x08),
649
+
QMP_PHY_INIT_CFG(QSERDES_V6_RX_UCDR_SB2_THRESH2, 0x08),
650
+
QMP_PHY_INIT_CFG(QSERDES_V6_RX_UCDR_SB2_GAIN1, 0x00),
651
+
QMP_PHY_INIT_CFG(QSERDES_V6_RX_UCDR_SB2_GAIN2, 0x0a),
652
+
QMP_PHY_INIT_CFG(QSERDES_V6_RX_AUX_DATA_TCOARSE_TFINE, 0xa0),
653
+
QMP_PHY_INIT_CFG(QSERDES_V6_RX_VGA_CAL_CNTRL1, 0x54),
654
+
QMP_PHY_INIT_CFG(QSERDES_V6_RX_VGA_CAL_CNTRL2, 0x0f),
655
+
QMP_PHY_INIT_CFG(QSERDES_V6_RX_GM_CAL, 0x13),
656
+
QMP_PHY_INIT_CFG(QSERDES_V6_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0f),
657
+
QMP_PHY_INIT_CFG(QSERDES_V6_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4a),
658
+
QMP_PHY_INIT_CFG(QSERDES_V6_RX_RX_EQU_ADAPTOR_CNTRL4, 0x0a),
659
+
QMP_PHY_INIT_CFG(QSERDES_V6_RX_RX_IDAC_TSETTLE_LOW, 0x07),
660
+
QMP_PHY_INIT_CFG(QSERDES_V6_RX_RX_IDAC_TSETTLE_HIGH, 0x00),
661
+
QMP_PHY_INIT_CFG(QSERDES_V6_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x47),
662
+
QMP_PHY_INIT_CFG(QSERDES_V6_RX_SIGDET_CNTRL, 0x04),
663
+
QMP_PHY_INIT_CFG(QSERDES_V6_RX_SIGDET_DEGLITCH_CNTRL, 0x0e),
664
+
QMP_PHY_INIT_CFG(QSERDES_V6_RX_RX_MODE_01_LOW, 0xdc),
665
+
QMP_PHY_INIT_CFG(QSERDES_V6_RX_RX_MODE_01_HIGH, 0x5c),
666
+
QMP_PHY_INIT_CFG(QSERDES_V6_RX_RX_MODE_01_HIGH2, 0x9c),
667
+
QMP_PHY_INIT_CFG(QSERDES_V6_RX_RX_MODE_01_HIGH3, 0x1d),
668
+
QMP_PHY_INIT_CFG(QSERDES_V6_RX_RX_MODE_01_HIGH4, 0x09),
669
+
QMP_PHY_INIT_CFG(QSERDES_V6_RX_DFE_EN_TIMER, 0x04),
670
+
QMP_PHY_INIT_CFG(QSERDES_V6_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38),
671
+
QMP_PHY_INIT_CFG(QSERDES_V6_RX_DCC_CTRL1, 0x0c),
672
+
QMP_PHY_INIT_CFG(QSERDES_V6_RX_VTH_CODE, 0x10),
673
+
QMP_PHY_INIT_CFG(QSERDES_V6_RX_SIGDET_CAL_CTRL1, 0x14),
674
+
QMP_PHY_INIT_CFG(QSERDES_V6_RX_SIGDET_CAL_TRIM, 0x08),
675
+
676
+
QMP_PHY_INIT_CFG_LANE(QSERDES_V6_RX_RX_MODE_00_LOW, 0x3f, 1),
677
+
QMP_PHY_INIT_CFG_LANE(QSERDES_V6_RX_RX_MODE_00_HIGH, 0xbf, 1),
678
+
QMP_PHY_INIT_CFG_LANE(QSERDES_V6_RX_RX_MODE_00_HIGH2, 0xff, 1),
679
+
QMP_PHY_INIT_CFG_LANE(QSERDES_V6_RX_RX_MODE_00_HIGH3, 0xdf, 1),
680
+
QMP_PHY_INIT_CFG_LANE(QSERDES_V6_RX_RX_MODE_00_HIGH4, 0xed, 1),
681
+
682
+
QMP_PHY_INIT_CFG_LANE(QSERDES_V6_RX_RX_MODE_00_LOW, 0xbf, 2),
683
+
QMP_PHY_INIT_CFG_LANE(QSERDES_V6_RX_RX_MODE_00_HIGH, 0xbf, 2),
684
+
QMP_PHY_INIT_CFG_LANE(QSERDES_V6_RX_RX_MODE_00_HIGH2, 0xbf, 2),
685
+
QMP_PHY_INIT_CFG_LANE(QSERDES_V6_RX_RX_MODE_00_HIGH3, 0xdf, 2),
686
+
QMP_PHY_INIT_CFG_LANE(QSERDES_V6_RX_RX_MODE_00_HIGH4, 0xfd, 2),
687
+
};
688
+
689
+
static const struct qmp_phy_init_tbl sm8550_usb3_pcs_tbl[] = {
690
+
QMP_PHY_INIT_CFG(QPHY_USB_V6_PCS_LOCK_DETECT_CONFIG1, 0xc4),
691
+
QMP_PHY_INIT_CFG(QPHY_USB_V6_PCS_LOCK_DETECT_CONFIG2, 0x89),
692
+
QMP_PHY_INIT_CFG(QPHY_USB_V6_PCS_LOCK_DETECT_CONFIG3, 0x20),
693
+
QMP_PHY_INIT_CFG(QPHY_USB_V6_PCS_LOCK_DETECT_CONFIG6, 0x13),
694
+
QMP_PHY_INIT_CFG(QPHY_USB_V6_PCS_REFGEN_REQ_CONFIG1, 0x21),
695
+
QMP_PHY_INIT_CFG(QPHY_USB_V6_PCS_RX_SIGDET_LVL, 0x99),
696
+
QMP_PHY_INIT_CFG(QPHY_USB_V6_PCS_RCVR_DTCT_DLY_P1U2_L, 0xe7),
697
+
QMP_PHY_INIT_CFG(QPHY_USB_V6_PCS_RCVR_DTCT_DLY_P1U2_H, 0x03),
698
+
QMP_PHY_INIT_CFG(QPHY_USB_V6_PCS_CDR_RESET_TIME, 0x0a),
699
+
QMP_PHY_INIT_CFG(QPHY_USB_V6_PCS_ALIGN_DETECT_CONFIG1, 0x88),
700
+
QMP_PHY_INIT_CFG(QPHY_USB_V6_PCS_ALIGN_DETECT_CONFIG2, 0x13),
701
+
QMP_PHY_INIT_CFG(QPHY_USB_V6_PCS_PCS_TX_RX_CONFIG, 0x0c),
702
+
QMP_PHY_INIT_CFG(QPHY_USB_V6_PCS_EQ_CONFIG1, 0x4b),
703
+
QMP_PHY_INIT_CFG(QPHY_USB_V6_PCS_EQ_CONFIG5, 0x10),
704
+
QMP_PHY_INIT_CFG(QPHY_USB_V6_PCS_USB3_POWER_STATE_CONFIG1, 0x68),
705
+
};
706
+
707
+
static const struct qmp_phy_init_tbl sm8550_usb3_pcs_usb_tbl[] = {
708
+
QMP_PHY_INIT_CFG(QPHY_USB_V6_PCS_USB3_LFPS_DET_HIGH_COUNT_VAL, 0xf8),
709
+
QMP_PHY_INIT_CFG(QPHY_USB_V6_PCS_USB3_RXEQTRAINING_DFE_TIME_S2, 0x07),
710
+
QMP_PHY_INIT_CFG(QPHY_USB_V6_PCS_USB3_RCVR_DTCT_DLY_U3_L, 0x40),
711
+
QMP_PHY_INIT_CFG(QPHY_USB_V6_PCS_USB3_RCVR_DTCT_DLY_U3_H, 0x00),
712
+
};
713
+
560
714
static const struct qmp_phy_init_tbl qmp_v4_dp_serdes_tbl[] = {
561
715
QMP_PHY_INIT_CFG(QSERDES_V4_COM_SVS_MODE_CLK_SEL, 0x05),
562
716
QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYSCLK_EN_SEL, 0x3b),
···
880
600
QMP_PHY_INIT_CFG(QSERDES_V4_COM_CORE_CLK_EN, 0x1f),
881
601
};
882
602
603
+
static const struct qmp_phy_init_tbl qmp_v5_dp_tx_tbl[] = {
604
+
QMP_PHY_INIT_CFG(QSERDES_V5_TX_VMODE_CTRL1, 0x40),
605
+
QMP_PHY_INIT_CFG(QSERDES_V5_TX_PRE_STALL_LDO_BOOST_EN, 0x30),
606
+
QMP_PHY_INIT_CFG(QSERDES_V5_TX_INTERFACE_SELECT, 0x3b),
607
+
QMP_PHY_INIT_CFG(QSERDES_V5_TX_CLKBUF_ENABLE, 0x0f),
608
+
QMP_PHY_INIT_CFG(QSERDES_V5_TX_RESET_TSYNC_EN, 0x03),
609
+
QMP_PHY_INIT_CFG(QSERDES_V5_TX_TRAN_DRVR_EMP_EN, 0x0f),
610
+
QMP_PHY_INIT_CFG(QSERDES_V5_TX_PARRATE_REC_DETECT_IDLE_EN, 0x00),
611
+
QMP_PHY_INIT_CFG(QSERDES_V5_TX_TX_INTERFACE_MODE, 0x00),
612
+
QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_OFFSET_TX, 0x11),
613
+
QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_OFFSET_RX, 0x11),
614
+
QMP_PHY_INIT_CFG(QSERDES_V5_TX_TX_BAND, 0x04),
615
+
};
616
+
883
617
static const struct qmp_phy_init_tbl qmp_v5_5nm_dp_tx_tbl[] = {
884
618
QMP_PHY_INIT_CFG(QSERDES_V5_5NM_TX_LANE_MODE_3, 0x51),
885
619
QMP_PHY_INIT_CFG(QSERDES_V5_5NM_TX_TRANSCEIVER_BIAS_EN, 0x1a),
···
907
613
QMP_PHY_INIT_CFG(QSERDES_V5_5NM_TX_RES_CODE_LANE_OFFSET_TX, 0x11),
908
614
QMP_PHY_INIT_CFG(QSERDES_V5_5NM_TX_RES_CODE_LANE_OFFSET_RX, 0x11),
909
615
QMP_PHY_INIT_CFG(QSERDES_V5_5NM_TX_TX_BAND, 0x01),
616
+
};
617
+
618
+
static const struct qmp_phy_init_tbl qmp_v6_dp_serdes_tbl[] = {
619
+
QMP_PHY_INIT_CFG(QSERDES_V6_COM_SVS_MODE_CLK_SEL, 0x15),
620
+
QMP_PHY_INIT_CFG(QSERDES_V6_COM_SYSCLK_EN_SEL, 0x3b),
621
+
QMP_PHY_INIT_CFG(QSERDES_V6_COM_SYS_CLK_CTRL, 0x02),
622
+
QMP_PHY_INIT_CFG(QSERDES_V6_COM_CLK_ENABLE1, 0x0c),
623
+
QMP_PHY_INIT_CFG(QSERDES_V6_COM_SYSCLK_BUF_ENABLE, 0x06),
624
+
QMP_PHY_INIT_CFG(QSERDES_V6_COM_CLK_SELECT, 0x30),
625
+
QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_IVCO, 0x0f),
626
+
QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_CCTRL_MODE0, 0x36),
627
+
QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_RCTRL_MODE0, 0x16),
628
+
QMP_PHY_INIT_CFG(QSERDES_V6_COM_CP_CTRL_MODE0, 0x06),
629
+
QMP_PHY_INIT_CFG(QSERDES_V6_COM_DIV_FRAC_START1_MODE0, 0x00),
630
+
QMP_PHY_INIT_CFG(QSERDES_V6_COM_CMN_CONFIG_1, 0x12),
631
+
QMP_PHY_INIT_CFG(QSERDES_V6_COM_INTEGLOOP_GAIN0_MODE0, 0x3f),
632
+
QMP_PHY_INIT_CFG(QSERDES_V6_COM_INTEGLOOP_GAIN1_MODE0, 0x00),
633
+
QMP_PHY_INIT_CFG(QSERDES_V6_COM_VCO_TUNE_MAP, 0x00),
634
+
QMP_PHY_INIT_CFG(QSERDES_V6_COM_BG_TIMER, 0x0a),
635
+
QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_CORE_CLK_DIV_MODE0, 0x14),
636
+
QMP_PHY_INIT_CFG(QSERDES_V6_COM_VCO_TUNE_CTRL, 0x00),
637
+
QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_BIAS_EN_CLK_BUFLR_EN, 0x17),
638
+
QMP_PHY_INIT_CFG(QSERDES_V6_COM_CORE_CLK_EN, 0x0f),
639
+
};
640
+
641
+
static const struct qmp_phy_init_tbl qmp_v6_dp_tx_tbl[] = {
642
+
QMP_PHY_INIT_CFG(QSERDES_V6_TX_VMODE_CTRL1, 0x40),
643
+
QMP_PHY_INIT_CFG(QSERDES_V6_TX_PRE_STALL_LDO_BOOST_EN, 0x30),
644
+
QMP_PHY_INIT_CFG(QSERDES_V6_TX_INTERFACE_SELECT, 0x3b),
645
+
QMP_PHY_INIT_CFG(QSERDES_V6_TX_CLKBUF_ENABLE, 0x0f),
646
+
QMP_PHY_INIT_CFG(QSERDES_V6_TX_RESET_TSYNC_EN, 0x03),
647
+
QMP_PHY_INIT_CFG(QSERDES_V6_TX_TRAN_DRVR_EMP_EN, 0x0f),
648
+
QMP_PHY_INIT_CFG(QSERDES_V6_TX_PARRATE_REC_DETECT_IDLE_EN, 0x00),
649
+
QMP_PHY_INIT_CFG(QSERDES_V6_TX_TX_INTERFACE_MODE, 0x00),
650
+
QMP_PHY_INIT_CFG(QSERDES_V6_TX_RES_CODE_LANE_OFFSET_TX, 0x0c),
651
+
QMP_PHY_INIT_CFG(QSERDES_V6_TX_RES_CODE_LANE_OFFSET_RX, 0x0c),
652
+
QMP_PHY_INIT_CFG(QSERDES_V6_TX_TX_BAND, 0x4),
653
+
};
654
+
655
+
static const struct qmp_phy_init_tbl qmp_v6_dp_serdes_tbl_rbr[] = {
656
+
QMP_PHY_INIT_CFG(QSERDES_V6_COM_HSCLK_SEL_1, 0x05),
657
+
QMP_PHY_INIT_CFG(QSERDES_V6_COM_DEC_START_MODE0, 0x34),
658
+
QMP_PHY_INIT_CFG(QSERDES_V6_COM_DIV_FRAC_START2_MODE0, 0xc0),
659
+
QMP_PHY_INIT_CFG(QSERDES_V6_COM_DIV_FRAC_START3_MODE0, 0x0b),
660
+
QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP1_MODE0, 0x37),
661
+
QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP2_MODE0, 0x04),
662
+
QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP_EN, 0x04),
663
+
QMP_PHY_INIT_CFG(QSERDES_V6_COM_BIN_VCOCAL_CMP_CODE1_MODE0, 0x71),
664
+
QMP_PHY_INIT_CFG(QSERDES_V6_COM_BIN_VCOCAL_CMP_CODE2_MODE0, 0x0c),
665
+
};
666
+
667
+
static const struct qmp_phy_init_tbl qmp_v6_dp_serdes_tbl_hbr[] = {
668
+
QMP_PHY_INIT_CFG(QSERDES_V6_COM_HSCLK_SEL_1, 0x03),
669
+
QMP_PHY_INIT_CFG(QSERDES_V6_COM_DEC_START_MODE0, 0x34),
670
+
QMP_PHY_INIT_CFG(QSERDES_V6_COM_DIV_FRAC_START2_MODE0, 0xc0),
671
+
QMP_PHY_INIT_CFG(QSERDES_V6_COM_DIV_FRAC_START3_MODE0, 0x0b),
672
+
QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP1_MODE0, 0x07),
673
+
QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP2_MODE0, 0x07),
674
+
QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP_EN, 0x08),
675
+
QMP_PHY_INIT_CFG(QSERDES_V6_COM_BIN_VCOCAL_CMP_CODE1_MODE0, 0x71),
676
+
QMP_PHY_INIT_CFG(QSERDES_V6_COM_BIN_VCOCAL_CMP_CODE2_MODE0, 0x0c),
677
+
};
678
+
679
+
static const struct qmp_phy_init_tbl qmp_v6_dp_serdes_tbl_hbr2[] = {
680
+
QMP_PHY_INIT_CFG(QSERDES_V6_COM_HSCLK_SEL_1, 0x01),
681
+
QMP_PHY_INIT_CFG(QSERDES_V6_COM_DEC_START_MODE0, 0x46),
682
+
QMP_PHY_INIT_CFG(QSERDES_V6_COM_DIV_FRAC_START2_MODE0, 0x00),
683
+
QMP_PHY_INIT_CFG(QSERDES_V6_COM_DIV_FRAC_START3_MODE0, 0x05),
684
+
QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP1_MODE0, 0x0f),
685
+
QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP2_MODE0, 0x0e),
686
+
QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP_EN, 0x08),
687
+
QMP_PHY_INIT_CFG(QSERDES_V6_COM_BIN_VCOCAL_CMP_CODE1_MODE0, 0x97),
688
+
QMP_PHY_INIT_CFG(QSERDES_V6_COM_BIN_VCOCAL_CMP_CODE2_MODE0, 0x10),
689
+
};
690
+
691
+
static const struct qmp_phy_init_tbl qmp_v6_dp_serdes_tbl_hbr3[] = {
692
+
QMP_PHY_INIT_CFG(QSERDES_V6_COM_HSCLK_SEL_1, 0x00),
693
+
QMP_PHY_INIT_CFG(QSERDES_V6_COM_DEC_START_MODE0, 0x34),
694
+
QMP_PHY_INIT_CFG(QSERDES_V6_COM_DIV_FRAC_START2_MODE0, 0xc0),
695
+
QMP_PHY_INIT_CFG(QSERDES_V6_COM_DIV_FRAC_START3_MODE0, 0x0b),
696
+
QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP1_MODE0, 0x17),
697
+
QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP2_MODE0, 0x15),
698
+
QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP_EN, 0x08),
699
+
QMP_PHY_INIT_CFG(QSERDES_V6_COM_BIN_VCOCAL_CMP_CODE1_MODE0, 0x71),
700
+
QMP_PHY_INIT_CFG(QSERDES_V6_COM_BIN_VCOCAL_CMP_CODE2_MODE0, 0x0c),
910
701
};
911
702
912
703
static const struct qmp_phy_init_tbl sc8280xp_usb43dp_serdes_tbl[] = {
···
1147
768
{ 0x1f, 0xff, 0xff, 0xff }
1148
769
};
1149
770
771
+
static const u8 qmp_dp_v4_pre_emphasis_hbr3_hbr2[4][4] = {
772
+
{ 0x00, 0x0c, 0x15, 0x1b },
773
+
{ 0x02, 0x0e, 0x16, 0xff },
774
+
{ 0x02, 0x11, 0xff, 0xff },
775
+
{ 0x04, 0xff, 0xff, 0xff }
776
+
};
777
+
778
+
static const u8 qmp_dp_v4_pre_emphasis_hbr_rbr[4][4] = {
779
+
{ 0x00, 0x0d, 0x14, 0x1a },
780
+
{ 0x00, 0x0e, 0x15, 0xff },
781
+
{ 0x00, 0x0d, 0xff, 0xff },
782
+
{ 0x03, 0xff, 0xff, 0xff }
783
+
};
784
+
785
+
static const u8 qmp_dp_v4_voltage_swing_hbr_rbr[4][4] = {
786
+
{ 0x08, 0x0f, 0x16, 0x1f },
787
+
{ 0x11, 0x1e, 0x1f, 0xff },
788
+
{ 0x16, 0x1f, 0xff, 0xff },
789
+
{ 0x1f, 0xff, 0xff, 0xff }
790
+
};
791
+
1150
792
static const u8 qmp_dp_v5_pre_emphasis_hbr3_hbr2[4][4] = {
1151
793
{ 0x20, 0x2c, 0x35, 0x3b },
1152
794
{ 0x22, 0x2e, 0x36, 0xff },
···
1196
796
{ 0x3f, 0xff, 0xff, 0xff }
1197
797
};
1198
798
799
+
static const u8 qmp_dp_v6_pre_emphasis_hbr_rbr[4][4] = {
800
+
{ 0x20, 0x2d, 0x34, 0x3a },
801
+
{ 0x20, 0x2e, 0x35, 0xff },
802
+
{ 0x20, 0x2e, 0xff, 0xff },
803
+
{ 0x22, 0xff, 0xff, 0xff }
804
+
};
805
+
1199
806
struct qmp_combo;
1200
807
1201
808
struct qmp_combo_offsets {
···
1216
809
u16 usb3_pcs;
1217
810
u16 usb3_pcs_usb;
1218
811
u16 dp_serdes;
812
+
u16 dp_txa;
813
+
u16 dp_txb;
1219
814
u16 dp_dp_phy;
1220
815
};
1221
816
···
1337
928
1338
929
static int qmp_v5_configure_dp_phy(struct qmp_combo *qmp);
1339
930
931
+
static void qmp_v6_dp_aux_init(struct qmp_combo *qmp);
932
+
static int qmp_v6_configure_dp_phy(struct qmp_combo *qmp);
933
+
1340
934
static inline void qphy_setbits(void __iomem *base, u32 offset, u32 val)
1341
935
{
1342
936
u32 reg;
···
1387
975
"phy",
1388
976
};
1389
977
978
+
static const struct qmp_combo_offsets qmp_combo_offsets_v3 = {
979
+
.com = 0x0000,
980
+
.txa = 0x1200,
981
+
.rxa = 0x1400,
982
+
.txb = 0x1600,
983
+
.rxb = 0x1800,
984
+
.usb3_serdes = 0x1000,
985
+
.usb3_pcs_misc = 0x1a00,
986
+
.usb3_pcs = 0x1c00,
987
+
.dp_serdes = 0x2000,
988
+
.dp_txa = 0x2200,
989
+
.dp_txb = 0x2600,
990
+
.dp_dp_phy = 0x2a00,
991
+
};
992
+
1390
993
static const struct qmp_combo_offsets qmp_combo_offsets_v5 = {
1391
994
.com = 0x0000,
1392
995
.txa = 0x0400,
···
1414
987
.usb3_pcs_usb = 0x1700,
1415
988
.dp_serdes = 0x2000,
1416
989
.dp_dp_phy = 0x2200,
990
+
};
991
+
992
+
static const struct qmp_combo_offsets qmp_combo_offsets_v6 = {
993
+
.com = 0x0000,
994
+
.txa = 0x1200,
995
+
.rxa = 0x1400,
996
+
.txb = 0x1600,
997
+
.rxb = 0x1800,
998
+
.usb3_serdes = 0x1000,
999
+
.usb3_pcs_misc = 0x1a00,
1000
+
.usb3_pcs = 0x1c00,
1001
+
.usb3_pcs_usb = 0x1f00,
1002
+
.dp_serdes = 0x2000,
1003
+
.dp_txa = 0x2200,
1004
+
.dp_txb = 0x2600,
1005
+
.dp_dp_phy = 0x2a00,
1417
1006
};
1418
1007
1419
1008
static const struct qmp_phy_cfg sc7180_usb3dpphy_cfg = {
···
1615
1172
.regs = qmp_v4_usb3phy_regs_layout,
1616
1173
};
1617
1174
1175
+
static const struct qmp_phy_cfg sm6350_usb3dpphy_cfg = {
1176
+
.offsets = &qmp_combo_offsets_v3,
1177
+
1178
+
.serdes_tbl = qmp_v3_usb3_serdes_tbl,
1179
+
.serdes_tbl_num = ARRAY_SIZE(qmp_v3_usb3_serdes_tbl),
1180
+
.tx_tbl = qmp_v3_usb3_tx_tbl,
1181
+
.tx_tbl_num = ARRAY_SIZE(qmp_v3_usb3_tx_tbl),
1182
+
.rx_tbl = sm6350_usb3_rx_tbl,
1183
+
.rx_tbl_num = ARRAY_SIZE(sm6350_usb3_rx_tbl),
1184
+
.pcs_tbl = sm6350_usb3_pcs_tbl,
1185
+
.pcs_tbl_num = ARRAY_SIZE(sm6350_usb3_pcs_tbl),
1186
+
1187
+
.dp_serdes_tbl = qmp_v3_dp_serdes_tbl,
1188
+
.dp_serdes_tbl_num = ARRAY_SIZE(qmp_v3_dp_serdes_tbl),
1189
+
.dp_tx_tbl = qmp_v3_dp_tx_tbl,
1190
+
.dp_tx_tbl_num = ARRAY_SIZE(qmp_v3_dp_tx_tbl),
1191
+
1192
+
.serdes_tbl_rbr = qmp_v3_dp_serdes_tbl_rbr,
1193
+
.serdes_tbl_rbr_num = ARRAY_SIZE(qmp_v3_dp_serdes_tbl_rbr),
1194
+
.serdes_tbl_hbr = qmp_v3_dp_serdes_tbl_hbr,
1195
+
.serdes_tbl_hbr_num = ARRAY_SIZE(qmp_v3_dp_serdes_tbl_hbr),
1196
+
.serdes_tbl_hbr2 = qmp_v3_dp_serdes_tbl_hbr2,
1197
+
.serdes_tbl_hbr2_num = ARRAY_SIZE(qmp_v3_dp_serdes_tbl_hbr2),
1198
+
.serdes_tbl_hbr3 = qmp_v3_dp_serdes_tbl_hbr3,
1199
+
.serdes_tbl_hbr3_num = ARRAY_SIZE(qmp_v3_dp_serdes_tbl_hbr3),
1200
+
1201
+
.swing_hbr_rbr = &qmp_dp_v3_voltage_swing_hbr_rbr,
1202
+
.pre_emphasis_hbr_rbr = &qmp_dp_v3_pre_emphasis_hbr_rbr,
1203
+
.swing_hbr3_hbr2 = &qmp_dp_v3_voltage_swing_hbr3_hbr2,
1204
+
.pre_emphasis_hbr3_hbr2 = &qmp_dp_v3_pre_emphasis_hbr3_hbr2,
1205
+
1206
+
.dp_aux_init = qmp_v3_dp_aux_init,
1207
+
.configure_dp_tx = qmp_v3_configure_dp_tx,
1208
+
.configure_dp_phy = qmp_v3_configure_dp_phy,
1209
+
.calibrate_dp_phy = qmp_v3_calibrate_dp_phy,
1210
+
1211
+
.clk_list = qmp_v4_phy_clk_l,
1212
+
.num_clks = ARRAY_SIZE(qmp_v4_phy_clk_l),
1213
+
.reset_list = msm8996_usb3phy_reset_l,
1214
+
.num_resets = ARRAY_SIZE(msm8996_usb3phy_reset_l),
1215
+
.vreg_list = qmp_phy_vreg_l,
1216
+
.num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
1217
+
.regs = qmp_v3_usb3phy_regs_layout,
1218
+
};
1219
+
1618
1220
static const struct qmp_phy_cfg sm8250_usb3dpphy_cfg = {
1619
1221
.serdes_tbl = sm8150_usb3_serdes_tbl,
1620
1222
.serdes_tbl_num = ARRAY_SIZE(sm8150_usb3_serdes_tbl),
···
1706
1218
.pcs_usb_offset = 0x300,
1707
1219
1708
1220
.has_pwrdn_delay = true,
1221
+
};
1222
+
1223
+
static const struct qmp_phy_cfg sm8350_usb3dpphy_cfg = {
1224
+
.offsets = &qmp_combo_offsets_v3,
1225
+
1226
+
.serdes_tbl = sm8150_usb3_serdes_tbl,
1227
+
.serdes_tbl_num = ARRAY_SIZE(sm8150_usb3_serdes_tbl),
1228
+
.tx_tbl = sm8350_usb3_tx_tbl,
1229
+
.tx_tbl_num = ARRAY_SIZE(sm8350_usb3_tx_tbl),
1230
+
.rx_tbl = sm8350_usb3_rx_tbl,
1231
+
.rx_tbl_num = ARRAY_SIZE(sm8350_usb3_rx_tbl),
1232
+
.pcs_tbl = sm8350_usb3_pcs_tbl,
1233
+
.pcs_tbl_num = ARRAY_SIZE(sm8350_usb3_pcs_tbl),
1234
+
.pcs_usb_tbl = sm8350_usb3_pcs_usb_tbl,
1235
+
.pcs_usb_tbl_num = ARRAY_SIZE(sm8350_usb3_pcs_usb_tbl),
1236
+
1237
+
.dp_serdes_tbl = qmp_v4_dp_serdes_tbl,
1238
+
.dp_serdes_tbl_num = ARRAY_SIZE(qmp_v4_dp_serdes_tbl),
1239
+
.dp_tx_tbl = qmp_v5_dp_tx_tbl,
1240
+
.dp_tx_tbl_num = ARRAY_SIZE(qmp_v5_dp_tx_tbl),
1241
+
1242
+
.serdes_tbl_rbr = qmp_v4_dp_serdes_tbl_rbr,
1243
+
.serdes_tbl_rbr_num = ARRAY_SIZE(qmp_v4_dp_serdes_tbl_rbr),
1244
+
.serdes_tbl_hbr = qmp_v4_dp_serdes_tbl_hbr,
1245
+
.serdes_tbl_hbr_num = ARRAY_SIZE(qmp_v4_dp_serdes_tbl_hbr),
1246
+
.serdes_tbl_hbr2 = qmp_v4_dp_serdes_tbl_hbr2,
1247
+
.serdes_tbl_hbr2_num = ARRAY_SIZE(qmp_v4_dp_serdes_tbl_hbr2),
1248
+
.serdes_tbl_hbr3 = qmp_v4_dp_serdes_tbl_hbr3,
1249
+
.serdes_tbl_hbr3_num = ARRAY_SIZE(qmp_v4_dp_serdes_tbl_hbr3),
1250
+
1251
+
.swing_hbr_rbr = &qmp_dp_v4_voltage_swing_hbr_rbr,
1252
+
.pre_emphasis_hbr_rbr = &qmp_dp_v4_pre_emphasis_hbr_rbr,
1253
+
.swing_hbr3_hbr2 = &qmp_dp_v3_voltage_swing_hbr3_hbr2,
1254
+
.pre_emphasis_hbr3_hbr2 = &qmp_dp_v4_pre_emphasis_hbr3_hbr2,
1255
+
1256
+
.dp_aux_init = qmp_v4_dp_aux_init,
1257
+
.configure_dp_tx = qmp_v4_configure_dp_tx,
1258
+
.configure_dp_phy = qmp_v4_configure_dp_phy,
1259
+
.calibrate_dp_phy = qmp_v4_calibrate_dp_phy,
1260
+
1261
+
.clk_list = qmp_v4_phy_clk_l,
1262
+
.num_clks = ARRAY_SIZE(qmp_v4_phy_clk_l),
1263
+
.reset_list = msm8996_usb3phy_reset_l,
1264
+
.num_resets = ARRAY_SIZE(msm8996_usb3phy_reset_l),
1265
+
.vreg_list = qmp_phy_vreg_l,
1266
+
.num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
1267
+
.regs = qmp_v4_usb3phy_regs_layout,
1268
+
1269
+
.has_pwrdn_delay = true,
1270
+
};
1271
+
1272
+
static const struct qmp_phy_cfg sm8550_usb3dpphy_cfg = {
1273
+
.offsets = &qmp_combo_offsets_v6,
1274
+
1275
+
.serdes_tbl = sm8550_usb3_serdes_tbl,
1276
+
.serdes_tbl_num = ARRAY_SIZE(sm8550_usb3_serdes_tbl),
1277
+
.tx_tbl = sm8550_usb3_tx_tbl,
1278
+
.tx_tbl_num = ARRAY_SIZE(sm8550_usb3_tx_tbl),
1279
+
.rx_tbl = sm8550_usb3_rx_tbl,
1280
+
.rx_tbl_num = ARRAY_SIZE(sm8550_usb3_rx_tbl),
1281
+
.pcs_tbl = sm8550_usb3_pcs_tbl,
1282
+
.pcs_tbl_num = ARRAY_SIZE(sm8550_usb3_pcs_tbl),
1283
+
.pcs_usb_tbl = sm8550_usb3_pcs_usb_tbl,
1284
+
.pcs_usb_tbl_num = ARRAY_SIZE(sm8550_usb3_pcs_usb_tbl),
1285
+
1286
+
.dp_serdes_tbl = qmp_v6_dp_serdes_tbl,
1287
+
.dp_serdes_tbl_num = ARRAY_SIZE(qmp_v6_dp_serdes_tbl),
1288
+
.dp_tx_tbl = qmp_v6_dp_tx_tbl,
1289
+
.dp_tx_tbl_num = ARRAY_SIZE(qmp_v6_dp_tx_tbl),
1290
+
1291
+
.serdes_tbl_rbr = qmp_v6_dp_serdes_tbl_rbr,
1292
+
.serdes_tbl_rbr_num = ARRAY_SIZE(qmp_v6_dp_serdes_tbl_rbr),
1293
+
.serdes_tbl_hbr = qmp_v6_dp_serdes_tbl_hbr,
1294
+
.serdes_tbl_hbr_num = ARRAY_SIZE(qmp_v6_dp_serdes_tbl_hbr),
1295
+
.serdes_tbl_hbr2 = qmp_v6_dp_serdes_tbl_hbr2,
1296
+
.serdes_tbl_hbr2_num = ARRAY_SIZE(qmp_v6_dp_serdes_tbl_hbr2),
1297
+
.serdes_tbl_hbr3 = qmp_v6_dp_serdes_tbl_hbr3,
1298
+
.serdes_tbl_hbr3_num = ARRAY_SIZE(qmp_v6_dp_serdes_tbl_hbr3),
1299
+
1300
+
.swing_hbr_rbr = &qmp_dp_v5_voltage_swing_hbr_rbr,
1301
+
.pre_emphasis_hbr_rbr = &qmp_dp_v6_pre_emphasis_hbr_rbr,
1302
+
.swing_hbr3_hbr2 = &qmp_dp_v5_voltage_swing_hbr3_hbr2,
1303
+
.pre_emphasis_hbr3_hbr2 = &qmp_dp_v5_pre_emphasis_hbr3_hbr2,
1304
+
1305
+
.dp_aux_init = qmp_v6_dp_aux_init,
1306
+
.configure_dp_tx = qmp_v4_configure_dp_tx,
1307
+
.configure_dp_phy = qmp_v6_configure_dp_phy,
1308
+
.calibrate_dp_phy = qmp_v4_calibrate_dp_phy,
1309
+
1310
+
.regs = qmp_v4_usb3phy_regs_layout,
1311
+
.clk_list = qmp_v4_phy_clk_l,
1312
+
.num_clks = ARRAY_SIZE(qmp_v4_phy_clk_l),
1313
+
.reset_list = msm8996_usb3phy_reset_l,
1314
+
.num_resets = ARRAY_SIZE(msm8996_usb3phy_reset_l),
1315
+
.vreg_list = qmp_phy_vreg_l,
1316
+
.num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
1709
1317
};
1710
1318
1711
1319
static void qmp_combo_configure_lane(void __iomem *base,
···
2114
1530
qmp->dp_dp_phy + QSERDES_V4_DP_PHY_AUX_INTERRUPT_MASK);
2115
1531
}
2116
1532
1533
+
static void qmp_v6_dp_aux_init(struct qmp_combo *qmp)
1534
+
{
1535
+
writel(DP_PHY_PD_CTL_PWRDN | DP_PHY_PD_CTL_PSR_PWRDN | DP_PHY_PD_CTL_AUX_PWRDN |
1536
+
DP_PHY_PD_CTL_PLL_PWRDN | DP_PHY_PD_CTL_DP_CLAMP_EN,
1537
+
qmp->dp_dp_phy + QSERDES_DP_PHY_PD_CTL);
1538
+
1539
+
/* Turn on BIAS current for PHY/PLL */
1540
+
writel(0x17, qmp->dp_serdes + QSERDES_V6_COM_PLL_BIAS_EN_CLK_BUFLR_EN);
1541
+
1542
+
writel(0x00, qmp->dp_dp_phy + QSERDES_DP_PHY_AUX_CFG0);
1543
+
writel(0x13, qmp->dp_dp_phy + QSERDES_DP_PHY_AUX_CFG1);
1544
+
writel(0xa4, qmp->dp_dp_phy + QSERDES_DP_PHY_AUX_CFG2);
1545
+
writel(0x00, qmp->dp_dp_phy + QSERDES_DP_PHY_AUX_CFG3);
1546
+
writel(0x0a, qmp->dp_dp_phy + QSERDES_DP_PHY_AUX_CFG4);
1547
+
writel(0x26, qmp->dp_dp_phy + QSERDES_DP_PHY_AUX_CFG5);
1548
+
writel(0x0a, qmp->dp_dp_phy + QSERDES_DP_PHY_AUX_CFG6);
1549
+
writel(0x03, qmp->dp_dp_phy + QSERDES_DP_PHY_AUX_CFG7);
1550
+
writel(0xb7, qmp->dp_dp_phy + QSERDES_DP_PHY_AUX_CFG8);
1551
+
writel(0x03, qmp->dp_dp_phy + QSERDES_DP_PHY_AUX_CFG9);
1552
+
qmp->dp_aux_cfg = 0;
1553
+
1554
+
writel(PHY_AUX_STOP_ERR_MASK | PHY_AUX_DEC_ERR_MASK |
1555
+
PHY_AUX_SYNC_ERR_MASK | PHY_AUX_ALIGN_ERR_MASK |
1556
+
PHY_AUX_REQ_ERR_MASK,
1557
+
qmp->dp_dp_phy + QSERDES_V4_DP_PHY_AUX_INTERRUPT_MASK);
1558
+
}
1559
+
2117
1560
static void qmp_v4_configure_dp_tx(struct qmp_combo *qmp)
2118
1561
{
2119
1562
/* Program default values before writing proper values */
···
2154
1543
QSERDES_V4_TX_TX_EMP_POST1_LVL);
2155
1544
}
2156
1545
2157
-
static int qmp_v45_configure_dp_phy(struct qmp_combo *qmp)
1546
+
static int qmp_v456_configure_dp_phy(struct qmp_combo *qmp,
1547
+
unsigned int com_resetm_ctrl_reg,
1548
+
unsigned int com_c_ready_status_reg,
1549
+
unsigned int dp_phy_status_reg)
2158
1550
{
2159
1551
const struct phy_configure_opts_dp *dp_opts = &qmp->dp_opts;
2160
1552
u32 phy_vco_div, status;
···
2204
1590
writel(0x01, qmp->dp_dp_phy + QSERDES_DP_PHY_CFG);
2205
1591
writel(0x09, qmp->dp_dp_phy + QSERDES_DP_PHY_CFG);
2206
1592
2207
-
writel(0x20, qmp->dp_serdes + QSERDES_V4_COM_RESETSM_CNTRL);
1593
+
writel(0x20, qmp->dp_serdes + com_resetm_ctrl_reg);
2208
1594
2209
-
if (readl_poll_timeout(qmp->dp_serdes + QSERDES_V4_COM_C_READY_STATUS,
1595
+
if (readl_poll_timeout(qmp->dp_serdes + com_c_ready_status_reg,
2210
1596
status,
2211
1597
((status & BIT(0)) > 0),
2212
1598
500,
···
2229
1615
2230
1616
writel(0x19, qmp->dp_dp_phy + QSERDES_DP_PHY_CFG);
2231
1617
2232
-
if (readl_poll_timeout(qmp->dp_dp_phy + QSERDES_V4_DP_PHY_STATUS,
1618
+
if (readl_poll_timeout(qmp->dp_dp_phy + dp_phy_status_reg,
2233
1619
status,
2234
1620
((status & BIT(0)) > 0),
2235
1621
500,
2236
1622
10000))
2237
1623
return -ETIMEDOUT;
2238
1624
2239
-
if (readl_poll_timeout(qmp->dp_dp_phy + QSERDES_V4_DP_PHY_STATUS,
1625
+
if (readl_poll_timeout(qmp->dp_dp_phy + dp_phy_status_reg,
2240
1626
status,
2241
1627
((status & BIT(1)) > 0),
2242
1628
500,
···
2254
1640
u32 status;
2255
1641
int ret;
2256
1642
2257
-
ret = qmp_v45_configure_dp_phy(qmp);
1643
+
ret = qmp_v456_configure_dp_phy(qmp, QSERDES_V4_COM_RESETSM_CNTRL,
1644
+
QSERDES_V4_COM_C_READY_STATUS,
1645
+
QSERDES_V4_DP_PHY_STATUS);
2258
1646
if (ret < 0)
2259
1647
return ret;
2260
1648
···
2318
1702
u32 status;
2319
1703
int ret;
2320
1704
2321
-
ret = qmp_v45_configure_dp_phy(qmp);
1705
+
ret = qmp_v456_configure_dp_phy(qmp, QSERDES_V4_COM_RESETSM_CNTRL,
1706
+
QSERDES_V4_COM_C_READY_STATUS,
1707
+
QSERDES_V4_DP_PHY_STATUS);
2322
1708
if (ret < 0)
2323
1709
return ret;
2324
1710
···
2365
1747
2366
1748
writel(0x20, qmp->dp_tx + QSERDES_V5_5NM_TX_TX_EMP_POST1_LVL);
2367
1749
writel(0x20, qmp->dp_tx2 + QSERDES_V5_5NM_TX_TX_EMP_POST1_LVL);
1750
+
1751
+
return 0;
1752
+
}
1753
+
1754
+
static int qmp_v6_configure_dp_phy(struct qmp_combo *qmp)
1755
+
{
1756
+
const struct phy_configure_opts_dp *dp_opts = &qmp->dp_opts;
1757
+
u32 bias0_en, drvr0_en, bias1_en, drvr1_en;
1758
+
bool reverse = false;
1759
+
u32 status;
1760
+
int ret;
1761
+
1762
+
ret = qmp_v456_configure_dp_phy(qmp, QSERDES_V6_COM_RESETSM_CNTRL,
1763
+
QSERDES_V6_COM_C_READY_STATUS,
1764
+
QSERDES_V6_DP_PHY_STATUS);
1765
+
if (ret < 0)
1766
+
return ret;
1767
+
1768
+
if (dp_opts->lanes == 1) {
1769
+
bias0_en = reverse ? 0x3e : 0x1a;
1770
+
drvr0_en = reverse ? 0x13 : 0x10;
1771
+
bias1_en = reverse ? 0x15 : 0x3e;
1772
+
drvr1_en = reverse ? 0x10 : 0x13;
1773
+
} else if (dp_opts->lanes == 2) {
1774
+
bias0_en = reverse ? 0x3f : 0x15;
1775
+
drvr0_en = 0x10;
1776
+
bias1_en = reverse ? 0x15 : 0x3f;
1777
+
drvr1_en = 0x10;
1778
+
} else {
1779
+
bias0_en = 0x3f;
1780
+
bias1_en = 0x3f;
1781
+
drvr0_en = 0x10;
1782
+
drvr1_en = 0x10;
1783
+
}
1784
+
1785
+
writel(drvr0_en, qmp->dp_tx + QSERDES_V4_TX_HIGHZ_DRVR_EN);
1786
+
writel(bias0_en, qmp->dp_tx + QSERDES_V4_TX_TRANSCEIVER_BIAS_EN);
1787
+
writel(drvr1_en, qmp->dp_tx2 + QSERDES_V4_TX_HIGHZ_DRVR_EN);
1788
+
writel(bias1_en, qmp->dp_tx2 + QSERDES_V4_TX_TRANSCEIVER_BIAS_EN);
1789
+
1790
+
writel(0x18, qmp->dp_dp_phy + QSERDES_DP_PHY_CFG);
1791
+
udelay(2000);
1792
+
writel(0x19, qmp->dp_dp_phy + QSERDES_DP_PHY_CFG);
1793
+
1794
+
if (readl_poll_timeout(qmp->dp_dp_phy + QSERDES_V6_DP_PHY_STATUS,
1795
+
status,
1796
+
((status & BIT(1)) > 0),
1797
+
500,
1798
+
10000))
1799
+
return -ETIMEDOUT;
1800
+
1801
+
writel(0x0a, qmp->dp_tx + QSERDES_V4_TX_TX_POL_INV);
1802
+
writel(0x0a, qmp->dp_tx2 + QSERDES_V4_TX_TX_POL_INV);
1803
+
1804
+
writel(0x27, qmp->dp_tx + QSERDES_V4_TX_TX_DRV_LVL);
1805
+
writel(0x27, qmp->dp_tx2 + QSERDES_V4_TX_TX_DRV_LVL);
1806
+
1807
+
writel(0x20, qmp->dp_tx + QSERDES_V4_TX_TX_EMP_POST1_LVL);
1808
+
writel(0x20, qmp->dp_tx2 + QSERDES_V4_TX_TX_EMP_POST1_LVL);
2368
1809
2369
1810
return 0;
2370
1811
}
···
3318
2641
qmp->pcs_usb = base + offs->usb3_pcs_usb;
3319
2642
3320
2643
qmp->dp_serdes = base + offs->dp_serdes;
3321
-
qmp->dp_tx = base + offs->txa;
3322
-
qmp->dp_tx2 = base + offs->txb;
2644
+
if (offs->dp_txa) {
2645
+
qmp->dp_tx = base + offs->dp_txa;
2646
+
qmp->dp_tx2 = base + offs->dp_txb;
2647
+
} else {
2648
+
qmp->dp_tx = base + offs->txa;
2649
+
qmp->dp_tx2 = base + offs->txb;
2650
+
}
3323
2651
qmp->dp_dp_phy = base + offs->dp_dp_phy;
3324
2652
3325
2653
qmp->pipe_clk = devm_clk_get(dev, "usb3_pipe");
···
3472
2790
.data = &sdm845_usb3dpphy_cfg,
3473
2791
},
3474
2792
{
2793
+
.compatible = "qcom,sm6350-qmp-usb3-dp-phy",
2794
+
.data = &sm6350_usb3dpphy_cfg,
2795
+
},
2796
+
{
3475
2797
.compatible = "qcom,sm8250-qmp-usb3-dp-phy",
3476
2798
.data = &sm8250_usb3dpphy_cfg,
2799
+
},
2800
+
{
2801
+
.compatible = "qcom,sm8350-qmp-usb3-dp-phy",
2802
+
.data = &sm8350_usb3dpphy_cfg,
2803
+
},
2804
+
{
2805
+
.compatible = "qcom,sm8450-qmp-usb3-dp-phy",
2806
+
.data = &sm8350_usb3dpphy_cfg,
2807
+
},
2808
+
{
2809
+
.compatible = "qcom,sm8550-qmp-usb3-dp-phy",
2810
+
.data = &sm8550_usb3dpphy_cfg,
3477
2811
},
3478
2812
{ }
3479
2813
};
+3
-3
drivers/phy/qualcomm/phy-qcom-qmp-pcie-msm8996.c
+3
-3
drivers/phy/qualcomm/phy-qcom-qmp-pcie-msm8996.c
···
84
84
[QPHY_COM_POWER_DOWN_CONTROL] = 0x404,
85
85
[QPHY_COM_START_CONTROL] = 0x408,
86
86
[QPHY_COM_PCS_READY_STATUS] = 0x448,
87
-
[QPHY_SW_RESET] = 0x00,
88
-
[QPHY_START_CTRL] = 0x08,
89
-
[QPHY_PCS_STATUS] = 0x174,
87
+
[QPHY_SW_RESET] = QPHY_V2_PCS_SW_RESET,
88
+
[QPHY_START_CTRL] = QPHY_V2_PCS_START_CONTROL,
89
+
[QPHY_PCS_STATUS] = QPHY_V2_PCS_PCI_PCS_STATUS,
90
90
};
91
91
92
92
static const struct qmp_phy_init_tbl msm8996_pcie_serdes_tbl[] = {
+535
-53
drivers/phy/qualcomm/phy-qcom-qmp-pcie.c
+535
-53
drivers/phy/qualcomm/phy-qcom-qmp-pcie.c
···
24
24
#include <linux/slab.h>
25
25
26
26
#include "phy-qcom-qmp.h"
27
+
#include "phy-qcom-qmp-pcs-misc-v3.h"
28
+
#include "phy-qcom-qmp-pcs-pcie-v4.h"
29
+
#include "phy-qcom-qmp-pcs-pcie-v4_20.h"
30
+
#include "phy-qcom-qmp-pcs-pcie-v5.h"
31
+
#include "phy-qcom-qmp-pcs-pcie-v5_20.h"
32
+
#include "phy-qcom-qmp-pcs-pcie-v6.h"
33
+
#include "phy-qcom-qmp-pcs-pcie-v6_20.h"
34
+
#include "phy-qcom-qmp-pcie-qhp.h"
27
35
28
36
/* QPHY_SW_RESET bit */
29
37
#define SW_RESET BIT(0)
···
82
74
QPHY_LAYOUT_SIZE
83
75
};
84
76
85
-
static const unsigned int ipq_pciephy_gen3_regs_layout[QPHY_LAYOUT_SIZE] = {
86
-
[QPHY_SW_RESET] = 0x00,
87
-
[QPHY_START_CTRL] = 0x44,
88
-
[QPHY_PCS_STATUS] = 0x14,
89
-
[QPHY_PCS_POWER_DOWN_CONTROL] = 0x40,
77
+
static const unsigned int pciephy_v2_regs_layout[QPHY_LAYOUT_SIZE] = {
78
+
[QPHY_SW_RESET] = QPHY_V2_PCS_SW_RESET,
79
+
[QPHY_START_CTRL] = QPHY_V2_PCS_START_CONTROL,
80
+
[QPHY_PCS_STATUS] = QPHY_V2_PCS_PCI_PCS_STATUS,
81
+
[QPHY_PCS_POWER_DOWN_CONTROL] = QPHY_V2_PCS_POWER_DOWN_CONTROL,
90
82
};
91
83
92
-
static const unsigned int pciephy_regs_layout[QPHY_LAYOUT_SIZE] = {
93
-
[QPHY_SW_RESET] = 0x00,
94
-
[QPHY_START_CTRL] = 0x08,
95
-
[QPHY_PCS_STATUS] = 0x174,
96
-
[QPHY_PCS_POWER_DOWN_CONTROL] = 0x04,
97
-
};
98
-
99
-
static const unsigned int sdm845_qmp_pciephy_regs_layout[QPHY_LAYOUT_SIZE] = {
100
-
[QPHY_SW_RESET] = 0x00,
101
-
[QPHY_START_CTRL] = 0x08,
102
-
[QPHY_PCS_STATUS] = 0x174,
103
-
[QPHY_PCS_POWER_DOWN_CONTROL] = 0x04,
84
+
static const unsigned int pciephy_v3_regs_layout[QPHY_LAYOUT_SIZE] = {
85
+
[QPHY_SW_RESET] = QPHY_V3_PCS_SW_RESET,
86
+
[QPHY_START_CTRL] = QPHY_V3_PCS_START_CONTROL,
87
+
[QPHY_PCS_STATUS] = QPHY_V3_PCS_PCS_STATUS,
88
+
[QPHY_PCS_POWER_DOWN_CONTROL] = QPHY_V3_PCS_POWER_DOWN_CONTROL,
104
89
};
105
90
106
91
static const unsigned int sdm845_qhp_pciephy_regs_layout[QPHY_LAYOUT_SIZE] = {
···
103
102
[QPHY_PCS_POWER_DOWN_CONTROL] = 0x04,
104
103
};
105
104
106
-
static const unsigned int sm8250_pcie_regs_layout[QPHY_LAYOUT_SIZE] = {
107
-
[QPHY_SW_RESET] = 0x00,
108
-
[QPHY_START_CTRL] = 0x44,
109
-
[QPHY_PCS_STATUS] = 0x14,
110
-
[QPHY_PCS_POWER_DOWN_CONTROL] = 0x40,
105
+
static const unsigned int pciephy_v4_regs_layout[QPHY_LAYOUT_SIZE] = {
106
+
[QPHY_SW_RESET] = QPHY_V4_PCS_SW_RESET,
107
+
[QPHY_START_CTRL] = QPHY_V4_PCS_START_CONTROL,
108
+
[QPHY_PCS_STATUS] = QPHY_V4_PCS_PCS_STATUS1,
109
+
[QPHY_PCS_POWER_DOWN_CONTROL] = QPHY_V4_PCS_POWER_DOWN_CONTROL,
110
+
};
111
+
112
+
static const unsigned int pciephy_v5_regs_layout[QPHY_LAYOUT_SIZE] = {
113
+
[QPHY_SW_RESET] = QPHY_V5_PCS_SW_RESET,
114
+
[QPHY_START_CTRL] = QPHY_V5_PCS_START_CONTROL,
115
+
[QPHY_PCS_STATUS] = QPHY_V5_PCS_PCS_STATUS1,
116
+
[QPHY_PCS_POWER_DOWN_CONTROL] = QPHY_V5_PCS_POWER_DOWN_CONTROL,
111
117
};
112
118
113
119
static const struct qmp_phy_init_tbl msm8998_pcie_serdes_tbl[] = {
···
1224
1216
QMP_PHY_INIT_CFG(QPHY_V4_20_PCS_LANE1_INSIG_MX_CTRL2, 0x00),
1225
1217
};
1226
1218
1227
-
static const struct qmp_phy_init_tbl sm8450_qmp_gen3x1_pcie_serdes_tbl[] = {
1219
+
static const struct qmp_phy_init_tbl sm8450_qmp_gen3_pcie_serdes_tbl[] = {
1228
1220
QMP_PHY_INIT_CFG(QSERDES_V5_COM_SYSCLK_EN_SEL, 0x08),
1229
1221
QMP_PHY_INIT_CFG(QSERDES_V5_COM_CLK_SELECT, 0x34),
1230
1222
QMP_PHY_INIT_CFG(QSERDES_V5_COM_CORECLK_DIV_MODE1, 0x08),
···
1258
1250
QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIN_VCOCAL_CMP_CODE1_MODE0, 0xca),
1259
1251
QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIN_VCOCAL_CMP_CODE2_MODE1, 0x18),
1260
1252
QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIN_VCOCAL_CMP_CODE1_MODE1, 0xa2),
1261
-
QMP_PHY_INIT_CFG(QSERDES_V5_COM_SYSCLK_BUF_ENABLE, 0x07),
1262
1253
QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_EN_CENTER, 0x01),
1263
1254
QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_PER1, 0x31),
1264
1255
QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_PER2, 0x01),
···
1268
1261
QMP_PHY_INIT_CFG(QSERDES_V5_COM_CLK_ENABLE1, 0x90),
1269
1262
};
1270
1263
1264
+
static const struct qmp_phy_init_tbl sm8450_qmp_gen3x1_pcie_rc_serdes_tbl[] = {
1265
+
QMP_PHY_INIT_CFG(QSERDES_V5_COM_SYSCLK_BUF_ENABLE, 0x07),
1266
+
};
1267
+
1271
1268
static const struct qmp_phy_init_tbl sm8450_qmp_gen3x1_pcie_tx_tbl[] = {
1272
1269
QMP_PHY_INIT_CFG(QSERDES_V5_TX_PI_QEC_CTRL, 0x20),
1273
1270
QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_1, 0x75),
···
1280
1269
QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_OFFSET_RX, 0x04),
1281
1270
};
1282
1271
1283
-
static const struct qmp_phy_init_tbl sm8450_qmp_gen3x1_pcie_rx_tbl[] = {
1272
+
static const struct qmp_phy_init_tbl sm8450_qmp_gen3_pcie_rx_tbl[] = {
1284
1273
QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_LOW, 0x7f),
1285
1274
QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH, 0xff),
1286
-
QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH2, 0xbf),
1287
-
QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH3, 0x3f),
1288
1275
QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH4, 0xd8),
1289
1276
QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_LOW, 0xdc),
1290
1277
QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH, 0xdc),
···
1290
1281
QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH3, 0x34),
1291
1282
QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH4, 0xa6),
1292
1283
QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_10_HIGH3, 0x34),
1293
-
QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_10_HIGH4, 0x38),
1294
-
QMP_PHY_INIT_CFG(QSERDES_V5_RX_VGA_CAL_CNTRL2, 0x07),
1295
1284
QMP_PHY_INIT_CFG(QSERDES_V5_RX_GM_CAL, 0x00),
1296
1285
QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_THRESH1, 0x08),
1297
1286
QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_THRESH2, 0x08),
1298
-
QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_PI_CONTROLS, 0xf0),
1299
1287
QMP_PHY_INIT_CFG(QSERDES_V5_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38),
1300
1288
QMP_PHY_INIT_CFG(QSERDES_V5_RX_TX_ADAPT_POST_THRESH, 0xf0),
1289
+
};
1290
+
1291
+
static const struct qmp_phy_init_tbl sm8450_qmp_gen3x1_pcie_rc_rx_tbl[] = {
1292
+
QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH2, 0xbf),
1293
+
QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH3, 0x3f),
1294
+
QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_10_HIGH4, 0x38),
1295
+
QMP_PHY_INIT_CFG(QSERDES_V5_RX_VGA_CAL_CNTRL2, 0x07),
1296
+
QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_PI_CONTROLS, 0xf0),
1301
1297
QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL4, 0x07),
1302
1298
QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FO_GAIN, 0x09),
1303
1299
QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SO_GAIN, 0x05),
1304
1300
};
1305
1301
1306
-
static const struct qmp_phy_init_tbl sm8450_qmp_gen3x1_pcie_pcs_tbl[] = {
1302
+
static const struct qmp_phy_init_tbl sm8450_qmp_gen3_pcie_pcs_tbl[] = {
1307
1303
QMP_PHY_INIT_CFG(QPHY_V5_PCS_RX_SIGDET_LVL, 0x77),
1308
1304
QMP_PHY_INIT_CFG(QPHY_V5_PCS_RATE_SLEW_CNTRL1, 0x0b),
1309
1305
QMP_PHY_INIT_CFG(QPHY_V5_PCS_REFGEN_REQ_CONFIG1, 0x05),
···
1319
1305
QMP_PHY_INIT_CFG(QPHY_V5_PCS_PCIE_INT_AUX_CLK_CONFIG1, 0x00),
1320
1306
QMP_PHY_INIT_CFG(QPHY_V5_PCS_PCIE_EQ_CONFIG2, 0x0f),
1321
1307
QMP_PHY_INIT_CFG(QPHY_V5_PCS_PCIE_ENDPOINT_REFCLK_DRIVE, 0xc1),
1308
+
};
1309
+
1310
+
static const struct qmp_phy_init_tbl sm8350_qmp_gen3x1_pcie_tx_tbl[] = {
1311
+
QMP_PHY_INIT_CFG(QSERDES_V5_TX_PI_QEC_CTRL, 0x20),
1312
+
QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_1, 0x75),
1313
+
QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_4, 0x3f),
1314
+
QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_OFFSET_TX, 0x1d),
1315
+
QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_OFFSET_RX, 0x0c),
1316
+
};
1317
+
1318
+
static const struct qmp_phy_init_tbl sm8350_qmp_gen3x1_pcie_rc_rx_tbl[] = {
1319
+
QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH2, 0xbf),
1320
+
QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH3, 0x3f),
1321
+
QMP_PHY_INIT_CFG(QSERDES_V5_RX_VGA_CAL_CNTRL2, 0x07),
1322
+
QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_PI_CONTROLS, 0xf0),
1323
+
};
1324
+
1325
+
static const struct qmp_phy_init_tbl sm8350_qmp_gen3x2_pcie_rc_rx_tbl[] = {
1326
+
QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH2, 0x7f),
1327
+
QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH3, 0x34),
1328
+
QMP_PHY_INIT_CFG(QSERDES_V5_RX_VGA_CAL_CNTRL2, 0x0f),
1329
+
};
1330
+
1331
+
static const struct qmp_phy_init_tbl sm8350_qmp_gen3x2_pcie_tx_tbl[] = {
1332
+
QMP_PHY_INIT_CFG_LANE(QSERDES_V5_TX_PI_QEC_CTRL, 0x02, 1),
1333
+
QMP_PHY_INIT_CFG_LANE(QSERDES_V5_TX_PI_QEC_CTRL, 0x04, 2),
1334
+
QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_1, 0xd5),
1335
+
QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_4, 0x3f),
1336
+
QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_OFFSET_TX, 0x1d),
1337
+
QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_OFFSET_RX, 0x0c),
1338
+
};
1339
+
1340
+
static const struct qmp_phy_init_tbl sm8350_qmp_gen3x2_pcie_rc_pcs_tbl[] = {
1341
+
QMP_PHY_INIT_CFG(QPHY_V5_PCS_EQ_CONFIG2, 0x0f),
1322
1342
};
1323
1343
1324
1344
static const struct qmp_phy_init_tbl sm8450_qmp_gen4x2_pcie_serdes_tbl[] = {
···
1506
1458
QMP_PHY_INIT_CFG(QPHY_V5_20_PCS_PCIE_OSC_DTCT_MODE2_CONFIG5, 0x08),
1507
1459
};
1508
1460
1461
+
static const struct qmp_phy_init_tbl sm8550_qmp_gen3x2_pcie_serdes_tbl[] = {
1462
+
QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_EN_CENTER, 0x01),
1463
+
QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_PER1, 0x62),
1464
+
QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_PER2, 0x02),
1465
+
QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_STEP_SIZE1_MODE0, 0xf8),
1466
+
QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_STEP_SIZE2_MODE0, 0x01),
1467
+
QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_STEP_SIZE1_MODE1, 0x93),
1468
+
QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_STEP_SIZE2_MODE1, 0x01),
1469
+
QMP_PHY_INIT_CFG(QSERDES_V6_COM_CLK_ENABLE1, 0x90),
1470
+
QMP_PHY_INIT_CFG(QSERDES_V6_COM_SYS_CLK_CTRL, 0x82),
1471
+
QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_IVCO, 0x07),
1472
+
QMP_PHY_INIT_CFG(QSERDES_V6_COM_CP_CTRL_MODE0, 0x02),
1473
+
QMP_PHY_INIT_CFG(QSERDES_V6_COM_CP_CTRL_MODE1, 0x02),
1474
+
QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_RCTRL_MODE0, 0x16),
1475
+
QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_RCTRL_MODE1, 0x16),
1476
+
QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_CCTRL_MODE0, 0x36),
1477
+
QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_CCTRL_MODE1, 0x36),
1478
+
QMP_PHY_INIT_CFG(QSERDES_V6_COM_SYSCLK_EN_SEL, 0x08),
1479
+
QMP_PHY_INIT_CFG(QSERDES_V6_COM_BG_TIMER, 0x0a),
1480
+
QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP_EN, 0x42),
1481
+
QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP1_MODE0, 0x04),
1482
+
QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP2_MODE0, 0x0d),
1483
+
QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP1_MODE1, 0x0a),
1484
+
QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP2_MODE1, 0x1a),
1485
+
QMP_PHY_INIT_CFG(QSERDES_V6_COM_DEC_START_MODE0, 0x41),
1486
+
QMP_PHY_INIT_CFG(QSERDES_V6_COM_DEC_START_MODE1, 0x34),
1487
+
QMP_PHY_INIT_CFG(QSERDES_V6_COM_DIV_FRAC_START1_MODE0, 0xab),
1488
+
QMP_PHY_INIT_CFG(QSERDES_V6_COM_DIV_FRAC_START2_MODE0, 0xaa),
1489
+
QMP_PHY_INIT_CFG(QSERDES_V6_COM_DIV_FRAC_START3_MODE0, 0x01),
1490
+
QMP_PHY_INIT_CFG(QSERDES_V6_COM_DIV_FRAC_START1_MODE1, 0x55),
1491
+
QMP_PHY_INIT_CFG(QSERDES_V6_COM_DIV_FRAC_START2_MODE1, 0x55),
1492
+
QMP_PHY_INIT_CFG(QSERDES_V6_COM_DIV_FRAC_START3_MODE1, 0x01),
1493
+
QMP_PHY_INIT_CFG(QSERDES_V6_COM_VCO_TUNE_MAP, 0x14),
1494
+
QMP_PHY_INIT_CFG(QSERDES_V6_COM_CLK_SELECT, 0x34),
1495
+
QMP_PHY_INIT_CFG(QSERDES_V6_COM_HSCLK_SEL_1, 0x01),
1496
+
QMP_PHY_INIT_CFG(QSERDES_V6_COM_CORECLK_DIV_MODE1, 0x04),
1497
+
QMP_PHY_INIT_CFG(QSERDES_V6_COM_CMN_CONFIG_1, 0x16),
1498
+
QMP_PHY_INIT_CFG(QSERDES_V6_COM_ADDITIONAL_MISC_3, 0x0f),
1499
+
QMP_PHY_INIT_CFG(QSERDES_V6_COM_CORE_CLK_EN, 0xa0),
1500
+
};
1501
+
1502
+
static const struct qmp_phy_init_tbl sm8550_qmp_gen3x2_pcie_tx_tbl[] = {
1503
+
QMP_PHY_INIT_CFG(QSERDES_V6_TX_LANE_MODE_1, 0x15),
1504
+
QMP_PHY_INIT_CFG(QSERDES_V6_TX_LANE_MODE_4, 0x3f),
1505
+
QMP_PHY_INIT_CFG(QSERDES_V6_TX_PI_QEC_CTRL, 0x02),
1506
+
QMP_PHY_INIT_CFG(QSERDES_V6_TX_RES_CODE_LANE_OFFSET_RX, 0x06),
1507
+
QMP_PHY_INIT_CFG(QSERDES_V6_TX_RES_CODE_LANE_OFFSET_TX, 0x18),
1508
+
};
1509
+
1510
+
static const struct qmp_phy_init_tbl sm8550_qmp_gen3x2_pcie_rx_tbl[] = {
1511
+
QMP_PHY_INIT_CFG(QSERDES_V6_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38),
1512
+
QMP_PHY_INIT_CFG(QSERDES_V6_RX_GM_CAL, 0x11),
1513
+
QMP_PHY_INIT_CFG(QSERDES_V6_RX_RX_MODE_00_HIGH, 0xbf),
1514
+
QMP_PHY_INIT_CFG(QSERDES_V6_RX_RX_MODE_00_HIGH2, 0xbf),
1515
+
QMP_PHY_INIT_CFG(QSERDES_V6_RX_RX_MODE_00_HIGH3, 0xb7),
1516
+
QMP_PHY_INIT_CFG(QSERDES_V6_RX_RX_MODE_00_HIGH4, 0xea),
1517
+
QMP_PHY_INIT_CFG(QSERDES_V6_RX_RX_MODE_00_LOW, 0x3f),
1518
+
QMP_PHY_INIT_CFG(QSERDES_V6_RX_RX_MODE_01_HIGH, 0x5c),
1519
+
QMP_PHY_INIT_CFG(QSERDES_V6_RX_RX_MODE_01_HIGH2, 0x9c),
1520
+
QMP_PHY_INIT_CFG(QSERDES_V6_RX_RX_MODE_01_HIGH3, 0x1a),
1521
+
QMP_PHY_INIT_CFG(QSERDES_V6_RX_RX_MODE_01_HIGH4, 0x89),
1522
+
QMP_PHY_INIT_CFG(QSERDES_V6_RX_RX_MODE_01_LOW, 0xdc),
1523
+
QMP_PHY_INIT_CFG(QSERDES_V6_RX_RX_MODE_10_HIGH, 0x94),
1524
+
QMP_PHY_INIT_CFG(QSERDES_V6_RX_RX_MODE_10_HIGH2, 0x5b),
1525
+
QMP_PHY_INIT_CFG(QSERDES_V6_RX_RX_MODE_10_HIGH3, 0x1a),
1526
+
QMP_PHY_INIT_CFG(QSERDES_V6_RX_RX_MODE_10_HIGH4, 0x89),
1527
+
QMP_PHY_INIT_CFG(QSERDES_V6_RX_TX_ADAPT_POST_THRESH, 0xf0),
1528
+
QMP_PHY_INIT_CFG(QSERDES_V6_RX_UCDR_FO_GAIN, 0x09),
1529
+
QMP_PHY_INIT_CFG(QSERDES_V6_RX_UCDR_SO_GAIN, 0x05),
1530
+
QMP_PHY_INIT_CFG(QSERDES_V6_RX_UCDR_SB2_THRESH1, 0x08),
1531
+
QMP_PHY_INIT_CFG(QSERDES_V6_RX_UCDR_SB2_THRESH2, 0x08),
1532
+
QMP_PHY_INIT_CFG(QSERDES_V6_RX_VGA_CAL_CNTRL2, 0x0f),
1533
+
QMP_PHY_INIT_CFG(QSERDES_V6_RX_SIDGET_ENABLES, 0x1c),
1534
+
QMP_PHY_INIT_CFG(QSERDES_V6_RX_RX_IDAC_TSETTLE_LOW, 0x07),
1535
+
QMP_PHY_INIT_CFG(QSERDES_V6_RX_SIGDET_CAL_TRIM, 0x08),
1536
+
};
1537
+
1538
+
static const struct qmp_phy_init_tbl sm8550_qmp_gen3x2_pcie_pcs_tbl[] = {
1539
+
QMP_PHY_INIT_CFG(QPHY_V6_PCS_REFGEN_REQ_CONFIG1, 0x05),
1540
+
QMP_PHY_INIT_CFG(QPHY_V6_PCS_RX_SIGDET_LVL, 0x77),
1541
+
QMP_PHY_INIT_CFG(QPHY_V6_PCS_RATE_SLEW_CNTRL1, 0x0b),
1542
+
QMP_PHY_INIT_CFG(QPHY_V6_PCS_EQ_CONFIG2, 0x0f),
1543
+
QMP_PHY_INIT_CFG(QPHY_V6_PCS_PCS_TX_RX_CONFIG, 0x8c),
1544
+
};
1545
+
1546
+
static const struct qmp_phy_init_tbl sm8550_qmp_gen3x2_pcie_pcs_misc_tbl[] = {
1547
+
QMP_PHY_INIT_CFG(QPHY_PCIE_V6_PCS_PCIE_POWER_STATE_CONFIG2, 0x1d),
1548
+
QMP_PHY_INIT_CFG(QPHY_PCIE_V6_PCS_PCIE_POWER_STATE_CONFIG4, 0x07),
1549
+
QMP_PHY_INIT_CFG(QPHY_PCIE_V6_PCS_PCIE_ENDPOINT_REFCLK_DRIVE, 0xc1),
1550
+
QMP_PHY_INIT_CFG(QPHY_PCIE_V6_PCS_PCIE_OSC_DTCT_ACTIONS, 0x00),
1551
+
};
1552
+
1553
+
static const struct qmp_phy_init_tbl sm8550_qmp_gen4x2_pcie_serdes_tbl[] = {
1554
+
QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_STEP_SIZE1_MODE1, 0x26),
1555
+
QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_STEP_SIZE2_MODE1, 0x03),
1556
+
QMP_PHY_INIT_CFG(QSERDES_V6_COM_CP_CTRL_MODE1, 0x06),
1557
+
QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_RCTRL_MODE1, 0x16),
1558
+
QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_CCTRL_MODE1, 0x36),
1559
+
QMP_PHY_INIT_CFG(QSERDES_V6_COM_CORECLK_DIV_MODE1, 0x04),
1560
+
QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP1_MODE1, 0x0a),
1561
+
QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP2_MODE1, 0x1a),
1562
+
QMP_PHY_INIT_CFG(QSERDES_V6_COM_DEC_START_MODE1, 0x68),
1563
+
QMP_PHY_INIT_CFG(QSERDES_V6_COM_DIV_FRAC_START1_MODE1, 0xab),
1564
+
QMP_PHY_INIT_CFG(QSERDES_V6_COM_DIV_FRAC_START2_MODE1, 0xaa),
1565
+
QMP_PHY_INIT_CFG(QSERDES_V6_COM_DIV_FRAC_START3_MODE1, 0x02),
1566
+
QMP_PHY_INIT_CFG(QSERDES_V6_COM_HSCLK_SEL_1, 0x12),
1567
+
QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_STEP_SIZE1_MODE0, 0xf8),
1568
+
QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_STEP_SIZE2_MODE0, 0x01),
1569
+
QMP_PHY_INIT_CFG(QSERDES_V6_COM_CP_CTRL_MODE0, 0x06),
1570
+
QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_RCTRL_MODE0, 0x16),
1571
+
QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_CCTRL_MODE0, 0x36),
1572
+
QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_CORE_CLK_DIV_MODE0, 0x0a),
1573
+
QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP1_MODE0, 0x04),
1574
+
QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP2_MODE0, 0x0d),
1575
+
QMP_PHY_INIT_CFG(QSERDES_V6_COM_DEC_START_MODE0, 0x41),
1576
+
QMP_PHY_INIT_CFG(QSERDES_V6_COM_DIV_FRAC_START1_MODE0, 0xab),
1577
+
QMP_PHY_INIT_CFG(QSERDES_V6_COM_DIV_FRAC_START2_MODE0, 0xaa),
1578
+
QMP_PHY_INIT_CFG(QSERDES_V6_COM_DIV_FRAC_START3_MODE0, 0x01),
1579
+
QMP_PHY_INIT_CFG(QSERDES_V6_COM_HSCLK_HS_SWITCH_SEL_1, 0x00),
1580
+
QMP_PHY_INIT_CFG(QSERDES_V6_COM_BG_TIMER, 0x0a),
1581
+
QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_EN_CENTER, 0x01),
1582
+
QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_PER1, 0x62),
1583
+
QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_PER2, 0x02),
1584
+
QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_POST_DIV_MUX, 0x40),
1585
+
QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_BIAS_EN_CLK_BUFLR_EN, 0x14),
1586
+
QMP_PHY_INIT_CFG(QSERDES_V6_COM_CLK_ENABLE1, 0x90),
1587
+
QMP_PHY_INIT_CFG(QSERDES_V6_COM_SYS_CLK_CTRL, 0x82),
1588
+
QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_IVCO, 0x0f),
1589
+
QMP_PHY_INIT_CFG(QSERDES_V6_COM_SYSCLK_EN_SEL, 0x08),
1590
+
QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP_EN, 0x46),
1591
+
QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP_CFG, 0x04),
1592
+
QMP_PHY_INIT_CFG(QSERDES_V6_COM_VCO_TUNE_MAP, 0x14),
1593
+
QMP_PHY_INIT_CFG(QSERDES_V6_COM_CLK_SELECT, 0x34),
1594
+
QMP_PHY_INIT_CFG(QSERDES_V6_COM_CORE_CLK_EN, 0xa0),
1595
+
QMP_PHY_INIT_CFG(QSERDES_V6_COM_CMN_CONFIG_1, 0x06),
1596
+
QMP_PHY_INIT_CFG(QSERDES_V6_COM_CMN_MISC_1, 0x88),
1597
+
QMP_PHY_INIT_CFG(QSERDES_V6_COM_CMN_MODE, 0x14),
1598
+
QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_VCO_DC_LEVEL_CTRL, 0x0f),
1599
+
};
1600
+
1601
+
static const struct qmp_phy_init_tbl sm8550_qmp_gen4x2_pcie_ln_shrd_tbl[] = {
1602
+
QMP_PHY_INIT_CFG(QSERDES_V6_LN_SHRD_RXCLK_DIV2_CTRL, 0x01),
1603
+
QMP_PHY_INIT_CFG(QSERDES_V6_LN_SHRD_RX_Q_EN_RATES, 0xe),
1604
+
QMP_PHY_INIT_CFG(QSERDES_V6_LN_SHRD_DFE_DAC_ENABLE1, 0x00),
1605
+
QMP_PHY_INIT_CFG(QSERDES_V6_LN_SHRD_TX_ADAPT_POST_THRESH1, 0x00),
1606
+
QMP_PHY_INIT_CFG(QSERDES_V6_LN_SHRD_TX_ADAPT_POST_THRESH2, 0x1f),
1607
+
QMP_PHY_INIT_CFG(QSERDES_V6_LN_SHRD_RX_MODE_RATE_0_1_B0, 0x12),
1608
+
QMP_PHY_INIT_CFG(QSERDES_V6_LN_SHRD_RX_MODE_RATE_0_1_B1, 0x12),
1609
+
QMP_PHY_INIT_CFG(QSERDES_V6_LN_SHRD_RX_MODE_RATE_0_1_B2, 0xdb),
1610
+
QMP_PHY_INIT_CFG(QSERDES_V6_LN_SHRD_RX_MODE_RATE_0_1_B3, 0x9a),
1611
+
QMP_PHY_INIT_CFG(QSERDES_V6_LN_SHRD_RX_MODE_RATE_0_1_B4, 0x38),
1612
+
QMP_PHY_INIT_CFG(QSERDES_V6_LN_SHRD_RX_MODE_RATE_0_1_B5, 0xb6),
1613
+
QMP_PHY_INIT_CFG(QSERDES_V6_LN_SHRD_RX_MODE_RATE_0_1_B6, 0x64),
1614
+
QMP_PHY_INIT_CFG(QSERDES_V6_LN_SHRD_RX_MARG_COARSE_THRESH1_RATE210, 0x1f),
1615
+
QMP_PHY_INIT_CFG(QSERDES_V6_LN_SHRD_RX_MARG_COARSE_THRESH1_RATE3, 0x1f),
1616
+
QMP_PHY_INIT_CFG(QSERDES_V6_LN_SHRD_RX_MARG_COARSE_THRESH2_RATE210, 0x1f),
1617
+
QMP_PHY_INIT_CFG(QSERDES_V6_LN_SHRD_RX_MARG_COARSE_THRESH2_RATE3, 0x1f),
1618
+
QMP_PHY_INIT_CFG(QSERDES_V6_LN_SHRD_RX_MARG_COARSE_THRESH3_RATE210, 0x1f),
1619
+
QMP_PHY_INIT_CFG(QSERDES_V6_LN_SHRD_RX_MARG_COARSE_THRESH3_RATE3, 0x1f),
1620
+
QMP_PHY_INIT_CFG(QSERDES_V6_LN_SHRD_RX_MARG_COARSE_THRESH4_RATE3, 0x1f),
1621
+
QMP_PHY_INIT_CFG(QSERDES_V6_LN_SHRD_RX_MARG_COARSE_THRESH5_RATE3, 0x1f),
1622
+
QMP_PHY_INIT_CFG(QSERDES_V6_LN_SHRD_RX_MARG_COARSE_THRESH6_RATE3, 0x1f),
1623
+
};
1624
+
1625
+
static const struct qmp_phy_init_tbl sm8550_qmp_gen4x2_pcie_tx_tbl[] = {
1626
+
QMP_PHY_INIT_CFG(QSERDES_V6_20_TX_RES_CODE_LANE_OFFSET_TX, 0x1d),
1627
+
QMP_PHY_INIT_CFG(QSERDES_V6_20_TX_RES_CODE_LANE_OFFSET_RX, 0x03),
1628
+
QMP_PHY_INIT_CFG(QSERDES_V6_20_TX_LANE_MODE_1, 0x01),
1629
+
QMP_PHY_INIT_CFG(QSERDES_V6_20_TX_LANE_MODE_2, 0x00),
1630
+
QMP_PHY_INIT_CFG(QSERDES_V6_20_TX_LANE_MODE_3, 0x51),
1631
+
QMP_PHY_INIT_CFG(QSERDES_V6_20_TX_TRAN_DRVR_EMP_EN, 0x34),
1632
+
};
1633
+
1634
+
static const struct qmp_phy_init_tbl sm8550_qmp_gen4x2_pcie_rx_tbl[] = {
1635
+
QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_UCDR_FO_GAIN_RATE_2, 0x0a),
1636
+
QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_UCDR_FO_GAIN_RATE_3, 0x0a),
1637
+
QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_UCDR_PI_CONTROLS, 0x16),
1638
+
QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_UCDR_SO_ACC_DEFAULT_VAL_RATE3, 0x00),
1639
+
QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_IVCM_CAL_CTRL2, 0x80),
1640
+
QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_IVCM_POSTCAL_OFFSET, 0x7c),
1641
+
QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_DFE_3, 0x05),
1642
+
QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_VGA_CAL_MAN_VAL, 0x0a),
1643
+
QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_GM_CAL, 0x0d),
1644
+
QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_EQU_ADAPTOR_CNTRL4, 0x0b),
1645
+
QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_SIGDET_ENABLES, 0x1c),
1646
+
QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_PHPRE_CTRL, 0x20),
1647
+
QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_DFE_CTLE_POST_CAL_OFFSET, 0x30),
1648
+
QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_Q_PI_INTRINSIC_BIAS_RATE32, 0x09),
1649
+
QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_MODE_RATE2_B0, 0x14),
1650
+
QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_MODE_RATE2_B1, 0xb3),
1651
+
QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_MODE_RATE2_B2, 0x58),
1652
+
QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_MODE_RATE2_B3, 0x9a),
1653
+
QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_MODE_RATE2_B4, 0x26),
1654
+
QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_MODE_RATE2_B5, 0xb6),
1655
+
QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_MODE_RATE2_B6, 0xee),
1656
+
QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_MODE_RATE3_B0, 0xdb),
1657
+
QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_MODE_RATE3_B1, 0xdb),
1658
+
QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_MODE_RATE3_B2, 0xa0),
1659
+
QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_MODE_RATE3_B3, 0xdf),
1660
+
QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_MODE_RATE3_B4, 0x78),
1661
+
QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_MODE_RATE3_B5, 0x76),
1662
+
QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_MODE_RATE3_B6, 0xff),
1663
+
};
1664
+
1665
+
static const struct qmp_phy_init_tbl sm8550_qmp_gen4x2_pcie_pcs_tbl[] = {
1666
+
QMP_PHY_INIT_CFG(QPHY_V6_20_PCS_G3S2_PRE_GAIN, 0x2e),
1667
+
QMP_PHY_INIT_CFG(QPHY_V6_20_PCS_COM_ELECIDLE_DLY_SEL, 0x25),
1668
+
QMP_PHY_INIT_CFG(QPHY_V6_20_PCS_EQ_CONFIG4, 0x00),
1669
+
QMP_PHY_INIT_CFG(QPHY_V6_20_PCS_EQ_CONFIG5, 0x22),
1670
+
QMP_PHY_INIT_CFG(QPHY_V6_20_PCS_TX_RX_CONFIG1, 0x04),
1671
+
QMP_PHY_INIT_CFG(QPHY_V6_20_PCS_TX_RX_CONFIG2, 0x02),
1672
+
};
1673
+
1674
+
static const struct qmp_phy_init_tbl sm8550_qmp_gen4x2_pcie_pcs_misc_tbl[] = {
1675
+
QMP_PHY_INIT_CFG(QPHY_PCIE_V6_20_PCS_ENDPOINT_REFCLK_DRIVE, 0xc1),
1676
+
QMP_PHY_INIT_CFG(QPHY_PCIE_V6_20_PCS_OSC_DTCT_ATCIONS, 0x00),
1677
+
QMP_PHY_INIT_CFG(QPHY_PCIE_V6_20_PCS_EQ_CONFIG1, 0x16),
1678
+
QMP_PHY_INIT_CFG(QPHY_PCIE_V6_20_PCS_EQ_CONFIG5, 0x02),
1679
+
QMP_PHY_INIT_CFG(QPHY_PCIE_V6_20_PCS_G4_PRE_GAIN, 0x2e),
1680
+
QMP_PHY_INIT_CFG(QPHY_PCIE_V6_20_PCS_RX_MARGINING_CONFIG1, 0x03),
1681
+
QMP_PHY_INIT_CFG(QPHY_PCIE_V6_20_PCS_RX_MARGINING_CONFIG3, 0x28),
1682
+
QMP_PHY_INIT_CFG(QPHY_PCIE_V6_20_PCS_TX_RX_CONFIG, 0xc0),
1683
+
QMP_PHY_INIT_CFG(QPHY_PCIE_V6_20_PCS_POWER_STATE_CONFIG2, 0x1d),
1684
+
QMP_PHY_INIT_CFG(QPHY_PCIE_V6_20_PCS_RX_MARGINING_CONFIG5, 0x0f),
1685
+
QMP_PHY_INIT_CFG(QPHY_PCIE_V6_20_PCS_G3_FOM_EQ_CONFIG5, 0xf2),
1686
+
QMP_PHY_INIT_CFG(QPHY_PCIE_V6_20_PCS_G4_FOM_EQ_CONFIG5, 0xf2),
1687
+
};
1688
+
1509
1689
struct qmp_pcie_offsets {
1510
1690
u16 serdes;
1511
1691
u16 pcs;
···
1742
1466
u16 rx;
1743
1467
u16 tx2;
1744
1468
u16 rx2;
1469
+
u16 ln_shrd;
1745
1470
};
1746
1471
1747
1472
struct qmp_phy_cfg_tbls {
···
1756
1479
int pcs_num;
1757
1480
const struct qmp_phy_init_tbl *pcs_misc;
1758
1481
int pcs_misc_num;
1482
+
const struct qmp_phy_init_tbl *ln_shrd;
1483
+
int ln_shrd_num;
1759
1484
};
1760
1485
1761
1486
/* struct qmp_phy_cfg - per-PHY initialization config */
···
1800
1521
1801
1522
bool skip_start_delay;
1802
1523
1524
+
bool has_nocsr_reset;
1525
+
1803
1526
/* QMP PHY pipe clock interface rate */
1804
1527
unsigned long pipe_clock_rate;
1805
1528
};
···
1819
1538
void __iomem *rx;
1820
1539
void __iomem *tx2;
1821
1540
void __iomem *rx2;
1541
+
void __iomem *ln_shrd;
1822
1542
1823
1543
void __iomem *port_b;
1824
1544
···
1828
1546
int num_pipe_clks;
1829
1547
1830
1548
struct reset_control_bulk_data *resets;
1549
+
struct reset_control *nocsr_reset;
1831
1550
struct regulator_bulk_data *vregs;
1832
1551
1833
1552
struct phy *phy;
···
1883
1600
"vdda-phy", "vdda-pll",
1884
1601
};
1885
1602
1603
+
static const char * const sm8550_qmp_phy_vreg_l[] = {
1604
+
"vdda-phy", "vdda-pll", "vdda-qref",
1605
+
};
1606
+
1886
1607
/* list of resets */
1887
1608
static const char * const ipq8074_pciephy_reset_l[] = {
1888
1609
"phy", "common",
···
1904
1617
.rx = 0x1000,
1905
1618
.tx2 = 0x1600,
1906
1619
.rx2 = 0x1800,
1620
+
};
1621
+
1622
+
static const struct qmp_pcie_offsets qmp_pcie_offsets_v6_20 = {
1623
+
.serdes = 0x1000,
1624
+
.pcs = 0x1200,
1625
+
.pcs_misc = 0x1400,
1626
+
.tx = 0x0000,
1627
+
.rx = 0x0200,
1628
+
.tx2 = 0x0800,
1629
+
.rx2 = 0x0a00,
1630
+
.ln_shrd = 0x0e00,
1907
1631
};
1908
1632
1909
1633
static const struct qmp_phy_cfg ipq8074_pciephy_cfg = {
···
1936
1638
.num_resets = ARRAY_SIZE(ipq8074_pciephy_reset_l),
1937
1639
.vreg_list = NULL,
1938
1640
.num_vregs = 0,
1939
-
.regs = pciephy_regs_layout,
1641
+
.regs = pciephy_v2_regs_layout,
1940
1642
1941
1643
.pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL,
1942
1644
.phy_status = PHYSTATUS,
···
1963
1665
.num_resets = ARRAY_SIZE(ipq8074_pciephy_reset_l),
1964
1666
.vreg_list = NULL,
1965
1667
.num_vregs = 0,
1966
-
.regs = ipq_pciephy_gen3_regs_layout,
1668
+
.regs = pciephy_v4_regs_layout,
1967
1669
1968
1670
.pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL,
1969
1671
.phy_status = PHYSTATUS,
···
1992
1694
.num_resets = ARRAY_SIZE(ipq8074_pciephy_reset_l),
1993
1695
.vreg_list = NULL,
1994
1696
.num_vregs = 0,
1995
-
.regs = ipq_pciephy_gen3_regs_layout,
1697
+
.regs = pciephy_v4_regs_layout,
1996
1698
1997
1699
.pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL,
1998
1700
.phy_status = PHYSTATUS,
···
2019
1721
.num_resets = ARRAY_SIZE(sdm845_pciephy_reset_l),
2020
1722
.vreg_list = qmp_phy_vreg_l,
2021
1723
.num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
2022
-
.regs = sdm845_qmp_pciephy_regs_layout,
1724
+
.regs = pciephy_v3_regs_layout,
2023
1725
2024
1726
.pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL,
2025
1727
.phy_status = PHYSTATUS,
···
2081
1783
.num_resets = ARRAY_SIZE(sdm845_pciephy_reset_l),
2082
1784
.vreg_list = qmp_phy_vreg_l,
2083
1785
.num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
2084
-
.regs = sm8250_pcie_regs_layout,
1786
+
.regs = pciephy_v4_regs_layout,
2085
1787
2086
1788
.pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL,
2087
1789
.phy_status = PHYSTATUS,
···
2118
1820
.num_resets = ARRAY_SIZE(sdm845_pciephy_reset_l),
2119
1821
.vreg_list = qmp_phy_vreg_l,
2120
1822
.num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
2121
-
.regs = sm8250_pcie_regs_layout,
1823
+
.regs = pciephy_v4_regs_layout,
2122
1824
2123
1825
.pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL,
2124
1826
.phy_status = PHYSTATUS,
···
2143
1845
.num_resets = ARRAY_SIZE(ipq8074_pciephy_reset_l),
2144
1846
.vreg_list = qmp_phy_vreg_l,
2145
1847
.num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
2146
-
.regs = pciephy_regs_layout,
1848
+
.regs = pciephy_v3_regs_layout,
2147
1849
2148
1850
.pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL,
2149
1851
.phy_status = PHYSTATUS,
···
2172
1874
.num_resets = ARRAY_SIZE(sdm845_pciephy_reset_l),
2173
1875
.vreg_list = qmp_phy_vreg_l,
2174
1876
.num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
2175
-
.regs = sm8250_pcie_regs_layout,
1877
+
.regs = pciephy_v4_regs_layout,
2176
1878
2177
1879
.pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL,
2178
1880
.phy_status = PHYSTATUS,
···
2207
1909
.num_resets = ARRAY_SIZE(sdm845_pciephy_reset_l),
2208
1910
.vreg_list = qmp_phy_vreg_l,
2209
1911
.num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
2210
-
.regs = sm8250_pcie_regs_layout,
1912
+
.regs = pciephy_v5_regs_layout,
2211
1913
2212
1914
.pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL,
2213
1915
.phy_status = PHYSTATUS,
···
2242
1944
.num_resets = ARRAY_SIZE(sdm845_pciephy_reset_l),
2243
1945
.vreg_list = qmp_phy_vreg_l,
2244
1946
.num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
2245
-
.regs = sm8250_pcie_regs_layout,
1947
+
.regs = pciephy_v5_regs_layout,
2246
1948
2247
1949
.pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL,
2248
1950
.phy_status = PHYSTATUS,
···
2280
1982
.num_resets = ARRAY_SIZE(sdm845_pciephy_reset_l),
2281
1983
.vreg_list = qmp_phy_vreg_l,
2282
1984
.num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
2283
-
.regs = sm8250_pcie_regs_layout,
1985
+
.regs = pciephy_v5_regs_layout,
2284
1986
2285
1987
.pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL,
2286
1988
.phy_status = PHYSTATUS,
···
2307
2009
.num_resets = ARRAY_SIZE(sdm845_pciephy_reset_l),
2308
2010
.vreg_list = qmp_phy_vreg_l,
2309
2011
.num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
2310
-
.regs = sm8250_pcie_regs_layout,
2012
+
.regs = pciephy_v4_regs_layout,
2311
2013
2312
2014
.pwrdn_ctrl = SW_PWRDN,
2313
2015
.phy_status = PHYSTATUS_4_20,
2016
+
};
2017
+
2018
+
static const struct qmp_phy_cfg sm8350_qmp_gen3x1_pciephy_cfg = {
2019
+
.lanes = 1,
2020
+
2021
+
.offsets = &qmp_pcie_offsets_v5,
2022
+
2023
+
.tbls = {
2024
+
.serdes = sm8450_qmp_gen3_pcie_serdes_tbl,
2025
+
.serdes_num = ARRAY_SIZE(sm8450_qmp_gen3_pcie_serdes_tbl),
2026
+
.tx = sm8350_qmp_gen3x1_pcie_tx_tbl,
2027
+
.tx_num = ARRAY_SIZE(sm8350_qmp_gen3x1_pcie_tx_tbl),
2028
+
.rx = sm8450_qmp_gen3_pcie_rx_tbl,
2029
+
.rx_num = ARRAY_SIZE(sm8450_qmp_gen3_pcie_rx_tbl),
2030
+
.pcs = sm8450_qmp_gen3_pcie_pcs_tbl,
2031
+
.pcs_num = ARRAY_SIZE(sm8450_qmp_gen3_pcie_pcs_tbl),
2032
+
.pcs_misc = sm8450_qmp_gen3x1_pcie_pcs_misc_tbl,
2033
+
.pcs_misc_num = ARRAY_SIZE(sm8450_qmp_gen3x1_pcie_pcs_misc_tbl),
2034
+
},
2035
+
2036
+
.tbls_rc = &(const struct qmp_phy_cfg_tbls) {
2037
+
.serdes = sm8450_qmp_gen3x1_pcie_rc_serdes_tbl,
2038
+
.serdes_num = ARRAY_SIZE(sm8450_qmp_gen3x1_pcie_rc_serdes_tbl),
2039
+
.rx = sm8350_qmp_gen3x1_pcie_rc_rx_tbl,
2040
+
.rx_num = ARRAY_SIZE(sm8350_qmp_gen3x1_pcie_rc_rx_tbl),
2041
+
},
2042
+
2043
+
.clk_list = sc8280xp_pciephy_clk_l,
2044
+
.num_clks = ARRAY_SIZE(sc8280xp_pciephy_clk_l),
2045
+
.reset_list = sdm845_pciephy_reset_l,
2046
+
.num_resets = ARRAY_SIZE(sdm845_pciephy_reset_l),
2047
+
.vreg_list = qmp_phy_vreg_l,
2048
+
.num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
2049
+
.regs = pciephy_v5_regs_layout,
2050
+
2051
+
.pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL,
2052
+
.phy_status = PHYSTATUS,
2053
+
};
2054
+
2055
+
static const struct qmp_phy_cfg sm8350_qmp_gen3x2_pciephy_cfg = {
2056
+
.lanes = 2,
2057
+
2058
+
.offsets = &qmp_pcie_offsets_v5,
2059
+
2060
+
.tbls = {
2061
+
.serdes = sm8450_qmp_gen3_pcie_serdes_tbl,
2062
+
.serdes_num = ARRAY_SIZE(sm8450_qmp_gen3_pcie_serdes_tbl),
2063
+
.tx = sm8350_qmp_gen3x2_pcie_tx_tbl,
2064
+
.tx_num = ARRAY_SIZE(sm8350_qmp_gen3x2_pcie_tx_tbl),
2065
+
.rx = sm8450_qmp_gen3_pcie_rx_tbl,
2066
+
.rx_num = ARRAY_SIZE(sm8450_qmp_gen3_pcie_rx_tbl),
2067
+
.pcs = sm8450_qmp_gen3_pcie_pcs_tbl,
2068
+
.pcs_num = ARRAY_SIZE(sm8450_qmp_gen3_pcie_pcs_tbl),
2069
+
.pcs_misc = sc8280xp_qmp_gen3x2_pcie_pcs_misc_tbl,
2070
+
.pcs_misc_num = ARRAY_SIZE(sc8280xp_qmp_gen3x2_pcie_pcs_misc_tbl),
2071
+
},
2072
+
2073
+
.tbls_rc = &(const struct qmp_phy_cfg_tbls) {
2074
+
.rx = sm8350_qmp_gen3x2_pcie_rc_rx_tbl,
2075
+
.rx_num = ARRAY_SIZE(sm8350_qmp_gen3x2_pcie_rc_rx_tbl),
2076
+
.pcs = sm8350_qmp_gen3x2_pcie_rc_pcs_tbl,
2077
+
.pcs_num = ARRAY_SIZE(sm8350_qmp_gen3x2_pcie_rc_pcs_tbl),
2078
+
},
2079
+
2080
+
.clk_list = sc8280xp_pciephy_clk_l,
2081
+
.num_clks = ARRAY_SIZE(sc8280xp_pciephy_clk_l),
2082
+
.reset_list = sdm845_pciephy_reset_l,
2083
+
.num_resets = ARRAY_SIZE(sdm845_pciephy_reset_l),
2084
+
.vreg_list = qmp_phy_vreg_l,
2085
+
.num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
2086
+
.regs = pciephy_v5_regs_layout,
2087
+
2088
+
.pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL,
2089
+
.phy_status = PHYSTATUS,
2314
2090
};
2315
2091
2316
2092
static const struct qmp_phy_cfg sm8450_qmp_gen3x1_pciephy_cfg = {
2317
2093
.lanes = 1,
2318
2094
2319
2095
.tbls = {
2320
-
.serdes = sm8450_qmp_gen3x1_pcie_serdes_tbl,
2321
-
.serdes_num = ARRAY_SIZE(sm8450_qmp_gen3x1_pcie_serdes_tbl),
2096
+
.serdes = sm8450_qmp_gen3_pcie_serdes_tbl,
2097
+
.serdes_num = ARRAY_SIZE(sm8450_qmp_gen3_pcie_serdes_tbl),
2322
2098
.tx = sm8450_qmp_gen3x1_pcie_tx_tbl,
2323
2099
.tx_num = ARRAY_SIZE(sm8450_qmp_gen3x1_pcie_tx_tbl),
2324
-
.rx = sm8450_qmp_gen3x1_pcie_rx_tbl,
2325
-
.rx_num = ARRAY_SIZE(sm8450_qmp_gen3x1_pcie_rx_tbl),
2326
-
.pcs = sm8450_qmp_gen3x1_pcie_pcs_tbl,
2327
-
.pcs_num = ARRAY_SIZE(sm8450_qmp_gen3x1_pcie_pcs_tbl),
2100
+
.rx = sm8450_qmp_gen3_pcie_rx_tbl,
2101
+
.rx_num = ARRAY_SIZE(sm8450_qmp_gen3_pcie_rx_tbl),
2102
+
.pcs = sm8450_qmp_gen3_pcie_pcs_tbl,
2103
+
.pcs_num = ARRAY_SIZE(sm8450_qmp_gen3_pcie_pcs_tbl),
2328
2104
.pcs_misc = sm8450_qmp_gen3x1_pcie_pcs_misc_tbl,
2329
2105
.pcs_misc_num = ARRAY_SIZE(sm8450_qmp_gen3x1_pcie_pcs_misc_tbl),
2330
2106
},
2107
+
2108
+
.tbls_rc = &(const struct qmp_phy_cfg_tbls) {
2109
+
.serdes = sm8450_qmp_gen3x1_pcie_rc_serdes_tbl,
2110
+
.serdes_num = ARRAY_SIZE(sm8450_qmp_gen3x1_pcie_rc_serdes_tbl),
2111
+
.rx = sm8450_qmp_gen3x1_pcie_rc_rx_tbl,
2112
+
.rx_num = ARRAY_SIZE(sm8450_qmp_gen3x1_pcie_rc_rx_tbl),
2113
+
},
2114
+
2331
2115
.clk_list = sdm845_pciephy_clk_l,
2332
2116
.num_clks = ARRAY_SIZE(sdm845_pciephy_clk_l),
2333
2117
.reset_list = sdm845_pciephy_reset_l,
2334
2118
.num_resets = ARRAY_SIZE(sdm845_pciephy_reset_l),
2335
2119
.vreg_list = qmp_phy_vreg_l,
2336
2120
.num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
2337
-
.regs = sm8250_pcie_regs_layout,
2121
+
.regs = pciephy_v5_regs_layout,
2338
2122
2339
2123
.pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL,
2340
2124
.phy_status = PHYSTATUS,
···
2458
2078
.num_resets = ARRAY_SIZE(sdm845_pciephy_reset_l),
2459
2079
.vreg_list = qmp_phy_vreg_l,
2460
2080
.num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
2461
-
.regs = sm8250_pcie_regs_layout,
2081
+
.regs = pciephy_v5_regs_layout,
2462
2082
2463
2083
.pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL,
2464
2084
.phy_status = PHYSTATUS_4_20,
2085
+
};
2086
+
2087
+
static const struct qmp_phy_cfg sm8550_qmp_gen3x2_pciephy_cfg = {
2088
+
.lanes = 2,
2089
+
2090
+
.offsets = &qmp_pcie_offsets_v5,
2091
+
2092
+
.tbls = {
2093
+
.serdes = sm8550_qmp_gen3x2_pcie_serdes_tbl,
2094
+
.serdes_num = ARRAY_SIZE(sm8550_qmp_gen3x2_pcie_serdes_tbl),
2095
+
.tx = sm8550_qmp_gen3x2_pcie_tx_tbl,
2096
+
.tx_num = ARRAY_SIZE(sm8550_qmp_gen3x2_pcie_tx_tbl),
2097
+
.rx = sm8550_qmp_gen3x2_pcie_rx_tbl,
2098
+
.rx_num = ARRAY_SIZE(sm8550_qmp_gen3x2_pcie_rx_tbl),
2099
+
.pcs = sm8550_qmp_gen3x2_pcie_pcs_tbl,
2100
+
.pcs_num = ARRAY_SIZE(sm8550_qmp_gen3x2_pcie_pcs_tbl),
2101
+
.pcs_misc = sm8550_qmp_gen3x2_pcie_pcs_misc_tbl,
2102
+
.pcs_misc_num = ARRAY_SIZE(sm8550_qmp_gen3x2_pcie_pcs_misc_tbl),
2103
+
},
2104
+
.clk_list = sc8280xp_pciephy_clk_l,
2105
+
.num_clks = ARRAY_SIZE(sc8280xp_pciephy_clk_l),
2106
+
.reset_list = sdm845_pciephy_reset_l,
2107
+
.num_resets = ARRAY_SIZE(sdm845_pciephy_reset_l),
2108
+
.vreg_list = qmp_phy_vreg_l,
2109
+
.num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
2110
+
.regs = pciephy_v5_regs_layout,
2111
+
2112
+
.pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL,
2113
+
.phy_status = PHYSTATUS,
2114
+
};
2115
+
2116
+
static const struct qmp_phy_cfg sm8550_qmp_gen4x2_pciephy_cfg = {
2117
+
.lanes = 2,
2118
+
2119
+
.offsets = &qmp_pcie_offsets_v6_20,
2120
+
2121
+
.tbls = {
2122
+
.serdes = sm8550_qmp_gen4x2_pcie_serdes_tbl,
2123
+
.serdes_num = ARRAY_SIZE(sm8550_qmp_gen4x2_pcie_serdes_tbl),
2124
+
.tx = sm8550_qmp_gen4x2_pcie_tx_tbl,
2125
+
.tx_num = ARRAY_SIZE(sm8550_qmp_gen4x2_pcie_tx_tbl),
2126
+
.rx = sm8550_qmp_gen4x2_pcie_rx_tbl,
2127
+
.rx_num = ARRAY_SIZE(sm8550_qmp_gen4x2_pcie_rx_tbl),
2128
+
.pcs = sm8550_qmp_gen4x2_pcie_pcs_tbl,
2129
+
.pcs_num = ARRAY_SIZE(sm8550_qmp_gen4x2_pcie_pcs_tbl),
2130
+
.pcs_misc = sm8550_qmp_gen4x2_pcie_pcs_misc_tbl,
2131
+
.pcs_misc_num = ARRAY_SIZE(sm8550_qmp_gen4x2_pcie_pcs_misc_tbl),
2132
+
.ln_shrd = sm8550_qmp_gen4x2_pcie_ln_shrd_tbl,
2133
+
.ln_shrd_num = ARRAY_SIZE(sm8550_qmp_gen4x2_pcie_ln_shrd_tbl),
2134
+
},
2135
+
.clk_list = sc8280xp_pciephy_clk_l,
2136
+
.num_clks = ARRAY_SIZE(sc8280xp_pciephy_clk_l),
2137
+
.reset_list = sdm845_pciephy_reset_l,
2138
+
.num_resets = ARRAY_SIZE(sdm845_pciephy_reset_l),
2139
+
.vreg_list = sm8550_qmp_phy_vreg_l,
2140
+
.num_vregs = ARRAY_SIZE(sm8550_qmp_phy_vreg_l),
2141
+
.regs = pciephy_v5_regs_layout,
2142
+
2143
+
.pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL,
2144
+
.phy_status = PHYSTATUS_4_20,
2145
+
.has_nocsr_reset = true,
2465
2146
};
2466
2147
2467
2148
static void qmp_pcie_configure_lane(void __iomem *base,
···
2579
2138
void __iomem *rx2 = qmp->rx2;
2580
2139
void __iomem *pcs = qmp->pcs;
2581
2140
void __iomem *pcs_misc = qmp->pcs_misc;
2141
+
void __iomem *ln_shrd = qmp->ln_shrd;
2582
2142
2583
2143
if (!tbls)
2584
2144
return;
···
2601
2159
qmp_pcie_configure(serdes, cfg->serdes_4ln_tbl, cfg->serdes_4ln_num);
2602
2160
qmp_pcie_init_port_b(qmp, tbls);
2603
2161
}
2162
+
2163
+
qmp_pcie_configure(ln_shrd, tbls->ln_shrd, tbls->ln_shrd_num);
2604
2164
}
2605
2165
2606
2166
static int qmp_pcie_init(struct phy *phy)
···
2623
2179
goto err_disable_regulators;
2624
2180
}
2625
2181
2182
+
ret = reset_control_assert(qmp->nocsr_reset);
2183
+
if (ret) {
2184
+
dev_err(qmp->dev, "no-csr reset assert failed\n");
2185
+
goto err_assert_reset;
2186
+
}
2187
+
2626
2188
usleep_range(200, 300);
2627
2189
2628
2190
ret = reset_control_bulk_deassert(cfg->num_resets, qmp->resets);
2629
2191
if (ret) {
2630
2192
dev_err(qmp->dev, "reset deassert failed\n");
2631
-
goto err_disable_regulators;
2193
+
goto err_assert_reset;
2632
2194
}
2633
2195
2634
2196
ret = clk_bulk_prepare_enable(cfg->num_clks, qmp->clks);
···
2689
2239
ret = clk_bulk_prepare_enable(qmp->num_pipe_clks, qmp->pipe_clks);
2690
2240
if (ret)
2691
2241
return ret;
2242
+
2243
+
ret = reset_control_deassert(qmp->nocsr_reset);
2244
+
if (ret) {
2245
+
dev_err(qmp->dev, "no-csr reset deassert failed\n");
2246
+
goto err_disable_pipe_clk;
2247
+
}
2692
2248
2693
2249
/* Pull PHY out of reset state */
2694
2250
qphy_clrbits(pcs, cfg->regs[QPHY_SW_RESET], SW_RESET);
···
2828
2372
ret = devm_reset_control_bulk_get_exclusive(dev, cfg->num_resets, qmp->resets);
2829
2373
if (ret)
2830
2374
return dev_err_probe(dev, ret, "failed to get resets\n");
2375
+
2376
+
if (cfg->has_nocsr_reset) {
2377
+
qmp->nocsr_reset = devm_reset_control_get_exclusive(dev, "phy_nocsr");
2378
+
if (IS_ERR(qmp->nocsr_reset))
2379
+
return dev_err_probe(dev, PTR_ERR(qmp->nocsr_reset),
2380
+
"failed to get no-csr reset\n");
2381
+
}
2831
2382
2832
2383
return 0;
2833
2384
}
···
3058
2595
return PTR_ERR(qmp->port_b);
3059
2596
}
3060
2597
2598
+
if (cfg->tbls.ln_shrd)
2599
+
qmp->ln_shrd = base + offs->ln_shrd;
2600
+
3061
2601
qmp->num_pipe_clks = 2;
3062
2602
qmp->pipe_clks[0].id = "pipe";
3063
2603
qmp->pipe_clks[1].id = "pipediv2";
3064
2604
3065
-
ret = devm_clk_bulk_get(dev, qmp->num_pipe_clks, qmp->pipe_clks);
2605
+
ret = devm_clk_bulk_get(dev, 1, qmp->pipe_clks);
2606
+
if (ret)
2607
+
return ret;
2608
+
2609
+
ret = devm_clk_bulk_get_optional(dev, qmp->num_pipe_clks - 1, qmp->pipe_clks + 1);
3066
2610
if (ret)
3067
2611
return ret;
3068
2612
···
3190
2720
.compatible = "qcom,sm8250-qmp-modem-pcie-phy",
3191
2721
.data = &sm8250_qmp_gen3x2_pciephy_cfg,
3192
2722
}, {
2723
+
.compatible = "qcom,sm8350-qmp-gen3x1-pcie-phy",
2724
+
.data = &sm8350_qmp_gen3x1_pciephy_cfg,
2725
+
}, {
2726
+
.compatible = "qcom,sm8350-qmp-gen3x2-pcie-phy",
2727
+
.data = &sm8350_qmp_gen3x2_pciephy_cfg,
2728
+
}, {
3193
2729
.compatible = "qcom,sm8450-qmp-gen3x1-pcie-phy",
3194
2730
.data = &sm8450_qmp_gen3x1_pciephy_cfg,
3195
2731
}, {
3196
2732
.compatible = "qcom,sm8450-qmp-gen4x2-pcie-phy",
3197
2733
.data = &sm8450_qmp_gen4x2_pciephy_cfg,
2734
+
}, {
2735
+
.compatible = "qcom,sm8550-qmp-gen3x2-pcie-phy",
2736
+
.data = &sm8550_qmp_gen3x2_pciephy_cfg,
2737
+
}, {
2738
+
.compatible = "qcom,sm8550-qmp-gen4x2-pcie-phy",
2739
+
.data = &sm8550_qmp_gen4x2_pciephy_cfg,
3198
2740
},
3199
2741
{ },
3200
2742
};
+15
drivers/phy/qualcomm/phy-qcom-qmp-pcs-pcie-v6.h
+15
drivers/phy/qualcomm/phy-qcom-qmp-pcs-pcie-v6.h
···
1
+
/* SPDX-License-Identifier: GPL-2.0 */
2
+
/*
3
+
* Copyright (c) 2023, Linaro Limited
4
+
*/
5
+
6
+
#ifndef QCOM_PHY_QMP_PCS_PCIE_V6_H_
7
+
#define QCOM_PHY_QMP_PCS_PCIE_V6_H_
8
+
9
+
/* Only for QMP V6 PHY - PCIE have different offsets than V5 */
10
+
#define QPHY_PCIE_V6_PCS_PCIE_POWER_STATE_CONFIG2 0x0c
11
+
#define QPHY_PCIE_V6_PCS_PCIE_POWER_STATE_CONFIG4 0x14
12
+
#define QPHY_PCIE_V6_PCS_PCIE_ENDPOINT_REFCLK_DRIVE 0x20
13
+
#define QPHY_PCIE_V6_PCS_PCIE_OSC_DTCT_ACTIONS 0x94
14
+
15
+
#endif
+23
drivers/phy/qualcomm/phy-qcom-qmp-pcs-pcie-v6_20.h
+23
drivers/phy/qualcomm/phy-qcom-qmp-pcs-pcie-v6_20.h
···
1
+
/* SPDX-License-Identifier: GPL-2.0 */
2
+
/*
3
+
* Copyright (c) 2023, Linaro Limited
4
+
*/
5
+
6
+
#ifndef QCOM_PHY_QMP_PCS_PCIE_V6_20_H_
7
+
#define QCOM_PHY_QMP_PCS_PCIE_V6_20_H_
8
+
9
+
/* Only for QMP V6_20 PHY - PCIE have different offsets than V5 */
10
+
#define QPHY_PCIE_V6_20_PCS_POWER_STATE_CONFIG2 0x00c
11
+
#define QPHY_PCIE_V6_20_PCS_TX_RX_CONFIG 0x018
12
+
#define QPHY_PCIE_V6_20_PCS_ENDPOINT_REFCLK_DRIVE 0x01c
13
+
#define QPHY_PCIE_V6_20_PCS_OSC_DTCT_ATCIONS 0x090
14
+
#define QPHY_PCIE_V6_20_PCS_EQ_CONFIG1 0x0a0
15
+
#define QPHY_PCIE_V6_20_PCS_EQ_CONFIG5 0x108
16
+
#define QPHY_PCIE_V6_20_PCS_G4_PRE_GAIN 0x15c
17
+
#define QPHY_PCIE_V6_20_PCS_RX_MARGINING_CONFIG1 0x17c
18
+
#define QPHY_PCIE_V6_20_PCS_RX_MARGINING_CONFIG3 0x184
19
+
#define QPHY_PCIE_V6_20_PCS_RX_MARGINING_CONFIG5 0x18c
20
+
#define QPHY_PCIE_V6_20_PCS_G3_FOM_EQ_CONFIG5 0x1ac
21
+
#define QPHY_PCIE_V6_20_PCS_G4_FOM_EQ_CONFIG5 0x1c0
22
+
23
+
#endif
+25
drivers/phy/qualcomm/phy-qcom-qmp-pcs-ufs-v2.h
+25
drivers/phy/qualcomm/phy-qcom-qmp-pcs-ufs-v2.h
···
1
+
/* SPDX-License-Identifier: GPL-2.0 */
2
+
/*
3
+
* Copyright (c) 2017, The Linux Foundation. All rights reserved.
4
+
*/
5
+
6
+
#ifndef QCOM_PHY_QMP_PCS_UFS_V2_H_
7
+
#define QCOM_PHY_QMP_PCS_UFS_V2_H_
8
+
9
+
#define QPHY_V2_PCS_UFS_PHY_START 0x000
10
+
#define QPHY_V2_PCS_UFS_POWER_DOWN_CONTROL 0x004
11
+
12
+
#define QPHY_V2_PCS_UFS_TX_LARGE_AMP_DRV_LVL 0x034
13
+
#define QPHY_V2_PCS_UFS_TX_LARGE_AMP_POST_EMP_LVL 0x038
14
+
#define QPHY_V2_PCS_UFS_TX_SMALL_AMP_DRV_LVL 0x03c
15
+
#define QPHY_V2_PCS_UFS_TX_SMALL_AMP_POST_EMP_LVL 0x040
16
+
17
+
#define QPHY_V2_PCS_UFS_RX_MIN_STALL_NOCONFIG_TIME_CAP 0x0cc
18
+
#define QPHY_V2_PCS_UFS_RX_SYM_RESYNC_CTRL 0x13c
19
+
#define QPHY_V2_PCS_UFS_RX_MIN_HIBERN8_TIME 0x140
20
+
#define QPHY_V2_PCS_UFS_RX_SIGDET_CTRL2 0x148
21
+
#define QPHY_V2_PCS_UFS_RX_PWM_GEAR_BAND 0x154
22
+
23
+
#define QPHY_V2_PCS_UFS_READY_STATUS 0x168
24
+
25
+
#endif
+3
drivers/phy/qualcomm/phy-qcom-qmp-pcs-ufs-v3.h
+3
drivers/phy/qualcomm/phy-qcom-qmp-pcs-ufs-v3.h
···
6
6
#ifndef QCOM_PHY_QMP_PCS_UFS_V3_H_
7
7
#define QCOM_PHY_QMP_PCS_UFS_V3_H_
8
8
9
+
#define QPHY_V3_PCS_UFS_PHY_START 0x000
10
+
#define QPHY_V3_PCS_UFS_POWER_DOWN_CONTROL 0x004
9
11
#define QPHY_V3_PCS_UFS_TX_LARGE_AMP_DRV_LVL 0x02c
10
12
#define QPHY_V3_PCS_UFS_TX_SMALL_AMP_DRV_LVL 0x034
11
13
#define QPHY_V3_PCS_UFS_RX_SYM_RESYNC_CTRL 0x134
12
14
#define QPHY_V3_PCS_UFS_RX_MIN_HIBERN8_TIME 0x138
13
15
#define QPHY_V3_PCS_UFS_RX_SIGDET_CTRL1 0x13c
14
16
#define QPHY_V3_PCS_UFS_RX_SIGDET_CTRL2 0x140
17
+
#define QPHY_V3_PCS_UFS_READY_STATUS 0x160
15
18
#define QPHY_V3_PCS_UFS_TX_MID_TERM_CTRL1 0x1bc
16
19
#define QPHY_V3_PCS_UFS_MULTI_LANE_CTRL1 0x1c4
17
20
+5
drivers/phy/qualcomm/phy-qcom-qmp-pcs-ufs-v5.h
+5
drivers/phy/qualcomm/phy-qcom-qmp-pcs-ufs-v5.h
···
8
8
#define QCOM_PHY_QMP_PCS_UFS_V5_H_
9
9
10
10
/* Only for QMP V5 PHY - UFS PCS registers */
11
+
#define QPHY_V5_PCS_UFS_PHY_START 0x000
12
+
#define QPHY_V5_PCS_UFS_POWER_DOWN_CONTROL 0x004
13
+
#define QPHY_V5_PCS_UFS_SW_RESET 0x008
11
14
#define QPHY_V5_PCS_UFS_TIMER_20US_CORECLK_STEPS_MSB 0x00c
12
15
#define QPHY_V5_PCS_UFS_TIMER_20US_CORECLK_STEPS_LSB 0x010
13
16
#define QPHY_V5_PCS_UFS_PLL_CNTL 0x02c
14
17
#define QPHY_V5_PCS_UFS_TX_LARGE_AMP_DRV_LVL 0x030
15
18
#define QPHY_V5_PCS_UFS_TX_SMALL_AMP_DRV_LVL 0x038
19
+
#define QPHY_V5_PCS_UFS_BIST_FIXED_PAT_CTRL 0x060
16
20
#define QPHY_V5_PCS_UFS_TX_HSGEAR_CAPABILITY 0x074
17
21
#define QPHY_V5_PCS_UFS_RX_HSGEAR_CAPABILITY 0x0b4
18
22
#define QPHY_V5_PCS_UFS_DEBUG_BUS_CLKSEL 0x124
···
25
21
#define QPHY_V5_PCS_UFS_RX_SIGDET_CTRL2 0x158
26
22
#define QPHY_V5_PCS_UFS_TX_PWM_GEAR_BAND 0x160
27
23
#define QPHY_V5_PCS_UFS_TX_HS_GEAR_BAND 0x168
24
+
#define QPHY_V5_PCS_UFS_READY_STATUS 0x180
28
25
#define QPHY_V5_PCS_UFS_TX_MID_TERM_CTRL1 0x1d8
29
26
#define QPHY_V5_PCS_UFS_MULTI_LANE_CTRL1 0x1e0
30
27
+31
drivers/phy/qualcomm/phy-qcom-qmp-pcs-ufs-v6.h
+31
drivers/phy/qualcomm/phy-qcom-qmp-pcs-ufs-v6.h
···
1
+
/* SPDX-License-Identifier: GPL-2.0 */
2
+
/*
3
+
* Copyright (c) 2023, Linaro Limited
4
+
*/
5
+
6
+
#ifndef QCOM_PHY_QMP_PCS_UFS_V6_H_
7
+
#define QCOM_PHY_QMP_PCS_UFS_V6_H_
8
+
9
+
/* Only for QMP V6 PHY - UFS PCS registers */
10
+
#define QPHY_V6_PCS_UFS_PHY_START 0x000
11
+
#define QPHY_V6_PCS_UFS_POWER_DOWN_CONTROL 0x004
12
+
#define QPHY_V6_PCS_UFS_SW_RESET 0x008
13
+
#define QPHY_V6_PCS_UFS_TIMER_20US_CORECLK_STEPS_MSB 0x00c
14
+
#define QPHY_V6_PCS_UFS_TIMER_20US_CORECLK_STEPS_LSB 0x010
15
+
#define QPHY_V6_PCS_UFS_PLL_CNTL 0x02c
16
+
#define QPHY_V6_PCS_UFS_TX_LARGE_AMP_DRV_LVL 0x030
17
+
#define QPHY_V6_PCS_UFS_TX_SMALL_AMP_DRV_LVL 0x038
18
+
#define QPHY_V6_PCS_UFS_BIST_FIXED_PAT_CTRL 0x060
19
+
#define QPHY_V6_PCS_UFS_TX_HSGEAR_CAPABILITY 0x074
20
+
#define QPHY_V6_PCS_UFS_RX_HSGEAR_CAPABILITY 0x0bc
21
+
#define QPHY_V6_PCS_UFS_DEBUG_BUS_CLKSEL 0x158
22
+
#define QPHY_V6_PCS_UFS_LINECFG_DISABLE 0x17c
23
+
#define QPHY_V6_PCS_UFS_RX_MIN_HIBERN8_TIME 0x184
24
+
#define QPHY_V6_PCS_UFS_RX_SIGDET_CTRL2 0x18c
25
+
#define QPHY_V6_PCS_UFS_TX_PWM_GEAR_BAND 0x178
26
+
#define QPHY_V6_PCS_UFS_TX_HS_GEAR_BAND 0x174
27
+
#define QPHY_V6_PCS_UFS_READY_STATUS 0x1a8
28
+
#define QPHY_V6_PCS_UFS_TX_MID_TERM_CTRL1 0x1f4
29
+
#define QPHY_V6_PCS_UFS_MULTI_LANE_CTRL1 0x1fc
30
+
31
+
#endif
+31
drivers/phy/qualcomm/phy-qcom-qmp-pcs-usb-v6.h
+31
drivers/phy/qualcomm/phy-qcom-qmp-pcs-usb-v6.h
···
1
+
/* SPDX-License-Identifier: GPL-2.0 */
2
+
/*
3
+
* Copyright (c) 2022, The Linux Foundation. All rights reserved.
4
+
*/
5
+
6
+
#ifndef QCOM_PHY_QMP_PCS_USB_V6_H_
7
+
#define QCOM_PHY_QMP_PCS_USB_V6_H_
8
+
9
+
/* Only for QMP V6 PHY - USB3 have different offsets than V5 */
10
+
#define QPHY_USB_V6_PCS_LOCK_DETECT_CONFIG1 0xc4
11
+
#define QPHY_USB_V6_PCS_LOCK_DETECT_CONFIG2 0xc8
12
+
#define QPHY_USB_V6_PCS_LOCK_DETECT_CONFIG3 0xcc
13
+
#define QPHY_USB_V6_PCS_LOCK_DETECT_CONFIG6 0xd8
14
+
#define QPHY_USB_V6_PCS_REFGEN_REQ_CONFIG1 0xdc
15
+
#define QPHY_USB_V6_PCS_USB3_POWER_STATE_CONFIG1 0x90
16
+
#define QPHY_USB_V6_PCS_RX_SIGDET_LVL 0x188
17
+
#define QPHY_USB_V6_PCS_RCVR_DTCT_DLY_P1U2_L 0x190
18
+
#define QPHY_USB_V6_PCS_RCVR_DTCT_DLY_P1U2_H 0x194
19
+
#define QPHY_USB_V6_PCS_CDR_RESET_TIME 0x1b0
20
+
#define QPHY_USB_V6_PCS_ALIGN_DETECT_CONFIG1 0x1c0
21
+
#define QPHY_USB_V6_PCS_ALIGN_DETECT_CONFIG2 0x1c4
22
+
#define QPHY_USB_V6_PCS_PCS_TX_RX_CONFIG 0x1d0
23
+
#define QPHY_USB_V6_PCS_EQ_CONFIG1 0x1dc
24
+
#define QPHY_USB_V6_PCS_EQ_CONFIG5 0x1ec
25
+
26
+
#define QPHY_USB_V6_PCS_USB3_LFPS_DET_HIGH_COUNT_VAL 0x18
27
+
#define QPHY_USB_V6_PCS_USB3_RXEQTRAINING_DFE_TIME_S2 0x3c
28
+
#define QPHY_USB_V6_PCS_USB3_RCVR_DTCT_DLY_U3_L 0x40
29
+
#define QPHY_USB_V6_PCS_USB3_RCVR_DTCT_DLY_U3_H 0x44
30
+
31
+
#endif
+8
-11
drivers/phy/qualcomm/phy-qcom-qmp-pcs-v2.h
+8
-11
drivers/phy/qualcomm/phy-qcom-qmp-pcs-v2.h
···
7
7
#define QCOM_PHY_QMP_PCS_V2_H_
8
8
9
9
/* Only for QMP V2 PHY - PCS registers */
10
+
#define QPHY_V2_PCS_SW_RESET 0x000
10
11
#define QPHY_V2_PCS_POWER_DOWN_CONTROL 0x004
12
+
#define QPHY_V2_PCS_START_CONTROL 0x008
11
13
#define QPHY_V2_PCS_TXDEEMPH_M6DB_V0 0x024
12
14
#define QPHY_V2_PCS_TXDEEMPH_M3P5DB_V0 0x028
13
-
#define QPHY_V2_PCS_TX_LARGE_AMP_DRV_LVL 0x034
14
-
#define QPHY_V2_PCS_TX_LARGE_AMP_POST_EMP_LVL 0x038
15
-
#define QPHY_V2_PCS_TX_SMALL_AMP_DRV_LVL 0x03c
16
-
#define QPHY_V2_PCS_TX_SMALL_AMP_POST_EMP_LVL 0x040
17
15
#define QPHY_V2_PCS_ENDPOINT_REFCLK_DRIVE 0x054
18
16
#define QPHY_V2_PCS_RX_IDLE_DTCT_CNTRL 0x058
19
17
#define QPHY_V2_PCS_POWER_STATE_CONFIG1 0x060
···
28
30
#define QPHY_V2_PCS_FLL_CNT_VAL_L 0x0c8
29
31
#define QPHY_V2_PCS_FLL_CNT_VAL_H_TOL 0x0cc
30
32
#define QPHY_V2_PCS_FLL_MAN_CODE 0x0d0
31
-
32
-
/* UFS only ? */
33
-
#define QPHY_V2_PCS_RX_MIN_STALL_NOCONFIG_TIME_CAP 0x0cc
34
-
#define QPHY_V2_PCS_RX_SYM_RESYNC_CTRL 0x13c
35
-
#define QPHY_V2_PCS_RX_MIN_HIBERN8_TIME 0x140
36
-
#define QPHY_V2_PCS_RX_SIGDET_CTRL2 0x148
37
-
#define QPHY_V2_PCS_RX_PWM_GEAR_BAND 0x154
33
+
#define QPHY_V2_PCS_AUTONOMOUS_MODE_CTRL 0x0d4
34
+
#define QPHY_V2_PCS_LFPS_RXTERM_IRQ_CLEAR 0x0d8
35
+
#define QPHY_V2_PCS_LFPS_RXTERM_IRQ_STATUS 0x178
36
+
#define QPHY_V2_PCS_USB_PCS_STATUS 0x17c /* USB */
38
37
#define QPHY_V2_PCS_PLL_LOCK_CHK_DLY_TIME_AUXCLK_LSB 0x1a8
39
38
#define QPHY_V2_PCS_OSC_DTCT_ACTIONS 0x1ac
40
39
#define QPHY_V2_PCS_RX_SIGDET_LVL 0x1d8
41
40
#define QPHY_V2_PCS_L1SS_WAKEUP_DLY_TIME_AUXCLK_LSB 0x1dc
42
41
#define QPHY_V2_PCS_L1SS_WAKEUP_DLY_TIME_AUXCLK_MSB 0x1e0
42
+
43
+
#define QPHY_V2_PCS_PCI_PCS_STATUS 0x174 /* PCI */
43
44
44
45
#endif
+4
drivers/phy/qualcomm/phy-qcom-qmp-pcs-v5.h
+4
drivers/phy/qualcomm/phy-qcom-qmp-pcs-v5.h
···
7
7
#define QCOM_PHY_QMP_PCS_V5_H_
8
8
9
9
/* Only for QMP V5 PHY - USB/PCIe PCS registers */
10
+
#define QPHY_V5_PCS_SW_RESET 0x000
11
+
#define QPHY_V5_PCS_PCS_STATUS1 0x014
12
+
#define QPHY_V5_PCS_POWER_DOWN_CONTROL 0x040
13
+
#define QPHY_V5_PCS_START_CONTROL 0x044
10
14
#define QPHY_V5_PCS_LOCK_DETECT_CONFIG1 0x0c4
11
15
#define QPHY_V5_PCS_LOCK_DETECT_CONFIG2 0x0c8
12
16
#define QPHY_V5_PCS_LOCK_DETECT_CONFIG3 0x0cc
+16
drivers/phy/qualcomm/phy-qcom-qmp-pcs-v6.h
+16
drivers/phy/qualcomm/phy-qcom-qmp-pcs-v6.h
···
1
+
/* SPDX-License-Identifier: GPL-2.0 */
2
+
/*
3
+
* Copyright (c) 2023, Linaro Limited
4
+
*/
5
+
6
+
#ifndef QCOM_PHY_QMP_PCS_V6_H_
7
+
#define QCOM_PHY_QMP_PCS_V6_H_
8
+
9
+
/* Only for QMP V6 PHY - USB/PCIe PCS registers */
10
+
#define QPHY_V6_PCS_REFGEN_REQ_CONFIG1 0xdc
11
+
#define QPHY_V6_PCS_RX_SIGDET_LVL 0x188
12
+
#define QPHY_V6_PCS_RATE_SLEW_CNTRL1 0x198
13
+
#define QPHY_V6_PCS_EQ_CONFIG2 0x1e0
14
+
#define QPHY_V6_PCS_PCS_TX_RX_CONFIG 0x1d0
15
+
16
+
#endif
+18
drivers/phy/qualcomm/phy-qcom-qmp-pcs-v6_20.h
+18
drivers/phy/qualcomm/phy-qcom-qmp-pcs-v6_20.h
···
1
+
/* SPDX-License-Identifier: GPL-2.0 */
2
+
/*
3
+
* Copyright (c) 2023, Linaro Limited
4
+
*/
5
+
6
+
#ifndef QCOM_PHY_QMP_PCS_V6_20_H_
7
+
#define QCOM_PHY_QMP_PCS_V6_20_H_
8
+
9
+
/* Only for QMP V6_20 PHY - USB/PCIe PCS registers */
10
+
#define QPHY_V6_20_PCS_G3S2_PRE_GAIN 0x178
11
+
#define QPHY_V6_20_PCS_RX_SIGDET_LVL 0x190
12
+
#define QPHY_V6_20_PCS_COM_ELECIDLE_DLY_SEL 0x1b8
13
+
#define QPHY_V6_20_PCS_TX_RX_CONFIG1 0x1dc
14
+
#define QPHY_V6_20_PCS_TX_RX_CONFIG2 0x1e0
15
+
#define QPHY_V6_20_PCS_EQ_CONFIG4 0x1f8
16
+
#define QPHY_V6_20_PCS_EQ_CONFIG5 0x1fc
17
+
18
+
#endif
+82
drivers/phy/qualcomm/phy-qcom-qmp-qserdes-com-v6.h
+82
drivers/phy/qualcomm/phy-qcom-qmp-qserdes-com-v6.h
···
1
+
/* SPDX-License-Identifier: GPL-2.0 */
2
+
/*
3
+
* Copyright (c) 2023, Linaro Limited
4
+
*/
5
+
6
+
#ifndef QCOM_PHY_QMP_QSERDES_COM_V6_H_
7
+
#define QCOM_PHY_QMP_QSERDES_COM_V6_H_
8
+
9
+
/* Only for QMP V6 PHY - QSERDES COM registers */
10
+
11
+
#define QSERDES_V6_COM_SSC_STEP_SIZE1_MODE1 0x00
12
+
#define QSERDES_V6_COM_SSC_STEP_SIZE2_MODE1 0x04
13
+
#define QSERDES_V6_COM_CP_CTRL_MODE1 0x10
14
+
#define QSERDES_V6_COM_PLL_RCTRL_MODE1 0x14
15
+
#define QSERDES_V6_COM_PLL_CCTRL_MODE1 0x18
16
+
#define QSERDES_V6_COM_CORECLK_DIV_MODE1 0x1c
17
+
#define QSERDES_V6_COM_LOCK_CMP1_MODE1 0x20
18
+
#define QSERDES_V6_COM_LOCK_CMP2_MODE1 0x24
19
+
#define QSERDES_V6_COM_DEC_START_MODE1 0x28
20
+
#define QSERDES_V6_COM_DEC_START_MSB_MODE1 0x2c
21
+
#define QSERDES_V6_COM_DIV_FRAC_START1_MODE1 0x30
22
+
#define QSERDES_V6_COM_DIV_FRAC_START2_MODE1 0x34
23
+
#define QSERDES_V6_COM_DIV_FRAC_START3_MODE1 0x38
24
+
#define QSERDES_V6_COM_HSCLK_SEL_1 0x3c
25
+
#define QSERDES_V6_COM_VCO_TUNE1_MODE1 0x48
26
+
#define QSERDES_V6_COM_VCO_TUNE2_MODE1 0x4c
27
+
#define QSERDES_V6_COM_BIN_VCOCAL_CMP_CODE1_MODE1 0x50
28
+
#define QSERDES_V6_COM_BIN_VCOCAL_CMP_CODE2_MODE1 0x54
29
+
#define QSERDES_V6_COM_BIN_VCOCAL_CMP_CODE1_MODE0 0x58
30
+
#define QSERDES_V6_COM_BIN_VCOCAL_CMP_CODE2_MODE0 0x5c
31
+
#define QSERDES_V6_COM_SSC_STEP_SIZE1_MODE0 0x60
32
+
#define QSERDES_V6_COM_SSC_STEP_SIZE2_MODE0 0x64
33
+
#define QSERDES_V6_COM_CP_CTRL_MODE0 0x70
34
+
#define QSERDES_V6_COM_PLL_RCTRL_MODE0 0x74
35
+
#define QSERDES_V6_COM_PLL_CCTRL_MODE0 0x78
36
+
#define QSERDES_V6_COM_PLL_CORE_CLK_DIV_MODE0 0x7c
37
+
#define QSERDES_V6_COM_LOCK_CMP1_MODE0 0x80
38
+
#define QSERDES_V6_COM_LOCK_CMP2_MODE0 0x84
39
+
#define QSERDES_V6_COM_DEC_START_MODE0 0x88
40
+
#define QSERDES_V6_COM_DEC_START_MSB_MODE0 0x8c
41
+
#define QSERDES_V6_COM_DIV_FRAC_START1_MODE0 0x90
42
+
#define QSERDES_V6_COM_DIV_FRAC_START2_MODE0 0x94
43
+
#define QSERDES_V6_COM_DIV_FRAC_START3_MODE0 0x98
44
+
#define QSERDES_V6_COM_HSCLK_HS_SWITCH_SEL_1 0x9c
45
+
#define QSERDES_V6_COM_INTEGLOOP_GAIN0_MODE0 0xa0
46
+
#define QSERDES_V6_COM_INTEGLOOP_GAIN1_MODE0 0xa4
47
+
#define QSERDES_V6_COM_VCO_TUNE1_MODE0 0xa8
48
+
#define QSERDES_V6_COM_VCO_TUNE2_MODE0 0xac
49
+
#define QSERDES_V6_COM_BG_TIMER 0xbc
50
+
#define QSERDES_V6_COM_SSC_EN_CENTER 0xc0
51
+
#define QSERDES_V6_COM_SSC_PER1 0xcc
52
+
#define QSERDES_V6_COM_SSC_PER2 0xd0
53
+
#define QSERDES_V6_COM_PLL_POST_DIV_MUX 0xd8
54
+
#define QSERDES_V6_COM_PLL_BIAS_EN_CLK_BUFLR_EN 0xdc
55
+
#define QSERDES_V6_COM_CLK_ENABLE1 0xe0
56
+
#define QSERDES_V6_COM_SYS_CLK_CTRL 0xe4
57
+
#define QSERDES_V6_COM_SYSCLK_BUF_ENABLE 0xe8
58
+
#define QSERDES_V6_COM_PLL_IVCO 0xf4
59
+
#define QSERDES_V6_COM_SYSCLK_EN_SEL 0x110
60
+
#define QSERDES_V6_COM_RESETSM_CNTRL 0x118
61
+
#define QSERDES_V6_COM_LOCK_CMP_EN 0x120
62
+
#define QSERDES_V6_COM_LOCK_CMP_CFG 0x124
63
+
#define QSERDES_V6_COM_VCO_TUNE_CTRL 0x13c
64
+
#define QSERDES_V6_COM_VCO_TUNE_MAP 0x140
65
+
#define QSERDES_V6_COM_VCO_TUNE_INITVAL2 0x148
66
+
#define QSERDES_V6_COM_CLK_SELECT 0x164
67
+
#define QSERDES_V6_COM_CORE_CLK_EN 0x170
68
+
#define QSERDES_V6_COM_CMN_CONFIG_1 0x174
69
+
#define QSERDES_V6_COM_SVS_MODE_CLK_SEL 0x17c
70
+
#define QSERDES_V6_COM_CMN_MISC_1 0x184
71
+
#define QSERDES_V6_COM_CMN_MODE 0x188
72
+
#define QSERDES_V6_COM_PLL_VCO_DC_LEVEL_CTRL 0x198
73
+
#define QSERDES_V6_COM_AUTO_GAIN_ADJ_CTRL_1 0x1a4
74
+
#define QSERDES_V6_COM_AUTO_GAIN_ADJ_CTRL_2 0x1a8
75
+
#define QSERDES_V6_COM_AUTO_GAIN_ADJ_CTRL_3 0x1ac
76
+
#define QSERDES_V6_COM_ADDITIONAL_MISC 0x1b4
77
+
#define QSERDES_V6_COM_ADDITIONAL_MISC_2 0x1b8
78
+
#define QSERDES_V6_COM_ADDITIONAL_MISC_3 0x1bc
79
+
#define QSERDES_V6_COM_CMN_STATUS 0x1d0
80
+
#define QSERDES_V6_COM_C_READY_STATUS 0x1f8
81
+
82
+
#endif
+1
-1
drivers/phy/qualcomm/phy-qcom-qmp-qserdes-com.h
+1
-1
drivers/phy/qualcomm/phy-qcom-qmp-qserdes-com.h
+32
drivers/phy/qualcomm/phy-qcom-qmp-qserdes-ln-shrd-v6.h
+32
drivers/phy/qualcomm/phy-qcom-qmp-qserdes-ln-shrd-v6.h
···
1
+
/* SPDX-License-Identifier: GPL-2.0 */
2
+
/*
3
+
* Copyright (c) 2023, Linaro Limited
4
+
*/
5
+
6
+
#ifndef QCOM_PHY_QMP_QSERDES_LN_SHRD_V6_H_
7
+
#define QCOM_PHY_QMP_QSERDES_LN_SHRD_V6_H_
8
+
9
+
#define QSERDES_V6_LN_SHRD_RXCLK_DIV2_CTRL 0xa0
10
+
#define QSERDES_V6_LN_SHRD_RX_Q_EN_RATES 0xb0
11
+
#define QSERDES_V6_LN_SHRD_DFE_DAC_ENABLE1 0xb4
12
+
#define QSERDES_V6_LN_SHRD_TX_ADAPT_POST_THRESH1 0xc4
13
+
#define QSERDES_V6_LN_SHRD_TX_ADAPT_POST_THRESH2 0xc8
14
+
#define QSERDES_V6_LN_SHRD_RX_MODE_RATE_0_1_B0 0xd4
15
+
#define QSERDES_V6_LN_SHRD_RX_MODE_RATE_0_1_B1 0xd8
16
+
#define QSERDES_V6_LN_SHRD_RX_MODE_RATE_0_1_B2 0xdc
17
+
#define QSERDES_V6_LN_SHRD_RX_MODE_RATE_0_1_B3 0xe0
18
+
#define QSERDES_V6_LN_SHRD_RX_MODE_RATE_0_1_B4 0xe4
19
+
#define QSERDES_V6_LN_SHRD_RX_MODE_RATE_0_1_B5 0xe8
20
+
#define QSERDES_V6_LN_SHRD_RX_MODE_RATE_0_1_B6 0xec
21
+
#define QSERDES_V6_LN_SHRD_RX_MARG_COARSE_THRESH1_RATE210 0xf0
22
+
#define QSERDES_V6_LN_SHRD_RX_MARG_COARSE_THRESH1_RATE3 0xf4
23
+
#define QSERDES_V6_LN_SHRD_RX_MARG_COARSE_THRESH2_RATE210 0xf8
24
+
#define QSERDES_V6_LN_SHRD_RX_MARG_COARSE_THRESH2_RATE3 0xfc
25
+
#define QSERDES_V6_LN_SHRD_RX_MARG_COARSE_THRESH3_RATE210 0x100
26
+
#define QSERDES_V6_LN_SHRD_RX_MARG_COARSE_THRESH3_RATE3 0x104
27
+
#define QSERDES_V6_LN_SHRD_RX_MARG_COARSE_THRESH4_RATE3 0x10c
28
+
#define QSERDES_V6_LN_SHRD_RX_MARG_COARSE_THRESH5_RATE3 0x114
29
+
#define QSERDES_V6_LN_SHRD_RX_MARG_COARSE_THRESH6_RATE3 0x11c
30
+
#define QSERDES_V6_LN_SHRD_RX_SUMMER_CAL_SPD_MODE 0x128
31
+
32
+
#endif
+30
drivers/phy/qualcomm/phy-qcom-qmp-qserdes-txrx-ufs-v6.h
+30
drivers/phy/qualcomm/phy-qcom-qmp-qserdes-txrx-ufs-v6.h
···
1
+
/* SPDX-License-Identifier: GPL-2.0 */
2
+
/*
3
+
* Copyright (c) 2023, Linaro Limited
4
+
*/
5
+
6
+
#ifndef QCOM_PHY_QMP_QSERDES_TXRX_UFS_V6_H_
7
+
#define QCOM_PHY_QMP_QSERDES_TXRX_UFS_V6_H_
8
+
9
+
#define QSERDES_UFS_V6_TX_RES_CODE_LANE_TX 0x28
10
+
#define QSERDES_UFS_V6_TX_RES_CODE_LANE_RX 0x2c
11
+
#define QSERDES_UFS_V6_TX_RES_CODE_LANE_OFFSET_TX 0x30
12
+
#define QSERDES_UFS_V6_TX_RES_CODE_LANE_OFFSET_RX 0x34
13
+
14
+
#define QSERDES_UFS_V6_RX_UCDR_FASTLOCK_FO_GAIN_RATE2 0x08
15
+
#define QSERDES_UFS_V6_RX_UCDR_FASTLOCK_FO_GAIN_RATE4 0x10
16
+
#define QSERDES_UFS_V6_RX_VGA_CAL_MAN_VAL 0x178
17
+
#define QSERDES_UFS_V6_RX_MODE_RATE_0_1_B0 0x208
18
+
#define QSERDES_UFS_V6_RX_MODE_RATE_0_1_B1 0x20c
19
+
#define QSERDES_UFS_V6_RX_MODE_RATE_0_1_B3 0x214
20
+
#define QSERDES_UFS_V6_RX_MODE_RATE_0_1_B6 0x220
21
+
#define QSERDES_UFS_V6_RX_MODE_RATE2_B3 0x238
22
+
#define QSERDES_UFS_V6_RX_MODE_RATE2_B6 0x244
23
+
#define QSERDES_UFS_V6_RX_MODE_RATE3_B3 0x25c
24
+
#define QSERDES_UFS_V6_RX_MODE_RATE3_B4 0x260
25
+
#define QSERDES_UFS_V6_RX_MODE_RATE3_B5 0x264
26
+
#define QSERDES_UFS_V6_RX_MODE_RATE3_B8 0x270
27
+
#define QSERDES_UFS_V6_RX_MODE_RATE4_B3 0x280
28
+
#define QSERDES_UFS_V6_RX_MODE_RATE4_B6 0x28c
29
+
30
+
#endif
-5
drivers/phy/qualcomm/phy-qcom-qmp-qserdes-txrx-v5_5nm.h
-5
drivers/phy/qualcomm/phy-qcom-qmp-qserdes-txrx-v5_5nm.h
···
7
7
#define QCOM_PHY_QMP_QSERDES_TXRX_V5_5NM_H_
8
8
9
9
/* Only for QMP V5 5NM PHY - TX registers */
10
-
#define QSERDES_V5_5NM_TX_RES_CODE_LANE_OFFSET_TX 0x30
11
-
#define QSERDES_V5_5NM_TX_RES_CODE_LANE_OFFSET_RX 0x34
12
-
#define QSERDES_V5_5NM_TX_LANE_MODE_1 0x78
13
-
#define QSERDES_V5_5NM_TX_LANE_MODE_2 0x7c
14
-
#define QSERDES_V5_5NM_TX_LANE_MODE_3 0x80
15
10
#define QSERDES_V5_5NM_TX_BIST_MODE_LANENO 0x00
16
11
#define QSERDES_V5_5NM_TX_BIST_INVERT 0x04
17
12
#define QSERDES_V5_5NM_TX_CLKBUF_ENABLE 0x08
+77
drivers/phy/qualcomm/phy-qcom-qmp-qserdes-txrx-v6.h
+77
drivers/phy/qualcomm/phy-qcom-qmp-qserdes-txrx-v6.h
···
1
+
/* SPDX-License-Identifier: GPL-2.0 */
2
+
/*
3
+
* Copyright (c) 2023, Linaro Limited
4
+
*/
5
+
6
+
#ifndef QCOM_PHY_QMP_QSERDES_TXRX_USB_V6_H_
7
+
#define QCOM_PHY_QMP_QSERDES_TXRX_USB_V6_H_
8
+
9
+
#define QSERDES_V6_TX_CLKBUF_ENABLE 0x08
10
+
#define QSERDES_V6_TX_RESET_TSYNC_EN 0x1c
11
+
#define QSERDES_V6_TX_PRE_STALL_LDO_BOOST_EN 0x20
12
+
#define QSERDES_V6_TX_TX_BAND 0x24
13
+
#define QSERDES_V6_TX_INTERFACE_SELECT 0x2c
14
+
#define QSERDES_V6_TX_RES_CODE_LANE_TX 0x34
15
+
#define QSERDES_V6_TX_RES_CODE_LANE_RX 0x38
16
+
#define QSERDES_V6_TX_RES_CODE_LANE_OFFSET_TX 0x3c
17
+
#define QSERDES_V6_TX_RES_CODE_LANE_OFFSET_RX 0x40
18
+
#define QSERDES_V6_TX_PARRATE_REC_DETECT_IDLE_EN 0x60
19
+
#define QSERDES_V6_TX_BIST_PATTERN7 0x7c
20
+
#define QSERDES_V6_TX_LANE_MODE_1 0x84
21
+
#define QSERDES_V6_TX_LANE_MODE_3 0x8c
22
+
#define QSERDES_V6_TX_LANE_MODE_4 0x90
23
+
#define QSERDES_V6_TX_LANE_MODE_5 0x94
24
+
#define QSERDES_V6_TX_RCV_DETECT_LVL_2 0xa4
25
+
#define QSERDES_V6_TX_TRAN_DRVR_EMP_EN 0xc0
26
+
#define QSERDES_V6_TX_TX_INTERFACE_MODE 0xc4
27
+
#define QSERDES_V6_TX_VMODE_CTRL1 0xc8
28
+
#define QSERDES_V6_TX_PI_QEC_CTRL 0xe4
29
+
30
+
#define QSERDES_V6_RX_UCDR_FO_GAIN 0x08
31
+
#define QSERDES_V6_RX_UCDR_SO_GAIN 0x14
32
+
#define QSERDES_V6_RX_UCDR_FASTLOCK_FO_GAIN 0x30
33
+
#define QSERDES_V6_RX_UCDR_SO_SATURATION_AND_ENABLE 0x34
34
+
#define QSERDES_V6_RX_UCDR_FASTLOCK_COUNT_LOW 0x3c
35
+
#define QSERDES_V6_RX_UCDR_FASTLOCK_COUNT_HIGH 0x40
36
+
#define QSERDES_V6_RX_UCDR_PI_CONTROLS 0x44
37
+
#define QSERDES_V6_RX_UCDR_SB2_THRESH1 0x4c
38
+
#define QSERDES_V6_RX_UCDR_SB2_THRESH2 0x50
39
+
#define QSERDES_V6_RX_UCDR_SB2_GAIN1 0x54
40
+
#define QSERDES_V6_RX_UCDR_SB2_GAIN2 0x58
41
+
#define QSERDES_V6_RX_AUX_DATA_TCOARSE_TFINE 0x60
42
+
#define QSERDES_V6_RX_TX_ADAPT_POST_THRESH 0xcc
43
+
#define QSERDES_V6_RX_VGA_CAL_CNTRL1 0xd4
44
+
#define QSERDES_V6_RX_VGA_CAL_CNTRL2 0xd8
45
+
#define QSERDES_V6_RX_GM_CAL 0xdc
46
+
#define QSERDES_V6_RX_RX_EQU_ADAPTOR_CNTRL2 0xec
47
+
#define QSERDES_V6_RX_RX_EQU_ADAPTOR_CNTRL3 0xf0
48
+
#define QSERDES_V6_RX_RX_EQU_ADAPTOR_CNTRL4 0xf4
49
+
#define QSERDES_V6_RX_RX_IDAC_TSETTLE_LOW 0xf8
50
+
#define QSERDES_V6_RX_RX_IDAC_TSETTLE_HIGH 0xfc
51
+
#define QSERDES_V6_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1 0x110
52
+
#define QSERDES_V6_RX_SIDGET_ENABLES 0x118
53
+
#define QSERDES_V6_RX_SIGDET_CNTRL 0x11c
54
+
#define QSERDES_V6_RX_SIGDET_DEGLITCH_CNTRL 0x124
55
+
#define QSERDES_V6_RX_RX_MODE_00_LOW 0x15c
56
+
#define QSERDES_V6_RX_RX_MODE_00_HIGH 0x160
57
+
#define QSERDES_V6_RX_RX_MODE_00_HIGH2 0x164
58
+
#define QSERDES_V6_RX_RX_MODE_00_HIGH3 0x168
59
+
#define QSERDES_V6_RX_RX_MODE_00_HIGH4 0x16c
60
+
#define QSERDES_V6_RX_RX_MODE_01_LOW 0x170
61
+
#define QSERDES_V6_RX_RX_MODE_01_HIGH 0x174
62
+
#define QSERDES_V6_RX_RX_MODE_01_HIGH2 0x178
63
+
#define QSERDES_V6_RX_RX_MODE_01_HIGH3 0x17c
64
+
#define QSERDES_V6_RX_RX_MODE_01_HIGH4 0x180
65
+
#define QSERDES_V6_RX_RX_MODE_10_LOW 0x184
66
+
#define QSERDES_V6_RX_RX_MODE_10_HIGH 0x188
67
+
#define QSERDES_V6_RX_RX_MODE_10_HIGH2 0x18c
68
+
#define QSERDES_V6_RX_RX_MODE_10_HIGH3 0x190
69
+
#define QSERDES_V6_RX_RX_MODE_10_HIGH4 0x194
70
+
#define QSERDES_V6_RX_DFE_EN_TIMER 0x1a0
71
+
#define QSERDES_V6_RX_DFE_CTLE_POST_CAL_OFFSET 0x1a4
72
+
#define QSERDES_V6_RX_DCC_CTRL1 0x1a8
73
+
#define QSERDES_V6_RX_VTH_CODE 0x1b0
74
+
#define QSERDES_V6_RX_SIGDET_CAL_CTRL1 0x1e4
75
+
#define QSERDES_V6_RX_SIGDET_CAL_TRIM 0x1f8
76
+
77
+
#endif
+45
drivers/phy/qualcomm/phy-qcom-qmp-qserdes-txrx-v6_20.h
+45
drivers/phy/qualcomm/phy-qcom-qmp-qserdes-txrx-v6_20.h
···
1
+
/* SPDX-License-Identifier: GPL-2.0 */
2
+
/*
3
+
* Copyright (c) 2023, Linaro Limited
4
+
*/
5
+
6
+
#ifndef QCOM_PHY_QMP_QSERDES_TXRX_PCIE_V6_20_H_
7
+
#define QCOM_PHY_QMP_QSERDES_TXRX_PCIE_V6_20_H_
8
+
9
+
#define QSERDES_V6_20_TX_RES_CODE_LANE_OFFSET_TX 0x30
10
+
#define QSERDES_V6_20_TX_RES_CODE_LANE_OFFSET_RX 0x34
11
+
#define QSERDES_V6_20_TX_TRAN_DRVR_EMP_EN 0xac
12
+
#define QSERDES_V6_20_TX_LANE_MODE_1 0x78
13
+
#define QSERDES_V6_20_TX_LANE_MODE_2 0x7c
14
+
#define QSERDES_V6_20_TX_LANE_MODE_3 0x80
15
+
16
+
#define QSERDES_V6_20_RX_UCDR_FO_GAIN_RATE_2 0x08
17
+
#define QSERDES_V6_20_RX_UCDR_FO_GAIN_RATE_3 0x0c
18
+
#define QSERDES_V6_20_RX_UCDR_PI_CONTROLS 0x20
19
+
#define QSERDES_V6_20_RX_UCDR_SO_ACC_DEFAULT_VAL_RATE3 0x34
20
+
#define QSERDES_V6_20_RX_IVCM_CAL_CTRL2 0x9c
21
+
#define QSERDES_V6_20_RX_IVCM_POSTCAL_OFFSET 0xa0
22
+
#define QSERDES_V6_20_RX_DFE_3 0xb4
23
+
#define QSERDES_V6_20_RX_VGA_CAL_MAN_VAL 0xe8
24
+
#define QSERDES_V6_20_RX_GM_CAL 0x10c
25
+
#define QSERDES_V6_20_RX_EQU_ADAPTOR_CNTRL4 0x120
26
+
#define QSERDES_V6_20_RX_SIGDET_ENABLES 0x148
27
+
#define QSERDES_V6_20_RX_PHPRE_CTRL 0x188
28
+
#define QSERDES_V6_20_RX_DFE_CTLE_POST_CAL_OFFSET 0x194
29
+
#define QSERDES_V6_20_RX_Q_PI_INTRINSIC_BIAS_RATE32 0x1dc
30
+
#define QSERDES_V6_20_RX_MODE_RATE2_B0 0x1f4
31
+
#define QSERDES_V6_20_RX_MODE_RATE2_B1 0x1f8
32
+
#define QSERDES_V6_20_RX_MODE_RATE2_B2 0x1fc
33
+
#define QSERDES_V6_20_RX_MODE_RATE2_B3 0x200
34
+
#define QSERDES_V6_20_RX_MODE_RATE2_B4 0x204
35
+
#define QSERDES_V6_20_RX_MODE_RATE2_B5 0x208
36
+
#define QSERDES_V6_20_RX_MODE_RATE2_B6 0x20c
37
+
#define QSERDES_V6_20_RX_MODE_RATE3_B0 0x210
38
+
#define QSERDES_V6_20_RX_MODE_RATE3_B1 0x214
39
+
#define QSERDES_V6_20_RX_MODE_RATE3_B2 0x218
40
+
#define QSERDES_V6_20_RX_MODE_RATE3_B3 0x21c
41
+
#define QSERDES_V6_20_RX_MODE_RATE3_B4 0x220
42
+
#define QSERDES_V6_20_RX_MODE_RATE3_B5 0x224
43
+
#define QSERDES_V6_20_RX_MODE_RATE3_B6 0x228
44
+
45
+
#endif
+538
-150
drivers/phy/qualcomm/phy-qcom-qmp-ufs.c
+538
-150
drivers/phy/qualcomm/phy-qcom-qmp-ufs.c
···
20
20
#include <linux/reset.h>
21
21
#include <linux/slab.h>
22
22
23
+
#include <ufs/unipro.h>
23
24
#include "phy-qcom-qmp.h"
25
+
#include "phy-qcom-qmp-pcs-ufs-v2.h"
26
+
#include "phy-qcom-qmp-pcs-ufs-v3.h"
27
+
#include "phy-qcom-qmp-pcs-ufs-v4.h"
28
+
#include "phy-qcom-qmp-pcs-ufs-v5.h"
29
+
#include "phy-qcom-qmp-pcs-ufs-v6.h"
30
+
31
+
#include "phy-qcom-qmp-qserdes-txrx-ufs-v6.h"
24
32
25
33
/* QPHY_SW_RESET bit */
26
34
#define SW_RESET BIT(0)
···
77
69
QPHY_LAYOUT_SIZE
78
70
};
79
71
80
-
static const unsigned int msm8996_ufsphy_regs_layout[QPHY_LAYOUT_SIZE] = {
81
-
[QPHY_START_CTRL] = 0x00,
82
-
[QPHY_PCS_READY_STATUS] = 0x168,
83
-
[QPHY_PCS_POWER_DOWN_CONTROL] = 0x04,
72
+
static const unsigned int ufsphy_v2_regs_layout[QPHY_LAYOUT_SIZE] = {
73
+
[QPHY_START_CTRL] = QPHY_V2_PCS_UFS_PHY_START,
74
+
[QPHY_PCS_READY_STATUS] = QPHY_V2_PCS_UFS_READY_STATUS,
75
+
[QPHY_PCS_POWER_DOWN_CONTROL] = QPHY_V2_PCS_UFS_POWER_DOWN_CONTROL,
84
76
};
85
77
86
-
static const unsigned int sdm845_ufsphy_regs_layout[QPHY_LAYOUT_SIZE] = {
87
-
[QPHY_START_CTRL] = 0x00,
88
-
[QPHY_PCS_READY_STATUS] = 0x160,
89
-
[QPHY_PCS_POWER_DOWN_CONTROL] = 0x04,
78
+
static const unsigned int ufsphy_v3_regs_layout[QPHY_LAYOUT_SIZE] = {
79
+
[QPHY_START_CTRL] = QPHY_V3_PCS_UFS_PHY_START,
80
+
[QPHY_PCS_READY_STATUS] = QPHY_V3_PCS_UFS_READY_STATUS,
81
+
[QPHY_PCS_POWER_DOWN_CONTROL] = QPHY_V3_PCS_UFS_POWER_DOWN_CONTROL,
90
82
};
91
83
92
-
static const unsigned int sm6115_ufsphy_regs_layout[QPHY_LAYOUT_SIZE] = {
93
-
[QPHY_START_CTRL] = 0x00,
94
-
[QPHY_PCS_READY_STATUS] = 0x168,
95
-
[QPHY_PCS_POWER_DOWN_CONTROL] = 0x04,
96
-
};
97
-
98
-
static const unsigned int sm8150_ufsphy_regs_layout[QPHY_LAYOUT_SIZE] = {
84
+
static const unsigned int ufsphy_v4_regs_layout[QPHY_LAYOUT_SIZE] = {
99
85
[QPHY_START_CTRL] = QPHY_V4_PCS_UFS_PHY_START,
100
86
[QPHY_PCS_READY_STATUS] = QPHY_V4_PCS_UFS_READY_STATUS,
101
87
[QPHY_SW_RESET] = QPHY_V4_PCS_UFS_SW_RESET,
102
88
[QPHY_PCS_POWER_DOWN_CONTROL] = QPHY_V4_PCS_UFS_POWER_DOWN_CONTROL,
103
89
};
104
90
105
-
static const struct qmp_phy_init_tbl msm8996_ufs_serdes_tbl[] = {
91
+
static const unsigned int ufsphy_v5_regs_layout[QPHY_LAYOUT_SIZE] = {
92
+
[QPHY_START_CTRL] = QPHY_V5_PCS_UFS_PHY_START,
93
+
[QPHY_PCS_READY_STATUS] = QPHY_V5_PCS_UFS_READY_STATUS,
94
+
[QPHY_SW_RESET] = QPHY_V5_PCS_UFS_SW_RESET,
95
+
[QPHY_PCS_POWER_DOWN_CONTROL] = QPHY_V5_PCS_UFS_POWER_DOWN_CONTROL,
96
+
};
97
+
98
+
static const unsigned int ufsphy_v6_regs_layout[QPHY_LAYOUT_SIZE] = {
99
+
[QPHY_START_CTRL] = QPHY_V6_PCS_UFS_PHY_START,
100
+
[QPHY_PCS_READY_STATUS] = QPHY_V6_PCS_UFS_READY_STATUS,
101
+
[QPHY_SW_RESET] = QPHY_V6_PCS_UFS_SW_RESET,
102
+
[QPHY_PCS_POWER_DOWN_CONTROL] = QPHY_V6_PCS_UFS_POWER_DOWN_CONTROL,
103
+
};
104
+
105
+
static const struct qmp_phy_init_tbl msm8996_ufsphy_serdes[] = {
106
106
QMP_PHY_INIT_CFG(QSERDES_COM_CMN_CONFIG, 0x0e),
107
107
QMP_PHY_INIT_CFG(QSERDES_COM_SYSCLK_EN_SEL, 0xd7),
108
108
QMP_PHY_INIT_CFG(QSERDES_COM_CLK_SELECT, 0x30),
···
159
143
QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP3_MODE1, 0x00),
160
144
};
161
145
162
-
static const struct qmp_phy_init_tbl msm8996_ufs_tx_tbl[] = {
146
+
static const struct qmp_phy_init_tbl msm8996_ufsphy_tx[] = {
163
147
QMP_PHY_INIT_CFG(QSERDES_TX_HIGHZ_TRANSCEIVEREN_BIAS_DRVR_EN, 0x45),
164
148
QMP_PHY_INIT_CFG(QSERDES_TX_LANE_MODE, 0x02),
165
149
};
166
150
167
-
static const struct qmp_phy_init_tbl msm8996_ufs_rx_tbl[] = {
151
+
static const struct qmp_phy_init_tbl msm8996_ufsphy_rx[] = {
168
152
QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_LVL, 0x24),
169
153
QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_CNTRL, 0x02),
170
154
QMP_PHY_INIT_CFG(QSERDES_RX_RX_INTERFACE_MODE, 0x00),
···
178
162
QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0E),
179
163
};
180
164
181
-
static const struct qmp_phy_init_tbl sm6115_ufsphy_serdes_tbl[] = {
165
+
static const struct qmp_phy_init_tbl sm6115_ufsphy_serdes[] = {
182
166
QMP_PHY_INIT_CFG(QSERDES_COM_CMN_CONFIG, 0x0e),
183
167
QMP_PHY_INIT_CFG(QSERDES_COM_SYSCLK_EN_SEL, 0x14),
184
168
QMP_PHY_INIT_CFG(QSERDES_COM_CLK_SELECT, 0x30),
···
229
213
QMP_PHY_INIT_CFG(QSERDES_COM_BG_TRIM, 0x0f),
230
214
QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_INITVAL1, 0xff),
231
215
QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_INITVAL2, 0x00),
216
+
};
232
217
233
-
/* Rate B */
218
+
static const struct qmp_phy_init_tbl sm6115_ufsphy_hs_b_serdes[] = {
234
219
QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_MAP, 0x44),
235
220
};
236
221
237
-
static const struct qmp_phy_init_tbl sm6115_ufsphy_tx_tbl[] = {
222
+
static const struct qmp_phy_init_tbl sm6115_ufsphy_tx[] = {
238
223
QMP_PHY_INIT_CFG(QSERDES_TX_HIGHZ_TRANSCEIVEREN_BIAS_DRVR_EN, 0x45),
239
224
QMP_PHY_INIT_CFG(QSERDES_TX_LANE_MODE, 0x06),
240
225
};
241
226
242
-
static const struct qmp_phy_init_tbl sm6115_ufsphy_rx_tbl[] = {
227
+
static const struct qmp_phy_init_tbl sm6115_ufsphy_rx[] = {
243
228
QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_LVL, 0x24),
244
229
QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_CNTRL, 0x0F),
245
230
QMP_PHY_INIT_CFG(QSERDES_RX_RX_INTERFACE_MODE, 0x40),
···
258
241
QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x5B),
259
242
};
260
243
261
-
static const struct qmp_phy_init_tbl sm6115_ufsphy_pcs_tbl[] = {
262
-
QMP_PHY_INIT_CFG(QPHY_V2_PCS_RX_PWM_GEAR_BAND, 0x15),
263
-
QMP_PHY_INIT_CFG(QPHY_V2_PCS_RX_SIGDET_CTRL2, 0x6d),
264
-
QMP_PHY_INIT_CFG(QPHY_V2_PCS_TX_LARGE_AMP_DRV_LVL, 0x0f),
265
-
QMP_PHY_INIT_CFG(QPHY_V2_PCS_TX_SMALL_AMP_DRV_LVL, 0x02),
266
-
QMP_PHY_INIT_CFG(QPHY_V2_PCS_RX_MIN_STALL_NOCONFIG_TIME_CAP, 0x28),
267
-
QMP_PHY_INIT_CFG(QPHY_V2_PCS_RX_SYM_RESYNC_CTRL, 0x03),
268
-
QMP_PHY_INIT_CFG(QPHY_V2_PCS_TX_LARGE_AMP_POST_EMP_LVL, 0x12),
269
-
QMP_PHY_INIT_CFG(QPHY_V2_PCS_TX_SMALL_AMP_POST_EMP_LVL, 0x0f),
270
-
QMP_PHY_INIT_CFG(QPHY_V2_PCS_RX_MIN_HIBERN8_TIME, 0x9a), /* 8 us */
244
+
static const struct qmp_phy_init_tbl sm6115_ufsphy_pcs[] = {
245
+
QMP_PHY_INIT_CFG(QPHY_V2_PCS_UFS_RX_PWM_GEAR_BAND, 0x15),
246
+
QMP_PHY_INIT_CFG(QPHY_V2_PCS_UFS_RX_SIGDET_CTRL2, 0x6d),
247
+
QMP_PHY_INIT_CFG(QPHY_V2_PCS_UFS_TX_LARGE_AMP_DRV_LVL, 0x0f),
248
+
QMP_PHY_INIT_CFG(QPHY_V2_PCS_UFS_TX_SMALL_AMP_DRV_LVL, 0x02),
249
+
QMP_PHY_INIT_CFG(QPHY_V2_PCS_UFS_RX_MIN_STALL_NOCONFIG_TIME_CAP, 0x28),
250
+
QMP_PHY_INIT_CFG(QPHY_V2_PCS_UFS_RX_SYM_RESYNC_CTRL, 0x03),
251
+
QMP_PHY_INIT_CFG(QPHY_V2_PCS_UFS_TX_LARGE_AMP_POST_EMP_LVL, 0x12),
252
+
QMP_PHY_INIT_CFG(QPHY_V2_PCS_UFS_TX_SMALL_AMP_POST_EMP_LVL, 0x0f),
253
+
QMP_PHY_INIT_CFG(QPHY_V2_PCS_UFS_RX_MIN_HIBERN8_TIME, 0x9a), /* 8 us */
271
254
};
272
255
273
-
static const struct qmp_phy_init_tbl sdm845_ufsphy_serdes_tbl[] = {
256
+
static const struct qmp_phy_init_tbl sdm845_ufsphy_serdes[] = {
274
257
QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYS_CLK_CTRL, 0x02),
275
258
QMP_PHY_INIT_CFG(QSERDES_V3_COM_BIAS_EN_CLKBUFLR_EN, 0x04),
276
259
QMP_PHY_INIT_CFG(QSERDES_V3_COM_BG_TIMER, 0x0a),
···
307
290
QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE2_MODE1, 0x00),
308
291
QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP1_MODE1, 0x32),
309
292
QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP2_MODE1, 0x0f),
293
+
};
310
294
311
-
/* Rate B */
295
+
static const struct qmp_phy_init_tbl sdm845_ufsphy_hs_b_serdes[] = {
312
296
QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_MAP, 0x44),
313
297
};
314
298
315
-
static const struct qmp_phy_init_tbl sdm845_ufsphy_tx_tbl[] = {
299
+
static const struct qmp_phy_init_tbl sdm845_ufsphy_tx[] = {
316
300
QMP_PHY_INIT_CFG(QSERDES_V3_TX_LANE_MODE_1, 0x06),
317
301
QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_TX, 0x04),
318
302
QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_RX, 0x07),
319
303
};
320
304
321
-
static const struct qmp_phy_init_tbl sdm845_ufsphy_rx_tbl[] = {
305
+
static const struct qmp_phy_init_tbl sdm845_ufsphy_rx[] = {
322
306
QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_LVL, 0x24),
323
307
QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_CNTRL, 0x0f),
324
308
QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_DEGLITCH_CNTRL, 0x1e),
···
338
320
QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_MODE_00, 0x59),
339
321
};
340
322
341
-
static const struct qmp_phy_init_tbl sdm845_ufsphy_pcs_tbl[] = {
323
+
static const struct qmp_phy_init_tbl sdm845_ufsphy_pcs[] = {
342
324
QMP_PHY_INIT_CFG(QPHY_V3_PCS_UFS_RX_SIGDET_CTRL2, 0x6e),
343
325
QMP_PHY_INIT_CFG(QPHY_V3_PCS_UFS_TX_LARGE_AMP_DRV_LVL, 0x0a),
344
326
QMP_PHY_INIT_CFG(QPHY_V3_PCS_UFS_TX_SMALL_AMP_DRV_LVL, 0x02),
···
349
331
QMP_PHY_INIT_CFG(QPHY_V3_PCS_UFS_MULTI_LANE_CTRL1, 0x02),
350
332
};
351
333
352
-
static const struct qmp_phy_init_tbl sm8150_ufsphy_serdes_tbl[] = {
334
+
static const struct qmp_phy_init_tbl sm8150_ufsphy_serdes[] = {
353
335
QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYSCLK_EN_SEL, 0xd9),
354
336
QMP_PHY_INIT_CFG(QSERDES_V4_COM_HSCLK_SEL, 0x11),
355
337
QMP_PHY_INIT_CFG(QSERDES_V4_COM_HSCLK_HS_SWITCH_SEL, 0x00),
···
374
356
QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE1, 0x0f),
375
357
QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE1, 0xdd),
376
358
QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE1, 0x23),
359
+
};
377
360
378
-
/* Rate B */
361
+
static const struct qmp_phy_init_tbl sm8150_ufsphy_hs_b_serdes[] = {
379
362
QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE_MAP, 0x06),
380
363
};
381
364
382
-
static const struct qmp_phy_init_tbl sm8150_ufsphy_tx_tbl[] = {
365
+
static const struct qmp_phy_init_tbl sm8150_ufsphy_tx[] = {
383
366
QMP_PHY_INIT_CFG(QSERDES_V4_TX_PWM_GEAR_1_DIVIDER_BAND0_1, 0x06),
384
367
QMP_PHY_INIT_CFG(QSERDES_V4_TX_PWM_GEAR_2_DIVIDER_BAND0_1, 0x03),
385
368
QMP_PHY_INIT_CFG(QSERDES_V4_TX_PWM_GEAR_3_DIVIDER_BAND0_1, 0x01),
···
389
370
QMP_PHY_INIT_CFG(QSERDES_V4_TX_TRAN_DRVR_EMP_EN, 0x0c),
390
371
};
391
372
392
-
static const struct qmp_phy_init_tbl sm8150_ufsphy_rx_tbl[] = {
373
+
static const struct qmp_phy_init_tbl sm8150_ufsphy_hs_g4_tx[] = {
374
+
QMP_PHY_INIT_CFG(QSERDES_V4_TX_LANE_MODE_1, 0x75),
375
+
};
376
+
377
+
static const struct qmp_phy_init_tbl sm8150_ufsphy_rx[] = {
393
378
QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_LVL, 0x24),
394
379
QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_CNTRL, 0x0f),
395
380
QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_DEGLITCH_CNTRL, 0x1e),
···
428
405
QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH2, 0xc8),
429
406
QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH3, 0x3b),
430
407
QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH4, 0xb1),
431
-
432
408
};
433
409
434
-
static const struct qmp_phy_init_tbl sm8150_ufsphy_pcs_tbl[] = {
410
+
static const struct qmp_phy_init_tbl sm8150_ufsphy_hs_g4_rx[] = {
411
+
QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x5a),
412
+
QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_PI_CTRL2, 0x81),
413
+
QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FO_GAIN, 0x0e),
414
+
QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_TERM_BW, 0x6f),
415
+
QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_MEASURE_TIME, 0x20),
416
+
QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_LOW, 0x80),
417
+
QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_HIGH, 0x01),
418
+
QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_LOW, 0x3f),
419
+
QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH, 0xff),
420
+
QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH2, 0xff),
421
+
QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH3, 0x7f),
422
+
QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH4, 0x6c),
423
+
QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_LOW, 0x6d),
424
+
QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH, 0x6d),
425
+
QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH2, 0xed),
426
+
QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH4, 0x3c),
427
+
};
428
+
429
+
static const struct qmp_phy_init_tbl sm8150_ufsphy_pcs[] = {
435
430
QMP_PHY_INIT_CFG(QPHY_V4_PCS_UFS_RX_SIGDET_CTRL2, 0x6d),
436
431
QMP_PHY_INIT_CFG(QPHY_V4_PCS_UFS_TX_LARGE_AMP_DRV_LVL, 0x0a),
437
432
QMP_PHY_INIT_CFG(QPHY_V4_PCS_UFS_TX_SMALL_AMP_DRV_LVL, 0x02),
···
459
418
QMP_PHY_INIT_CFG(QPHY_V4_PCS_UFS_MULTI_LANE_CTRL1, 0x02),
460
419
};
461
420
462
-
static const struct qmp_phy_init_tbl sm8350_ufsphy_serdes_tbl[] = {
421
+
static const struct qmp_phy_init_tbl sm8150_ufsphy_hs_g4_pcs[] = {
422
+
QMP_PHY_INIT_CFG(QPHY_V4_PCS_UFS_TX_LARGE_AMP_DRV_LVL, 0x10),
423
+
QMP_PHY_INIT_CFG(QPHY_V4_PCS_UFS_BIST_FIXED_PAT_CTRL, 0x0a),
424
+
};
425
+
426
+
static const struct qmp_phy_init_tbl sm8250_ufsphy_hs_g4_tx[] = {
427
+
QMP_PHY_INIT_CFG(QSERDES_V4_TX_LANE_MODE_1, 0xe5),
428
+
};
429
+
430
+
static const struct qmp_phy_init_tbl sm8250_ufsphy_hs_g4_rx[] = {
431
+
QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x5a),
432
+
QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_PI_CTRL2, 0x81),
433
+
QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FO_GAIN, 0x0e),
434
+
QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_TERM_BW, 0x6f),
435
+
QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL1, 0x04),
436
+
QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL2, 0x00),
437
+
QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL3, 0x09),
438
+
QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL4, 0x07),
439
+
QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x17),
440
+
QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_MEASURE_TIME, 0x20),
441
+
QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_LOW, 0x80),
442
+
QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_HIGH, 0x01),
443
+
QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_LOW, 0x3f),
444
+
QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH, 0xff),
445
+
QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH2, 0xff),
446
+
QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH3, 0x7f),
447
+
QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH4, 0x2c),
448
+
QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_LOW, 0x6d),
449
+
QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH, 0x6d),
450
+
QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH2, 0xed),
451
+
QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH4, 0x3c),
452
+
};
453
+
454
+
static const struct qmp_phy_init_tbl sm8350_ufsphy_serdes[] = {
463
455
QMP_PHY_INIT_CFG(QSERDES_V5_COM_SYSCLK_EN_SEL, 0xd9),
464
456
QMP_PHY_INIT_CFG(QSERDES_V5_COM_HSCLK_SEL, 0x11),
465
457
QMP_PHY_INIT_CFG(QSERDES_V5_COM_HSCLK_HS_SWITCH_SEL, 0x00),
···
517
443
QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP2_MODE1, 0x1e),
518
444
QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIN_VCOCAL_CMP_CODE1_MODE1, 0xdd),
519
445
QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIN_VCOCAL_CMP_CODE2_MODE1, 0x23),
446
+
};
520
447
521
-
/* Rate B */
448
+
static const struct qmp_phy_init_tbl sm8350_ufsphy_hs_b_serdes[] = {
522
449
QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_TUNE_MAP, 0x06),
523
450
};
524
451
525
-
static const struct qmp_phy_init_tbl sm8350_ufsphy_tx_tbl[] = {
452
+
static const struct qmp_phy_init_tbl sm8350_ufsphy_tx[] = {
526
453
QMP_PHY_INIT_CFG(QSERDES_V5_TX_PWM_GEAR_1_DIVIDER_BAND0_1, 0x06),
527
454
QMP_PHY_INIT_CFG(QSERDES_V5_TX_PWM_GEAR_2_DIVIDER_BAND0_1, 0x03),
528
455
QMP_PHY_INIT_CFG(QSERDES_V5_TX_PWM_GEAR_3_DIVIDER_BAND0_1, 0x01),
···
535
460
QMP_PHY_INIT_CFG(QSERDES_V5_TX_TRAN_DRVR_EMP_EN, 0x0c),
536
461
};
537
462
538
-
static const struct qmp_phy_init_tbl sm8350_ufsphy_rx_tbl[] = {
463
+
static const struct qmp_phy_init_tbl sm8350_ufsphy_rx[] = {
539
464
QMP_PHY_INIT_CFG(QSERDES_V5_RX_SIGDET_LVL, 0x24),
540
465
QMP_PHY_INIT_CFG(QSERDES_V5_RX_SIGDET_CNTRL, 0x0f),
541
466
QMP_PHY_INIT_CFG(QSERDES_V5_RX_SIGDET_DEGLITCH_CNTRL, 0x1e),
···
575
500
QMP_PHY_INIT_CFG(QSERDES_V5_RX_DCC_CTRL1, 0x0c),
576
501
};
577
502
578
-
static const struct qmp_phy_init_tbl sm8350_ufsphy_pcs_tbl[] = {
503
+
static const struct qmp_phy_init_tbl sm8350_ufsphy_pcs[] = {
579
504
QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_RX_SIGDET_CTRL2, 0x6d),
580
505
QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_TX_LARGE_AMP_DRV_LVL, 0x0a),
581
506
QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_TX_SMALL_AMP_DRV_LVL, 0x02),
582
507
QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_TX_MID_TERM_CTRL1, 0x43),
583
508
QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_DEBUG_BUS_CLKSEL, 0x1f),
584
509
QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_RX_MIN_HIBERN8_TIME, 0xff),
585
-
QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_PLL_CNTL, 0x03),
586
-
QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_TIMER_20US_CORECLK_STEPS_MSB, 0x16),
587
-
QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_TIMER_20US_CORECLK_STEPS_LSB, 0xd8),
588
-
QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_TX_PWM_GEAR_BAND, 0xaa),
589
-
QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_TX_HS_GEAR_BAND, 0x06),
590
-
QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_TX_HSGEAR_CAPABILITY, 0x03),
591
-
QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_RX_HSGEAR_CAPABILITY, 0x03),
592
510
QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_RX_SIGDET_CTRL1, 0x0e),
593
511
QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_MULTI_LANE_CTRL1, 0x02),
512
+
};
513
+
514
+
static const struct qmp_phy_init_tbl sm8350_ufsphy_g4_tx[] = {
515
+
QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_1, 0xe5),
516
+
};
517
+
518
+
static const struct qmp_phy_init_tbl sm8350_ufsphy_g4_rx[] = {
519
+
QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_PI_CTRL2, 0x81),
520
+
QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_TERM_BW, 0x6f),
521
+
QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL2, 0x00),
522
+
QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4a),
523
+
QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL4, 0x0a),
524
+
QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_IDAC_MEASURE_TIME, 0x20),
525
+
QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_IDAC_TSETTLE_LOW, 0x80),
526
+
QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_IDAC_TSETTLE_HIGH, 0x01),
527
+
QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_LOW, 0xbf),
528
+
QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH, 0xbf),
529
+
QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH2, 0x7f),
530
+
QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH3, 0x7f),
531
+
QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH4, 0x2d),
532
+
QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_LOW, 0x6d),
533
+
QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH, 0x6d),
534
+
QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH2, 0xed),
535
+
QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH4, 0x3c),
536
+
};
537
+
538
+
static const struct qmp_phy_init_tbl sm8350_ufsphy_g4_pcs[] = {
539
+
QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_BIST_FIXED_PAT_CTRL, 0x0a),
540
+
};
541
+
542
+
static const struct qmp_phy_init_tbl sm8550_ufsphy_serdes[] = {
543
+
QMP_PHY_INIT_CFG(QSERDES_V6_COM_SYSCLK_EN_SEL, 0xd9),
544
+
QMP_PHY_INIT_CFG(QSERDES_V6_COM_CMN_CONFIG_1, 0x16),
545
+
QMP_PHY_INIT_CFG(QSERDES_V6_COM_HSCLK_SEL_1, 0x11),
546
+
QMP_PHY_INIT_CFG(QSERDES_V6_COM_HSCLK_HS_SWITCH_SEL_1, 0x00),
547
+
QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP_EN, 0x01),
548
+
QMP_PHY_INIT_CFG(QSERDES_V6_COM_VCO_TUNE_MAP, 0x04),
549
+
QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_IVCO, 0x0f),
550
+
QMP_PHY_INIT_CFG(QSERDES_V6_COM_VCO_TUNE_INITVAL2, 0x00),
551
+
QMP_PHY_INIT_CFG(QSERDES_V6_COM_DEC_START_MODE0, 0x41),
552
+
QMP_PHY_INIT_CFG(QSERDES_V6_COM_CP_CTRL_MODE0, 0x0a),
553
+
QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_RCTRL_MODE0, 0x18),
554
+
QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_CCTRL_MODE0, 0x14),
555
+
QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP1_MODE0, 0x7f),
556
+
QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP2_MODE0, 0x06),
557
+
QMP_PHY_INIT_CFG(QSERDES_V6_COM_DEC_START_MODE0, 0x4c),
558
+
QMP_PHY_INIT_CFG(QSERDES_V6_COM_CP_CTRL_MODE0, 0x0a),
559
+
QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_RCTRL_MODE0, 0x18),
560
+
QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_CCTRL_MODE0, 0x14),
561
+
QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP1_MODE0, 0x99),
562
+
QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP2_MODE0, 0x07),
563
+
};
564
+
565
+
static const struct qmp_phy_init_tbl sm8550_ufsphy_tx[] = {
566
+
QMP_PHY_INIT_CFG(QSERDES_V6_TX_LANE_MODE_1, 0x05),
567
+
QMP_PHY_INIT_CFG(QSERDES_UFS_V6_TX_RES_CODE_LANE_OFFSET_TX, 0x07),
568
+
};
569
+
570
+
static const struct qmp_phy_init_tbl sm8550_ufsphy_rx[] = {
571
+
QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_UCDR_FASTLOCK_FO_GAIN_RATE2, 0x0c),
572
+
QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_UCDR_FASTLOCK_FO_GAIN_RATE4, 0x0f),
573
+
QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_VGA_CAL_MAN_VAL, 0x0e),
574
+
575
+
QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_MODE_RATE_0_1_B0, 0xc2),
576
+
QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_MODE_RATE_0_1_B1, 0xc2),
577
+
QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_MODE_RATE_0_1_B3, 0x1a),
578
+
QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_MODE_RATE_0_1_B6, 0x60),
579
+
580
+
QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_MODE_RATE2_B3, 0x9e),
581
+
QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_MODE_RATE2_B6, 0x60),
582
+
583
+
QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_MODE_RATE3_B3, 0x9e),
584
+
QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_MODE_RATE3_B4, 0x0e),
585
+
QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_MODE_RATE3_B5, 0x36),
586
+
QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_MODE_RATE3_B8, 0x02),
587
+
};
588
+
589
+
static const struct qmp_phy_init_tbl sm8550_ufsphy_pcs[] = {
590
+
QMP_PHY_INIT_CFG(QPHY_V6_PCS_UFS_RX_SIGDET_CTRL2, 0x69),
591
+
QMP_PHY_INIT_CFG(QPHY_V6_PCS_UFS_TX_LARGE_AMP_DRV_LVL, 0x0f),
592
+
QMP_PHY_INIT_CFG(QPHY_V6_PCS_UFS_TX_MID_TERM_CTRL1, 0x43),
593
+
QMP_PHY_INIT_CFG(QPHY_V6_PCS_UFS_PLL_CNTL, 0x2b),
594
+
QMP_PHY_INIT_CFG(QPHY_V6_PCS_UFS_MULTI_LANE_CTRL1, 0x02),
594
595
};
595
596
596
597
struct qmp_ufs_offsets {
···
678
527
u16 rx2;
679
528
};
680
529
530
+
struct qmp_phy_cfg_tbls {
531
+
/* Init sequence for PHY blocks - serdes, tx, rx, pcs */
532
+
const struct qmp_phy_init_tbl *serdes;
533
+
int serdes_num;
534
+
const struct qmp_phy_init_tbl *tx;
535
+
int tx_num;
536
+
const struct qmp_phy_init_tbl *rx;
537
+
int rx_num;
538
+
const struct qmp_phy_init_tbl *pcs;
539
+
int pcs_num;
540
+
};
541
+
681
542
/* struct qmp_phy_cfg - per-PHY initialization config */
682
543
struct qmp_phy_cfg {
683
544
int lanes;
684
545
685
546
const struct qmp_ufs_offsets *offsets;
686
547
687
-
/* Init sequence for PHY blocks - serdes, tx, rx, pcs */
688
-
const struct qmp_phy_init_tbl *serdes_tbl;
689
-
int serdes_tbl_num;
690
-
const struct qmp_phy_init_tbl *tx_tbl;
691
-
int tx_tbl_num;
692
-
const struct qmp_phy_init_tbl *rx_tbl;
693
-
int rx_tbl_num;
694
-
const struct qmp_phy_init_tbl *pcs_tbl;
695
-
int pcs_tbl_num;
548
+
/* Main init sequence for PHY blocks - serdes, tx, rx, pcs */
549
+
const struct qmp_phy_cfg_tbls tbls;
550
+
/* Additional sequence for HS Series B */
551
+
const struct qmp_phy_cfg_tbls tbls_hs_b;
552
+
/* Additional sequence for HS G4 */
553
+
const struct qmp_phy_cfg_tbls tbls_hs_g4;
696
554
697
555
/* clock ids to be requested */
698
556
const char * const *clk_list;
···
735
575
struct reset_control *ufs_reset;
736
576
737
577
struct phy *phy;
578
+
u32 mode;
579
+
u32 submode;
738
580
};
739
581
740
582
static inline void qphy_setbits(void __iomem *base, u32 offset, u32 val)
···
782
620
"vdda-phy", "vdda-pll",
783
621
};
784
622
785
-
static const struct qmp_ufs_offsets qmp_ufs_offsets_v5 = {
623
+
static const struct qmp_ufs_offsets qmp_ufs_offsets = {
786
624
.serdes = 0,
787
625
.pcs = 0xc00,
788
626
.tx = 0x400,
···
791
629
.rx2 = 0xa00,
792
630
};
793
631
794
-
static const struct qmp_phy_cfg msm8996_ufs_cfg = {
632
+
static const struct qmp_ufs_offsets qmp_ufs_offsets_v6 = {
633
+
.serdes = 0,
634
+
.pcs = 0x0400,
635
+
.tx = 0x1000,
636
+
.rx = 0x1200,
637
+
.tx2 = 0x1800,
638
+
.rx2 = 0x1a00,
639
+
};
640
+
641
+
static const struct qmp_phy_cfg msm8996_ufsphy_cfg = {
795
642
.lanes = 1,
796
643
797
-
.serdes_tbl = msm8996_ufs_serdes_tbl,
798
-
.serdes_tbl_num = ARRAY_SIZE(msm8996_ufs_serdes_tbl),
799
-
.tx_tbl = msm8996_ufs_tx_tbl,
800
-
.tx_tbl_num = ARRAY_SIZE(msm8996_ufs_tx_tbl),
801
-
.rx_tbl = msm8996_ufs_rx_tbl,
802
-
.rx_tbl_num = ARRAY_SIZE(msm8996_ufs_rx_tbl),
644
+
.tbls = {
645
+
.serdes = msm8996_ufsphy_serdes,
646
+
.serdes_num = ARRAY_SIZE(msm8996_ufsphy_serdes),
647
+
.tx = msm8996_ufsphy_tx,
648
+
.tx_num = ARRAY_SIZE(msm8996_ufsphy_tx),
649
+
.rx = msm8996_ufsphy_rx,
650
+
.rx_num = ARRAY_SIZE(msm8996_ufsphy_rx),
651
+
},
803
652
804
653
.clk_list = msm8996_ufs_phy_clk_l,
805
654
.num_clks = ARRAY_SIZE(msm8996_ufs_phy_clk_l),
···
818
645
.vreg_list = qmp_phy_vreg_l,
819
646
.num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
820
647
821
-
.regs = msm8996_ufsphy_regs_layout,
648
+
.regs = ufsphy_v2_regs_layout,
822
649
823
650
.no_pcs_sw_reset = true,
824
651
};
···
826
653
static const struct qmp_phy_cfg sc8280xp_ufsphy_cfg = {
827
654
.lanes = 2,
828
655
829
-
.offsets = &qmp_ufs_offsets_v5,
656
+
.offsets = &qmp_ufs_offsets,
830
657
831
-
.serdes_tbl = sm8350_ufsphy_serdes_tbl,
832
-
.serdes_tbl_num = ARRAY_SIZE(sm8350_ufsphy_serdes_tbl),
833
-
.tx_tbl = sm8350_ufsphy_tx_tbl,
834
-
.tx_tbl_num = ARRAY_SIZE(sm8350_ufsphy_tx_tbl),
835
-
.rx_tbl = sm8350_ufsphy_rx_tbl,
836
-
.rx_tbl_num = ARRAY_SIZE(sm8350_ufsphy_rx_tbl),
837
-
.pcs_tbl = sm8350_ufsphy_pcs_tbl,
838
-
.pcs_tbl_num = ARRAY_SIZE(sm8350_ufsphy_pcs_tbl),
658
+
.tbls = {
659
+
.serdes = sm8350_ufsphy_serdes,
660
+
.serdes_num = ARRAY_SIZE(sm8350_ufsphy_serdes),
661
+
.tx = sm8350_ufsphy_tx,
662
+
.tx_num = ARRAY_SIZE(sm8350_ufsphy_tx),
663
+
.rx = sm8350_ufsphy_rx,
664
+
.rx_num = ARRAY_SIZE(sm8350_ufsphy_rx),
665
+
.pcs = sm8350_ufsphy_pcs,
666
+
.pcs_num = ARRAY_SIZE(sm8350_ufsphy_pcs),
667
+
},
668
+
.tbls_hs_b = {
669
+
.serdes = sm8350_ufsphy_hs_b_serdes,
670
+
.serdes_num = ARRAY_SIZE(sm8350_ufsphy_hs_b_serdes),
671
+
},
672
+
.tbls_hs_g4 = {
673
+
.tx = sm8350_ufsphy_g4_tx,
674
+
.tx_num = ARRAY_SIZE(sm8350_ufsphy_g4_tx),
675
+
.rx = sm8350_ufsphy_g4_rx,
676
+
.rx_num = ARRAY_SIZE(sm8350_ufsphy_g4_rx),
677
+
.pcs = sm8350_ufsphy_g4_pcs,
678
+
.pcs_num = ARRAY_SIZE(sm8350_ufsphy_g4_pcs),
679
+
},
839
680
.clk_list = sdm845_ufs_phy_clk_l,
840
681
.num_clks = ARRAY_SIZE(sdm845_ufs_phy_clk_l),
841
682
.vreg_list = qmp_phy_vreg_l,
842
683
.num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
843
-
.regs = sm8150_ufsphy_regs_layout,
684
+
.regs = ufsphy_v5_regs_layout,
844
685
};
845
686
846
687
static const struct qmp_phy_cfg sdm845_ufsphy_cfg = {
847
688
.lanes = 2,
848
689
849
-
.serdes_tbl = sdm845_ufsphy_serdes_tbl,
850
-
.serdes_tbl_num = ARRAY_SIZE(sdm845_ufsphy_serdes_tbl),
851
-
.tx_tbl = sdm845_ufsphy_tx_tbl,
852
-
.tx_tbl_num = ARRAY_SIZE(sdm845_ufsphy_tx_tbl),
853
-
.rx_tbl = sdm845_ufsphy_rx_tbl,
854
-
.rx_tbl_num = ARRAY_SIZE(sdm845_ufsphy_rx_tbl),
855
-
.pcs_tbl = sdm845_ufsphy_pcs_tbl,
856
-
.pcs_tbl_num = ARRAY_SIZE(sdm845_ufsphy_pcs_tbl),
690
+
.tbls = {
691
+
.serdes = sdm845_ufsphy_serdes,
692
+
.serdes_num = ARRAY_SIZE(sdm845_ufsphy_serdes),
693
+
.tx = sdm845_ufsphy_tx,
694
+
.tx_num = ARRAY_SIZE(sdm845_ufsphy_tx),
695
+
.rx = sdm845_ufsphy_rx,
696
+
.rx_num = ARRAY_SIZE(sdm845_ufsphy_rx),
697
+
.pcs = sdm845_ufsphy_pcs,
698
+
.pcs_num = ARRAY_SIZE(sdm845_ufsphy_pcs),
699
+
},
700
+
.tbls_hs_b = {
701
+
.serdes = sdm845_ufsphy_hs_b_serdes,
702
+
.serdes_num = ARRAY_SIZE(sdm845_ufsphy_hs_b_serdes),
703
+
},
857
704
.clk_list = sdm845_ufs_phy_clk_l,
858
705
.num_clks = ARRAY_SIZE(sdm845_ufs_phy_clk_l),
859
706
.vreg_list = qmp_phy_vreg_l,
860
707
.num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
861
-
.regs = sdm845_ufsphy_regs_layout,
708
+
.regs = ufsphy_v3_regs_layout,
862
709
863
710
.no_pcs_sw_reset = true,
864
711
};
···
886
693
static const struct qmp_phy_cfg sm6115_ufsphy_cfg = {
887
694
.lanes = 1,
888
695
889
-
.serdes_tbl = sm6115_ufsphy_serdes_tbl,
890
-
.serdes_tbl_num = ARRAY_SIZE(sm6115_ufsphy_serdes_tbl),
891
-
.tx_tbl = sm6115_ufsphy_tx_tbl,
892
-
.tx_tbl_num = ARRAY_SIZE(sm6115_ufsphy_tx_tbl),
893
-
.rx_tbl = sm6115_ufsphy_rx_tbl,
894
-
.rx_tbl_num = ARRAY_SIZE(sm6115_ufsphy_rx_tbl),
895
-
.pcs_tbl = sm6115_ufsphy_pcs_tbl,
896
-
.pcs_tbl_num = ARRAY_SIZE(sm6115_ufsphy_pcs_tbl),
696
+
.offsets = &qmp_ufs_offsets,
697
+
698
+
.tbls = {
699
+
.serdes = sm6115_ufsphy_serdes,
700
+
.serdes_num = ARRAY_SIZE(sm6115_ufsphy_serdes),
701
+
.tx = sm6115_ufsphy_tx,
702
+
.tx_num = ARRAY_SIZE(sm6115_ufsphy_tx),
703
+
.rx = sm6115_ufsphy_rx,
704
+
.rx_num = ARRAY_SIZE(sm6115_ufsphy_rx),
705
+
.pcs = sm6115_ufsphy_pcs,
706
+
.pcs_num = ARRAY_SIZE(sm6115_ufsphy_pcs),
707
+
},
708
+
.tbls_hs_b = {
709
+
.serdes = sm6115_ufsphy_hs_b_serdes,
710
+
.serdes_num = ARRAY_SIZE(sm6115_ufsphy_hs_b_serdes),
711
+
},
897
712
.clk_list = sdm845_ufs_phy_clk_l,
898
713
.num_clks = ARRAY_SIZE(sdm845_ufs_phy_clk_l),
899
714
.vreg_list = qmp_phy_vreg_l,
900
715
.num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
901
-
.regs = sm6115_ufsphy_regs_layout,
716
+
.regs = ufsphy_v2_regs_layout,
902
717
903
718
.no_pcs_sw_reset = true,
904
719
};
···
914
713
static const struct qmp_phy_cfg sm8150_ufsphy_cfg = {
915
714
.lanes = 2,
916
715
917
-
.serdes_tbl = sm8150_ufsphy_serdes_tbl,
918
-
.serdes_tbl_num = ARRAY_SIZE(sm8150_ufsphy_serdes_tbl),
919
-
.tx_tbl = sm8150_ufsphy_tx_tbl,
920
-
.tx_tbl_num = ARRAY_SIZE(sm8150_ufsphy_tx_tbl),
921
-
.rx_tbl = sm8150_ufsphy_rx_tbl,
922
-
.rx_tbl_num = ARRAY_SIZE(sm8150_ufsphy_rx_tbl),
923
-
.pcs_tbl = sm8150_ufsphy_pcs_tbl,
924
-
.pcs_tbl_num = ARRAY_SIZE(sm8150_ufsphy_pcs_tbl),
716
+
.tbls = {
717
+
.serdes = sm8150_ufsphy_serdes,
718
+
.serdes_num = ARRAY_SIZE(sm8150_ufsphy_serdes),
719
+
.tx = sm8150_ufsphy_tx,
720
+
.tx_num = ARRAY_SIZE(sm8150_ufsphy_tx),
721
+
.rx = sm8150_ufsphy_rx,
722
+
.rx_num = ARRAY_SIZE(sm8150_ufsphy_rx),
723
+
.pcs = sm8150_ufsphy_pcs,
724
+
.pcs_num = ARRAY_SIZE(sm8150_ufsphy_pcs),
725
+
},
726
+
.tbls_hs_b = {
727
+
.serdes = sm8150_ufsphy_hs_b_serdes,
728
+
.serdes_num = ARRAY_SIZE(sm8150_ufsphy_hs_b_serdes),
729
+
},
730
+
.tbls_hs_g4 = {
731
+
.tx = sm8150_ufsphy_hs_g4_tx,
732
+
.tx_num = ARRAY_SIZE(sm8150_ufsphy_hs_g4_tx),
733
+
.rx = sm8150_ufsphy_hs_g4_rx,
734
+
.rx_num = ARRAY_SIZE(sm8150_ufsphy_hs_g4_rx),
735
+
.pcs = sm8150_ufsphy_hs_g4_pcs,
736
+
.pcs_num = ARRAY_SIZE(sm8150_ufsphy_hs_g4_pcs),
737
+
},
925
738
.clk_list = sdm845_ufs_phy_clk_l,
926
739
.num_clks = ARRAY_SIZE(sdm845_ufs_phy_clk_l),
927
740
.vreg_list = qmp_phy_vreg_l,
928
741
.num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
929
-
.regs = sm8150_ufsphy_regs_layout,
742
+
.regs = ufsphy_v4_regs_layout,
743
+
};
744
+
745
+
static const struct qmp_phy_cfg sm8250_ufsphy_cfg = {
746
+
.lanes = 2,
747
+
748
+
.tbls = {
749
+
.serdes = sm8150_ufsphy_serdes,
750
+
.serdes_num = ARRAY_SIZE(sm8150_ufsphy_serdes),
751
+
.tx = sm8150_ufsphy_tx,
752
+
.tx_num = ARRAY_SIZE(sm8150_ufsphy_tx),
753
+
.rx = sm8150_ufsphy_rx,
754
+
.rx_num = ARRAY_SIZE(sm8150_ufsphy_rx),
755
+
.pcs = sm8150_ufsphy_pcs,
756
+
.pcs_num = ARRAY_SIZE(sm8150_ufsphy_pcs),
757
+
},
758
+
.tbls_hs_b = {
759
+
.serdes = sm8150_ufsphy_hs_b_serdes,
760
+
.serdes_num = ARRAY_SIZE(sm8150_ufsphy_hs_b_serdes),
761
+
},
762
+
.tbls_hs_g4 = {
763
+
.tx = sm8250_ufsphy_hs_g4_tx,
764
+
.tx_num = ARRAY_SIZE(sm8250_ufsphy_hs_g4_tx),
765
+
.rx = sm8250_ufsphy_hs_g4_rx,
766
+
.rx_num = ARRAY_SIZE(sm8250_ufsphy_hs_g4_rx),
767
+
.pcs = sm8150_ufsphy_hs_g4_pcs,
768
+
.pcs_num = ARRAY_SIZE(sm8150_ufsphy_hs_g4_pcs),
769
+
},
770
+
.clk_list = sdm845_ufs_phy_clk_l,
771
+
.num_clks = ARRAY_SIZE(sdm845_ufs_phy_clk_l),
772
+
.vreg_list = qmp_phy_vreg_l,
773
+
.num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
774
+
.regs = ufsphy_v4_regs_layout,
930
775
};
931
776
932
777
static const struct qmp_phy_cfg sm8350_ufsphy_cfg = {
933
778
.lanes = 2,
934
779
935
-
.serdes_tbl = sm8350_ufsphy_serdes_tbl,
936
-
.serdes_tbl_num = ARRAY_SIZE(sm8350_ufsphy_serdes_tbl),
937
-
.tx_tbl = sm8350_ufsphy_tx_tbl,
938
-
.tx_tbl_num = ARRAY_SIZE(sm8350_ufsphy_tx_tbl),
939
-
.rx_tbl = sm8350_ufsphy_rx_tbl,
940
-
.rx_tbl_num = ARRAY_SIZE(sm8350_ufsphy_rx_tbl),
941
-
.pcs_tbl = sm8350_ufsphy_pcs_tbl,
942
-
.pcs_tbl_num = ARRAY_SIZE(sm8350_ufsphy_pcs_tbl),
780
+
.tbls = {
781
+
.serdes = sm8350_ufsphy_serdes,
782
+
.serdes_num = ARRAY_SIZE(sm8350_ufsphy_serdes),
783
+
.tx = sm8350_ufsphy_tx,
784
+
.tx_num = ARRAY_SIZE(sm8350_ufsphy_tx),
785
+
.rx = sm8350_ufsphy_rx,
786
+
.rx_num = ARRAY_SIZE(sm8350_ufsphy_rx),
787
+
.pcs = sm8350_ufsphy_pcs,
788
+
.pcs_num = ARRAY_SIZE(sm8350_ufsphy_pcs),
789
+
},
790
+
.tbls_hs_b = {
791
+
.serdes = sm8350_ufsphy_hs_b_serdes,
792
+
.serdes_num = ARRAY_SIZE(sm8350_ufsphy_hs_b_serdes),
793
+
},
794
+
.tbls_hs_g4 = {
795
+
.tx = sm8350_ufsphy_g4_tx,
796
+
.tx_num = ARRAY_SIZE(sm8350_ufsphy_g4_tx),
797
+
.rx = sm8350_ufsphy_g4_rx,
798
+
.rx_num = ARRAY_SIZE(sm8350_ufsphy_g4_rx),
799
+
.pcs = sm8350_ufsphy_g4_pcs,
800
+
.pcs_num = ARRAY_SIZE(sm8350_ufsphy_g4_pcs),
801
+
},
943
802
.clk_list = sdm845_ufs_phy_clk_l,
944
803
.num_clks = ARRAY_SIZE(sdm845_ufs_phy_clk_l),
945
804
.vreg_list = qmp_phy_vreg_l,
946
805
.num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
947
-
.regs = sm8150_ufsphy_regs_layout,
806
+
.regs = ufsphy_v5_regs_layout,
948
807
};
949
808
950
809
static const struct qmp_phy_cfg sm8450_ufsphy_cfg = {
951
810
.lanes = 2,
952
811
953
-
.serdes_tbl = sm8350_ufsphy_serdes_tbl,
954
-
.serdes_tbl_num = ARRAY_SIZE(sm8350_ufsphy_serdes_tbl),
955
-
.tx_tbl = sm8350_ufsphy_tx_tbl,
956
-
.tx_tbl_num = ARRAY_SIZE(sm8350_ufsphy_tx_tbl),
957
-
.rx_tbl = sm8350_ufsphy_rx_tbl,
958
-
.rx_tbl_num = ARRAY_SIZE(sm8350_ufsphy_rx_tbl),
959
-
.pcs_tbl = sm8350_ufsphy_pcs_tbl,
960
-
.pcs_tbl_num = ARRAY_SIZE(sm8350_ufsphy_pcs_tbl),
812
+
.tbls = {
813
+
.serdes = sm8350_ufsphy_serdes,
814
+
.serdes_num = ARRAY_SIZE(sm8350_ufsphy_serdes),
815
+
.tx = sm8350_ufsphy_tx,
816
+
.tx_num = ARRAY_SIZE(sm8350_ufsphy_tx),
817
+
.rx = sm8350_ufsphy_rx,
818
+
.rx_num = ARRAY_SIZE(sm8350_ufsphy_rx),
819
+
.pcs = sm8350_ufsphy_pcs,
820
+
.pcs_num = ARRAY_SIZE(sm8350_ufsphy_pcs),
821
+
},
822
+
.tbls_hs_b = {
823
+
.serdes = sm8350_ufsphy_hs_b_serdes,
824
+
.serdes_num = ARRAY_SIZE(sm8350_ufsphy_hs_b_serdes),
825
+
},
826
+
.tbls_hs_g4 = {
827
+
.tx = sm8350_ufsphy_g4_tx,
828
+
.tx_num = ARRAY_SIZE(sm8350_ufsphy_g4_tx),
829
+
.rx = sm8350_ufsphy_g4_rx,
830
+
.rx_num = ARRAY_SIZE(sm8350_ufsphy_g4_rx),
831
+
.pcs = sm8350_ufsphy_g4_pcs,
832
+
.pcs_num = ARRAY_SIZE(sm8350_ufsphy_g4_pcs),
833
+
},
961
834
.clk_list = sm8450_ufs_phy_clk_l,
962
835
.num_clks = ARRAY_SIZE(sm8450_ufs_phy_clk_l),
963
836
.vreg_list = qmp_phy_vreg_l,
964
837
.num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
965
-
.regs = sm8150_ufsphy_regs_layout,
838
+
.regs = ufsphy_v5_regs_layout,
839
+
};
840
+
841
+
static const struct qmp_phy_cfg sm8550_ufsphy_cfg = {
842
+
.lanes = 2,
843
+
844
+
.offsets = &qmp_ufs_offsets_v6,
845
+
846
+
.tbls = {
847
+
.serdes = sm8550_ufsphy_serdes,
848
+
.serdes_num = ARRAY_SIZE(sm8550_ufsphy_serdes),
849
+
.tx = sm8550_ufsphy_tx,
850
+
.tx_num = ARRAY_SIZE(sm8550_ufsphy_tx),
851
+
.rx = sm8550_ufsphy_rx,
852
+
.rx_num = ARRAY_SIZE(sm8550_ufsphy_rx),
853
+
.pcs = sm8550_ufsphy_pcs,
854
+
.pcs_num = ARRAY_SIZE(sm8550_ufsphy_pcs),
855
+
},
856
+
.clk_list = sdm845_ufs_phy_clk_l,
857
+
.num_clks = ARRAY_SIZE(sdm845_ufs_phy_clk_l),
858
+
.vreg_list = qmp_phy_vreg_l,
859
+
.num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
860
+
.regs = ufsphy_v6_regs_layout,
966
861
};
967
862
968
863
static void qmp_ufs_configure_lane(void __iomem *base,
···
1087
790
qmp_ufs_configure_lane(base, tbl, num, 0xff);
1088
791
}
1089
792
1090
-
static int qmp_ufs_serdes_init(struct qmp_ufs *qmp)
793
+
static void qmp_ufs_serdes_init(struct qmp_ufs *qmp, const struct qmp_phy_cfg_tbls *tbls)
794
+
{
795
+
void __iomem *serdes = qmp->serdes;
796
+
797
+
qmp_ufs_configure(serdes, tbls->serdes, tbls->serdes_num);
798
+
}
799
+
800
+
static void qmp_ufs_lanes_init(struct qmp_ufs *qmp, const struct qmp_phy_cfg_tbls *tbls)
1091
801
{
1092
802
const struct qmp_phy_cfg *cfg = qmp->cfg;
1093
-
void __iomem *serdes = qmp->serdes;
1094
-
const struct qmp_phy_init_tbl *serdes_tbl = cfg->serdes_tbl;
1095
-
int serdes_tbl_num = cfg->serdes_tbl_num;
803
+
void __iomem *tx = qmp->tx;
804
+
void __iomem *rx = qmp->rx;
1096
805
1097
-
qmp_ufs_configure(serdes, serdes_tbl, serdes_tbl_num);
806
+
qmp_ufs_configure_lane(tx, tbls->tx, tbls->tx_num, 1);
807
+
qmp_ufs_configure_lane(rx, tbls->rx, tbls->rx_num, 1);
1098
808
1099
-
return 0;
809
+
if (cfg->lanes >= 2) {
810
+
qmp_ufs_configure_lane(qmp->tx2, tbls->tx, tbls->tx_num, 2);
811
+
qmp_ufs_configure_lane(qmp->rx2, tbls->rx, tbls->rx_num, 2);
812
+
}
813
+
}
814
+
815
+
static void qmp_ufs_pcs_init(struct qmp_ufs *qmp, const struct qmp_phy_cfg_tbls *tbls)
816
+
{
817
+
void __iomem *pcs = qmp->pcs;
818
+
819
+
qmp_ufs_configure(pcs, tbls->pcs, tbls->pcs_num);
820
+
}
821
+
822
+
static void qmp_ufs_init_registers(struct qmp_ufs *qmp, const struct qmp_phy_cfg *cfg)
823
+
{
824
+
qmp_ufs_serdes_init(qmp, &cfg->tbls);
825
+
if (qmp->mode == PHY_MODE_UFS_HS_B)
826
+
qmp_ufs_serdes_init(qmp, &cfg->tbls_hs_b);
827
+
qmp_ufs_lanes_init(qmp, &cfg->tbls);
828
+
if (qmp->submode == UFS_HS_G4)
829
+
qmp_ufs_lanes_init(qmp, &cfg->tbls_hs_g4);
830
+
qmp_ufs_pcs_init(qmp, &cfg->tbls);
831
+
if (qmp->submode == UFS_HS_G4)
832
+
qmp_ufs_pcs_init(qmp, &cfg->tbls_hs_g4);
1100
833
}
1101
834
1102
835
static int qmp_ufs_com_init(struct qmp_ufs *qmp)
···
1213
886
{
1214
887
struct qmp_ufs *qmp = phy_get_drvdata(phy);
1215
888
const struct qmp_phy_cfg *cfg = qmp->cfg;
1216
-
void __iomem *tx = qmp->tx;
1217
-
void __iomem *rx = qmp->rx;
1218
889
void __iomem *pcs = qmp->pcs;
1219
890
void __iomem *status;
1220
891
unsigned int val;
1221
892
int ret;
1222
893
1223
-
qmp_ufs_serdes_init(qmp);
1224
-
1225
-
/* Tx, Rx, and PCS configurations */
1226
-
qmp_ufs_configure_lane(tx, cfg->tx_tbl, cfg->tx_tbl_num, 1);
1227
-
qmp_ufs_configure_lane(rx, cfg->rx_tbl, cfg->rx_tbl_num, 1);
1228
-
1229
-
if (cfg->lanes >= 2) {
1230
-
qmp_ufs_configure_lane(qmp->tx2, cfg->tx_tbl, cfg->tx_tbl_num, 2);
1231
-
qmp_ufs_configure_lane(qmp->rx2, cfg->rx_tbl, cfg->rx_tbl_num, 2);
1232
-
}
1233
-
1234
-
qmp_ufs_configure(pcs, cfg->pcs_tbl, cfg->pcs_tbl_num);
894
+
qmp_ufs_init_registers(qmp, cfg);
1235
895
1236
896
ret = reset_control_deassert(qmp->ufs_reset);
1237
897
if (ret)
···
1295
981
return qmp_ufs_exit(phy);
1296
982
}
1297
983
984
+
static int qmp_ufs_set_mode(struct phy *phy, enum phy_mode mode, int submode)
985
+
{
986
+
struct qmp_ufs *qmp = phy_get_drvdata(phy);
987
+
988
+
qmp->mode = mode;
989
+
qmp->submode = submode;
990
+
991
+
return 0;
992
+
}
993
+
1298
994
static const struct phy_ops qcom_qmp_ufs_phy_ops = {
1299
995
.power_on = qmp_ufs_enable,
1300
996
.power_off = qmp_ufs_disable,
997
+
.set_mode = qmp_ufs_set_mode,
1301
998
.owner = THIS_MODULE,
1302
999
};
1303
1000
···
1344
1019
qmp->clks[i].id = cfg->clk_list[i];
1345
1020
1346
1021
return devm_clk_bulk_get(dev, num, qmp->clks);
1022
+
}
1023
+
1024
+
static void qmp_ufs_clk_release_provider(void *res)
1025
+
{
1026
+
of_clk_del_provider(res);
1027
+
}
1028
+
1029
+
#define UFS_SYMBOL_CLOCKS 3
1030
+
1031
+
static int qmp_ufs_register_clocks(struct qmp_ufs *qmp, struct device_node *np)
1032
+
{
1033
+
struct clk_hw_onecell_data *clk_data;
1034
+
struct clk_hw *hw;
1035
+
char name[64];
1036
+
int ret;
1037
+
1038
+
clk_data = devm_kzalloc(qmp->dev,
1039
+
struct_size(clk_data, hws, UFS_SYMBOL_CLOCKS),
1040
+
GFP_KERNEL);
1041
+
if (!clk_data)
1042
+
return -ENOMEM;
1043
+
1044
+
clk_data->num = UFS_SYMBOL_CLOCKS;
1045
+
1046
+
snprintf(name, sizeof(name), "%s::rx_symbol_0", dev_name(qmp->dev));
1047
+
hw = devm_clk_hw_register_fixed_rate(qmp->dev, name, NULL, 0, 0);
1048
+
if (IS_ERR(hw))
1049
+
return PTR_ERR(hw);
1050
+
1051
+
clk_data->hws[0] = hw;
1052
+
1053
+
snprintf(name, sizeof(name), "%s::rx_symbol_1", dev_name(qmp->dev));
1054
+
hw = devm_clk_hw_register_fixed_rate(qmp->dev, name, NULL, 0, 0);
1055
+
if (IS_ERR(hw))
1056
+
return PTR_ERR(hw);
1057
+
1058
+
clk_data->hws[1] = hw;
1059
+
1060
+
snprintf(name, sizeof(name), "%s::tx_symbol_0", dev_name(qmp->dev));
1061
+
hw = devm_clk_hw_register_fixed_rate(qmp->dev, name, NULL, 0, 0);
1062
+
if (IS_ERR(hw))
1063
+
return PTR_ERR(hw);
1064
+
1065
+
clk_data->hws[2] = hw;
1066
+
1067
+
ret = of_clk_add_hw_provider(np, of_clk_hw_onecell_get, clk_data);
1068
+
if (ret)
1069
+
return ret;
1070
+
1071
+
/*
1072
+
* Roll a devm action because the clock provider can be a child node.
1073
+
*/
1074
+
return devm_add_action_or_reset(qmp->dev, qmp_ufs_clk_release_provider, np);
1347
1075
}
1348
1076
1349
1077
static int qmp_ufs_parse_dt_legacy(struct qmp_ufs *qmp, struct device_node *np)
···
1511
1133
if (ret)
1512
1134
goto err_node_put;
1513
1135
1136
+
ret = qmp_ufs_register_clocks(qmp, np);
1137
+
if (ret)
1138
+
goto err_node_put;
1139
+
1514
1140
qmp->phy = devm_phy_create(dev, np, &qcom_qmp_ufs_phy_ops);
1515
1141
if (IS_ERR(qmp->phy)) {
1516
1142
ret = PTR_ERR(qmp->phy);
···
1538
1156
static const struct of_device_id qmp_ufs_of_match_table[] = {
1539
1157
{
1540
1158
.compatible = "qcom,msm8996-qmp-ufs-phy",
1541
-
.data = &msm8996_ufs_cfg,
1159
+
.data = &msm8996_ufsphy_cfg,
1542
1160
}, {
1543
1161
.compatible = "qcom,msm8998-qmp-ufs-phy",
1544
1162
.data = &sdm845_ufsphy_cfg,
···
1555
1173
.compatible = "qcom,sm6115-qmp-ufs-phy",
1556
1174
.data = &sm6115_ufsphy_cfg,
1557
1175
}, {
1176
+
.compatible = "qcom,sm6125-qmp-ufs-phy",
1177
+
.data = &sm6115_ufsphy_cfg,
1178
+
}, {
1558
1179
.compatible = "qcom,sm6350-qmp-ufs-phy",
1559
1180
.data = &sdm845_ufsphy_cfg,
1560
1181
}, {
···
1565
1180
.data = &sm8150_ufsphy_cfg,
1566
1181
}, {
1567
1182
.compatible = "qcom,sm8250-qmp-ufs-phy",
1568
-
.data = &sm8150_ufsphy_cfg,
1183
+
.data = &sm8250_ufsphy_cfg,
1569
1184
}, {
1570
1185
.compatible = "qcom,sm8350-qmp-ufs-phy",
1571
1186
.data = &sm8350_ufsphy_cfg,
1572
1187
}, {
1573
1188
.compatible = "qcom,sm8450-qmp-ufs-phy",
1574
1189
.data = &sm8450_ufsphy_cfg,
1190
+
}, {
1191
+
.compatible = "qcom,sm8550-qmp-ufs-phy",
1192
+
.data = &sm8550_ufsphy_cfg,
1575
1193
},
1576
1194
{ },
1577
1195
};
+41
-42
drivers/phy/qualcomm/phy-qcom-qmp-usb.c
+41
-42
drivers/phy/qualcomm/phy-qcom-qmp-usb.c
···
21
21
#include <linux/slab.h>
22
22
23
23
#include "phy-qcom-qmp.h"
24
+
#include "phy-qcom-qmp-pcs-misc-v3.h"
25
+
#include "phy-qcom-qmp-pcs-usb-v4.h"
26
+
#include "phy-qcom-qmp-pcs-usb-v5.h"
24
27
25
28
/* QPHY_SW_RESET bit */
26
29
#define SW_RESET BIT(0)
···
56
53
57
54
/* QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR register bits */
58
55
#define IRQ_CLEAR BIT(0)
59
-
60
-
/* QPHY_PCS_LFPS_RXTERM_IRQ_STATUS register bits */
61
-
#define RCVR_DETECT BIT(0)
62
56
63
57
/* QPHY_V3_PCS_MISC_CLAMP_ENABLE register bits */
64
58
#define CLAMP_EN BIT(0) /* enables i/o clamp_n */
···
94
94
QPHY_PCS_STATUS,
95
95
QPHY_PCS_AUTONOMOUS_MODE_CTRL,
96
96
QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR,
97
-
QPHY_PCS_LFPS_RXTERM_IRQ_STATUS,
98
97
QPHY_PCS_POWER_DOWN_CONTROL,
99
-
/* PCS_MISC registers */
100
-
QPHY_PCS_MISC_TYPEC_CTRL,
101
98
/* Keep last to ensure regs_layout arrays are properly initialized */
102
99
QPHY_LAYOUT_SIZE
103
100
};
104
101
105
-
static const unsigned int usb3phy_regs_layout[QPHY_LAYOUT_SIZE] = {
106
-
[QPHY_SW_RESET] = 0x00,
107
-
[QPHY_START_CTRL] = 0x08,
108
-
[QPHY_PCS_STATUS] = 0x17c,
109
-
[QPHY_PCS_AUTONOMOUS_MODE_CTRL] = 0x0d4,
110
-
[QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR] = 0x0d8,
111
-
[QPHY_PCS_LFPS_RXTERM_IRQ_STATUS] = 0x178,
112
-
[QPHY_PCS_POWER_DOWN_CONTROL] = 0x04,
102
+
static const unsigned int qmp_v2_usb3phy_regs_layout[QPHY_LAYOUT_SIZE] = {
103
+
[QPHY_SW_RESET] = QPHY_V2_PCS_SW_RESET,
104
+
[QPHY_START_CTRL] = QPHY_V2_PCS_START_CONTROL,
105
+
[QPHY_PCS_STATUS] = QPHY_V2_PCS_USB_PCS_STATUS,
106
+
[QPHY_PCS_AUTONOMOUS_MODE_CTRL] = QPHY_V2_PCS_AUTONOMOUS_MODE_CTRL,
107
+
[QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR] = QPHY_V2_PCS_LFPS_RXTERM_IRQ_CLEAR,
108
+
[QPHY_PCS_POWER_DOWN_CONTROL] = QPHY_V2_PCS_POWER_DOWN_CONTROL,
113
109
};
114
110
115
111
static const unsigned int qmp_v3_usb3phy_regs_layout[QPHY_LAYOUT_SIZE] = {
116
-
[QPHY_SW_RESET] = 0x00,
117
-
[QPHY_START_CTRL] = 0x08,
118
-
[QPHY_PCS_STATUS] = 0x174,
119
-
[QPHY_PCS_AUTONOMOUS_MODE_CTRL] = 0x0d8,
120
-
[QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR] = 0x0dc,
121
-
[QPHY_PCS_LFPS_RXTERM_IRQ_STATUS] = 0x170,
122
-
[QPHY_PCS_POWER_DOWN_CONTROL] = 0x04,
112
+
[QPHY_SW_RESET] = QPHY_V3_PCS_SW_RESET,
113
+
[QPHY_START_CTRL] = QPHY_V3_PCS_START_CONTROL,
114
+
[QPHY_PCS_STATUS] = QPHY_V3_PCS_PCS_STATUS,
115
+
[QPHY_PCS_AUTONOMOUS_MODE_CTRL] = QPHY_V3_PCS_AUTONOMOUS_MODE_CTRL,
116
+
[QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR] = QPHY_V3_PCS_LFPS_RXTERM_IRQ_CLEAR,
117
+
[QPHY_PCS_POWER_DOWN_CONTROL] = QPHY_V3_PCS_POWER_DOWN_CONTROL,
123
118
};
124
119
125
120
static const unsigned int qmp_v4_usb3phy_regs_layout[QPHY_LAYOUT_SIZE] = {
126
-
[QPHY_SW_RESET] = 0x00,
127
-
[QPHY_START_CTRL] = 0x44,
128
-
[QPHY_PCS_STATUS] = 0x14,
129
-
[QPHY_PCS_POWER_DOWN_CONTROL] = 0x40,
121
+
[QPHY_SW_RESET] = QPHY_V4_PCS_SW_RESET,
122
+
[QPHY_START_CTRL] = QPHY_V4_PCS_START_CONTROL,
123
+
[QPHY_PCS_STATUS] = QPHY_V4_PCS_PCS_STATUS1,
124
+
[QPHY_PCS_POWER_DOWN_CONTROL] = QPHY_V4_PCS_POWER_DOWN_CONTROL,
130
125
131
126
/* In PCS_USB */
132
-
[QPHY_PCS_AUTONOMOUS_MODE_CTRL] = 0x008,
133
-
[QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR] = 0x014,
127
+
[QPHY_PCS_AUTONOMOUS_MODE_CTRL] = QPHY_V4_PCS_USB3_AUTONOMOUS_MODE_CTRL,
128
+
[QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR] = QPHY_V4_PCS_USB3_LFPS_RXTERM_IRQ_CLEAR,
134
129
};
135
130
136
-
static const unsigned int qcm2290_usb3phy_regs_layout[QPHY_LAYOUT_SIZE] = {
137
-
[QPHY_SW_RESET] = 0x00,
138
-
[QPHY_PCS_POWER_DOWN_CONTROL] = 0x04,
139
-
[QPHY_START_CTRL] = 0x08,
140
-
[QPHY_PCS_AUTONOMOUS_MODE_CTRL] = 0xd8,
141
-
[QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR] = 0xdc,
142
-
[QPHY_PCS_STATUS] = 0x174,
143
-
[QPHY_PCS_MISC_TYPEC_CTRL] = 0x00,
131
+
static const unsigned int qmp_v5_usb3phy_regs_layout[QPHY_LAYOUT_SIZE] = {
132
+
[QPHY_SW_RESET] = QPHY_V5_PCS_SW_RESET,
133
+
[QPHY_START_CTRL] = QPHY_V5_PCS_START_CONTROL,
134
+
[QPHY_PCS_STATUS] = QPHY_V5_PCS_PCS_STATUS1,
135
+
[QPHY_PCS_POWER_DOWN_CONTROL] = QPHY_V5_PCS_POWER_DOWN_CONTROL,
136
+
137
+
/* In PCS_USB */
138
+
[QPHY_PCS_AUTONOMOUS_MODE_CTRL] = QPHY_V5_PCS_USB3_AUTONOMOUS_MODE_CTRL,
139
+
[QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR] = QPHY_V5_PCS_USB3_LFPS_RXTERM_IRQ_CLEAR,
144
140
};
145
141
146
142
static const struct qmp_phy_init_tbl ipq8074_usb3_serdes_tbl[] = {
···
1261
1265
1262
1266
static const struct qmp_phy_init_tbl qcm2290_usb3_rx_tbl[] = {
1263
1267
QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_FO_GAIN, 0x0b),
1264
-
QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_PI_CONTROLS, 0x00),
1268
+
QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_PI_CONTROLS, 0x80),
1265
1269
QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_COUNT_LOW, 0x00),
1266
1270
QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_COUNT_HIGH, 0x00),
1267
1271
QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FO_GAIN, 0x0a),
···
1603
1607
.num_resets = ARRAY_SIZE(msm8996_usb3phy_reset_l),
1604
1608
.vreg_list = qmp_phy_vreg_l,
1605
1609
.num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
1606
-
.regs = usb3phy_regs_layout,
1610
+
.regs = qmp_v2_usb3phy_regs_layout,
1607
1611
};
1608
1612
1609
1613
static const struct qmp_phy_cfg qmp_v3_usb3phy_cfg = {
···
1671
1675
.num_resets = ARRAY_SIZE(qcm2290_usb3phy_reset_l),
1672
1676
.vreg_list = qmp_phy_vreg_l,
1673
1677
.num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
1674
-
.regs = qmp_v4_usb3phy_regs_layout,
1678
+
.regs = qmp_v5_usb3phy_regs_layout,
1675
1679
};
1676
1680
1677
1681
static const struct qmp_phy_cfg qmp_v3_usb3_uniphy_cfg = {
···
1862
1866
.num_resets = ARRAY_SIZE(msm8996_usb3phy_reset_l),
1863
1867
.vreg_list = qmp_phy_vreg_l,
1864
1868
.num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
1865
-
.regs = qmp_v4_usb3phy_regs_layout,
1869
+
.regs = qmp_v5_usb3phy_regs_layout,
1866
1870
.pcs_usb_offset = 0x1000,
1867
1871
1868
1872
.has_pwrdn_delay = true,
···
1887
1891
.num_resets = ARRAY_SIZE(msm8996_usb3phy_reset_l),
1888
1892
.vreg_list = qmp_phy_vreg_l,
1889
1893
.num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
1890
-
.regs = qmp_v4_usb3phy_regs_layout,
1894
+
.regs = qmp_v5_usb3phy_regs_layout,
1891
1895
.pcs_usb_offset = 0x300,
1892
1896
1893
1897
.has_pwrdn_delay = true,
···
1913
1917
.num_resets = ARRAY_SIZE(msm8996_usb3phy_reset_l),
1914
1918
.vreg_list = qmp_phy_vreg_l,
1915
1919
.num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
1916
-
.regs = qmp_v4_usb3phy_regs_layout,
1920
+
.regs = qmp_v5_usb3phy_regs_layout,
1917
1921
.pcs_usb_offset = 0x1000,
1918
1922
1919
1923
.has_pwrdn_delay = true,
···
1936
1940
.num_resets = ARRAY_SIZE(qcm2290_usb3phy_reset_l),
1937
1941
.vreg_list = qmp_phy_vreg_l,
1938
1942
.num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
1939
-
.regs = qcm2290_usb3phy_regs_layout,
1943
+
.regs = qmp_v3_usb3phy_regs_layout,
1940
1944
};
1941
1945
1942
1946
static void qmp_usb_configure_lane(void __iomem *base,
···
2618
2622
}, {
2619
2623
.compatible = "qcom,sdx65-qmp-usb3-uni-phy",
2620
2624
.data = &sdx65_usb3_uniphy_cfg,
2625
+
}, {
2626
+
.compatible = "qcom,sm6115-qmp-usb3-phy",
2627
+
.data = &qcm2290_usb3phy_cfg,
2621
2628
}, {
2622
2629
.compatible = "qcom,sm8150-qmp-usb3-phy",
2623
2630
.data = &sm8150_usb3phy_cfg,
+12
-11
drivers/phy/qualcomm/phy-qcom-qmp.h
+12
-11
drivers/phy/qualcomm/phy-qcom-qmp.h
···
21
21
#include "phy-qcom-qmp-qserdes-txrx-v5_20.h"
22
22
#include "phy-qcom-qmp-qserdes-txrx-v5_5nm.h"
23
23
24
+
#include "phy-qcom-qmp-qserdes-com-v6.h"
25
+
#include "phy-qcom-qmp-qserdes-txrx-v6.h"
26
+
#include "phy-qcom-qmp-qserdes-txrx-v6_20.h"
27
+
#include "phy-qcom-qmp-qserdes-ln-shrd-v6.h"
28
+
24
29
#include "phy-qcom-qmp-qserdes-pll.h"
25
30
26
31
#include "phy-qcom-qmp-pcs-v2.h"
27
32
28
33
#include "phy-qcom-qmp-pcs-v3.h"
29
-
#include "phy-qcom-qmp-pcs-misc-v3.h"
30
-
#include "phy-qcom-qmp-pcs-ufs-v3.h"
31
34
32
35
#include "phy-qcom-qmp-pcs-v4.h"
33
-
#include "phy-qcom-qmp-pcs-pcie-v4.h"
34
-
#include "phy-qcom-qmp-pcs-usb-v4.h"
35
-
#include "phy-qcom-qmp-pcs-ufs-v4.h"
36
36
37
37
#include "phy-qcom-qmp-pcs-v4_20.h"
38
-
#include "phy-qcom-qmp-pcs-pcie-v4_20.h"
39
38
40
39
#include "phy-qcom-qmp-pcs-v5.h"
40
+
41
41
#include "phy-qcom-qmp-pcs-v5_20.h"
42
-
#include "phy-qcom-qmp-pcs-pcie-v5.h"
43
-
#include "phy-qcom-qmp-pcs-usb-v5.h"
44
-
#include "phy-qcom-qmp-pcs-ufs-v5.h"
45
42
46
-
#include "phy-qcom-qmp-pcs-pcie-v5_20.h"
43
+
#include "phy-qcom-qmp-pcs-v6.h"
47
44
48
-
#include "phy-qcom-qmp-pcie-qhp.h"
45
+
#include "phy-qcom-qmp-pcs-v6_20.h"
49
46
50
47
/* Only for QMP V3 & V4 PHY - DP COM registers */
51
48
#define QPHY_V3_DP_COM_PHY_MODE_CTRL 0x00
···
133
136
#define QPHY_V4_PCS_MISC_CLAMP_ENABLE 0x0c
134
137
#define QPHY_V4_PCS_MISC_TYPEC_STATUS 0x10
135
138
#define QPHY_V4_PCS_MISC_PLACEHOLDER_STATUS 0x14
139
+
140
+
/* Only for QMP V6 PHY - DP PHY registers */
141
+
#define QSERDES_V6_DP_PHY_AUX_INTERRUPT_STATUS 0x0e0
142
+
#define QSERDES_V6_DP_PHY_STATUS 0x0e4
136
143
137
144
#endif
+441
drivers/phy/qualcomm/phy-qcom-snps-eusb2.c
+441
drivers/phy/qualcomm/phy-qcom-snps-eusb2.c
···
1
+
// SPDX-License-Identifier: GPL-2.0
2
+
/*
3
+
* Copyright (c) 2023, Linaro Limited
4
+
*/
5
+
6
+
#include <linux/bitfield.h>
7
+
#include <linux/clk.h>
8
+
#include <linux/delay.h>
9
+
#include <linux/iopoll.h>
10
+
#include <linux/phy/phy.h>
11
+
#include <linux/platform_device.h>
12
+
#include <linux/regulator/consumer.h>
13
+
#include <linux/reset.h>
14
+
15
+
#define USB_PHY_UTMI_CTRL0 (0x3c)
16
+
#define SLEEPM BIT(0)
17
+
#define OPMODE_MASK GENMASK(4, 3)
18
+
#define OPMODE_NONDRIVING BIT(3)
19
+
20
+
#define USB_PHY_UTMI_CTRL5 (0x50)
21
+
#define POR BIT(1)
22
+
23
+
#define USB_PHY_HS_PHY_CTRL_COMMON0 (0x54)
24
+
#define PHY_ENABLE BIT(0)
25
+
#define SIDDQ_SEL BIT(1)
26
+
#define SIDDQ BIT(2)
27
+
#define RETENABLEN BIT(3)
28
+
#define FSEL_MASK GENMASK(6, 4)
29
+
#define FSEL_19_2_MHZ_VAL (0x0)
30
+
#define FSEL_38_4_MHZ_VAL (0x4)
31
+
32
+
#define USB_PHY_CFG_CTRL_1 (0x58)
33
+
#define PHY_CFG_PLL_CPBIAS_CNTRL_MASK GENMASK(7, 1)
34
+
35
+
#define USB_PHY_CFG_CTRL_2 (0x5c)
36
+
#define PHY_CFG_PLL_FB_DIV_7_0_MASK GENMASK(7, 0)
37
+
#define DIV_7_0_19_2_MHZ_VAL (0x90)
38
+
#define DIV_7_0_38_4_MHZ_VAL (0xc8)
39
+
40
+
#define USB_PHY_CFG_CTRL_3 (0x60)
41
+
#define PHY_CFG_PLL_FB_DIV_11_8_MASK GENMASK(3, 0)
42
+
#define DIV_11_8_19_2_MHZ_VAL (0x1)
43
+
#define DIV_11_8_38_4_MHZ_VAL (0x0)
44
+
45
+
#define PHY_CFG_PLL_REF_DIV GENMASK(7, 4)
46
+
#define PLL_REF_DIV_VAL (0x0)
47
+
48
+
#define USB_PHY_HS_PHY_CTRL2 (0x64)
49
+
#define VBUSVLDEXT0 BIT(0)
50
+
#define USB2_SUSPEND_N BIT(2)
51
+
#define USB2_SUSPEND_N_SEL BIT(3)
52
+
#define VBUS_DET_EXT_SEL BIT(4)
53
+
54
+
#define USB_PHY_CFG_CTRL_4 (0x68)
55
+
#define PHY_CFG_PLL_GMP_CNTRL_MASK GENMASK(1, 0)
56
+
#define PHY_CFG_PLL_INT_CNTRL_MASK GENMASK(7, 2)
57
+
58
+
#define USB_PHY_CFG_CTRL_5 (0x6c)
59
+
#define PHY_CFG_PLL_PROP_CNTRL_MASK GENMASK(4, 0)
60
+
#define PHY_CFG_PLL_VREF_TUNE_MASK GENMASK(7, 6)
61
+
62
+
#define USB_PHY_CFG_CTRL_6 (0x70)
63
+
#define PHY_CFG_PLL_VCO_CNTRL_MASK GENMASK(2, 0)
64
+
65
+
#define USB_PHY_CFG_CTRL_7 (0x74)
66
+
67
+
#define USB_PHY_CFG_CTRL_8 (0x78)
68
+
#define PHY_CFG_TX_FSLS_VREF_TUNE_MASK GENMASK(1, 0)
69
+
#define PHY_CFG_TX_FSLS_VREG_BYPASS BIT(2)
70
+
#define PHY_CFG_TX_HS_VREF_TUNE_MASK GENMASK(5, 3)
71
+
#define PHY_CFG_TX_HS_XV_TUNE_MASK GENMASK(7, 6)
72
+
73
+
#define USB_PHY_CFG_CTRL_9 (0x7c)
74
+
#define PHY_CFG_TX_PREEMP_TUNE_MASK GENMASK(2, 0)
75
+
#define PHY_CFG_TX_RES_TUNE_MASK GENMASK(4, 3)
76
+
#define PHY_CFG_TX_RISE_TUNE_MASK GENMASK(6, 5)
77
+
#define PHY_CFG_RCAL_BYPASS BIT(7)
78
+
79
+
#define USB_PHY_CFG_CTRL_10 (0x80)
80
+
81
+
#define USB_PHY_CFG0 (0x94)
82
+
#define DATAPATH_CTRL_OVERRIDE_EN BIT(0)
83
+
#define CMN_CTRL_OVERRIDE_EN BIT(1)
84
+
85
+
#define UTMI_PHY_CMN_CTRL0 (0x98)
86
+
#define TESTBURNIN BIT(6)
87
+
88
+
#define USB_PHY_FSEL_SEL (0xb8)
89
+
#define FSEL_SEL BIT(0)
90
+
91
+
#define USB_PHY_APB_ACCESS_CMD (0x130)
92
+
#define RW_ACCESS BIT(0)
93
+
#define APB_START_CMD BIT(1)
94
+
#define APB_LOGIC_RESET BIT(2)
95
+
96
+
#define USB_PHY_APB_ACCESS_STATUS (0x134)
97
+
#define ACCESS_DONE BIT(0)
98
+
#define TIMED_OUT BIT(1)
99
+
#define ACCESS_ERROR BIT(2)
100
+
#define ACCESS_IN_PROGRESS BIT(3)
101
+
102
+
#define USB_PHY_APB_ADDRESS (0x138)
103
+
#define APB_REG_ADDR_MASK GENMASK(7, 0)
104
+
105
+
#define USB_PHY_APB_WRDATA_LSB (0x13c)
106
+
#define APB_REG_WRDATA_7_0_MASK GENMASK(3, 0)
107
+
108
+
#define USB_PHY_APB_WRDATA_MSB (0x140)
109
+
#define APB_REG_WRDATA_15_8_MASK GENMASK(7, 4)
110
+
111
+
#define USB_PHY_APB_RDDATA_LSB (0x144)
112
+
#define APB_REG_RDDATA_7_0_MASK GENMASK(3, 0)
113
+
114
+
#define USB_PHY_APB_RDDATA_MSB (0x148)
115
+
#define APB_REG_RDDATA_15_8_MASK GENMASK(7, 4)
116
+
117
+
static const char * const eusb2_hsphy_vreg_names[] = {
118
+
"vdd", "vdda12",
119
+
};
120
+
121
+
#define EUSB2_NUM_VREGS ARRAY_SIZE(eusb2_hsphy_vreg_names)
122
+
123
+
struct qcom_snps_eusb2_hsphy {
124
+
struct phy *phy;
125
+
void __iomem *base;
126
+
127
+
struct clk *ref_clk;
128
+
struct reset_control *phy_reset;
129
+
130
+
struct regulator_bulk_data vregs[EUSB2_NUM_VREGS];
131
+
132
+
enum phy_mode mode;
133
+
134
+
struct phy *repeater;
135
+
};
136
+
137
+
static int qcom_snps_eusb2_hsphy_set_mode(struct phy *p, enum phy_mode mode, int submode)
138
+
{
139
+
struct qcom_snps_eusb2_hsphy *phy = phy_get_drvdata(p);
140
+
141
+
phy->mode = mode;
142
+
143
+
return phy_set_mode_ext(phy->repeater, mode, submode);
144
+
}
145
+
146
+
static void qcom_snps_eusb2_hsphy_write_mask(void __iomem *base, u32 offset,
147
+
u32 mask, u32 val)
148
+
{
149
+
u32 reg;
150
+
151
+
reg = readl_relaxed(base + offset);
152
+
reg &= ~mask;
153
+
reg |= val & mask;
154
+
writel_relaxed(reg, base + offset);
155
+
156
+
/* Ensure above write is completed */
157
+
readl_relaxed(base + offset);
158
+
}
159
+
160
+
static void qcom_eusb2_default_parameters(struct qcom_snps_eusb2_hsphy *phy)
161
+
{
162
+
/* default parameters: tx pre-emphasis */
163
+
qcom_snps_eusb2_hsphy_write_mask(phy->base, USB_PHY_CFG_CTRL_9,
164
+
PHY_CFG_TX_PREEMP_TUNE_MASK,
165
+
FIELD_PREP(PHY_CFG_TX_PREEMP_TUNE_MASK, 0));
166
+
167
+
/* tx rise/fall time */
168
+
qcom_snps_eusb2_hsphy_write_mask(phy->base, USB_PHY_CFG_CTRL_9,
169
+
PHY_CFG_TX_RISE_TUNE_MASK,
170
+
FIELD_PREP(PHY_CFG_TX_RISE_TUNE_MASK, 0x2));
171
+
172
+
/* source impedance adjustment */
173
+
qcom_snps_eusb2_hsphy_write_mask(phy->base, USB_PHY_CFG_CTRL_9,
174
+
PHY_CFG_TX_RES_TUNE_MASK,
175
+
FIELD_PREP(PHY_CFG_TX_RES_TUNE_MASK, 0x1));
176
+
177
+
/* dc voltage level adjustement */
178
+
qcom_snps_eusb2_hsphy_write_mask(phy->base, USB_PHY_CFG_CTRL_8,
179
+
PHY_CFG_TX_HS_VREF_TUNE_MASK,
180
+
FIELD_PREP(PHY_CFG_TX_HS_VREF_TUNE_MASK, 0x3));
181
+
182
+
/* transmitter HS crossover adjustement */
183
+
qcom_snps_eusb2_hsphy_write_mask(phy->base, USB_PHY_CFG_CTRL_8,
184
+
PHY_CFG_TX_HS_XV_TUNE_MASK,
185
+
FIELD_PREP(PHY_CFG_TX_HS_XV_TUNE_MASK, 0x0));
186
+
}
187
+
188
+
static int qcom_eusb2_ref_clk_init(struct qcom_snps_eusb2_hsphy *phy)
189
+
{
190
+
unsigned long ref_clk_freq = clk_get_rate(phy->ref_clk);
191
+
192
+
switch (ref_clk_freq) {
193
+
case 19200000:
194
+
qcom_snps_eusb2_hsphy_write_mask(phy->base, USB_PHY_HS_PHY_CTRL_COMMON0,
195
+
FSEL_MASK,
196
+
FIELD_PREP(FSEL_MASK, FSEL_19_2_MHZ_VAL));
197
+
198
+
qcom_snps_eusb2_hsphy_write_mask(phy->base, USB_PHY_CFG_CTRL_2,
199
+
PHY_CFG_PLL_FB_DIV_7_0_MASK,
200
+
DIV_7_0_19_2_MHZ_VAL);
201
+
202
+
qcom_snps_eusb2_hsphy_write_mask(phy->base, USB_PHY_CFG_CTRL_3,
203
+
PHY_CFG_PLL_FB_DIV_11_8_MASK,
204
+
DIV_11_8_19_2_MHZ_VAL);
205
+
break;
206
+
207
+
case 38400000:
208
+
qcom_snps_eusb2_hsphy_write_mask(phy->base, USB_PHY_HS_PHY_CTRL_COMMON0,
209
+
FSEL_MASK,
210
+
FIELD_PREP(FSEL_MASK, FSEL_38_4_MHZ_VAL));
211
+
212
+
qcom_snps_eusb2_hsphy_write_mask(phy->base, USB_PHY_CFG_CTRL_2,
213
+
PHY_CFG_PLL_FB_DIV_7_0_MASK,
214
+
DIV_7_0_38_4_MHZ_VAL);
215
+
216
+
qcom_snps_eusb2_hsphy_write_mask(phy->base, USB_PHY_CFG_CTRL_3,
217
+
PHY_CFG_PLL_FB_DIV_11_8_MASK,
218
+
DIV_11_8_38_4_MHZ_VAL);
219
+
break;
220
+
221
+
default:
222
+
dev_err(&phy->phy->dev, "unsupported ref_clk_freq:%lu\n", ref_clk_freq);
223
+
return -EINVAL;
224
+
}
225
+
226
+
qcom_snps_eusb2_hsphy_write_mask(phy->base, USB_PHY_CFG_CTRL_3,
227
+
PHY_CFG_PLL_REF_DIV, PLL_REF_DIV_VAL);
228
+
229
+
return 0;
230
+
}
231
+
232
+
static int qcom_snps_eusb2_hsphy_init(struct phy *p)
233
+
{
234
+
struct qcom_snps_eusb2_hsphy *phy = phy_get_drvdata(p);
235
+
int ret;
236
+
237
+
ret = regulator_bulk_enable(ARRAY_SIZE(phy->vregs), phy->vregs);
238
+
if (ret)
239
+
return ret;
240
+
241
+
ret = phy_init(phy->repeater);
242
+
if (ret) {
243
+
dev_err(&p->dev, "repeater init failed. %d\n", ret);
244
+
goto disable_vreg;
245
+
}
246
+
247
+
ret = clk_prepare_enable(phy->ref_clk);
248
+
if (ret) {
249
+
dev_err(&p->dev, "failed to enable ref clock, %d\n", ret);
250
+
goto disable_vreg;
251
+
}
252
+
253
+
ret = reset_control_assert(phy->phy_reset);
254
+
if (ret) {
255
+
dev_err(&p->dev, "failed to assert phy_reset, %d\n", ret);
256
+
goto disable_ref_clk;
257
+
}
258
+
259
+
usleep_range(100, 150);
260
+
261
+
ret = reset_control_deassert(phy->phy_reset);
262
+
if (ret) {
263
+
dev_err(&p->dev, "failed to de-assert phy_reset, %d\n", ret);
264
+
goto disable_ref_clk;
265
+
}
266
+
267
+
qcom_snps_eusb2_hsphy_write_mask(phy->base, USB_PHY_CFG0,
268
+
CMN_CTRL_OVERRIDE_EN, CMN_CTRL_OVERRIDE_EN);
269
+
270
+
qcom_snps_eusb2_hsphy_write_mask(phy->base, USB_PHY_UTMI_CTRL5, POR, POR);
271
+
272
+
qcom_snps_eusb2_hsphy_write_mask(phy->base, USB_PHY_HS_PHY_CTRL_COMMON0,
273
+
PHY_ENABLE | RETENABLEN, PHY_ENABLE | RETENABLEN);
274
+
275
+
qcom_snps_eusb2_hsphy_write_mask(phy->base, USB_PHY_APB_ACCESS_CMD,
276
+
APB_LOGIC_RESET, APB_LOGIC_RESET);
277
+
278
+
qcom_snps_eusb2_hsphy_write_mask(phy->base, UTMI_PHY_CMN_CTRL0, TESTBURNIN, 0);
279
+
280
+
qcom_snps_eusb2_hsphy_write_mask(phy->base, USB_PHY_FSEL_SEL,
281
+
FSEL_SEL, FSEL_SEL);
282
+
283
+
/* update ref_clk related registers */
284
+
ret = qcom_eusb2_ref_clk_init(phy);
285
+
if (ret)
286
+
goto disable_ref_clk;
287
+
288
+
qcom_snps_eusb2_hsphy_write_mask(phy->base, USB_PHY_CFG_CTRL_1,
289
+
PHY_CFG_PLL_CPBIAS_CNTRL_MASK,
290
+
FIELD_PREP(PHY_CFG_PLL_CPBIAS_CNTRL_MASK, 0x1));
291
+
292
+
qcom_snps_eusb2_hsphy_write_mask(phy->base, USB_PHY_CFG_CTRL_4,
293
+
PHY_CFG_PLL_INT_CNTRL_MASK,
294
+
FIELD_PREP(PHY_CFG_PLL_INT_CNTRL_MASK, 0x8));
295
+
296
+
qcom_snps_eusb2_hsphy_write_mask(phy->base, USB_PHY_CFG_CTRL_4,
297
+
PHY_CFG_PLL_GMP_CNTRL_MASK,
298
+
FIELD_PREP(PHY_CFG_PLL_GMP_CNTRL_MASK, 0x1));
299
+
300
+
qcom_snps_eusb2_hsphy_write_mask(phy->base, USB_PHY_CFG_CTRL_5,
301
+
PHY_CFG_PLL_PROP_CNTRL_MASK,
302
+
FIELD_PREP(PHY_CFG_PLL_PROP_CNTRL_MASK, 0x10));
303
+
304
+
qcom_snps_eusb2_hsphy_write_mask(phy->base, USB_PHY_CFG_CTRL_6,
305
+
PHY_CFG_PLL_VCO_CNTRL_MASK,
306
+
FIELD_PREP(PHY_CFG_PLL_VCO_CNTRL_MASK, 0x0));
307
+
308
+
qcom_snps_eusb2_hsphy_write_mask(phy->base, USB_PHY_CFG_CTRL_5,
309
+
PHY_CFG_PLL_VREF_TUNE_MASK,
310
+
FIELD_PREP(PHY_CFG_PLL_VREF_TUNE_MASK, 0x1));
311
+
312
+
qcom_snps_eusb2_hsphy_write_mask(phy->base, USB_PHY_HS_PHY_CTRL2,
313
+
VBUS_DET_EXT_SEL, VBUS_DET_EXT_SEL);
314
+
315
+
/* set default parameters */
316
+
qcom_eusb2_default_parameters(phy);
317
+
318
+
qcom_snps_eusb2_hsphy_write_mask(phy->base, USB_PHY_HS_PHY_CTRL2,
319
+
USB2_SUSPEND_N_SEL | USB2_SUSPEND_N,
320
+
USB2_SUSPEND_N_SEL | USB2_SUSPEND_N);
321
+
322
+
qcom_snps_eusb2_hsphy_write_mask(phy->base, USB_PHY_UTMI_CTRL0, SLEEPM, SLEEPM);
323
+
324
+
qcom_snps_eusb2_hsphy_write_mask(phy->base, USB_PHY_HS_PHY_CTRL_COMMON0,
325
+
SIDDQ_SEL, SIDDQ_SEL);
326
+
327
+
qcom_snps_eusb2_hsphy_write_mask(phy->base, USB_PHY_HS_PHY_CTRL_COMMON0,
328
+
SIDDQ, 0);
329
+
330
+
qcom_snps_eusb2_hsphy_write_mask(phy->base, USB_PHY_UTMI_CTRL5, POR, 0);
331
+
332
+
qcom_snps_eusb2_hsphy_write_mask(phy->base, USB_PHY_HS_PHY_CTRL2,
333
+
USB2_SUSPEND_N_SEL, 0);
334
+
335
+
return 0;
336
+
337
+
disable_ref_clk:
338
+
clk_disable_unprepare(phy->ref_clk);
339
+
340
+
disable_vreg:
341
+
regulator_bulk_disable(ARRAY_SIZE(phy->vregs), phy->vregs);
342
+
343
+
return ret;
344
+
}
345
+
346
+
static int qcom_snps_eusb2_hsphy_exit(struct phy *p)
347
+
{
348
+
struct qcom_snps_eusb2_hsphy *phy = phy_get_drvdata(p);
349
+
350
+
clk_disable_unprepare(phy->ref_clk);
351
+
352
+
regulator_bulk_disable(ARRAY_SIZE(phy->vregs), phy->vregs);
353
+
354
+
phy_exit(phy->repeater);
355
+
356
+
return 0;
357
+
}
358
+
359
+
static const struct phy_ops qcom_snps_eusb2_hsphy_ops = {
360
+
.init = qcom_snps_eusb2_hsphy_init,
361
+
.exit = qcom_snps_eusb2_hsphy_exit,
362
+
.set_mode = qcom_snps_eusb2_hsphy_set_mode,
363
+
.owner = THIS_MODULE,
364
+
};
365
+
366
+
static int qcom_snps_eusb2_hsphy_probe(struct platform_device *pdev)
367
+
{
368
+
struct device *dev = &pdev->dev;
369
+
struct device_node *np = dev->of_node;
370
+
struct qcom_snps_eusb2_hsphy *phy;
371
+
struct phy_provider *phy_provider;
372
+
struct phy *generic_phy;
373
+
int ret, i;
374
+
int num;
375
+
376
+
phy = devm_kzalloc(dev, sizeof(*phy), GFP_KERNEL);
377
+
if (!phy)
378
+
return -ENOMEM;
379
+
380
+
phy->base = devm_platform_ioremap_resource(pdev, 0);
381
+
if (IS_ERR(phy->base))
382
+
return PTR_ERR(phy->base);
383
+
384
+
phy->phy_reset = devm_reset_control_get_exclusive(dev, NULL);
385
+
if (IS_ERR(phy->phy_reset))
386
+
return PTR_ERR(phy->phy_reset);
387
+
388
+
phy->ref_clk = devm_clk_get(dev, "ref");
389
+
if (IS_ERR(phy->ref_clk))
390
+
return dev_err_probe(dev, PTR_ERR(phy->ref_clk),
391
+
"failed to get ref clk\n");
392
+
393
+
num = ARRAY_SIZE(phy->vregs);
394
+
for (i = 0; i < num; i++)
395
+
phy->vregs[i].supply = eusb2_hsphy_vreg_names[i];
396
+
397
+
ret = devm_regulator_bulk_get(dev, num, phy->vregs);
398
+
if (ret)
399
+
return dev_err_probe(dev, ret,
400
+
"failed to get regulator supplies\n");
401
+
402
+
phy->repeater = devm_of_phy_get_by_index(dev, np, 0);
403
+
if (IS_ERR(phy->repeater))
404
+
return dev_err_probe(dev, PTR_ERR(phy->repeater),
405
+
"failed to get repeater\n");
406
+
407
+
generic_phy = devm_phy_create(dev, NULL, &qcom_snps_eusb2_hsphy_ops);
408
+
if (IS_ERR(generic_phy)) {
409
+
dev_err(dev, "failed to create phy %d\n", ret);
410
+
return PTR_ERR(generic_phy);
411
+
}
412
+
413
+
dev_set_drvdata(dev, phy);
414
+
phy_set_drvdata(generic_phy, phy);
415
+
416
+
phy_provider = devm_of_phy_provider_register(dev, of_phy_simple_xlate);
417
+
if (IS_ERR(phy_provider))
418
+
return PTR_ERR(phy_provider);
419
+
420
+
dev_info(dev, "Registered Qcom-eUSB2 phy\n");
421
+
422
+
return 0;
423
+
}
424
+
425
+
static const struct of_device_id qcom_snps_eusb2_hsphy_of_match_table[] = {
426
+
{ .compatible = "qcom,sm8550-snps-eusb2-phy", },
427
+
{ },
428
+
};
429
+
MODULE_DEVICE_TABLE(of, qcom_snps_eusb2_hsphy_of_match_table);
430
+
431
+
static struct platform_driver qcom_snps_eusb2_hsphy_driver = {
432
+
.probe = qcom_snps_eusb2_hsphy_probe,
433
+
.driver = {
434
+
.name = "qcom-snps-eusb2-hsphy",
435
+
.of_match_table = qcom_snps_eusb2_hsphy_of_match_table,
436
+
},
437
+
};
438
+
439
+
module_platform_driver(qcom_snps_eusb2_hsphy_driver);
440
+
MODULE_DESCRIPTION("Qualcomm SNPS eUSB2 HS PHY driver");
441
+
MODULE_LICENSE("GPL");
+33
-38
drivers/phy/renesas/r8a779f0-ether-serdes.c
+33
-38
drivers/phy/renesas/r8a779f0-ether-serdes.c
···
18
18
#define R8A779F0_ETH_SERDES_BANK_SELECT 0x03fc
19
19
#define R8A779F0_ETH_SERDES_TIMEOUT_US 100000
20
20
#define R8A779F0_ETH_SERDES_NUM_RETRY_LINKUP 3
21
-
#define R8A779F0_ETH_SERDES_NUM_RETRY_INIT 3
22
21
23
22
struct r8a779f0_eth_serdes_drv_data;
24
23
struct r8a779f0_eth_serdes_channel {
···
241
242
if (ret)
242
243
return ret;
243
244
244
-
ret = r8a779f0_eth_serdes_reg_wait(&dd->channel[0], 0x0000, 0x380, BIT(15), 0);
245
-
if (ret)
246
-
return ret;
247
-
248
-
for (i = 0; i < R8A779F0_ETH_SERDES_NUM; i++) {
249
-
ret = r8a779f0_eth_serdes_chan_setting(&dd->channel[i]);
250
-
if (ret)
251
-
return ret;
252
-
}
253
-
254
-
for (i = 0; i < R8A779F0_ETH_SERDES_NUM; i++) {
255
-
ret = r8a779f0_eth_serdes_chan_speed(&dd->channel[i]);
256
-
if (ret)
257
-
return ret;
258
-
}
259
-
260
-
for (i = 0; i < R8A779F0_ETH_SERDES_NUM; i++)
261
-
r8a779f0_eth_serdes_write32(dd->channel[i].addr, 0x03c0, 0x380, 0x0000);
262
-
for (i = 0; i < R8A779F0_ETH_SERDES_NUM; i++)
263
-
r8a779f0_eth_serdes_write32(dd->channel[i].addr, 0x03d0, 0x380, 0x0000);
264
-
265
-
for (i = 0; i < R8A779F0_ETH_SERDES_NUM; i++) {
266
-
ret = r8a779f0_eth_serdes_monitor_linkup(&dd->channel[i]);
267
-
if (ret)
268
-
return ret;
269
-
}
270
-
271
-
return 0;
245
+
return r8a779f0_eth_serdes_reg_wait(&dd->channel[0], 0x0000, 0x380, BIT(15), 0);
272
246
}
273
247
274
248
static int r8a779f0_eth_serdes_init(struct phy *p)
275
249
{
276
250
struct r8a779f0_eth_serdes_channel *channel = phy_get_drvdata(p);
277
-
int i, ret;
251
+
int ret;
278
252
279
-
for (i = 0; i < R8A779F0_ETH_SERDES_NUM_RETRY_INIT; i++) {
280
-
ret = r8a779f0_eth_serdes_hw_init(channel);
281
-
if (!ret) {
282
-
channel->dd->initialized = true;
283
-
break;
284
-
}
285
-
usleep_range(1000, 2000);
286
-
}
253
+
ret = r8a779f0_eth_serdes_hw_init(channel);
254
+
if (!ret)
255
+
channel->dd->initialized = true;
287
256
288
257
return ret;
258
+
}
259
+
260
+
static int r8a779f0_eth_serdes_hw_init_late(struct r8a779f0_eth_serdes_channel
261
+
*channel)
262
+
{
263
+
int ret;
264
+
265
+
ret = r8a779f0_eth_serdes_chan_setting(channel);
266
+
if (ret)
267
+
return ret;
268
+
269
+
ret = r8a779f0_eth_serdes_chan_speed(channel);
270
+
if (ret)
271
+
return ret;
272
+
273
+
r8a779f0_eth_serdes_write32(channel->addr, 0x03c0, 0x380, 0x0000);
274
+
275
+
r8a779f0_eth_serdes_write32(channel->addr, 0x03d0, 0x380, 0x0000);
276
+
277
+
return r8a779f0_eth_serdes_monitor_linkup(channel);
278
+
}
279
+
280
+
static int r8a779f0_eth_serdes_power_on(struct phy *p)
281
+
{
282
+
struct r8a779f0_eth_serdes_channel *channel = phy_get_drvdata(p);
283
+
284
+
return r8a779f0_eth_serdes_hw_init_late(channel);
289
285
}
290
286
291
287
static int r8a779f0_eth_serdes_set_mode(struct phy *p, enum phy_mode mode,
···
313
319
314
320
static const struct phy_ops r8a779f0_eth_serdes_ops = {
315
321
.init = r8a779f0_eth_serdes_init,
322
+
.power_on = r8a779f0_eth_serdes_power_on,
316
323
.set_mode = r8a779f0_eth_serdes_set_mode,
317
324
.set_speed = r8a779f0_eth_serdes_set_speed,
318
325
};
+3
-4
drivers/phy/rockchip/phy-rockchip-typec.c
+3
-4
drivers/phy/rockchip/phy-rockchip-typec.c
···
808
808
struct extcon_dev *edev = tcphy->extcon;
809
809
union extcon_property_value property;
810
810
unsigned int id;
811
-
bool ufp, dp;
812
811
u8 mode;
813
-
int ret;
812
+
int ret, ufp, dp;
814
813
815
814
if (!edev)
816
815
return MODE_DFP_USB;
···
820
821
mode = MODE_DFP_USB;
821
822
id = EXTCON_USB_HOST;
822
823
823
-
if (ufp) {
824
+
if (ufp > 0) {
824
825
mode = MODE_UFP_USB;
825
826
id = EXTCON_USB;
826
-
} else if (dp) {
827
+
} else if (dp > 0) {
827
828
mode = MODE_DFP_DP;
828
829
id = EXTCON_DISP_DP;
829
830
+17
drivers/phy/tegra/xusb.c
+17
drivers/phy/tegra/xusb.c
···
718
718
return err;
719
719
}
720
720
721
+
static void tegra_xusb_parse_usb_role_default_mode(struct tegra_xusb_port *port)
722
+
{
723
+
enum usb_role role = USB_ROLE_NONE;
724
+
enum usb_dr_mode mode = usb_get_role_switch_default_mode(&port->dev);
725
+
726
+
if (mode == USB_DR_MODE_HOST)
727
+
role = USB_ROLE_HOST;
728
+
else if (mode == USB_DR_MODE_PERIPHERAL)
729
+
role = USB_ROLE_DEVICE;
730
+
731
+
if (role != USB_ROLE_NONE) {
732
+
usb_role_switch_set_role(port->usb_role_sw, role);
733
+
dev_dbg(&port->dev, "usb role default mode is %s", modes[mode]);
734
+
}
735
+
}
736
+
721
737
static int tegra_xusb_usb2_port_parse_dt(struct tegra_xusb_usb2_port *usb2)
722
738
{
723
739
struct tegra_xusb_port *port = &usb2->base;
···
763
747
err = tegra_xusb_setup_usb_role_switch(port);
764
748
if (err < 0)
765
749
return err;
750
+
tegra_xusb_parse_usb_role_default_mode(port);
766
751
} else {
767
752
dev_err(&port->dev, "usb-role-switch not found for %s mode",
768
753
modes[usb2->mode]);
+55
-9
drivers/phy/ti/phy-j721e-wiz.c
+55
-9
drivers/phy/ti/phy-j721e-wiz.c
···
58
58
LANE_MODE_GEN4,
59
59
};
60
60
61
+
/*
62
+
* List of master lanes used for lane swapping
63
+
*/
64
+
enum wiz_typec_master_lane {
65
+
LANE0 = 0,
66
+
LANE2 = 2,
67
+
};
68
+
61
69
enum wiz_refclk_mux_sel {
62
70
PLL0_REFCLK,
63
71
PLL1_REFCLK,
···
201
193
202
194
static const struct reg_field typec_ln10_swap =
203
195
REG_FIELD(WIZ_SERDES_TYPEC, 30, 30);
196
+
197
+
static const struct reg_field typec_ln23_swap =
198
+
REG_FIELD(WIZ_SERDES_TYPEC, 31, 31);
204
199
205
200
struct wiz_clk_mux {
206
201
struct clk_hw hw;
···
378
367
struct regmap_field *mux_sel_field[WIZ_MUX_NUM_CLOCKS];
379
368
struct regmap_field *div_sel_field[WIZ_DIV_NUM_CLOCKS_16G];
380
369
struct regmap_field *typec_ln10_swap;
370
+
struct regmap_field *typec_ln23_swap;
381
371
struct regmap_field *sup_legacy_clk_override;
382
372
383
373
struct device *dev;
···
388
376
struct gpio_desc *gpio_typec_dir;
389
377
int typec_dir_delay;
390
378
u32 lane_phy_type[WIZ_MAX_LANES];
379
+
u32 master_lane_num[WIZ_MAX_LANES];
391
380
struct clk *input_clks[WIZ_MAX_INPUT_CLOCKS];
392
381
struct clk *output_clks[WIZ_MAX_OUTPUT_CLOCKS];
393
382
struct clk_onecell_data clk_data;
···
686
673
if (IS_ERR(wiz->typec_ln10_swap)) {
687
674
dev_err(dev, "LN10_SWAP reg field init failed\n");
688
675
return PTR_ERR(wiz->typec_ln10_swap);
676
+
}
677
+
678
+
wiz->typec_ln23_swap = devm_regmap_field_alloc(dev, regmap,
679
+
typec_ln23_swap);
680
+
if (IS_ERR(wiz->typec_ln23_swap)) {
681
+
dev_err(dev, "LN23_SWAP reg field init failed\n");
682
+
return PTR_ERR(wiz->typec_ln23_swap);
689
683
}
690
684
691
685
wiz->phy_en_refclk = devm_regmap_field_alloc(dev, regmap, phy_en_refclk);
···
1254
1234
struct wiz *wiz = dev_get_drvdata(dev);
1255
1235
int ret;
1256
1236
1257
-
/* if typec-dir gpio was specified, set LN10 SWAP bit based on that */
1258
-
if (id == 0 && wiz->gpio_typec_dir) {
1259
-
if (wiz->typec_dir_delay)
1260
-
msleep_interruptible(wiz->typec_dir_delay);
1237
+
if (id == 0) {
1238
+
/* if typec-dir gpio was specified, set LN10 SWAP bit based on that */
1239
+
if (wiz->gpio_typec_dir) {
1240
+
if (wiz->typec_dir_delay)
1241
+
msleep_interruptible(wiz->typec_dir_delay);
1261
1242
1262
-
if (gpiod_get_value_cansleep(wiz->gpio_typec_dir))
1263
-
regmap_field_write(wiz->typec_ln10_swap, 1);
1264
-
else
1265
-
regmap_field_write(wiz->typec_ln10_swap, 0);
1243
+
if (gpiod_get_value_cansleep(wiz->gpio_typec_dir))
1244
+
regmap_field_write(wiz->typec_ln10_swap, 1);
1245
+
else
1246
+
regmap_field_write(wiz->typec_ln10_swap, 0);
1247
+
} else {
1248
+
/* if no typec-dir gpio is specified and PHY type is USB3
1249
+
* with master lane number is '0' or '2', then set LN10 or
1250
+
* LN23 SWAP bit to '1' respectively.
1251
+
*/
1252
+
u32 num_lanes = wiz->num_lanes;
1253
+
int i;
1254
+
1255
+
for (i = 0; i < num_lanes; i++) {
1256
+
if (wiz->lane_phy_type[i] == PHY_TYPE_USB3) {
1257
+
switch (wiz->master_lane_num[i]) {
1258
+
case LANE0:
1259
+
regmap_field_write(wiz->typec_ln10_swap, 1);
1260
+
break;
1261
+
case LANE2:
1262
+
regmap_field_write(wiz->typec_ln23_swap, 1);
1263
+
break;
1264
+
default:
1265
+
break;
1266
+
}
1267
+
}
1268
+
}
1269
+
}
1266
1270
}
1267
1271
1268
1272
if (id == 0) {
···
1430
1386
dev_dbg(dev, "%s: Lanes %u-%u have phy-type %u\n", __func__,
1431
1387
reg, reg + num_lanes - 1, phy_type);
1432
1388
1433
-
for (i = reg; i < reg + num_lanes; i++)
1389
+
for (i = reg; i < reg + num_lanes; i++) {
1390
+
wiz->master_lane_num[i] = reg;
1434
1391
wiz->lane_phy_type[i] = phy_type;
1392
+
}
1435
1393
}
1436
1394
1437
1395
return 0;
+6
-17
drivers/usb/host/ehci-exynos.c
+6
-17
drivers/usb/host/ehci-exynos.c
···
80
80
return -EINVAL;
81
81
}
82
82
83
-
phy = devm_of_phy_get(dev, child, NULL);
83
+
phy = devm_of_phy_optional_get(dev, child, NULL);
84
84
exynos_ehci->phy[phy_number] = phy;
85
85
if (IS_ERR(phy)) {
86
-
ret = PTR_ERR(phy);
87
-
if (ret == -EPROBE_DEFER) {
88
-
of_node_put(child);
89
-
return ret;
90
-
} else if (ret != -ENOSYS && ret != -ENODEV) {
91
-
dev_err(dev,
92
-
"Error retrieving usb2 phy: %d\n", ret);
93
-
of_node_put(child);
94
-
return ret;
95
-
}
86
+
of_node_put(child);
87
+
return PTR_ERR(phy);
96
88
}
97
89
}
98
90
···
100
108
int ret = 0;
101
109
102
110
for (i = 0; ret == 0 && i < PHY_NUMBER; i++)
103
-
if (!IS_ERR(exynos_ehci->phy[i]))
104
-
ret = phy_power_on(exynos_ehci->phy[i]);
111
+
ret = phy_power_on(exynos_ehci->phy[i]);
105
112
if (ret)
106
113
for (i--; i >= 0; i--)
107
-
if (!IS_ERR(exynos_ehci->phy[i]))
108
-
phy_power_off(exynos_ehci->phy[i]);
114
+
phy_power_off(exynos_ehci->phy[i]);
109
115
110
116
return ret;
111
117
}
···
115
125
int i;
116
126
117
127
for (i = 0; i < PHY_NUMBER; i++)
118
-
if (!IS_ERR(exynos_ehci->phy[i]))
119
-
phy_power_off(exynos_ehci->phy[i]);
128
+
phy_power_off(exynos_ehci->phy[i]);
120
129
}
121
130
122
131
static void exynos_setup_vbus_gpio(struct device *dev)
+6
-17
drivers/usb/host/ohci-exynos.c
+6
-17
drivers/usb/host/ohci-exynos.c
···
69
69
return -EINVAL;
70
70
}
71
71
72
-
phy = devm_of_phy_get(dev, child, NULL);
72
+
phy = devm_of_phy_optional_get(dev, child, NULL);
73
73
exynos_ohci->phy[phy_number] = phy;
74
74
if (IS_ERR(phy)) {
75
-
ret = PTR_ERR(phy);
76
-
if (ret == -EPROBE_DEFER) {
77
-
of_node_put(child);
78
-
return ret;
79
-
} else if (ret != -ENOSYS && ret != -ENODEV) {
80
-
dev_err(dev,
81
-
"Error retrieving usb2 phy: %d\n", ret);
82
-
of_node_put(child);
83
-
return ret;
84
-
}
75
+
of_node_put(child);
76
+
return PTR_ERR(phy);
85
77
}
86
78
}
87
79
···
89
97
int ret = 0;
90
98
91
99
for (i = 0; ret == 0 && i < PHY_NUMBER; i++)
92
-
if (!IS_ERR(exynos_ohci->phy[i]))
93
-
ret = phy_power_on(exynos_ohci->phy[i]);
100
+
ret = phy_power_on(exynos_ohci->phy[i]);
94
101
if (ret)
95
102
for (i--; i >= 0; i--)
96
-
if (!IS_ERR(exynos_ohci->phy[i]))
97
-
phy_power_off(exynos_ohci->phy[i]);
103
+
phy_power_off(exynos_ohci->phy[i]);
98
104
99
105
return ret;
100
106
}
···
104
114
int i;
105
115
106
116
for (i = 0; i < PHY_NUMBER; i++)
107
-
if (!IS_ERR(exynos_ohci->phy[i]))
108
-
phy_power_off(exynos_ohci->phy[i]);
117
+
phy_power_off(exynos_ohci->phy[i]);
109
118
}
110
119
111
120
static int exynos_ohci_probe(struct platform_device *pdev)
+9
-7
include/linux/phy/phy.h
+9
-7
include/linux/phy/phy.h
···
250
250
phy->attrs.bus_width = bus_width;
251
251
}
252
252
struct phy *phy_get(struct device *dev, const char *string);
253
-
struct phy *phy_optional_get(struct device *dev, const char *string);
254
253
struct phy *devm_phy_get(struct device *dev, const char *string);
255
254
struct phy *devm_phy_optional_get(struct device *dev, const char *string);
256
255
struct phy *devm_of_phy_get(struct device *dev, struct device_node *np,
257
256
const char *con_id);
257
+
struct phy *devm_of_phy_optional_get(struct device *dev, struct device_node *np,
258
+
const char *con_id);
258
259
struct phy *devm_of_phy_get_by_index(struct device *dev, struct device_node *np,
259
260
int index);
260
261
void of_phy_put(struct phy *phy);
···
427
426
return ERR_PTR(-ENOSYS);
428
427
}
429
428
430
-
static inline struct phy *phy_optional_get(struct device *dev,
431
-
const char *string)
432
-
{
433
-
return ERR_PTR(-ENOSYS);
434
-
}
435
-
436
429
static inline struct phy *devm_phy_get(struct device *dev, const char *string)
437
430
{
438
431
return ERR_PTR(-ENOSYS);
···
443
448
const char *con_id)
444
449
{
445
450
return ERR_PTR(-ENOSYS);
451
+
}
452
+
453
+
static inline struct phy *devm_of_phy_optional_get(struct device *dev,
454
+
struct device_node *np,
455
+
const char *con_id)
456
+
{
457
+
return NULL;
446
458
}
447
459
448
460
static inline struct phy *devm_of_phy_get_by_index(struct device *dev,