Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
Merge tag 'pinctrl-v4.19-4' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl
Linus writes:
"Pin control fixes for v4.19:
- Fixes to x86 hardware:
- AMD interrupt debounce issues
- Faulty Intel cannonlake register offset
- Revert pin translation IRQ locking"
* tag 'pinctrl-v4.19-4' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl:
Revert "pinctrl: intel: Do pin translation when lock IRQ"
pinctrl: cannonlake: Fix HOSTSW_OWN register offset of H variant
pinctrl/amd: poll InterruptEnable bits in amd_gpio_irq_set_type
+43
-55
+20
-13
drivers/pinctrl/intel/pinctrl-cannonlake.c
+20
-13
drivers/pinctrl/intel/pinctrl-cannonlake.c
···
15
15
16
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#include "pinctrl-intel.h"
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18
-
#define CNL_PAD_OWN 0x020
19
-
#define CNL_PADCFGLOCK 0x080
20
-
#define CNL_HOSTSW_OWN 0x0b0
21
-
#define CNL_GPI_IE 0x120
18
+
#define CNL_PAD_OWN 0x020
19
+
#define CNL_PADCFGLOCK 0x080
20
+
#define CNL_LP_HOSTSW_OWN 0x0b0
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+
#define CNL_H_HOSTSW_OWN 0x0c0
22
+
#define CNL_GPI_IE 0x120
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#define CNL_GPP(r, s, e, g) \
24
25
{ \
···
31
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32
31
#define CNL_NO_GPIO -1
33
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34
-
#define CNL_COMMUNITY(b, s, e, g) \
33
+
#define CNL_COMMUNITY(b, s, e, o, g) \
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34
{ \
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35
.barno = (b), \
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.padown_offset = CNL_PAD_OWN, \
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.padcfglock_offset = CNL_PADCFGLOCK, \
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-
.hostown_offset = CNL_HOSTSW_OWN, \
38
+
.hostown_offset = (o), \
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.ie_offset = CNL_GPI_IE, \
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.pin_base = (s), \
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.npins = ((e) - (s) + 1), \
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.gpps = (g), \
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.ngpps = ARRAY_SIZE(g), \
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44
}
45
+
46
+
#define CNLLP_COMMUNITY(b, s, e, g) \
47
+
CNL_COMMUNITY(b, s, e, CNL_LP_HOSTSW_OWN, g)
48
+
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+
#define CNLH_COMMUNITY(b, s, e, g) \
50
+
CNL_COMMUNITY(b, s, e, CNL_H_HOSTSW_OWN, g)
46
51
47
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/* Cannon Lake-H */
48
53
static const struct pinctrl_pin_desc cnlh_pins[] = {
···
449
442
};
450
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static const struct intel_community cnlh_communities[] = {
452
-
CNL_COMMUNITY(0, 0, 50, cnlh_community0_gpps),
453
-
CNL_COMMUNITY(1, 51, 154, cnlh_community1_gpps),
454
-
CNL_COMMUNITY(2, 155, 248, cnlh_community3_gpps),
455
-
CNL_COMMUNITY(3, 249, 298, cnlh_community4_gpps),
445
+
CNLH_COMMUNITY(0, 0, 50, cnlh_community0_gpps),
446
+
CNLH_COMMUNITY(1, 51, 154, cnlh_community1_gpps),
447
+
CNLH_COMMUNITY(2, 155, 248, cnlh_community3_gpps),
448
+
CNLH_COMMUNITY(3, 249, 298, cnlh_community4_gpps),
456
449
};
457
450
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static const struct intel_pinctrl_soc_data cnlh_soc_data = {
···
810
803
};
811
804
812
805
static const struct intel_community cnllp_communities[] = {
813
-
CNL_COMMUNITY(0, 0, 67, cnllp_community0_gpps),
814
-
CNL_COMMUNITY(1, 68, 180, cnllp_community1_gpps),
815
-
CNL_COMMUNITY(2, 181, 243, cnllp_community4_gpps),
806
+
CNLLP_COMMUNITY(0, 0, 67, cnllp_community0_gpps),
807
+
CNLLP_COMMUNITY(1, 68, 180, cnllp_community1_gpps),
808
+
CNLLP_COMMUNITY(2, 181, 243, cnllp_community4_gpps),
816
809
};
817
810
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811
static const struct intel_pinctrl_soc_data cnllp_soc_data = {
-32
drivers/pinctrl/intel/pinctrl-intel.c
-32
drivers/pinctrl/intel/pinctrl-intel.c
···
887
887
.set_config = gpiochip_generic_config,
888
888
};
889
889
890
-
static int intel_gpio_irq_reqres(struct irq_data *d)
891
-
{
892
-
struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
893
-
struct intel_pinctrl *pctrl = gpiochip_get_data(gc);
894
-
int pin;
895
-
int ret;
896
-
897
-
pin = intel_gpio_to_pin(pctrl, irqd_to_hwirq(d), NULL, NULL);
898
-
if (pin >= 0) {
899
-
ret = gpiochip_lock_as_irq(gc, pin);
900
-
if (ret) {
901
-
dev_err(pctrl->dev, "unable to lock HW IRQ %d for IRQ\n",
902
-
pin);
903
-
return ret;
904
-
}
905
-
}
906
-
return 0;
907
-
}
908
-
909
-
static void intel_gpio_irq_relres(struct irq_data *d)
910
-
{
911
-
struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
912
-
struct intel_pinctrl *pctrl = gpiochip_get_data(gc);
913
-
int pin;
914
-
915
-
pin = intel_gpio_to_pin(pctrl, irqd_to_hwirq(d), NULL, NULL);
916
-
if (pin >= 0)
917
-
gpiochip_unlock_as_irq(gc, pin);
918
-
}
919
-
920
890
static void intel_gpio_irq_ack(struct irq_data *d)
921
891
{
922
892
struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
···
1102
1132
1103
1133
static struct irq_chip intel_gpio_irqchip = {
1104
1134
.name = "intel-gpio",
1105
-
.irq_request_resources = intel_gpio_irq_reqres,
1106
-
.irq_release_resources = intel_gpio_irq_relres,
1107
1135
.irq_enable = intel_gpio_irq_enable,
1108
1136
.irq_ack = intel_gpio_irq_ack,
1109
1137
.irq_mask = intel_gpio_irq_mask,
+23
-10
drivers/pinctrl/pinctrl-amd.c
+23
-10
drivers/pinctrl/pinctrl-amd.c
···
348
348
unsigned long flags;
349
349
struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
350
350
struct amd_gpio *gpio_dev = gpiochip_get_data(gc);
351
-
u32 mask = BIT(INTERRUPT_ENABLE_OFF) | BIT(INTERRUPT_MASK_OFF);
352
351
353
352
raw_spin_lock_irqsave(&gpio_dev->lock, flags);
354
353
pin_reg = readl(gpio_dev->base + (d->hwirq)*4);
355
354
pin_reg |= BIT(INTERRUPT_ENABLE_OFF);
356
355
pin_reg |= BIT(INTERRUPT_MASK_OFF);
357
356
writel(pin_reg, gpio_dev->base + (d->hwirq)*4);
358
-
/*
359
-
* When debounce logic is enabled it takes ~900 us before interrupts
360
-
* can be enabled. During this "debounce warm up" period the
361
-
* "INTERRUPT_ENABLE" bit will read as 0. Poll the bit here until it
362
-
* reads back as 1, signaling that interrupts are now enabled.
363
-
*/
364
-
while ((readl(gpio_dev->base + (d->hwirq)*4) & mask) != mask)
365
-
continue;
366
357
raw_spin_unlock_irqrestore(&gpio_dev->lock, flags);
367
358
}
368
359
···
417
426
static int amd_gpio_irq_set_type(struct irq_data *d, unsigned int type)
418
427
{
419
428
int ret = 0;
420
-
u32 pin_reg;
429
+
u32 pin_reg, pin_reg_irq_en, mask;
421
430
unsigned long flags, irq_flags;
422
431
struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
423
432
struct amd_gpio *gpio_dev = gpiochip_get_data(gc);
···
486
495
}
487
496
488
497
pin_reg |= CLR_INTR_STAT << INTERRUPT_STS_OFF;
498
+
/*
499
+
* If WAKE_INT_MASTER_REG.MaskStsEn is set, a software write to the
500
+
* debounce registers of any GPIO will block wake/interrupt status
501
+
* generation for *all* GPIOs for a lenght of time that depends on
502
+
* WAKE_INT_MASTER_REG.MaskStsLength[11:0]. During this period the
503
+
* INTERRUPT_ENABLE bit will read as 0.
504
+
*
505
+
* We temporarily enable irq for the GPIO whose configuration is
506
+
* changing, and then wait for it to read back as 1 to know when
507
+
* debounce has settled and then disable the irq again.
508
+
* We do this polling with the spinlock held to ensure other GPIO
509
+
* access routines do not read an incorrect value for the irq enable
510
+
* bit of other GPIOs. We keep the GPIO masked while polling to avoid
511
+
* spurious irqs, and disable the irq again after polling.
512
+
*/
513
+
mask = BIT(INTERRUPT_ENABLE_OFF);
514
+
pin_reg_irq_en = pin_reg;
515
+
pin_reg_irq_en |= mask;
516
+
pin_reg_irq_en &= ~BIT(INTERRUPT_MASK_OFF);
517
+
writel(pin_reg_irq_en, gpio_dev->base + (d->hwirq)*4);
518
+
while ((readl(gpio_dev->base + (d->hwirq)*4) & mask) != mask)
519
+
continue;
489
520
writel(pin_reg, gpio_dev->base + (d->hwirq)*4);
490
521
raw_spin_unlock_irqrestore(&gpio_dev->lock, flags);
491
522