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clk: samsung: exynoautov9: do not define number of clocks in bindings
Number of clocks supported by Linux drivers might vary - sometimes we
add new clocks, not exposed previously. Therefore these numbers of
clocks should not be in the bindings, as that prevents changing them.
Define number of clocks per each clock controller inside the driver
directly.
Reviewed-by: Alim Akhtar <alim.akhtar@samsung.com>
Reviewed-by: Chanwoo Choi <cw00.choi@samsung.com>
Link: https://lore.kernel.org/r/20230808082738.122804-11-krzysztof.kozlowski@linaro.org
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
+20
-9
+20
-9
drivers/clk/samsung/clk-exynosautov9.c
+20
-9
drivers/clk/samsung/clk-exynosautov9.c
···
18
18
#include "clk.h"
19
19
#include "clk-exynos-arm64.h"
20
20
21
+
/* NOTE: Must be equal to the last clock ID increased by one */
22
+
#define CLKS_NR_TOP (GOUT_CLKCMU_PERIS_BUS + 1)
23
+
#define CLKS_NR_BUSMC (CLK_GOUT_BUSMC_SPDMA_PCLK + 1)
24
+
#define CLKS_NR_CORE (CLK_GOUT_CORE_CMU_CORE_PCLK + 1)
25
+
#define CLKS_NR_FSYS0 (CLK_GOUT_FSYS0_PCIE_GEN3B_4L_CLK + 1)
26
+
#define CLKS_NR_FSYS1 (CLK_GOUT_FSYS1_USB30_1_ACLK + 1)
27
+
#define CLKS_NR_FSYS2 (CLK_GOUT_FSYS2_UFS_EMBD1_UNIPRO + 1)
28
+
#define CLKS_NR_PERIC0 (CLK_GOUT_PERIC0_PCLK_11 + 1)
29
+
#define CLKS_NR_PERIC1 (CLK_GOUT_PERIC1_PCLK_11 + 1)
30
+
#define CLKS_NR_PERIS (CLK_GOUT_WDT_CLUSTER1 + 1)
31
+
21
32
/* ---- CMU_TOP ------------------------------------------------------------ */
22
33
23
34
/* Register Offset definitions for CMU_TOP (0x1b240000) */
···
954
943
.nr_fixed_factor_clks = ARRAY_SIZE(top_fixed_factor_clks),
955
944
.gate_clks = top_gate_clks,
956
945
.nr_gate_clks = ARRAY_SIZE(top_gate_clks),
957
-
.nr_clk_ids = TOP_NR_CLK,
946
+
.nr_clk_ids = CLKS_NR_TOP,
958
947
.clk_regs = top_clk_regs,
959
948
.nr_clk_regs = ARRAY_SIZE(top_clk_regs),
960
949
};
···
1014
1003
.nr_div_clks = ARRAY_SIZE(busmc_div_clks),
1015
1004
.gate_clks = busmc_gate_clks,
1016
1005
.nr_gate_clks = ARRAY_SIZE(busmc_gate_clks),
1017
-
.nr_clk_ids = BUSMC_NR_CLK,
1006
+
.nr_clk_ids = CLKS_NR_BUSMC,
1018
1007
.clk_regs = busmc_clk_regs,
1019
1008
.nr_clk_regs = ARRAY_SIZE(busmc_clk_regs),
1020
1009
.clk_name = "dout_clkcmu_busmc_bus",
···
1072
1061
.nr_div_clks = ARRAY_SIZE(core_div_clks),
1073
1062
.gate_clks = core_gate_clks,
1074
1063
.nr_gate_clks = ARRAY_SIZE(core_gate_clks),
1075
-
.nr_clk_ids = CORE_NR_CLK,
1064
+
.nr_clk_ids = CLKS_NR_CORE,
1076
1065
.clk_regs = core_clk_regs,
1077
1066
.nr_clk_regs = ARRAY_SIZE(core_clk_regs),
1078
1067
.clk_name = "dout_clkcmu_core_bus",
···
1312
1301
.nr_mux_clks = ARRAY_SIZE(fsys0_mux_clks),
1313
1302
.gate_clks = fsys0_gate_clks,
1314
1303
.nr_gate_clks = ARRAY_SIZE(fsys0_gate_clks),
1315
-
.nr_clk_ids = FSYS0_NR_CLK,
1304
+
.nr_clk_ids = CLKS_NR_FSYS0,
1316
1305
.clk_regs = fsys0_clk_regs,
1317
1306
.nr_clk_regs = ARRAY_SIZE(fsys0_clk_regs),
1318
1307
.clk_name = "dout_clkcmu_fsys0_bus",
···
1439
1428
.nr_div_clks = ARRAY_SIZE(fsys1_div_clks),
1440
1429
.gate_clks = fsys1_gate_clks,
1441
1430
.nr_gate_clks = ARRAY_SIZE(fsys1_gate_clks),
1442
-
.nr_clk_ids = FSYS1_NR_CLK,
1431
+
.nr_clk_ids = CLKS_NR_FSYS1,
1443
1432
.clk_regs = fsys1_clk_regs,
1444
1433
.nr_clk_regs = ARRAY_SIZE(fsys1_clk_regs),
1445
1434
.clk_name = "dout_clkcmu_fsys1_bus",
···
1506
1495
.nr_mux_clks = ARRAY_SIZE(fsys2_mux_clks),
1507
1496
.gate_clks = fsys2_gate_clks,
1508
1497
.nr_gate_clks = ARRAY_SIZE(fsys2_gate_clks),
1509
-
.nr_clk_ids = FSYS2_NR_CLK,
1498
+
.nr_clk_ids = CLKS_NR_FSYS2,
1510
1499
.clk_regs = fsys2_clk_regs,
1511
1500
.nr_clk_regs = ARRAY_SIZE(fsys2_clk_regs),
1512
1501
.clk_name = "dout_clkcmu_fsys2_bus",
···
1761
1750
.nr_div_clks = ARRAY_SIZE(peric0_div_clks),
1762
1751
.gate_clks = peric0_gate_clks,
1763
1752
.nr_gate_clks = ARRAY_SIZE(peric0_gate_clks),
1764
-
.nr_clk_ids = PERIC0_NR_CLK,
1753
+
.nr_clk_ids = CLKS_NR_PERIC0,
1765
1754
.clk_regs = peric0_clk_regs,
1766
1755
.nr_clk_regs = ARRAY_SIZE(peric0_clk_regs),
1767
1756
.clk_name = "dout_clkcmu_peric0_bus",
···
2016
2005
.nr_div_clks = ARRAY_SIZE(peric1_div_clks),
2017
2006
.gate_clks = peric1_gate_clks,
2018
2007
.nr_gate_clks = ARRAY_SIZE(peric1_gate_clks),
2019
-
.nr_clk_ids = PERIC1_NR_CLK,
2008
+
.nr_clk_ids = CLKS_NR_PERIC1,
2020
2009
.clk_regs = peric1_clk_regs,
2021
2010
.nr_clk_regs = ARRAY_SIZE(peric1_clk_regs),
2022
2011
.clk_name = "dout_clkcmu_peric1_bus",
···
2063
2052
.nr_mux_clks = ARRAY_SIZE(peris_mux_clks),
2064
2053
.gate_clks = peris_gate_clks,
2065
2054
.nr_gate_clks = ARRAY_SIZE(peris_gate_clks),
2066
-
.nr_clk_ids = PERIS_NR_CLK,
2055
+
.nr_clk_ids = CLKS_NR_PERIS,
2067
2056
.clk_regs = peris_clk_regs,
2068
2057
.nr_clk_regs = ARRAY_SIZE(peris_clk_regs),
2069
2058
.clk_name = "dout_clkcmu_peris_bus",