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git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
clk: qcom: ipq5332: drop the gcc_apss_axi_clk_src clock
With the removal of the mem noc clocks in the commit e224dc703521 ("clk:
qcom: gcc-ipq5332: drop the mem noc clocks"), we can drop the
gcc_apss_axi_clk_src clock as well, since there are no clocks uses this
clock as a parent.
Signed-off-by: Kathiravan T <quic_kathirav@quicinc.com>
Link: https://lore.kernel.org/r/20230710102807.1189942-3-quic_kathirav@quicinc.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
authored by
Kathiravan T
and committed by
Bjorn Andersson
90d5c043
1784d031
+40
-73
+40
-73
drivers/clk/qcom/gcc-ipq5332.c
+40
-73
drivers/clk/qcom/gcc-ipq5332.c
···
226
226
static const struct parent_map gcc_parent_map_5[] = {
227
227
{ P_XO, 0 },
228
228
{ P_GPLL0_OUT_MAIN, 1 },
229
-
{ P_GPLL2_OUT_AUX, 2 },
230
-
{ P_GPLL4_OUT_AUX, 3 },
231
-
{ P_GCC_GPLL0_OUT_MAIN_DIV_CLK_SRC, 4 },
232
-
{ P_GPLL0_OUT_AUX, 5 },
229
+
{ P_GPLL0_OUT_AUX, 2 },
230
+
{ P_SLEEP_CLK, 6 },
233
231
};
234
232
235
233
static const struct clk_parent_data gcc_parent_data_5[] = {
236
234
{ .index = DT_XO },
237
235
{ .hw = &gpll0.clkr.hw },
238
-
{ .hw = &gpll2.clkr.hw },
239
-
{ .hw = &gpll4.clkr.hw },
240
-
{ .hw = &gpll0_div2.hw },
241
236
{ .hw = &gpll0.clkr.hw },
237
+
{ .index = DT_SLEEP_CLK },
242
238
};
243
239
244
240
static const struct parent_map gcc_parent_map_6[] = {
245
241
{ P_XO, 0 },
246
242
{ P_GPLL0_OUT_MAIN, 1 },
247
-
{ P_GPLL0_OUT_AUX, 2 },
243
+
{ P_GPLL2_OUT_AUX, 2 },
244
+
{ P_GPLL4_OUT_AUX, 3 },
248
245
{ P_SLEEP_CLK, 6 },
249
246
};
250
247
251
248
static const struct clk_parent_data gcc_parent_data_6[] = {
252
249
{ .index = DT_XO },
253
250
{ .hw = &gpll0.clkr.hw },
254
-
{ .hw = &gpll0.clkr.hw },
251
+
{ .hw = &gpll2.clkr.hw },
252
+
{ .hw = &gpll4.clkr.hw },
255
253
{ .index = DT_SLEEP_CLK },
256
254
};
257
255
···
257
259
{ P_XO, 0 },
258
260
{ P_GPLL0_OUT_MAIN, 1 },
259
261
{ P_GPLL2_OUT_AUX, 2 },
260
-
{ P_GPLL4_OUT_AUX, 3 },
261
-
{ P_SLEEP_CLK, 6 },
262
262
};
263
263
264
264
static const struct clk_parent_data gcc_parent_data_7[] = {
265
265
{ .index = DT_XO },
266
266
{ .hw = &gpll0.clkr.hw },
267
267
{ .hw = &gpll2.clkr.hw },
268
-
{ .hw = &gpll4.clkr.hw },
269
-
{ .index = DT_SLEEP_CLK },
270
268
};
271
269
272
270
static const struct parent_map gcc_parent_map_8[] = {
273
-
{ P_XO, 0 },
274
-
{ P_GPLL0_OUT_MAIN, 1 },
275
-
{ P_GPLL2_OUT_AUX, 2 },
276
-
};
277
-
278
-
static const struct clk_parent_data gcc_parent_data_8[] = {
279
-
{ .index = DT_XO },
280
-
{ .hw = &gpll0.clkr.hw },
281
-
{ .hw = &gpll2.clkr.hw },
282
-
};
283
-
284
-
static const struct parent_map gcc_parent_map_9[] = {
285
271
{ P_XO, 0 },
286
272
{ P_GPLL0_OUT_MAIN, 1 },
287
273
{ P_GPLL2_OUT_MAIN, 2 },
288
274
{ P_GCC_GPLL0_OUT_MAIN_DIV_CLK_SRC, 4 },
289
275
};
290
276
291
-
static const struct clk_parent_data gcc_parent_data_9[] = {
277
+
static const struct clk_parent_data gcc_parent_data_8[] = {
292
278
{ .index = DT_XO },
293
279
{ .hw = &gpll0.clkr.hw },
294
280
{ .hw = &gpll2.clkr.hw },
295
281
{ .hw = &gpll0_div2.hw },
296
282
};
297
283
298
-
static const struct parent_map gcc_parent_map_10[] = {
284
+
static const struct parent_map gcc_parent_map_9[] = {
299
285
{ P_SLEEP_CLK, 6 },
300
286
};
301
287
302
-
static const struct clk_parent_data gcc_parent_data_10[] = {
288
+
static const struct clk_parent_data gcc_parent_data_9[] = {
303
289
{ .index = DT_SLEEP_CLK },
304
290
};
305
291
306
-
static const struct parent_map gcc_parent_map_11[] = {
292
+
static const struct parent_map gcc_parent_map_10[] = {
307
293
{ P_XO, 0 },
308
294
{ P_GPLL0_OUT_MAIN, 1 },
309
295
{ P_GPLL4_OUT_MAIN, 2 },
310
296
{ P_GCC_GPLL0_OUT_MAIN_DIV_CLK_SRC, 3 },
311
297
};
312
298
313
-
static const struct clk_parent_data gcc_parent_data_11[] = {
299
+
static const struct clk_parent_data gcc_parent_data_10[] = {
314
300
{ .index = DT_XO },
315
301
{ .hw = &gpll0.clkr.hw },
316
302
{ .hw = &gpll4.clkr.hw },
317
303
{ .hw = &gpll0_div2.hw },
318
304
};
319
305
320
-
static const struct parent_map gcc_parent_map_12[] = {
306
+
static const struct parent_map gcc_parent_map_11[] = {
321
307
{ P_XO, 0 },
322
308
{ P_GPLL0_OUT_AUX, 2 },
323
309
{ P_SLEEP_CLK, 6 },
324
310
};
325
311
326
-
static const struct clk_parent_data gcc_parent_data_12[] = {
312
+
static const struct clk_parent_data gcc_parent_data_11[] = {
327
313
{ .index = DT_XO },
328
314
{ .hw = &gpll0.clkr.hw },
329
315
{ .index = DT_SLEEP_CLK },
330
316
};
331
317
332
-
static const struct parent_map gcc_parent_map_13[] = {
318
+
static const struct parent_map gcc_parent_map_12[] = {
333
319
{ P_XO, 0 },
334
320
{ P_GPLL4_OUT_AUX, 1 },
335
321
{ P_GPLL0_OUT_MAIN, 3 },
336
322
{ P_GCC_GPLL0_OUT_MAIN_DIV_CLK_SRC, 4 },
337
323
};
338
324
339
-
static const struct clk_parent_data gcc_parent_data_13[] = {
325
+
static const struct clk_parent_data gcc_parent_data_12[] = {
340
326
{ .index = DT_XO },
341
327
{ .hw = &gpll4.clkr.hw },
342
328
{ .hw = &gpll0.clkr.hw },
···
351
369
F(480000000, P_GPLL4_OUT_AUX, 2.5, 0, 0),
352
370
F(533333333, P_GPLL0_OUT_MAIN, 1.5, 0, 0),
353
371
{ }
354
-
};
355
-
356
-
static struct clk_rcg2 gcc_apss_axi_clk_src = {
357
-
.cmd_rcgr = 0x24004,
358
-
.mnd_width = 0,
359
-
.hid_width = 5,
360
-
.parent_map = gcc_parent_map_5,
361
-
.freq_tbl = ftbl_gcc_apss_axi_clk_src,
362
-
.clkr.hw.init = &(const struct clk_init_data) {
363
-
.name = "gcc_apss_axi_clk_src",
364
-
.parent_data = gcc_parent_data_5,
365
-
.num_parents = ARRAY_SIZE(gcc_parent_data_5),
366
-
.ops = &clk_rcg2_ops,
367
-
},
368
372
};
369
373
370
374
static const struct freq_tbl ftbl_gcc_blsp1_qup1_spi_apps_clk_src[] = {
···
701
733
.cmd_rcgr = 0x28004,
702
734
.mnd_width = 16,
703
735
.hid_width = 5,
704
-
.parent_map = gcc_parent_map_6,
736
+
.parent_map = gcc_parent_map_5,
705
737
.freq_tbl = ftbl_gcc_pcie_aux_clk_src,
706
738
.clkr.hw.init = &(const struct clk_init_data) {
707
739
.name = "gcc_pcie_aux_clk_src",
708
-
.parent_data = gcc_parent_data_6,
709
-
.num_parents = ARRAY_SIZE(gcc_parent_data_6),
740
+
.parent_data = gcc_parent_data_5,
741
+
.num_parents = ARRAY_SIZE(gcc_parent_data_5),
710
742
.ops = &clk_rcg2_ops,
711
743
},
712
744
};
···
778
810
.cmd_rcgr = 0x25004,
779
811
.mnd_width = 0,
780
812
.hid_width = 5,
781
-
.parent_map = gcc_parent_map_7,
813
+
.parent_map = gcc_parent_map_6,
782
814
.freq_tbl = ftbl_gcc_apss_axi_clk_src,
783
815
.clkr.hw.init = &(const struct clk_init_data) {
784
816
.name = "gcc_q6_axim_clk_src",
785
-
.parent_data = gcc_parent_data_7,
786
-
.num_parents = ARRAY_SIZE(gcc_parent_data_7),
817
+
.parent_data = gcc_parent_data_6,
818
+
.num_parents = ARRAY_SIZE(gcc_parent_data_6),
787
819
.ops = &clk_rcg2_ops,
788
820
},
789
821
};
···
899
931
.cmd_rcgr = 0x32004,
900
932
.mnd_width = 0,
901
933
.hid_width = 5,
902
-
.parent_map = gcc_parent_map_8,
934
+
.parent_map = gcc_parent_map_7,
903
935
.freq_tbl = ftbl_gcc_qpic_io_macro_clk_src,
904
936
.clkr.hw.init = &(const struct clk_init_data) {
905
937
.name = "gcc_qpic_io_macro_clk_src",
906
-
.parent_data = gcc_parent_data_8,
907
-
.num_parents = ARRAY_SIZE(gcc_parent_data_8),
938
+
.parent_data = gcc_parent_data_7,
939
+
.num_parents = ARRAY_SIZE(gcc_parent_data_7),
908
940
.ops = &clk_rcg2_ops,
909
941
},
910
942
};
···
925
957
.cmd_rcgr = 0x33004,
926
958
.mnd_width = 8,
927
959
.hid_width = 5,
928
-
.parent_map = gcc_parent_map_9,
960
+
.parent_map = gcc_parent_map_8,
929
961
.freq_tbl = ftbl_gcc_sdcc1_apps_clk_src,
930
962
.clkr.hw.init = &(const struct clk_init_data) {
931
963
.name = "gcc_sdcc1_apps_clk_src",
932
-
.parent_data = gcc_parent_data_9,
933
-
.num_parents = ARRAY_SIZE(gcc_parent_data_9),
964
+
.parent_data = gcc_parent_data_8,
965
+
.num_parents = ARRAY_SIZE(gcc_parent_data_8),
934
966
.ops = &clk_rcg2_floor_ops,
935
967
},
936
968
};
···
944
976
.cmd_rcgr = 0x3400c,
945
977
.mnd_width = 0,
946
978
.hid_width = 5,
947
-
.parent_map = gcc_parent_map_10,
979
+
.parent_map = gcc_parent_map_9,
948
980
.freq_tbl = ftbl_gcc_sleep_clk_src,
949
981
.clkr.hw.init = &(const struct clk_init_data) {
950
982
.name = "gcc_sleep_clk_src",
951
-
.parent_data = gcc_parent_data_10,
952
-
.num_parents = ARRAY_SIZE(gcc_parent_data_10),
983
+
.parent_data = gcc_parent_data_9,
984
+
.num_parents = ARRAY_SIZE(gcc_parent_data_9),
953
985
.ops = &clk_rcg2_ops,
954
986
},
955
987
};
···
966
998
.cmd_rcgr = 0x2e004,
967
999
.mnd_width = 0,
968
1000
.hid_width = 5,
969
-
.parent_map = gcc_parent_map_11,
1001
+
.parent_map = gcc_parent_map_10,
970
1002
.freq_tbl = ftbl_gcc_system_noc_bfdcd_clk_src,
971
1003
.clkr.hw.init = &(const struct clk_init_data) {
972
1004
.name = "gcc_system_noc_bfdcd_clk_src",
973
-
.parent_data = gcc_parent_data_11,
974
-
.num_parents = ARRAY_SIZE(gcc_parent_data_11),
1005
+
.parent_data = gcc_parent_data_10,
1006
+
.num_parents = ARRAY_SIZE(gcc_parent_data_10),
975
1007
.ops = &clk_rcg2_ops,
976
1008
},
977
1009
};
···
1007
1039
.cmd_rcgr = 0x2c018,
1008
1040
.mnd_width = 16,
1009
1041
.hid_width = 5,
1010
-
.parent_map = gcc_parent_map_12,
1042
+
.parent_map = gcc_parent_map_11,
1011
1043
.freq_tbl = ftbl_gcc_pcie_aux_clk_src,
1012
1044
.clkr.hw.init = &(const struct clk_init_data) {
1013
1045
.name = "gcc_usb0_aux_clk_src",
1014
-
.parent_data = gcc_parent_data_12,
1015
-
.num_parents = ARRAY_SIZE(gcc_parent_data_12),
1046
+
.parent_data = gcc_parent_data_11,
1047
+
.num_parents = ARRAY_SIZE(gcc_parent_data_11),
1016
1048
.ops = &clk_rcg2_ops,
1017
1049
},
1018
1050
};
···
1059
1091
.cmd_rcgr = 0x2c02c,
1060
1092
.mnd_width = 8,
1061
1093
.hid_width = 5,
1062
-
.parent_map = gcc_parent_map_13,
1094
+
.parent_map = gcc_parent_map_12,
1063
1095
.freq_tbl = ftbl_gcc_usb0_mock_utmi_clk_src,
1064
1096
.clkr.hw.init = &(const struct clk_init_data) {
1065
1097
.name = "gcc_usb0_mock_utmi_clk_src",
1066
-
.parent_data = gcc_parent_data_13,
1067
-
.num_parents = ARRAY_SIZE(gcc_parent_data_13),
1098
+
.parent_data = gcc_parent_data_12,
1099
+
.num_parents = ARRAY_SIZE(gcc_parent_data_12),
1068
1100
.ops = &clk_rcg2_ops,
1069
1101
},
1070
1102
};
···
3296
3328
[GCC_ADSS_PWM_CLK] = &gcc_adss_pwm_clk.clkr,
3297
3329
[GCC_ADSS_PWM_CLK_SRC] = &gcc_adss_pwm_clk_src.clkr,
3298
3330
[GCC_AHB_CLK] = &gcc_ahb_clk.clkr,
3299
-
[GCC_APSS_AXI_CLK_SRC] = &gcc_apss_axi_clk_src.clkr,
3300
3331
[GCC_BLSP1_AHB_CLK] = &gcc_blsp1_ahb_clk.clkr,
3301
3332
[GCC_BLSP1_QUP1_I2C_APPS_CLK] = &gcc_blsp1_qup1_i2c_apps_clk.clkr,
3302
3333
[GCC_BLSP1_QUP1_SPI_APPS_CLK] = &gcc_blsp1_qup1_spi_apps_clk.clkr,