tjh.dev / kernel
Linux kernel mirror (for testing) git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel os linux
1
fork

Configure Feed

Select the types of activity you want to include in your feed.

drm/amdgpu: update cp packets for gfx v12_1

Clean up some unsupport CP packets for gfx v12_1.
Update CP packets for gfx v12_1 with some new definition.

Signed-off-by: Likun Gao <Likun.Gao@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

authored by

Likun Gao and committed by
Alex Deucher 90ddf279 426ffb70

+101 -122
+101 -122
drivers/gpu/drm/amd/amdgpu/gfx_v12_1_pkt.h
··· 53 53 54 54 /* Packet 3 types */ 55 55 #define PACKET3_NOP 0x10 56 - #define PACKET3_SET_BASE 0x11 57 - #define PACKET3_BASE_INDEX(x) ((x) << 0) 58 - #define CE_PARTITION_BASE 3 59 56 #define PACKET3_CLEAR_STATE 0x12 60 57 #define PACKET3_INDEX_BUFFER_SIZE 0x13 61 58 #define PACKET3_DISPATCH_DIRECT 0x15 62 59 #define PACKET3_DISPATCH_INDIRECT 0x16 63 - #define PACKET3_INDIRECT_BUFFER_END 0x17 64 - #define PACKET3_INDIRECT_BUFFER_CNST_END 0x19 65 - #define PACKET3_ATOMIC_GDS 0x1D 66 60 #define PACKET3_ATOMIC_MEM 0x1E 67 61 #define PACKET3_OCCLUSION_QUERY 0x1F 68 62 #define PACKET3_SET_PREDICATION 0x20 ··· 68 74 #define PACKET3_INDEX_BASE 0x26 69 75 #define PACKET3_DRAW_INDEX_2 0x27 70 76 #define PACKET3_CONTEXT_CONTROL 0x28 71 - #define PACKET3_INDEX_TYPE 0x2A 72 77 #define PACKET3_DRAW_INDIRECT_MULTI 0x2C 73 78 #define PACKET3_DRAW_INDEX_AUTO 0x2D 74 79 #define PACKET3_NUM_INSTANCES 0x2F 75 80 #define PACKET3_DRAW_INDEX_MULTI_AUTO 0x30 76 - #define PACKET3_INDIRECT_BUFFER_PRIV 0x32 77 - #define PACKET3_INDIRECT_BUFFER_CNST 0x33 78 - #define PACKET3_COND_INDIRECT_BUFFER_CNST 0x33 79 - #define PACKET3_STRMOUT_BUFFER_UPDATE 0x34 80 81 #define PACKET3_DRAW_INDEX_OFFSET_2 0x35 81 - #define PACKET3_DRAW_PREAMBLE 0x36 82 82 #define PACKET3_WRITE_DATA 0x37 83 - #define WRITE_DATA_DST_SEL(x) ((x) << 8) 83 + #define WRITE_DATA_DST_SEL(x) (((x) & 0xf) << 8) 84 84 /* 0 - register 85 - * 1 - memory (sync - via GRBM) 86 - * 2 - gl2 87 - * 3 - gds 85 + * 1 - reserved 86 + * 2 - tc_l2 87 + * 3 - reserved 88 88 * 4 - reserved 89 - * 5 - memory (async - direct) 89 + * 5 - memory (same as tc_l2) 90 + * 6 - memory_mapped_adc_persistent_state 90 91 */ 91 - #define WR_ONE_ADDR (1 << 16) 92 + #define WRITE_DATA_SCOPE(x) (((x) & 0x3) << 12) 93 + #define WRITE_DATA_MODE(x) (((x) & 0x3) << 14) 94 + /* 0 - local xcd 95 + * 1 - remote/local aid 96 + * 2 - remote xcd 97 + * 3 - remote mid 98 + */ 99 + #define WRITE_DATA_ADDR_INCR (1 << 16) 100 + #define WRITE_DATA_MID_DIE_ID(x) (((x) & 0x3) << 18) 92 101 #define WR_CONFIRM (1 << 20) 93 - #define WRITE_DATA_CACHE_POLICY(x) ((x) << 25) 94 - /* 0 - LRU 95 - * 1 - Stream 102 + #define WRITE_DATA_XCD_DIE_ID(x) (((x) & 0xf) << 21) 103 + #define WRITE_DATA_TEMPORAL(x) (((x) & 0x3) << 25) 104 + /* 0 - rt 105 + * 1 - nt 106 + * 2 - ht 107 + * 3 - lu 96 108 */ 97 - #define WRITE_DATA_ENGINE_SEL(x) ((x) << 30) 98 - /* 0 - me 99 - * 1 - pfp 100 - * 2 - ce 101 - */ 109 + #define WRITE_DATA_COOP_DISABLE (1 << 27) 102 110 #define PACKET3_DRAW_INDEX_INDIRECT_MULTI 0x38 103 - #define PACKET3_MEM_SEMAPHORE 0x39 104 - # define PACKET3_SEM_USE_MAILBOX (0x1 << 16) 105 - # define PACKET3_SEM_SEL_SIGNAL_TYPE (0x1 << 20) /* 0 = increment, 1 = write 1 */ 106 - # define PACKET3_SEM_SEL_SIGNAL (0x6 << 29) 107 - # define PACKET3_SEM_SEL_WAIT (0x7 << 29) 108 - #define PACKET3_DRAW_INDEX_MULTI_INST 0x3A 109 - #define PACKET3_COPY_DW 0x3B 110 111 #define PACKET3_WAIT_REG_MEM 0x3C 111 - #define WAIT_REG_MEM_FUNCTION(x) ((x) << 0) 112 + #define WAIT_REG_MEM_FUNCTION(x) (((x) & 0x7) << 0) 112 113 /* 0 - always 113 114 * 1 - < 114 115 * 2 - <= ··· 112 123 * 5 - >= 113 124 * 6 - > 114 125 */ 115 - #define WAIT_REG_MEM_MEM_SPACE(x) ((x) << 4) 126 + #define WAIT_REG_MEM_MEM_SPACE(x) (((x) & 0x3) << 4) 116 127 /* 0 - reg 117 128 * 1 - mem 118 129 */ 119 - #define WAIT_REG_MEM_OPERATION(x) ((x) << 6) 130 + #define WAIT_REG_MEM_OPERATION(x) (((x) & 0x3) << 6) 120 131 /* 0 - wait_reg_mem 121 132 * 1 - wr_wait_wr_reg 122 133 */ 123 - #define WAIT_REG_MEM_ENGINE(x) ((x) << 8) 124 - /* 0 - me 125 - * 1 - pfp 134 + #define WAIT_REG_MEM_MODE(x) (((x) & 0x3) << 10) 135 + /* 0 - local xcd 136 + * 1 - remote/local aid 137 + * 2 - remote xcd 138 + * 3 - remote mid 139 + */ 140 + #define WAIT_REG_MEM_MID_DIE_ID(x) (((x) & 0x3) << 12) 141 + #define WAIT_REG_MEM_XCD_DIE_ID(x) (((x) & 0xf) << 14) 142 + #define WAIT_REG_MEM_MES_INTR_PIPE(x) (((x) & 0x3) << 22) 143 + #define WAIT_REG_MEM_MES_ACTION(x) (((x) & 0x1) << 24) 144 + #define WAIT_REG_MEM_TEMPORAL(x) (((x) & 0x3) << 25) 145 + /* 0 - rt 146 + * 1 - nt 147 + * 2 - ht 148 + * 3 - lu 126 149 */ 127 150 #define PACKET3_INDIRECT_BUFFER 0x3F 128 151 #define INDIRECT_BUFFER_VALID (1 << 23) 129 - #define INDIRECT_BUFFER_CACHE_POLICY(x) ((x) << 28) 130 - /* 0 - LRU 131 - * 1 - Stream 132 - * 2 - Bypass 152 + #define INDIRECT_BUFFER_TEMPORAL(x) (x) << 28) 153 + /* 0 - rt 154 + * 1 - nt 155 + * 2 - ht 156 + * 3 - lu 133 157 */ 134 - #define INDIRECT_BUFFER_PRE_ENB(x) ((x) << 21) 135 - #define INDIRECT_BUFFER_PRE_RESUME(x) ((x) << 30) 136 158 #define PACKET3_COND_INDIRECT_BUFFER 0x3F 137 159 #define PACKET3_COPY_DATA 0x40 138 - #define PACKET3_CP_DMA 0x41 160 + #define COPY_DATA_SRC_SEL(x) (((x) & 0xf) << 0) 161 + #define COPY_DATA_DST_SEL(x) (((x) & 0xf) << 8) 162 + #define COPY_DATA_SRC_SCOPE(x) (((x) & 0x3) << 4) 163 + #define COPY_DATA_DST_SCOPE(x) (((x) & 0x3) << 27) 164 + #define COPY_DATA_MODE(x) (((x) & 0x3) << 6) 165 + /* 0 - local xcd 166 + * 1 - remote/local aid 167 + * 2 - remote xcd 168 + * 3 - remote mid 169 + */ 170 + #define COPY_DATA_SRC_TEMPORAL(x) (((x) & 0x3) << 13) 171 + #define COPY_DATA_DST_TEMPORAL(x) (((x) & 0x3) << 25) 172 + /* 0 - rt 173 + * 1 - nt 174 + * 2 - ht 175 + * 3 - lu 176 + */ 177 + #define COPY_DATA_COUNT_SEL (1 << 16) 178 + #define COPY_DATA_SRC_DST_REMOTE_MODE(x) (((x)) & 0x1 << 16) 179 + /* 0 - src remote 180 + * 1 - dst remote 181 + */ 182 + #define COPY_DATA_MID_DIE_ID(x) (((x) & 0x3) << 18) 183 + #define COPY_DATA_XCD_DIE_ID(x) (((x) & 0xf) << 21) 184 + #define COPY_DATA_PQ_EXE_STATUS (1 << 27) 139 185 #define PACKET3_PFP_SYNC_ME 0x42 140 - #define PACKET3_SURFACE_SYNC 0x43 141 - #define PACKET3_ME_INITIALIZE 0x44 142 186 #define PACKET3_COND_WRITE 0x45 143 187 #define PACKET3_EVENT_WRITE 0x46 144 188 #define EVENT_TYPE(x) ((x) << 0) ··· 182 160 * 3 - SAMPLE_STREAMOUTSTAT* 183 161 * 4 - *S_PARTIAL_FLUSH 184 162 */ 185 - #define PACKET3_EVENT_WRITE_EOP 0x47 186 - #define PACKET3_EVENT_WRITE_EOS 0x48 187 163 #define PACKET3_RELEASE_MEM 0x49 188 164 #define PACKET3_RELEASE_MEM_EVENT_TYPE(x) ((x) << 0) 189 165 #define PACKET3_RELEASE_MEM_EVENT_INDEX(x) ((x) << 8) ··· 200 180 * 2 - temporal__release_mem__ht 201 181 * 3 - temporal__release_mem__lu 202 182 */ 203 - #define PACKET3_RELEASE_MEM_EXECUTE (1 << 28) 183 + #define PACKET3_RELEASE_MEM_PQ_EXE_STATUS (1 << 28) 184 + #define PACKET3_RELEASE_MEM_GCR_GLK_INV (1 << 30) 204 185 186 + #define PACKET3_RELEASE_MEM_DST_SEL(x) ((x) << 16) 187 + /* 0 - memory controller 188 + * 1 - TC/L2 189 + * 2 - register 190 + */ 191 + #define PACKET3_RELEASE_MEM_MES_INTR_PIPE(x) ((x) << 20) 192 + #define PACKET3_RELEASE_MEM_MES_ACTION_ID(x) ((x) << 22) 193 + #define PACKET3_RELEASE_MEM_INT_SEL(x) ((x) << 24) 194 + /* 0 - none 195 + * 1 - interrupt only (DATA_SEL = 0) 196 + * 2 - interrupt when data write is confirmed 197 + */ 198 + #define PACKET3_RELEASE_MEM_ADD_DOOREBLL_OFFSET(x) (1 << 28) 205 199 #define PACKET3_RELEASE_MEM_DATA_SEL(x) ((x) << 29) 206 200 /* 0 - discard 207 201 * 1 - send low 32bit data ··· 223 189 * 3 - send 64bit GPU counter value 224 190 * 4 - send 64bit sys counter value 225 191 */ 226 - #define PACKET3_RELEASE_MEM_INT_SEL(x) ((x) << 24) 227 - /* 0 - none 228 - * 1 - interrupt only (DATA_SEL = 0) 229 - * 2 - interrupt when data write is confirmed 230 - */ 231 - #define PACKET3_RELEASE_MEM_DST_SEL(x) ((x) << 16) 232 - /* 0 - MC 233 - * 1 - TC/L2 234 - */ 235 - 236 - 237 192 238 193 #define PACKET3_PREAMBLE_CNTL 0x4A 239 194 # define PACKET3_PREAMBLE_BEGIN_CLEAR_STATE (2 << 28) ··· 241 218 /* 0 - ME 242 219 * 1 - PFP 243 220 */ 244 - # define PACKET3_DMA_DATA_SRC_CACHE_POLICY(x) ((x) << 13) 245 - /* 0 - LRU 246 - * 1 - Stream 221 + # define PACKET3_DMA_DATA_SRC_TEMPORAL(x) ((x) << 13) 222 + /* 0 - rt 223 + * 1 - nt 224 + * 2 - ht 225 + * 3 - lu 247 226 */ 248 - # define PACKET3_DMA_DATA_DST_SEL(x) ((x) << 20) 227 + # define PACKET3_DMA_DATA_SRC_SCOPE(x) ((x) << 15) 228 + # define PACKET3_DMA_DATA_DST_SEL(x) ((x) << 20) 249 229 /* 0 - DST_ADDR using DAS 250 230 * 1 - GDS 251 231 * 3 - DST_ADDR using L2 252 232 */ 253 - # define PACKET3_DMA_DATA_DST_CACHE_POLICY(x) ((x) << 25) 233 + # define PACKET3_DMA_DATA_DST_TEMPORAL(x) ((x) << 25) 254 234 /* 0 - LRU 255 235 * 1 - Stream 256 236 */ 257 - # define PACKET3_DMA_DATA_SRC_SEL(x) ((x) << 29) 237 + # define PACKET3_DMA_DATA_DST_SCOPE(x) ((x) << 27) 238 + # define PACKET3_DMA_DATA_SRC_SEL(x) ((x) << 29) 258 239 /* 0 - SRC_ADDR using SAS 259 240 * 1 - GDS 260 241 * 2 - DATA 261 242 * 3 - SRC_ADDR using L2 262 243 */ 263 - # define PACKET3_DMA_DATA_CP_SYNC (1 << 31) 264 244 /* COMMAND */ 265 245 # define PACKET3_DMA_DATA_CMD_SAS (1 << 26) 266 246 /* 0 - memory ··· 273 247 /* 0 - memory 274 248 * 1 - register 275 249 */ 276 - # define PACKET3_DMA_DATA_CMD_SAIC (1 << 28) 277 - # define PACKET3_DMA_DATA_CMD_DAIC (1 << 29) 278 - # define PACKET3_DMA_DATA_CMD_RAW_WAIT (1 << 30) 250 + # define PACKET3_DMA_DATA_CMD_SAIC (1 << 28) 251 + # define PACKET3_DMA_DATA_CMD_DAIC (1 << 29) 252 + # define PACKET3_DMA_DATA_CMD_RAW_WAIT (1 << 30) 253 + # define PACKET3_DMA_DATA_CMD_DIS_WC (1 << 30) 279 254 #define PACKET3_CONTEXT_REG_RMW 0x51 280 - #define PACKET3_GFX_CNTX_UPDATE 0x52 281 - #define PACKET3_BLK_CNTX_UPDATE 0x53 282 - #define PACKET3_INCR_UPDT_STATE 0x55 283 255 #define PACKET3_ACQUIRE_MEM 0x58 284 256 /* 1. HEADER 285 257 * 2. COHER_CNTL [30:0] ··· 331 307 * 2: REVERSE 332 308 */ 333 309 #define PACKET3_ACQUIRE_MEM_GCR_RANGE_IS_PA (1 << 18) 334 - #define PACKET3_REWIND 0x59 335 - #define PACKET3_INTERRUPT 0x5A 336 310 #define PACKET3_GEN_PDEPTE 0x5B 337 - #define PACKET3_INDIRECT_BUFFER_PASID 0x5C 338 311 #define PACKET3_PRIME_UTCL2 0x5D 339 312 #define PACKET3_LOAD_UCONFIG_REG 0x5E 340 313 #define PACKET3_LOAD_SH_REG 0x5F ··· 345 324 #define PACKET3_SET_CONTEXT_REG 0x69 346 325 #define PACKET3_SET_CONTEXT_REG_START 0x0000a000 347 326 #define PACKET3_SET_CONTEXT_REG_END 0x0000a400 348 - #define PACKET3_SET_CONTEXT_REG_INDEX 0x6A 349 - #define PACKET3_SET_VGPR_REG_DI_MULTI 0x71 350 - #define PACKET3_SET_SH_REG_DI 0x72 351 - #define PACKET3_SET_CONTEXT_REG_INDIRECT 0x73 352 - #define PACKET3_SET_SH_REG_DI_MULTI 0x74 353 - #define PACKET3_GFX_PIPE_LOCK 0x75 354 327 #define PACKET3_SET_SH_REG 0x76 355 328 #define PACKET3_SET_SH_REG_START 0x00002c00 356 329 #define PACKET3_SET_SH_REG_END 0x00003000 ··· 354 339 #define PACKET3_SET_UCONFIG_REG_START 0x0000c000 355 340 #define PACKET3_SET_UCONFIG_REG_END 0x0000c400 356 341 #define PACKET3_SET_UCONFIG_REG_INDEX 0x7A 357 - #define PACKET3_FORWARD_HEADER 0x7C 358 - #define PACKET3_SCRATCH_RAM_WRITE 0x7D 359 - #define PACKET3_SCRATCH_RAM_READ 0x7E 360 - #define PACKET3_LOAD_CONST_RAM 0x80 361 - #define PACKET3_WRITE_CONST_RAM 0x81 362 - #define PACKET3_DUMP_CONST_RAM 0x83 363 - #define PACKET3_INCREMENT_CE_COUNTER 0x84 364 - #define PACKET3_INCREMENT_DE_COUNTER 0x85 365 - #define PACKET3_WAIT_ON_CE_COUNTER 0x86 366 - #define PACKET3_WAIT_ON_DE_COUNTER_DIFF 0x88 367 - #define PACKET3_SWITCH_BUFFER 0x8B 368 342 #define PACKET3_DISPATCH_DRAW_PREAMBLE 0x8C 369 - #define PACKET3_DISPATCH_DRAW_PREAMBLE_ACE 0x8C 370 343 #define PACKET3_DISPATCH_DRAW 0x8D 371 - #define PACKET3_DISPATCH_DRAW_ACE 0x8D 372 - #define PACKET3_GET_LOD_STATS 0x8E 373 - #define PACKET3_DRAW_MULTI_PREAMBLE 0x8F 374 - #define PACKET3_FRAME_CONTROL 0x90 375 - # define FRAME_TMZ (1 << 0) 376 - # define FRAME_CMD(x) ((x) << 28) 377 - /* 378 - * x=0: tmz_begin 379 - * x=1: tmz_end 380 - */ 381 344 #define PACKET3_INDEX_ATTRIBUTES_INDIRECT 0x91 382 345 #define PACKET3_WAIT_REG_MEM64 0x93 383 - #define PACKET3_COND_PREEMPT 0x94 384 346 #define PACKET3_HDP_FLUSH 0x95 385 - #define PACKET3_COPY_DATA_RB 0x96 386 347 #define PACKET3_INVALIDATE_TLBS 0x98 387 348 #define PACKET3_INVALIDATE_TLBS_DST_SEL(x) ((x) << 0) 388 349 #define PACKET3_INVALIDATE_TLBS_ALL_HUB(x) ((x) << 4) 389 350 #define PACKET3_INVALIDATE_TLBS_PASID(x) ((x) << 5) 390 351 #define PACKET3_INVALIDATE_TLBS_FLUSH_TYPE(x) ((x) << 29) 391 352 392 - #define PACKET3_AQL_PACKET 0x99 393 353 #define PACKET3_DMA_DATA_FILL_MULTI 0x9A 394 354 #define PACKET3_SET_SH_REG_INDEX 0x9B 395 - #define PACKET3_DRAW_INDIRECT_COUNT_MULTI 0x9C 396 - #define PACKET3_DRAW_INDEX_INDIRECT_COUNT_MULTI 0x9D 397 - #define PACKET3_DUMP_CONST_RAM_OFFSET 0x9E 398 355 #define PACKET3_LOAD_CONTEXT_REG_INDEX 0x9F 399 356 #define PACKET3_SET_RESOURCES 0xA0 400 357 /* 1. header ··· 381 394 # define PACKET3_SET_RESOURCES_VMID_MASK(x) ((x) << 0) 382 395 # define PACKET3_SET_RESOURCES_UNMAP_LATENTY(x) ((x) << 16) 383 396 # define PACKET3_SET_RESOURCES_QUEUE_TYPE(x) ((x) << 29) 384 - #define PACKET3_MAP_PROCESS 0xA1 385 397 #define PACKET3_MAP_QUEUES 0xA2 386 398 /* 1. header 387 399 * 2. CONTROL ··· 397 411 # define PACKET3_MAP_QUEUES_PIPE(x) ((x) << 16) 398 412 # define PACKET3_MAP_QUEUES_ME(x) ((x) << 18) 399 413 # define PACKET3_MAP_QUEUES_QUEUE_TYPE(x) ((x) << 21) 400 - # define PACKET3_MAP_QUEUES_ALLOC_FORMAT(x) ((x) << 24) 414 + # define PACKET3_MAP_QUEUES_QUEUE_GROUP(x) ((x) << 24) 401 415 # define PACKET3_MAP_QUEUES_ENGINE_SEL(x) ((x) << 26) 402 416 # define PACKET3_MAP_QUEUES_NUM_QUEUES(x) ((x) << 29) 403 417 /* CONTROL2 */ 404 - # define PACKET3_MAP_QUEUES_CHECK_DISABLE(x) ((x) << 1) 405 418 # define PACKET3_MAP_QUEUES_DOORBELL_OFFSET(x) ((x) << 2) 406 419 #define PACKET3_UNMAP_QUEUES 0xA3 407 420 /* 1. header ··· 449 464 # define PACKET3_QUERY_STATUS_PASID(x) ((x) << 0) 450 465 /* CONTROL2b */ 451 466 # define PACKET3_QUERY_STATUS_DOORBELL_OFFSET(x) ((x) << 2) 452 - # define PACKET3_QUERY_STATUS_ENG_SEL(x) ((x) << 25) 453 - #define PACKET3_RUN_LIST 0xA5 454 - #define PACKET3_MAP_PROCESS_VM 0xA6 455 - /* GFX11 */ 456 - #define PACKET3_SET_Q_PREEMPTION_MODE 0xF0 457 - # define PACKET3_SET_Q_PREEMPTION_MODE_IB_VMID(x) ((x) << 0) 458 - # define PACKET3_SET_Q_PREEMPTION_MODE_INIT_SHADOW_MEM (1 << 0) 467 + # define PACKET3_QUERY_STATUS_ENG_SEL(x) ((x) << 28) 459 468 460 469 #endif