Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
Merge branch 'fixes' of master.kernel.org:/home/rmk/linux-2.6-arm
* 'fixes' of master.kernel.org:/home/rmk/linux-2.6-arm:
ARM: pm: avoid writing the auxillary control register for ARMv7
ARM: pm: some ARMv7 requires a dsb in resume to ensure correctness
ARM: pm: arm920/926: fix number of registers saved
ARM: pm: CPU specific code should not overwrite r1 (v:p offset)
ARM: 7066/1: proc-v7: disable SCTLR.TE when disabling MMU
ARM: 7065/1: kexec: ensure new kernel is entered in ARM state
ARM: 7003/1: vexpress: Add clock definition for the SP805.
ARM: 7051/1: cpuimx* boards: fix mach-types errors
ARM: 7019/1: Footbridge: select CLKEVT_I8253 for ARCH_NETWINDER
ARM: 7015/1: ARM errata: Possible cache data corruption with hit-under-miss enabled
ARM: 7014/1: cache-l2x0: Fix L2 Cache size calculation.
ARM: 6967/1: ep93xx: ts72xx: fix board model detection
ARM: 6965/1: ep93xx: add model detection for ts-7300 and ts-7400 boards
ARM: cache: detect VIPT aliasing I-cache on ARMv6
ARM: twd: register clockevents device before enabling PPI
ARM: realview: ensure visibility of writes during reset
ARM: perf: make name of arm_pmu_type consistent
ARM: perf: fix prototype of release_pmu
ARM: fix perf build with uclibc toolchains
+114
-50
+12
arch/arm/Kconfig
+12
arch/arm/Kconfig
···
1271
1271
This workaround defines cpu_relax() as smp_mb(), preventing correctly
1272
1272
written polling loops from denying visibility of updates to memory.
1273
1273
1274
+
config ARM_ERRATA_364296
1275
+
bool "ARM errata: Possible cache data corruption with hit-under-miss enabled"
1276
+
depends on CPU_V6 && !SMP
1277
+
help
1278
+
This options enables the workaround for the 364296 ARM1136
1279
+
r0p2 erratum (possible cache data corruption with
1280
+
hit-under-miss enabled). It sets the undocumented bit 31 in
1281
+
the auxiliary control register and the FI bit in the control
1282
+
register, thus disabling hit-under-miss without putting the
1283
+
processor into full low interrupt latency mode. ARM11MPCore
1284
+
is not affected.
1285
+
1274
1286
endmenu
1275
1287
1276
1288
source "arch/arm/common/Kconfig"
+1
-1
arch/arm/include/asm/hardware/cache-l2x0.h
+1
-1
arch/arm/include/asm/hardware/cache-l2x0.h
···
64
64
#define L2X0_AUX_CTRL_MASK 0xc0000fff
65
65
#define L2X0_AUX_CTRL_ASSOCIATIVITY_SHIFT 16
66
66
#define L2X0_AUX_CTRL_WAY_SIZE_SHIFT 17
67
-
#define L2X0_AUX_CTRL_WAY_SIZE_MASK (0x3 << 17)
67
+
#define L2X0_AUX_CTRL_WAY_SIZE_MASK (0x7 << 17)
68
68
#define L2X0_AUX_CTRL_SHARE_OVERRIDE_SHIFT 22
69
69
#define L2X0_AUX_CTRL_NS_LOCKDOWN_SHIFT 26
70
70
#define L2X0_AUX_CTRL_NS_INT_CTRL_SHIFT 27
+5
-5
arch/arm/include/asm/pmu.h
+5
-5
arch/arm/include/asm/pmu.h
···
41
41
* encoded error on failure.
42
42
*/
43
43
extern struct platform_device *
44
-
reserve_pmu(enum arm_pmu_type device);
44
+
reserve_pmu(enum arm_pmu_type type);
45
45
46
46
/**
47
47
* release_pmu() - Relinquish control of the performance counters
···
62
62
* the actual hardware initialisation.
63
63
*/
64
64
extern int
65
-
init_pmu(enum arm_pmu_type device);
65
+
init_pmu(enum arm_pmu_type type);
66
66
67
67
#else /* CONFIG_CPU_HAS_PMU */
68
68
69
69
#include <linux/err.h>
70
70
71
71
static inline struct platform_device *
72
-
reserve_pmu(enum arm_pmu_type device)
72
+
reserve_pmu(enum arm_pmu_type type)
73
73
{
74
74
return ERR_PTR(-ENODEV);
75
75
}
76
76
77
77
static inline int
78
-
release_pmu(struct platform_device *pdev)
78
+
release_pmu(enum arm_pmu_type type)
79
79
{
80
80
return -ENODEV;
81
81
}
82
82
83
83
static inline int
84
-
init_pmu(enum arm_pmu_type device)
84
+
init_pmu(enum arm_pmu_type type)
85
85
{
86
86
return -ENODEV;
87
87
}
+13
-13
arch/arm/kernel/pmu.c
+13
-13
arch/arm/kernel/pmu.c
···
31
31
{
32
32
if (type < 0 || type >= ARM_NUM_PMU_DEVICES) {
33
33
pr_warning("received registration request for unknown "
34
-
"device %d\n", type);
34
+
"PMU device type %d\n", type);
35
35
return -EINVAL;
36
36
}
37
37
···
112
112
device_initcall(register_pmu_driver);
113
113
114
114
struct platform_device *
115
-
reserve_pmu(enum arm_pmu_type device)
115
+
reserve_pmu(enum arm_pmu_type type)
116
116
{
117
117
struct platform_device *pdev;
118
118
119
-
if (test_and_set_bit_lock(device, &pmu_lock)) {
119
+
if (test_and_set_bit_lock(type, &pmu_lock)) {
120
120
pdev = ERR_PTR(-EBUSY);
121
-
} else if (pmu_devices[device] == NULL) {
122
-
clear_bit_unlock(device, &pmu_lock);
121
+
} else if (pmu_devices[type] == NULL) {
122
+
clear_bit_unlock(type, &pmu_lock);
123
123
pdev = ERR_PTR(-ENODEV);
124
124
} else {
125
-
pdev = pmu_devices[device];
125
+
pdev = pmu_devices[type];
126
126
}
127
127
128
128
return pdev;
···
130
130
EXPORT_SYMBOL_GPL(reserve_pmu);
131
131
132
132
int
133
-
release_pmu(enum arm_pmu_type device)
133
+
release_pmu(enum arm_pmu_type type)
134
134
{
135
-
if (WARN_ON(!pmu_devices[device]))
135
+
if (WARN_ON(!pmu_devices[type]))
136
136
return -EINVAL;
137
-
clear_bit_unlock(device, &pmu_lock);
137
+
clear_bit_unlock(type, &pmu_lock);
138
138
return 0;
139
139
}
140
140
EXPORT_SYMBOL_GPL(release_pmu);
···
182
182
}
183
183
184
184
int
185
-
init_pmu(enum arm_pmu_type device)
185
+
init_pmu(enum arm_pmu_type type)
186
186
{
187
187
int err = 0;
188
188
189
-
switch (device) {
189
+
switch (type) {
190
190
case ARM_PMU_DEVICE_CPU:
191
191
err = init_cpu_pmu();
192
192
break;
193
193
default:
194
-
pr_warning("attempt to initialise unknown device %d\n",
195
-
device);
194
+
pr_warning("attempt to initialise PMU of unknown "
195
+
"type %d\n", type);
196
196
err = -EINVAL;
197
197
}
198
198
+2
-1
arch/arm/kernel/relocate_kernel.S
+2
-1
arch/arm/kernel/relocate_kernel.S
+8
-7
arch/arm/kernel/setup.c
+8
-7
arch/arm/kernel/setup.c
···
280
280
if (arch >= CPU_ARCH_ARMv6) {
281
281
if ((cachetype & (7 << 29)) == 4 << 29) {
282
282
/* ARMv7 register format */
283
+
arch = CPU_ARCH_ARMv7;
283
284
cacheid = CACHEID_VIPT_NONALIASING;
284
285
if ((cachetype & (3 << 14)) == 1 << 14)
285
286
cacheid |= CACHEID_ASID_TAGGED;
286
-
else if (cpu_has_aliasing_icache(CPU_ARCH_ARMv7))
287
-
cacheid |= CACHEID_VIPT_I_ALIASING;
288
-
} else if (cachetype & (1 << 23)) {
289
-
cacheid = CACHEID_VIPT_ALIASING;
290
287
} else {
291
-
cacheid = CACHEID_VIPT_NONALIASING;
292
-
if (cpu_has_aliasing_icache(CPU_ARCH_ARMv6))
293
-
cacheid |= CACHEID_VIPT_I_ALIASING;
288
+
arch = CPU_ARCH_ARMv6;
289
+
if (cachetype & (1 << 23))
290
+
cacheid = CACHEID_VIPT_ALIASING;
291
+
else
292
+
cacheid = CACHEID_VIPT_NONALIASING;
294
293
}
294
+
if (cpu_has_aliasing_icache(arch))
295
+
cacheid |= CACHEID_VIPT_I_ALIASING;
295
296
} else {
296
297
cacheid = CACHEID_VIVT;
297
298
}
+2
-2
arch/arm/kernel/smp_twd.c
+2
-2
arch/arm/kernel/smp_twd.c
···
137
137
clk->max_delta_ns = clockevent_delta2ns(0xffffffff, clk);
138
138
clk->min_delta_ns = clockevent_delta2ns(0xf, clk);
139
139
140
+
clockevents_register_device(clk);
141
+
140
142
/* Make sure our local interrupt controller has this enabled */
141
143
gic_enable_ppi(clk->irq);
142
-
143
-
clockevents_register_device(clk);
144
144
}
+22
-4
arch/arm/mach-ep93xx/include/mach/ts72xx.h
+22
-4
arch/arm/mach-ep93xx/include/mach/ts72xx.h
···
6
6
* TS72xx memory map:
7
7
*
8
8
* virt phys size
9
-
* febff000 22000000 4K model number register
9
+
* febff000 22000000 4K model number register (bits 0-2)
10
10
* febfe000 22400000 4K options register
11
11
* febfd000 22800000 4K options register #2
12
12
* febf9000 10800000 4K TS-5620 RTC index register
···
20
20
#define TS72XX_MODEL_TS7200 0x00
21
21
#define TS72XX_MODEL_TS7250 0x01
22
22
#define TS72XX_MODEL_TS7260 0x02
23
+
#define TS72XX_MODEL_TS7300 0x03
24
+
#define TS72XX_MODEL_TS7400 0x04
25
+
#define TS72XX_MODEL_MASK 0x07
23
26
24
27
25
28
#define TS72XX_OPTIONS_PHYS_BASE 0x22400000
···
54
51
55
52
#ifndef __ASSEMBLY__
56
53
54
+
static inline int ts72xx_model(void)
55
+
{
56
+
return __raw_readb(TS72XX_MODEL_VIRT_BASE) & TS72XX_MODEL_MASK;
57
+
}
58
+
57
59
static inline int board_is_ts7200(void)
58
60
{
59
-
return __raw_readb(TS72XX_MODEL_VIRT_BASE) == TS72XX_MODEL_TS7200;
61
+
return ts72xx_model() == TS72XX_MODEL_TS7200;
60
62
}
61
63
62
64
static inline int board_is_ts7250(void)
63
65
{
64
-
return __raw_readb(TS72XX_MODEL_VIRT_BASE) == TS72XX_MODEL_TS7250;
66
+
return ts72xx_model() == TS72XX_MODEL_TS7250;
65
67
}
66
68
67
69
static inline int board_is_ts7260(void)
68
70
{
69
-
return __raw_readb(TS72XX_MODEL_VIRT_BASE) == TS72XX_MODEL_TS7260;
71
+
return ts72xx_model() == TS72XX_MODEL_TS7260;
72
+
}
73
+
74
+
static inline int board_is_ts7300(void)
75
+
{
76
+
return ts72xx_model() == TS72XX_MODEL_TS7300;
77
+
}
78
+
79
+
static inline int board_is_ts7400(void)
80
+
{
81
+
return ts72xx_model() == TS72XX_MODEL_TS7400;
70
82
}
71
83
72
84
static inline int is_max197_installed(void)
+1
arch/arm/mach-footbridge/Kconfig
+1
arch/arm/mach-footbridge/Kconfig
+1
-1
arch/arm/mach-imx/mach-cpuimx27.c
+1
-1
arch/arm/mach-imx/mach-cpuimx27.c
+1
-1
arch/arm/mach-imx/mach-cpuimx35.c
+1
-1
arch/arm/mach-imx/mach-cpuimx35.c
···
192
192
.init = eukrea_cpuimx35_timer_init,
193
193
};
194
194
195
-
MACHINE_START(EUKREA_CPUIMX35, "Eukrea CPUIMX35")
195
+
MACHINE_START(EUKREA_CPUIMX35SD, "Eukrea CPUIMX35")
196
196
/* Maintainer: Eukrea Electromatique */
197
197
.boot_params = MX3x_PHYS_OFFSET + 0x100,
198
198
.map_io = mx35_map_io,
+1
-1
arch/arm/mach-imx/mach-eukrea_cpuimx25.c
+1
-1
arch/arm/mach-imx/mach-eukrea_cpuimx25.c
···
161
161
.init = eukrea_cpuimx25_timer_init,
162
162
};
163
163
164
-
MACHINE_START(EUKREA_CPUIMX25, "Eukrea CPUIMX25")
164
+
MACHINE_START(EUKREA_CPUIMX25SD, "Eukrea CPUIMX25")
165
165
/* Maintainer: Eukrea Electromatique */
166
166
.boot_params = MX25_PHYS_OFFSET + 0x100,
167
167
.map_io = mx25_map_io,
+1
arch/arm/mach-realview/include/mach/system.h
+1
arch/arm/mach-realview/include/mach/system.h
+7
arch/arm/mach-vexpress/v2m.c
+7
arch/arm/mach-vexpress/v2m.c
···
318
318
.rate = 1000000,
319
319
};
320
320
321
+
static struct clk v2m_ref_clk = {
322
+
.rate = 32768,
323
+
};
324
+
321
325
static struct clk dummy_apb_pclk;
322
326
323
327
static struct clk_lookup v2m_lookups[] = {
···
352
348
}, { /* CLCD */
353
349
.dev_id = "mb:clcd",
354
350
.clk = &osc1_clk,
351
+
}, { /* SP805 WDT */
352
+
.dev_id = "mb:wdt",
353
+
.clk = &v2m_ref_clk,
355
354
}, { /* SP804 timers */
356
355
.dev_id = "sp804",
357
356
.con_id = "v2m-timer0",
+1
-1
arch/arm/mm/proc-arm920.S
+1
-1
arch/arm/mm/proc-arm920.S
···
379
379
380
380
/* Suspend/resume support: taken from arch/arm/plat-s3c24xx/sleep.S */
381
381
.globl cpu_arm920_suspend_size
382
-
.equ cpu_arm920_suspend_size, 4 * 3
382
+
.equ cpu_arm920_suspend_size, 4 * 4
383
383
#ifdef CONFIG_PM_SLEEP
384
384
ENTRY(cpu_arm920_do_suspend)
385
385
stmfd sp!, {r4 - r7, lr}
+1
-1
arch/arm/mm/proc-arm926.S
+1
-1
arch/arm/mm/proc-arm926.S
···
394
394
395
395
/* Suspend/resume support: taken from arch/arm/plat-s3c24xx/sleep.S */
396
396
.globl cpu_arm926_suspend_size
397
-
.equ cpu_arm926_suspend_size, 4 * 3
397
+
.equ cpu_arm926_suspend_size, 4 * 4
398
398
#ifdef CONFIG_PM_SLEEP
399
399
ENTRY(cpu_arm926_do_suspend)
400
400
stmfd sp!, {r4 - r7, lr}
+5
-5
arch/arm/mm/proc-sa1100.S
+5
-5
arch/arm/mm/proc-sa1100.S
···
182
182
183
183
ENTRY(cpu_sa1100_do_resume)
184
184
ldmia r0, {r4 - r7} @ load cp regs
185
-
mov r1, #0
186
-
mcr p15, 0, r1, c8, c7, 0 @ flush I+D TLBs
187
-
mcr p15, 0, r1, c7, c7, 0 @ flush I&D cache
188
-
mcr p15, 0, r1, c9, c0, 0 @ invalidate RB
189
-
mcr p15, 0, r1, c9, c0, 5 @ allow user space to use RB
185
+
mov ip, #0
186
+
mcr p15, 0, ip, c8, c7, 0 @ flush I+D TLBs
187
+
mcr p15, 0, ip, c7, c7, 0 @ flush I&D cache
188
+
mcr p15, 0, ip, c9, c0, 0 @ invalidate RB
189
+
mcr p15, 0, ip, c9, c0, 5 @ allow user space to use RB
190
190
191
191
mcr p15, 0, r4, c3, c0, 0 @ domain ID
192
192
mcr p15, 0, r5, c2, c0, 0 @ translation table base addr
+16
arch/arm/mm/proc-v6.S
+16
arch/arm/mm/proc-v6.S
···
223
223
mrc p15, 0, r0, c1, c0, 0 @ read control register
224
224
bic r0, r0, r5 @ clear bits them
225
225
orr r0, r0, r6 @ set them
226
+
#ifdef CONFIG_ARM_ERRATA_364296
227
+
/*
228
+
* Workaround for the 364296 ARM1136 r0p2 erratum (possible cache data
229
+
* corruption with hit-under-miss enabled). The conditional code below
230
+
* (setting the undocumented bit 31 in the auxiliary control register
231
+
* and the FI bit in the control register) disables hit-under-miss
232
+
* without putting the processor into full low interrupt latency mode.
233
+
*/
234
+
ldr r6, =0x4107b362 @ id for ARM1136 r0p2
235
+
mrc p15, 0, r5, c0, c0, 0 @ get processor id
236
+
teq r5, r6 @ check for the faulty core
237
+
mrceq p15, 0, r5, c1, c0, 1 @ load aux control reg
238
+
orreq r5, r5, #(1 << 31) @ set the undocumented bit 31
239
+
mcreq p15, 0, r5, c1, c0, 1 @ write aux control reg
240
+
orreq r0, r0, #(1 << 21) @ low interrupt latency configuration
241
+
#endif
226
242
mov pc, lr @ return to head.S:__ret
227
243
228
244
/*
+5
-1
arch/arm/mm/proc-v7.S
+5
-1
arch/arm/mm/proc-v7.S
···
66
66
ENTRY(cpu_v7_reset)
67
67
mrc p15, 0, r1, c1, c0, 0 @ ctrl register
68
68
bic r1, r1, #0x1 @ ...............m
69
+
THUMB( bic r1, r1, #1 << 30 ) @ SCTLR.TE (Thumb exceptions)
69
70
mcr p15, 0, r1, c1, c0, 0 @ disable MMU
70
71
isb
71
72
mov pc, r0
···
248
247
mcr p15, 0, r7, c2, c0, 0 @ TTB 0
249
248
mcr p15, 0, r8, c2, c0, 1 @ TTB 1
250
249
mcr p15, 0, ip, c2, c0, 2 @ TTB control register
251
-
mcr p15, 0, r10, c1, c0, 1 @ Auxiliary control register
250
+
mrc p15, 0, r4, c1, c0, 1 @ Read Auxiliary control register
251
+
teq r4, r10 @ Is it already set?
252
+
mcrne p15, 0, r10, c1, c0, 1 @ No, so write it
252
253
mcr p15, 0, r11, c1, c0, 2 @ Co-processor access control
253
254
ldr r4, =PRRR @ PRRR
254
255
ldr r5, =NMRR @ NMRR
255
256
mcr p15, 0, r4, c10, c2, 0 @ write PRRR
256
257
mcr p15, 0, r5, c10, c2, 1 @ write NMRR
257
258
isb
259
+
dsb
258
260
mov r0, r9 @ control register
259
261
mov r2, r7, lsr #14 @ get TTB0 base
260
262
mov r2, r2, lsl #14
+3
-3
arch/arm/mm/proc-xsc3.S
+3
-3
arch/arm/mm/proc-xsc3.S
···
406
406
.align
407
407
408
408
.globl cpu_xsc3_suspend_size
409
-
.equ cpu_xsc3_suspend_size, 4 * 8
409
+
.equ cpu_xsc3_suspend_size, 4 * 7
410
410
#ifdef CONFIG_PM_SLEEP
411
411
ENTRY(cpu_xsc3_do_suspend)
412
412
stmfd sp!, {r4 - r10, lr}
···
418
418
mrc p15, 0, r9, c1, c0, 1 @ auxiliary control reg
419
419
mrc p15, 0, r10, c1, c0, 0 @ control reg
420
420
bic r4, r4, #2 @ clear frequency change bit
421
-
stmia r0, {r1, r4 - r10} @ store v:p offset + cp regs
421
+
stmia r0, {r4 - r10} @ store cp regs
422
422
ldmia sp!, {r4 - r10, pc}
423
423
ENDPROC(cpu_xsc3_do_suspend)
424
424
425
425
ENTRY(cpu_xsc3_do_resume)
426
-
ldmia r0, {r1, r4 - r10} @ load v:p offset + cp regs
426
+
ldmia r0, {r4 - r10} @ load cp regs
427
427
mov ip, #0
428
428
mcr p15, 0, ip, c7, c7, 0 @ invalidate I & D caches, BTB
429
429
mcr p15, 0, ip, c7, c10, 4 @ drain write (&fill) buffer
+3
-3
arch/arm/tools/mach-types
+3
-3
arch/arm/tools/mach-types
···
351
351
nokia_rx51 MACH_NOKIA_RX51 NOKIA_RX51 1955
352
352
omap_zoom2 MACH_OMAP_ZOOM2 OMAP_ZOOM2 1967
353
353
cpuat9260 MACH_CPUAT9260 CPUAT9260 1973
354
-
eukrea_cpuimx27 MACH_CPUIMX27 CPUIMX27 1975
354
+
eukrea_cpuimx27 MACH_EUKREA_CPUIMX27 EUKREA_CPUIMX27 1975
355
355
acs5k MACH_ACS5K ACS5K 1982
356
356
snapper_9260 MACH_SNAPPER_9260 SNAPPER_9260 1987
357
357
dsm320 MACH_DSM320 DSM320 1988
···
476
476
omap4_panda MACH_OMAP4_PANDA OMAP4_PANDA 2791
477
477
ti8168evm MACH_TI8168EVM TI8168EVM 2800
478
478
teton_bga MACH_TETON_BGA TETON_BGA 2816
479
-
eukrea_cpuimx25sd MACH_EUKREA_CPUIMX25 EUKREA_CPUIMX25 2820
480
-
eukrea_cpuimx35sd MACH_EUKREA_CPUIMX35 EUKREA_CPUIMX35 2821
479
+
eukrea_cpuimx25sd MACH_EUKREA_CPUIMX25SD EUKREA_CPUIMX25SD 2820
480
+
eukrea_cpuimx35sd MACH_EUKREA_CPUIMX35SD EUKREA_CPUIMX35SD 2821
481
481
eukrea_cpuimx51sd MACH_EUKREA_CPUIMX51SD EUKREA_CPUIMX51SD 2822
482
482
eukrea_cpuimx51 MACH_EUKREA_CPUIMX51 EUKREA_CPUIMX51 2823
483
483
smdkc210 MACH_SMDKC210 SMDKC210 2838