tjh.dev / kernel
Linux kernel mirror (for testing) git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
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drm/msm/a6xx: Add a pwrup_list field to a6xx_info

Add a field to contain the pwup_reglist needed for preemption.

Signed-off-by: Antonino Maniscalco <antomani103@gmail.com>
Patchwork: https://patchwork.freedesktop.org/patch/618018/
Signed-off-by: Rob Clark <robdclark@chromium.org>

authored by

Antonino Maniscalco and committed by
Rob Clark 91389b4e c7546e2c

+41
+26
drivers/gpu/drm/msm/adreno/a6xx_catalog.c
··· 1281 1281 }; 1282 1282 DECLARE_ADRENO_PROTECT(a730_protect, 48); 1283 1283 1284 + static const uint32_t a7xx_pwrup_reglist_regs[] = { 1285 + REG_A6XX_UCHE_TRAP_BASE, 1286 + REG_A6XX_UCHE_TRAP_BASE + 1, 1287 + REG_A6XX_UCHE_WRITE_THRU_BASE, 1288 + REG_A6XX_UCHE_WRITE_THRU_BASE + 1, 1289 + REG_A6XX_UCHE_GMEM_RANGE_MIN, 1290 + REG_A6XX_UCHE_GMEM_RANGE_MIN + 1, 1291 + REG_A6XX_UCHE_GMEM_RANGE_MAX, 1292 + REG_A6XX_UCHE_GMEM_RANGE_MAX + 1, 1293 + REG_A6XX_UCHE_CACHE_WAYS, 1294 + REG_A6XX_UCHE_MODE_CNTL, 1295 + REG_A6XX_RB_NC_MODE_CNTL, 1296 + REG_A6XX_RB_CMP_DBG_ECO_CNTL, 1297 + REG_A7XX_GRAS_NC_MODE_CNTL, 1298 + REG_A6XX_RB_CONTEXT_SWITCH_GMEM_SAVE_RESTORE, 1299 + REG_A6XX_UCHE_GBIF_GX_CONFIG, 1300 + REG_A6XX_UCHE_CLIENT_PF, 1301 + REG_A6XX_TPL1_DBG_ECO_CNTL1, 1302 + }; 1303 + 1304 + DECLARE_ADRENO_REGLIST_LIST(a7xx_pwrup_reglist); 1305 + 1284 1306 static const struct adreno_info a7xx_gpus[] = { 1285 1307 { 1286 1308 .chip_ids = ADRENO_CHIP_IDS(0x07000200), ··· 1343 1321 .a6xx = &(const struct a6xx_info) { 1344 1322 .hwcg = a730_hwcg, 1345 1323 .protect = &a730_protect, 1324 + .pwrup_reglist = &a7xx_pwrup_reglist, 1346 1325 .gmu_cgc_mode = 0x00020000, 1347 1326 }, 1348 1327 .address_space_size = SZ_16G, ··· 1364 1341 .a6xx = &(const struct a6xx_info) { 1365 1342 .hwcg = a740_hwcg, 1366 1343 .protect = &a730_protect, 1344 + .pwrup_reglist = &a7xx_pwrup_reglist, 1367 1345 .gmu_chipid = 0x7020100, 1368 1346 .gmu_cgc_mode = 0x00020202, 1369 1347 }, ··· 1385 1361 .a6xx = &(const struct a6xx_info) { 1386 1362 .hwcg = a740_hwcg, 1387 1363 .protect = &a730_protect, 1364 + .pwrup_reglist = &a7xx_pwrup_reglist, 1388 1365 .gmu_chipid = 0x7050001, 1389 1366 .gmu_cgc_mode = 0x00020202, 1390 1367 }, ··· 1406 1381 .zapfw = "gen70900_zap.mbn", 1407 1382 .a6xx = &(const struct a6xx_info) { 1408 1383 .protect = &a730_protect, 1384 + .pwrup_reglist = &a7xx_pwrup_reglist, 1409 1385 .gmu_chipid = 0x7090100, 1410 1386 .gmu_cgc_mode = 0x00020202, 1411 1387 },
+2
drivers/gpu/drm/msm/adreno/a6xx_gpu.h
··· 17 17 * 18 18 * @hwcg: hw clock gating register sequence 19 19 * @protect: CP_PROTECT settings 20 + * @pwrup_reglist pwrup reglist for preemption 20 21 */ 21 22 struct a6xx_info { 22 23 const struct adreno_reglist *hwcg; 23 24 const struct adreno_protect *protect; 25 + const struct adreno_reglist_list *pwrup_reglist; 24 26 u32 gmu_chipid; 25 27 u32 gmu_cgc_mode; 26 28 u32 prim_fifo_threshold;
+13
drivers/gpu/drm/msm/adreno/adreno_gpu.h
··· 157 157 .count_max = __count_max, \ 158 158 }; 159 159 160 + struct adreno_reglist_list { 161 + /** @reg: List of register **/ 162 + const u32 *regs; 163 + /** @count: Number of registers in the list **/ 164 + u32 count; 165 + }; 166 + 167 + #define DECLARE_ADRENO_REGLIST_LIST(name) \ 168 + static const struct adreno_reglist_list name = { \ 169 + .regs = name ## _regs, \ 170 + .count = ARRAY_SIZE(name ## _regs), \ 171 + }; 172 + 160 173 struct adreno_gpu { 161 174 struct msm_gpu base; 162 175 const struct adreno_info *info;