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drm/msm/dpu: get rid of DPU_SSPP_QOS_8LVL

Continue migration to the MDSS-revision based checks and replace
DPU_SSPP_QOS_8LVL feature bit with the core_major_ver >= 4 check.

Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org>
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
Patchwork: https://patchwork.freedesktop.org/patch/655406/
Link: https://lore.kernel.org/r/20250522-dpu-drop-features-v5-26-3b2085a07884@oss.qualcomm.com

authored by

Dmitry Baryshkov and committed by
Dmitry Baryshkov 914a4b96 3e6d0543

+9 -6
+3 -3
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
··· 35 35 (VIG_MASK | BIT(DPU_SSPP_SCALER_QSEED3_COMPATIBLE)) 36 36 37 37 #define VIG_SDM845_MASK_NO_SDMA \ 38 - (VIG_MASK | BIT(DPU_SSPP_QOS_8LVL) | BIT(DPU_SSPP_SCALER_QSEED3_COMPATIBLE)) 38 + (VIG_MASK | BIT(DPU_SSPP_SCALER_QSEED3_COMPATIBLE)) 39 39 40 40 #define VIG_SDM845_MASK_SDMA \ 41 41 (VIG_SDM845_MASK_NO_SDMA | BIT(DPU_SSPP_SMART_DMA_V2)) 42 42 43 - #define VIG_QCM2290_MASK (VIG_BASE_MASK | BIT(DPU_SSPP_QOS_8LVL)) 43 + #define VIG_QCM2290_MASK (VIG_BASE_MASK) 44 44 45 45 #define DMA_MSM8953_MASK \ 46 46 (BIT(DPU_SSPP_QOS)) ··· 60 60 (VIG_SC7280_MASK | BIT(DPU_SSPP_SMART_DMA_V2)) 61 61 62 62 #define DMA_SDM845_MASK_NO_SDMA \ 63 - (BIT(DPU_SSPP_QOS) | BIT(DPU_SSPP_QOS_8LVL) |\ 63 + (BIT(DPU_SSPP_QOS) | \ 64 64 BIT(DPU_SSPP_TS_PREFILL) | BIT(DPU_SSPP_TS_PREFILL_REC1) |\ 65 65 BIT(DPU_SSPP_CDP) | BIT(DPU_SSPP_EXCL_RECT)) 66 66
-2
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h
··· 50 50 * @DPU_SSPP_CSC_10BIT, Support of 10-bit Color space conversion 51 51 * @DPU_SSPP_CURSOR, SSPP can be used as a cursor layer 52 52 * @DPU_SSPP_QOS, SSPP support QoS control, danger/safe/creq 53 - * @DPU_SSPP_QOS_8LVL, SSPP support 8-level QoS control 54 53 * @DPU_SSPP_EXCL_RECT, SSPP supports exclusion rect 55 54 * @DPU_SSPP_SMART_DMA_V1, SmartDMA 1.0 support 56 55 * @DPU_SSPP_SMART_DMA_V2, SmartDMA 2.0 support ··· 67 68 DPU_SSPP_CSC_10BIT, 68 69 DPU_SSPP_CURSOR, 69 70 DPU_SSPP_QOS, 70 - DPU_SSPP_QOS_8LVL, 71 71 DPU_SSPP_EXCL_RECT, 72 72 DPU_SSPP_SMART_DMA_V1, 73 73 DPU_SSPP_SMART_DMA_V2,
+4 -1
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c
··· 543 543 return; 544 544 545 545 _dpu_hw_setup_qos_lut(&ctx->hw, SSPP_DANGER_LUT, 546 - test_bit(DPU_SSPP_QOS_8LVL, &ctx->cap->features), 546 + ctx->mdss_ver->core_major_ver >= 4, 547 547 cfg); 548 548 } 549 549 ··· 703 703 hw_pipe->ubwc = mdss_data; 704 704 hw_pipe->idx = cfg->id; 705 705 hw_pipe->cap = cfg; 706 + 707 + hw_pipe->mdss_ver = mdss_rev; 708 + 706 709 _setup_layer_ops(hw_pipe, hw_pipe->cap->features, mdss_rev); 707 710 708 711 return hw_pipe;
+2
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.h
··· 314 314 enum dpu_sspp idx; 315 315 const struct dpu_sspp_cfg *cap; 316 316 317 + const struct dpu_mdss_version *mdss_ver; 318 + 317 319 /* Ops */ 318 320 struct dpu_hw_sspp_ops ops; 319 321 };